* [dpdk-dev] [PATCH] compress/qat: add compression PMD
@ 2018-05-23 18:40 Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 00/16] " Fiona Trahe
` (16 more replies)
0 siblings, 17 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-05-23 18:40 UTC (permalink / raw)
To: dev
Cc: pablo.de.lara.guarch, fiona.trahe, deepak.k.jain,
tomaszx.jozwiak, lee.daly
Create compression PMD for Intel QuickAssist devices
Currently only the C62x device is supported.
The qat comp PMD supports
- stateless compression and
decompression using the deflate algorithm.
- checksum generation: Adler32, CRC32 and combined.
The compression service is hosted on a QuickAssist VF PCI
device, which is managed by code in the
drivers/common/qat directory.
This patch depends on the following patchset:
crypto/qat: move files to drivers/common directory
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
MAINTAINERS | 5 +
config/common_base | 2 +
doc/guides/compressdevs/features/qat.ini | 22 +
drivers/common/qat/Makefile | 60 ++-
drivers/common/qat/qat_adf/icp_qat_fw_comp.h | 586 ++++++++++++++++++++++++++
drivers/common/qat/qat_common.c | 17 +-
drivers/common/qat/qat_common.h | 18 +-
drivers/common/qat/qat_device.c | 3 +
drivers/common/qat/qat_device.h | 10 +
drivers/common/qat/qat_qp.c | 11 +-
drivers/common/qat/qat_qp.h | 5 +
drivers/compress/qat/qat_comp.c | 383 +++++++++++++++++
drivers/compress/qat/qat_comp.h | 78 ++++
drivers/compress/qat/qat_comp_pmd.c | 479 +++++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 40 ++
drivers/crypto/qat/qat_sym.c | 12 +-
drivers/crypto/qat/qat_sym.h | 14 +-
17 files changed, 1702 insertions(+), 43 deletions(-)
create mode 100644 doc/guides/compressdevs/features/qat.ini
create mode 100644 drivers/common/qat/qat_adf/icp_qat_fw_comp.h
create mode 100644 drivers/compress/qat/qat_comp.c
create mode 100644 drivers/compress/qat/qat_comp.h
create mode 100644 drivers/compress/qat/qat_comp_pmd.c
create mode 100644 drivers/compress/qat/qat_comp_pmd.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 7cc8860..5381f0c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -831,6 +831,11 @@ F: drivers/compress/isal/
F: doc/guides/compressdevs/isal.rst
F: doc/guides/compressdevs/features/isal.ini
+Intel QuickAssist
+M: Fiona Trahe <fiona.trahe@intel.com>
+F: drivers/compress/qat/
+F: drivers/common/qat/
+F: doc/guides/compressdevs/features/qat.ini
Eventdev Drivers
----------------
diff --git a/config/common_base b/config/common_base
index f456f95..b85c990 100644
--- a/config/common_base
+++ b/config/common_base
@@ -487,6 +487,8 @@ CONFIG_RTE_LIBRTE_PMD_QAT=y
# Max. number of QuickAssist devices, which can be detected and attached
#
CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES=48
+CONFIG_RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS=16
+CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE=131072
#
# Compile PMD for virtio crypto devices
#
diff --git a/doc/guides/compressdevs/features/qat.ini b/doc/guides/compressdevs/features/qat.ini
new file mode 100644
index 0000000..d99b5de
--- /dev/null
+++ b/doc/guides/compressdevs/features/qat.ini
@@ -0,0 +1,22 @@
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+; Supported features of 'QAT' compression driver.
+;
+[Features]
+HW Accelerated = Y
+CPU SSE =
+CPU AVX =
+CPU AVX2 =
+CPU AVX512 =
+CPU NEON =
+Stateful =
+By-Pass =
+Chained mbufs = Y
+Deflate = Y
+LZS =
+Adler32 = Y
+Crc32 = Y
+Adler32&Crc32 = Y
+Fixed = Y
+Dynamic = Y
diff --git a/drivers/common/qat/Makefile b/drivers/common/qat/Makefile
index c023c34..a8545f4 100644
--- a/drivers/common/qat/Makefile
+++ b/drivers/common/qat/Makefile
@@ -6,29 +6,24 @@ include $(RTE_SDK)/mk/rte.vars.mk
# libcrypto detection
LIBCRYPTO := $(shell pkg-config --exists libcrypto 1>&2 2> /dev/null; echo $$?)
-# library name
-LIB = librte_pmd_qat.a
-
-# library version
-LIBABIVER := 1
-
-# build flags
-CFLAGS += $(WERROR_FLAGS)
-CFLAGS += -O3
-
# build directories
QAT_CRYPTO_DIR := $(RTE_SDK)/drivers/crypto/qat
+QAT_COMPRESS_DIR := $(RTE_SDK)/drivers/compress/qat
# external library include paths
CFLAGS += -I$(SRCDIR)/qat_adf
CFLAGS += -I$(SRCDIR)
+
CFLAGS += -I$(QAT_CRYPTO_DIR)
+CFLAGS += -I$(QAT_COMPRESS_DIR)
-# library common source files
-SRCS-y += qat_device.c
-SRCS-y += qat_common.c
-SRCS-y += qat_logs.c
-SRCS-y += qat_qp.c
+ifeq ($(CONFIG_RTE_LIBRTE_COMPRESSDEV),y)
+ CFLAGS += -DALLOW_EXPERIMENTAL_API
+ LDLIBS += -lrte_compressdev
+ SRCS-y += $(QAT_COMPRESS_DIR)/qat_comp.c
+ SRCS-y += $(QAT_COMPRESS_DIR)/qat_comp_pmd.c
+ build_qat = yes
+endif
ifeq ($(LIBCRYPTO),0)
LDLIBS += -lrte_cryptodev
@@ -37,15 +32,38 @@ ifeq ($(LIBCRYPTO),0)
SRCS-y += $(QAT_CRYPTO_DIR)/qat_sym.c
SRCS-y += $(QAT_CRYPTO_DIR)/qat_sym_session.c
SRCS-y += $(QAT_CRYPTO_DIR)/qat_sym_pmd.c
+ build_qat = yes
endif
-LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool
-LDLIBS += -lrte_pci -lrte_bus_pci
-# export include files
-SYMLINK-y-include +=
-# versioning export map
-EXPORT_MAP := qat/rte_pmd_qat_version.map
+ifdef build_qat
+
+ # library name
+ LIB = librte_pmd_qat.a
+
+ # library version
+ LIBABIVER := 1
+
+ # build flags
+ CFLAGS += $(WERROR_FLAGS)
+ CFLAGS += -O3
+
+ # library common source files
+ SRCS-y += qat_device.c
+ SRCS-y += qat_common.c
+ SRCS-y += qat_logs.c
+ SRCS-y += qat_qp.c
+
+ LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool
+ LDLIBS += -lrte_pci -lrte_bus_pci
+
+ # export include files
+ SYMLINK-y-include +=
+
+ # versioning export map
+ EXPORT_MAP := qat/rte_pmd_qat_version.map
+
+endif
include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_comp.h b/drivers/common/qat/qat_adf/icp_qat_fw_comp.h
new file mode 100644
index 0000000..4ad1d30
--- /dev/null
+++ b/drivers/common/qat/qat_adf/icp_qat_fw_comp.h
@@ -0,0 +1,586 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+#ifndef _ICP_QAT_FW_COMP_H_
+#define _ICP_QAT_FW_COMP_H_
+
+#include "icp_qat_fw.h"
+
+/* Next curr slice */
+#define ICP_QAT_FW_COMN_NEXT_ID_BITPOS 4
+#define ICP_QAT_FW_COMN_NEXT_ID_MASK 0xF0
+#define ICP_QAT_FW_COMN_CURR_ID_BITPOS 0
+#define ICP_QAT_FW_COMN_CURR_ID_MASK 0x0F
+
+#define ICP_QAT_FW_COMN_NEXT_ID_SET_2(next_curr_id, val) \
+ do { \
+ (next_curr_id) = \
+ (((next_curr_id)&ICP_QAT_FW_COMN_CURR_ID_MASK) | \
+ (((val) << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) & \
+ ICP_QAT_FW_COMN_NEXT_ID_MASK)) \
+ } while (0)
+
+#define ICP_QAT_FW_COMN_CURR_ID_SET_2(next_curr_id, val) \
+ do { \
+ (next_curr_id) = \
+ (((next_curr_id)&ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
+ ((val)&ICP_QAT_FW_COMN_CURR_ID_MASK)) \
+ } while (0)
+
+/* Private defines */
+#define QAT_COMPRESSION_DIR_BITPOS 4
+/**< @ingroup icp_qat_hw_defs
+ * Define for the compression direction bit position
+ */
+
+#define QAT_COMPRESSION_DIR_MASK 0x7
+/**< @ingroup icp_qat_hw_defs
+ * Define for the compression direction mask (three bits)
+ */
+
+#define QAT_COMPRESSION_DELAYED_MATCH_BITPOS 16
+/**< @ingroup icp_qat_hw_defs
+ * Define for the compression delayed match bit position
+ */
+
+#define QAT_COMPRESSION_DELAYED_MATCH_MASK 0x1
+/**< @ingroup icp_qat_hw_defs
+ * Define for the delayed match mask (one bit)
+ */
+
+#define QAT_COMPRESSION_ALGO_BITPOS 31
+/**< @ingroup icp_qat_hw_defs
+ * Define for the compression algorithm bit position
+ */
+
+#define QAT_COMPRESSION_ALGO_MASK 0x1
+/**< @ingroup icp_qat_hw_defs
+ * Define for the compression algorithm mask (one bit)
+ */
+
+#define QAT_COMPRESSION_DEPTH_BITPOS 28
+/**< @ingroup icp_qat_hw_defs
+ * Define for the compression depth bit position
+ */
+
+#define QAT_COMPRESSION_DEPTH_MASK 0x7
+/**< @ingroup icp_qat_hw_defs
+ * Define for the compression depth mask (three bits)
+ */
+
+#define QAT_COMPRESSION_FILE_TYPE_BITPOS 24
+/**< @ingroup icp_qat_hw_defs
+ * Define for the compression file type bit position
+ */
+
+#define QAT_COMPRESSION_FILE_TYPE_MASK 0xF
+/**< @ingroup icp_qat_hw_defs
+ * Define for the compression file type mask (four bits)
+ */
+
+#define ICP_QAT_FW_COMP_NOT_SOP 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request is NOT Start of Packet
+ */
+
+#define ICP_QAT_FW_COMP_SOP 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request IS Start of Packet
+ */
+
+#define ICP_QAT_FW_COMP_NOT_EOP 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request is NOT Start of Packet
+ */
+
+#define ICP_QAT_FW_COMP_EOP 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request IS End of Packet
+ */
+
+#define ICP_QAT_FW_COMP_NOT_BFINAL 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing to indicate firmware this is not the last block
+ */
+
+#define ICP_QAT_FW_COMP_BFINAL 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing to indicate firmware this is the last block
+ */
+
+#define ICP_QAT_FW_COMP_NO_MCA 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that NO mca check is to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_MCA 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that an mca check IS to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_SOP_BITPOS 0
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for SOP
+ */
+
+#define ICP_QAT_FW_COMP_SOP_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask used to determine SOP
+ */
+
+#define ICP_QAT_FW_COMP_EOP_BITPOS 1
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for EOP
+ */
+
+#define ICP_QAT_FW_COMP_EOP_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask used to determine EOP
+ */
+
+#define ICP_QAT_FW_COMP_BFINAL_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for the bfinal bit
+ */
+
+#define ICP_QAT_FW_COMP_BFINAL_BITPOS 6
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the bfinal bit
+ */
+
+#define ICP_QAT_FW_COMP_MCA_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for the MCA bit
+ */
+
+#define ICP_QAT_FW_COMP_MCA_BITPOS 16
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the MCA bit
+ */
+
+#define ICP_QAT_HW_COMPRESSION_CONFIG_BUILD(dir, delayed, algo, depth, \
+ filetype) \
+ ((((dir)&QAT_COMPRESSION_DIR_MASK) << QAT_COMPRESSION_DIR_BITPOS) | \
+ (((delayed)&QAT_COMPRESSION_DELAYED_MATCH_MASK) \
+ << QAT_COMPRESSION_DELAYED_MATCH_BITPOS) | \
+ (((algo)&QAT_COMPRESSION_ALGO_MASK) << QAT_COMPRESSION_ALGO_BITPOS) | \
+ (((depth)&QAT_COMPRESSION_DEPTH_MASK) \
+ << QAT_COMPRESSION_DEPTH_BITPOS) | \
+ (((filetype)&QAT_COMPRESSION_FILE_TYPE_MASK) \
+ << QAT_COMPRESSION_FILE_TYPE_BITPOS))
+
+/**< Flag usage */
+
+#define ICP_QAT_FW_COMP_STATELESS_SESSION 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that session is stateless
+ */
+
+#define ICP_QAT_FW_COMP_STATEFUL_SESSION 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that session is stateful
+ */
+
+#define ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that autoselectbest is NOT used
+ */
+
+#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that autoselectbest is used
+ */
+
+#define ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is NOT used
+ */
+
+#define ICP_QAT_FW_COMP_ENH_AUTO_SELECT_BEST 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is used
+ */
+
+#define ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is NOT used
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is used
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_USED_AS_INTMD_BUF 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing secure RAM from being used as
+ * an intermediate buffer is DISABLED.
+ */
+
+#define ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing secure RAM from being used as
+ * an intermediate buffer is ENABLED.
+ */
+
+/**< Flag mask & bit position */
+
+#define ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS 2
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the session type
+ */
+
+#define ICP_QAT_FW_COMP_SESSION_TYPE_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask used to determine the session type
+ */
+
+#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS 3
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for auto select best
+ */
+
+#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for auto select best
+ */
+
+#define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS 4
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for enhanced auto select best
+ */
+
+#define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for enhanced auto select best
+ */
+
+#define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS 5
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for disabling type zero header write back
+ * when Enhanced autoselect best is enabled. If set firmware does
+ * not return type0 store block header, only copies src to dest.
+ * (if best output is Type0)
+ */
+
+#define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for auto select best
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS 7
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for flag used to disable secure ram from
+ * being used as an intermediate buffer.
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for disable secure ram for use as an intermediate
+ * buffer.
+ */
+
+#define ICP_QAT_FW_COMP_FLAGS_BUILD(sesstype, autoselect, enhanced_asb, \
+ ret_uncomp, secure_ram) \
+ ((((sesstype)&ICP_QAT_FW_COMP_SESSION_TYPE_MASK) \
+ << ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS) | \
+ (((autoselect)&ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK) \
+ << ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS) | \
+ (((enhanced_asb)&ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK) \
+ << ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS) | \
+ (((ret_uncomp)&ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK) \
+ << ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS) | \
+ (((secure_ram)&ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK) \
+ << ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS))
+
+enum icp_qat_hw_compression_algo {
+ ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE = 0, /*!< Deflate compression */
+ ICP_QAT_HW_COMPRESSION_ALGO_LZS = 1, /*!< LZS compression */
+ ICP_QAT_HW_COMPRESSION_ALGO_DELIMITER = 2 /**< Delimiter type */
+};
+
+enum icp_qat_hw_compression_file_type {
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_0 = 0,
+ /*!< Use Static Trees */
+
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_1 = 1,
+ /*!< Use Semi-Dynamic Trees at offset 0 */
+
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_2 = 2,
+ /*!< Use Semi-Dynamic Trees at offset 320 */
+
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_3 = 3,
+ /*!< Use Semi-Dynamic Trees at offset 640 */
+
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_4 = 4,
+ /*!< Use Semi-Dynamic Trees at offset 960 */
+
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_DELIMITER = 5
+ /**< Delimiter type */
+};
+
+enum icp_qat_hw_compression_depth {
+ ICP_QAT_HW_COMPRESSION_DEPTH_1 = 0,
+ /*!< Search depth 1 (Fastest least exhaustive) */
+
+ ICP_QAT_HW_COMPRESSION_DEPTH_4 = 1,
+ /*!< Search depth 4 */
+
+ ICP_QAT_HW_COMPRESSION_DEPTH_8 = 2,
+ /*!< Search depth 8 */
+
+ ICP_QAT_HW_COMPRESSION_DEPTH_16 = 3,
+ /*!< Search depth 16 (Slowest, most exhaustive) */
+
+ ICP_QAT_HW_COMPRESSION_DEPTH_DELIMITER = 4
+ /**< Delimiter type */
+};
+
+enum icp_qat_hw_compression_delayed_match {
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED = 0,
+ /*!< Delayed match disabled */
+
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_ENABLED = 1,
+ /*!< Delayed match enabled
+ * Note: This is the only valid mode - refer to CPM1.6 SAS
+ */
+
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DELIMITER = 2
+ /**< Delimiter type */
+};
+
+enum icp_qat_fw_comp_cmd_id {
+ ICP_QAT_FW_COMP_CMD_STATIC = 0,
+ /*!< Static Compress Request */
+
+ ICP_QAT_FW_COMP_CMD_DYNAMIC = 1,
+ /*!< Dynamic Compress Request */
+
+ ICP_QAT_FW_COMP_CMD_DECOMPRESS = 2,
+ /*!< Decompress Request */
+
+ ICP_QAT_FW_COMP_CMD_DELIMITER
+ /**< Delimiter type */
+};
+
+enum { ICP_QAT_HW_COMPRESSION_DIR_COMPRESS = 0, /*!< Compression */
+ ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS = 1, /*!< Decompression */
+ ICP_QAT_HW_COMPRESSION_DIR_DELIMITER = 2 /**< Delimiter type */
+} icp_qat_hw_compression_direction;
+
+enum qat_comp_request {
+ QAT_COMP_REQUEST_STATIC_COMP_STATELESS,
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS,
+ QAT_COMP_REQUEST_DECOMPRESS,
+ REQ_COMP_END
+};
+
+union icp_qat_fw_comp_req_hdr_cd_pars {
+ /**< LWs 2-5 */
+ struct {
+ uint64_t content_desc_addr;
+ /**< Address of the content descriptor */
+
+ uint16_t content_desc_resrvd1;
+ /**< Content descriptor reserved field */
+
+ uint8_t content_desc_params_sz;
+ /**< Size of the content descriptor parameters in quad words.
+ * These parameters describe the session setup configuration
+ * info for the slices that this request relies upon i.e.
+ * the configuration word and cipher key needed by the cipher
+ * slice if there is a request for cipher processing.
+ */
+
+ uint8_t content_desc_hdr_resrvd2;
+ /**< Content descriptor reserved field */
+
+ uint32_t content_desc_resrvd3;
+ /**< Content descriptor reserved field */
+ } s;
+
+ struct {
+ uint32_t comp_slice_cfg_word[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /* Compression Slice Config Word */
+
+ uint32_t content_desc_resrvd4;
+ /**< Content descriptor reserved field */
+
+ } sl;
+
+};
+
+struct icp_qat_fw_comp_req_params {
+ /**< LW 14 */
+ uint32_t comp_len;
+ /**< Size of input to process in bytes Note: Only EOP requests can be
+ * odd for decompression. IA must set LSB to zero for odd sized
+ * intermediate inputs
+ */
+
+ /**< LW 15 */
+ uint32_t out_buffer_sz;
+ /**< Size of output buffer in bytes */
+
+ /**< LW 16 */
+ uint32_t initial_crc32;
+ /**< CRC of previously processed bytes */
+
+ /**< LW 17 */
+ uint32_t initial_adler;
+ /**< Adler of previously processed bytes */
+
+ /**< LW 18 */
+ uint32_t req_par_flags;
+
+ /**< LW 19 */
+ uint32_t rsrvd;
+};
+
+struct icp_qat_fw_xlt_req_params {
+ /**< LWs 20-21 */
+ uint64_t inter_buff_ptr;
+ /**< This field specifies the physical address of an intermediate
+ * buffer SGL array. The array contains a pair of 64-bit
+ * intermediate buffer pointers to SGL buffer descriptors, one pair
+ * per CPM. Please refer to the CPM1.6 Firmware Interface HLD
+ * specification for more details.
+ */
+};
+
+struct icp_qat_fw_comp_cd_hdr {
+ /**< LW 24 */
+ uint16_t ram_bank_flags;
+ /**< Flags to show which ram banks to access */
+
+ uint8_t comp_cfg_offset;
+ /**< Quad word offset from the content descriptor parameters address
+ * to the parameters for the compression processing
+ */
+
+ uint8_t next_curr_id;
+ /**< This field combines the next and current id (each four bits) -
+ * the next id is the most significant nibble.
+ * Next Id: Set to the next slice to pass the compressed data through.
+ * Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through
+ * anymore slices after compression
+ * Current Id: Initialised with the compression slice type
+ */
+
+ /**< LW 25 */
+ uint32_t resrvd;
+
+ /**< LWs 26-27 */
+ uint64_t comp_state_addr;
+ /**< Pointer to compression state */
+
+ /**< LWs 28-29 */
+ uint64_t ram_banks_addr;
+ /**< Pointer to banks */
+
+};
+
+struct icp_qat_fw_xlt_cd_hdr {
+ /**< LW 30 */
+ uint16_t resrvd1;
+ /**< Reserved field and assumed set to 0 */
+
+ uint8_t resrvd2;
+ /**< Reserved field and assumed set to 0 */
+
+ uint8_t next_curr_id;
+ /**< This field combines the next and current id (each four bits) -
+ * the next id is the most significant nibble.
+ * Next Id: Set to the next slice to pass the translated data through.
+ * Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through
+ * any more slices after compression
+ * Current Id: Initialised with the translation slice type
+ */
+
+ /**< LW 31 */
+ uint32_t resrvd3;
+ /**< Reserved and should be set to zero, needed for quadword
+ * alignment
+ */
+};
+
+struct icp_qat_fw_comp_req {
+ /**< LWs 0-1 */
+ struct icp_qat_fw_comn_req_hdr comn_hdr;
+ /**< Common request header - for Service Command Id,
+ * use service-specific Compression Command Id.
+ * Service Specific Flags - use Compression Command Flags
+ */
+
+ /**< LWs 2-5 */
+ union icp_qat_fw_comp_req_hdr_cd_pars cd_pars;
+ /**< Compression service-specific content descriptor field which points
+ * either to a content descriptor parameter block or contains the
+ * compression slice config word.
+ */
+
+ /**< LWs 6-13 */
+ struct icp_qat_fw_comn_req_mid comn_mid;
+ /**< Common request middle section */
+
+ /**< LWs 14-19 */
+ struct icp_qat_fw_comp_req_params comp_pars;
+ /**< Compression request Parameters block */
+
+ /**< LWs 20-21 */
+ union {
+ struct icp_qat_fw_xlt_req_params xlt_pars;
+ /**< Translation request Parameters block */
+
+ uint32_t resrvd1[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /**< Reserved if not used for translation */
+
+ } u1;
+
+ /**< LWs 22-23 */
+ union {
+ uint32_t resrvd2[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /**< Reserved - not used if Batch and Pack is disabled.*/
+
+ uint64_t bnp_res_table_addr;
+ /**< A generic pointer to the unbounded list of
+ * icp_qat_fw_resp_comp_pars_t members. This pointer is only
+ * used when the Batch and Pack is enabled.
+ */
+ } u3;
+
+ /**< LWs 24-29 */
+ struct icp_qat_fw_comp_cd_hdr comp_cd_ctrl;
+ /**< Compression request content descriptor control block header */
+
+ /**< LWs 30-31 */
+ union {
+ struct icp_qat_fw_xlt_cd_hdr xlt_cd_ctrl;
+ /**< Translation request content descriptor
+ * control block header
+ */
+
+ uint32_t resrvd3[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /**< Reserved if not used for translation */
+ } u2;
+};
+
+struct qat_comp_res_data {
+ uint32_t consumed;
+ uint32_t produced;
+ union {
+ uint64_t curr_chksum;
+ struct {
+ uint32_t curr_crc;
+ uint32_t curr_adler;
+ };
+ };
+};
+
+#define ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(sop, eop, bfinal, mca) \
+ ((((sop)&ICP_QAT_FW_COMP_SOP_MASK) << ICP_QAT_FW_COMP_SOP_BITPOS) | \
+ (((eop)&ICP_QAT_FW_COMP_EOP_MASK) << ICP_QAT_FW_COMP_EOP_BITPOS) | \
+ (((bfinal)&ICP_QAT_FW_COMP_BFINAL_MASK) \
+ << ICP_QAT_FW_COMP_BFINAL_BITPOS) | \
+ (((mca)&ICP_QAT_FW_COMP_MCA_MASK) << ICP_QAT_FW_COMP_MCA_BITPOS))
+#endif
diff --git a/drivers/common/qat/qat_common.c b/drivers/common/qat/qat_common.c
index c206d3b..b05c09f 100644
--- a/drivers/common/qat/qat_common.c
+++ b/drivers/common/qat/qat_common.c
@@ -8,11 +8,12 @@
int
qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buf_start,
- struct qat_sgl *list, uint32_t data_len)
+ void *lst, uint32_t data_len,
+ const int32_t max_segs)
{
int nr = 1;
-
- uint32_t buf_len = rte_pktmbuf_iova(buf) -
+ struct qat_sgl *list = (struct qat_sgl *)lst;
+ uint32_t buf_len = rte_pktmbuf_mtophys(buf) -
buf_start + rte_pktmbuf_data_len(buf);
list->buffers[0].addr = buf_start;
@@ -27,16 +28,16 @@
buf = buf->next;
while (buf) {
- if (unlikely(nr == QAT_SGL_MAX_NUMBER)) {
- QAT_LOG(ERR,
- "QAT PMD exceeded size of QAT SGL entry(%u)",
- QAT_SGL_MAX_NUMBER);
+ if (unlikely(nr == max_segs)) {
+ QAT_LOG(ERR, "QAT PMD exceeded size of QAT SGL"
+ " entry(%u)",
+ max_segs);
return -EINVAL;
}
list->buffers[nr].len = rte_pktmbuf_data_len(buf);
list->buffers[nr].resrvd = 0;
- list->buffers[nr].addr = rte_pktmbuf_iova(buf);
+ list->buffers[nr].addr = rte_pktmbuf_mtophys(buf);
buf_len += list->buffers[nr].len;
buf = buf->next;
diff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h
index db85d54..a011f5a 100644
--- a/drivers/common/qat/qat_common.h
+++ b/drivers/common/qat/qat_common.h
@@ -31,6 +31,7 @@ enum qat_service_type {
QAT_SERVICE_COMPRESSION,
QAT_SERVICE_INVALID
};
+
#define QAT_MAX_SERVICES (QAT_SERVICE_INVALID)
/**< Common struct for scatter-gather list operations */
@@ -40,11 +41,17 @@ struct qat_flat_buf {
uint64_t addr;
} __rte_packed;
+#define qat_sgl_hdr struct { \
+ uint64_t resrvd; \
+ uint32_t num_bufs; \
+ uint32_t num_mapped_bufs; \
+}
+
+__extension__
struct qat_sgl {
- uint64_t resrvd;
- uint32_t num_bufs;
- uint32_t num_mapped_bufs;
- struct qat_flat_buf buffers[QAT_SGL_MAX_NUMBER];
+ qat_sgl_hdr;
+ /* flexible array of flat buffers*/
+ struct qat_flat_buf buffers[0];
} __rte_packed __rte_cache_aligned;
/** Common, i.e. not service-specific, statistics */
@@ -64,7 +71,8 @@ struct qat_common_stats {
int
qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buf_start,
- struct qat_sgl *list, uint32_t data_len);
+ void *lst, uint32_t data_len,
+ const int32_t max_segs);
void
qat_stats_get(struct qat_pci_device *dev,
struct qat_common_stats *stats,
diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c
index 64f236e..0dadc8f 100644
--- a/drivers/common/qat/qat_device.c
+++ b/drivers/common/qat/qat_device.c
@@ -5,6 +5,7 @@
#include "qat_device.h"
#include "adf_transport_access_macros.h"
#include "qat_sym_pmd.h"
+#include "qat_comp_pmd.h"
/* Hardware device information per generation */
__extension__
@@ -12,11 +13,13 @@ struct qat_gen_hw_data qat_gen_config[] = {
[QAT_GEN1] = {
.dev_gen = QAT_GEN1,
.qp_hw_data = qat_gen1_qps,
+ .comp_num_im_bufs_required = QAT_NUM_INTERM_BUFS_GEN1
},
[QAT_GEN2] = {
.dev_gen = QAT_GEN2,
.qp_hw_data = qat_gen1_qps,
/* gen2 has same ring layout as gen1 */
+ .comp_num_im_bufs_required = QAT_NUM_INTERM_BUFS_GEN2
},
};
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index 0cb370c..41f874b 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -16,6 +16,11 @@
#define QAT_DEV_NAME_MAX_LEN 64
+enum qat_comp_num_im_buffers {
+ QAT_NUM_INTERM_BUFS_GEN1 = 12,
+ QAT_NUM_INTERM_BUFS_GEN2 = 20
+};
+
/*
* This struct holds all the data about a QAT pci device
* including data about all services it supports.
@@ -25,6 +30,8 @@
* - runtime data
*/
struct qat_sym_dev_private;
+struct qat_comp_dev_private;
+
struct qat_pci_device {
/* Data used by all services */
@@ -55,6 +62,8 @@ struct qat_pci_device {
*/
/* Data relating to compression service */
+ struct qat_comp_dev_private *comp_dev;
+ /**< link back to compressdev private data */
/* Data relating to asymmetric crypto service */
@@ -63,6 +72,7 @@ struct qat_pci_device {
struct qat_gen_hw_data {
enum qat_device_gen dev_gen;
const struct qat_qp_hw_data (*qp_hw_data)[ADF_MAX_QPS_ON_ANY_SERVICE];
+ enum qat_comp_num_im_buffers comp_num_im_bufs_required;
};
extern struct qat_gen_hw_data qat_gen_config[];
diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c
index 32c1759..7ca7a45 100644
--- a/drivers/common/qat/qat_qp.c
+++ b/drivers/common/qat/qat_qp.c
@@ -15,6 +15,7 @@
#include "qat_device.h"
#include "qat_qp.h"
#include "qat_sym.h"
+#include "qat_comp.h"
#include "adf_transport_access_macros.h"
@@ -606,8 +607,8 @@ void rxq_free_desc(struct qat_qp *qp, struct qat_queue *q)
if (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC)
qat_sym_process_response(ops, resp_msg);
- /* add qat_asym_process_response here */
- /* add qat_comp_process_response here */
+ else if (tmp_qp->service_type == QAT_SERVICE_COMPRESSION)
+ qat_comp_process_response(ops, resp_msg);
head = adf_modulo(head + rx_queue->msg_size,
rx_queue->modulo_mask);
@@ -633,3 +634,9 @@ void rxq_free_desc(struct qat_qp *qp, struct qat_queue *q)
}
return resp_counter;
}
+
+__attribute__((weak)) int
+qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused)
+{
+ return 0;
+}
diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h
index 59db945..69f8a61 100644
--- a/drivers/common/qat/qat_qp.h
+++ b/drivers/common/qat/qat_qp.h
@@ -103,4 +103,9 @@ struct qat_qp {
int
qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,
enum qat_service_type service);
+
+/* Needed for weak function*/
+int
+qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused);
+
#endif /* _QAT_QP_H_ */
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
new file mode 100644
index 0000000..813d841
--- /dev/null
+++ b/drivers/compress/qat/qat_comp.c
@@ -0,0 +1,383 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Intel Corporation
+ */
+
+#include <rte_mempool.h>
+#include <rte_mbuf.h>
+#include <rte_hexdump.h>
+#include <rte_comp.h>
+#include <rte_bus_pci.h>
+#include <rte_byteorder.h>
+#include <rte_memcpy.h>
+#include <rte_common.h>
+#include <rte_spinlock.h>
+#include <rte_log.h>
+#include <rte_malloc.h>
+
+#include "qat_logs.h"
+#include "qat_comp.h"
+#include "qat_comp_pmd.h"
+
+int
+qat_comp_build_request(void *in_op, uint8_t *out_msg, void *op_cookie,
+ enum qat_device_gen qat_dev_gen __rte_unused)
+{
+ struct rte_comp_op *op = in_op;
+ struct qat_comp_op_cookie *cookie =
+ (struct qat_comp_op_cookie *)op_cookie;
+ struct qat_comp_xform *qat_xform = op->private_xform;
+ const uint8_t *tmpl = (uint8_t *)&qat_xform->qat_comp_req_tmpl;
+ struct icp_qat_fw_comp_req *comp_req =
+ (struct icp_qat_fw_comp_req *)out_msg;
+
+ if (unlikely(op->op_type != RTE_COMP_OP_STATELESS)) {
+ QAT_DP_LOG(ERR, "QAT PMD only supports stateless compression "
+ "operation requests, op (%p) is not a "
+ "stateless operation.", op);
+ return -EINVAL;
+ }
+
+ rte_mov128(out_msg, tmpl);
+ comp_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
+
+ /* common for sgl and flat buffers */
+ comp_req->comp_pars.comp_len = op->src.length;
+ comp_req->comp_pars.out_buffer_sz = rte_pktmbuf_pkt_len(op->m_dst);
+
+ /* sgl */
+ if (op->m_src->next != NULL || op->m_dst->next != NULL) {
+ if (unlikely(op->m_src->next == NULL ||
+ op->m_dst->next == NULL)) {
+ QAT_DP_LOG(ERR, "QAT PMD doesn't support SGL on one "
+ "side only: src->next (%p), dst->next (%p)",
+ op->m_src->next, op->m_dst->next);
+ return -EINVAL;
+ }
+
+ int ret = 0;
+
+ ICP_QAT_FW_COMN_PTR_TYPE_SET(comp_req->comn_hdr.comn_req_flags,
+ QAT_COMN_PTR_TYPE_SGL);
+ ret = qat_sgl_fill_array(op->m_src,
+ rte_pktmbuf_mtophys_offset(op->m_src,
+ op->src.offset),
+ &cookie->qat_sgl_src,
+ op->src.length,
+ RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS);
+ if (ret) {
+ QAT_DP_LOG(ERR, "QAT PMD Cannot fill sgl array");
+ return ret;
+ }
+
+ ret = qat_sgl_fill_array(op->m_dst,
+ rte_pktmbuf_mtophys_offset(op->m_dst,
+ op->dst.offset),
+ &cookie->qat_sgl_dst,
+ comp_req->comp_pars.out_buffer_sz,
+ RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS);
+ if (ret) {
+ QAT_DP_LOG(ERR, "QAT PMD Cannot fill sgl array");
+ return ret;
+ }
+
+ comp_req->comn_mid.src_data_addr =
+ cookie->qat_sgl_src_phys_addr;
+ comp_req->comn_mid.dest_data_addr =
+ cookie->qat_sgl_dst_phys_addr;
+ comp_req->comn_mid.src_length = 0;
+ comp_req->comn_mid.dst_length = 0;
+
+ } else {
+ ICP_QAT_FW_COMN_PTR_TYPE_SET(comp_req->comn_hdr.comn_req_flags,
+ QAT_COMN_PTR_TYPE_FLAT);
+ comp_req->comn_mid.src_length = rte_pktmbuf_data_len(op->m_src);
+ comp_req->comn_mid.dst_length = rte_pktmbuf_data_len(op->m_dst);
+
+ comp_req->comn_mid.src_data_addr =
+ rte_pktmbuf_mtophys_offset(op->m_src, op->src.offset);
+ comp_req->comn_mid.dest_data_addr =
+ rte_pktmbuf_mtophys_offset(op->m_dst, op->dst.offset);
+ }
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_HEXDUMP_LOG(DEBUG, "qat compression message:", comp_req,
+ sizeof(struct icp_qat_fw_comp_req));
+#endif
+ return 0;
+}
+
+int
+qat_comp_process_response(void **op, uint8_t *resp)
+{
+ struct icp_qat_fw_comn_resp *resp_msg =
+ (struct icp_qat_fw_comn_resp *)resp;
+ struct rte_comp_op *rx_op = (struct rte_comp_op *)(uintptr_t)
+ (resp_msg->opaque_data);
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_HEXDUMP_LOG(DEBUG, "qat_response:", (uint8_t *)resp_msg,
+ sizeof(struct icp_qat_fw_comn_resp));
+#endif
+
+ if ((ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(resp_msg->comn_hdr.comn_status) |
+ ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(
+ resp_msg->comn_hdr.comn_status)) !=
+ ICP_QAT_FW_COMN_STATUS_FLAG_OK) {
+
+ rx_op->status = RTE_COMP_OP_STATUS_ERROR;
+ rx_op->debug_status =
+ *((uint16_t *)(&resp_msg->comn_hdr.comn_error));
+ } else {
+ struct qat_comp_xform *qat_xform = rx_op->private_xform;
+ struct qat_comp_res_data *comp_resp =
+ (struct qat_comp_res_data *)&resp_msg->resrvd;
+
+ rx_op->status = RTE_COMP_OP_STATUS_SUCCESS;
+ rx_op->consumed = comp_resp->consumed;
+ rx_op->produced = comp_resp->produced;
+
+ if (qat_xform->checksum_type != RTE_COMP_CHECKSUM_NONE) {
+ if (qat_xform->checksum_type == RTE_COMP_CHECKSUM_CRC32)
+ rx_op->output_chksum = comp_resp->curr_crc;
+ else if (qat_xform->checksum_type ==
+ RTE_COMP_CHECKSUM_ADLER32)
+ rx_op->output_chksum = comp_resp->curr_adler;
+ else
+ rx_op->output_chksum = comp_resp->curr_chksum;
+ }
+ }
+ *op = (void *)rx_op;
+
+ return 0;
+}
+
+unsigned int
+qat_comp_xform_size(void)
+{
+ return RTE_ALIGN_CEIL(sizeof(struct qat_comp_xform), 8);
+}
+
+static void qat_comp_create_req_hdr(struct icp_qat_fw_comn_req_hdr *header,
+ enum qat_comp_request request)
+{
+ if (request == QAT_COMP_REQUEST_FIXED_COMP_STATELESS)
+ header->service_cmd_id = ICP_QAT_FW_COMP_CMD_STATIC;
+ else if (request == QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS)
+ header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DYNAMIC;
+ else if (request == QAT_COMP_REQUEST_DECOMPRESS)
+ header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DECOMPRESS;
+
+ header->service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_COMP;
+ header->hdr_flags =
+ ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
+
+ header->comn_req_flags = ICP_QAT_FW_COMN_FLAGS_BUILD(
+ QAT_COMN_CD_FLD_TYPE_16BYTE_DATA, QAT_COMN_PTR_TYPE_FLAT);
+}
+
+static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,
+ const struct rte_memzone *interm_buff_mz,
+ const struct rte_comp_xform *xform)
+{
+ struct icp_qat_fw_comp_req *comp_req;
+ int comp_level, algo;
+ int direction = ICP_QAT_HW_COMPRESSION_DIR_COMPRESS;
+
+ if (unlikely(qat_xform == NULL)) {
+ QAT_LOG(ERR, "Session was not created for this device");
+ return -EINVAL;
+ }
+
+ if (qat_xform->qat_comp_request == QAT_COMP_REQUEST_DECOMPRESS) {
+ direction = ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS;
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_1;
+
+ } else {
+ if (xform->compress.level == RTE_COMP_LEVEL_PMD_DEFAULT)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_8;
+ else if (xform->compress.level == 1)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_1;
+ else if (xform->compress.level == 2)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_4;
+ else if (xform->compress.level == 3)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_8;
+ else if (xform->compress.level >= 4 &&
+ xform->compress.level <= 9)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_16;
+ else {
+ QAT_LOG(ERR, "compression level not supported");
+ return -EINVAL;
+ }
+ }
+
+ switch (xform->compress.algo) {
+ case RTE_COMP_ALGO_DEFLATE:
+ algo = ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE;
+ break;
+ case RTE_COMP_ALGO_LZS:
+ default:
+ /* RTE_COMP_NULL */
+ QAT_LOG(ERR, "compression algorithm not supported");
+ return -EINVAL;
+ }
+
+ comp_req = &qat_xform->qat_comp_req_tmpl;
+
+ /* Initialize header */
+ qat_comp_create_req_hdr(&comp_req->comn_hdr,
+ qat_xform->qat_comp_request);
+
+ comp_req->comn_hdr.serv_specif_flags = ICP_QAT_FW_COMP_FLAGS_BUILD(
+ ICP_QAT_FW_COMP_STATELESS_SESSION,
+ ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST,
+ ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST,
+ ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST,
+ ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_USED_AS_INTMD_BUF);
+
+ comp_req->cd_pars.sl.comp_slice_cfg_word[0] =
+ ICP_QAT_HW_COMPRESSION_CONFIG_BUILD(
+ direction,
+ /* In CPM 1.6 only valid mode ! */
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_ENABLED, algo,
+ /* Translate level to depth */
+ comp_level, ICP_QAT_HW_COMPRESSION_FILE_TYPE_0);
+
+ comp_req->comp_pars.initial_adler = 1;
+ comp_req->comp_pars.initial_crc32 = 0;
+ comp_req->comp_pars.req_par_flags =
+ ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(
+ ICP_QAT_FW_COMP_SOP, ICP_QAT_FW_COMP_EOP,
+ ICP_QAT_FW_COMP_BFINAL, ICP_QAT_FW_COMP_NO_MCA);
+
+ if (qat_xform->qat_comp_request == QAT_COMP_REQUEST_FIXED_COMP_STATELESS
+ || qat_xform->qat_comp_request == QAT_COMP_REQUEST_DECOMPRESS) {
+ ICP_QAT_FW_COMN_NEXT_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_DRAM_WR);
+ ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_COMP);
+ } else if (qat_xform->qat_comp_request ==
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {
+
+ ICP_QAT_FW_COMN_NEXT_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_XLAT);
+ ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_COMP);
+
+ ICP_QAT_FW_COMN_NEXT_ID_SET(&comp_req->u2.xlt_cd_ctrl,
+ ICP_QAT_FW_SLICE_DRAM_WR);
+ ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->u2.xlt_cd_ctrl,
+ ICP_QAT_FW_SLICE_XLAT);
+
+ comp_req->u1.xlt_pars.inter_buff_ptr =
+ interm_buff_mz->phys_addr;
+ }
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_HEXDUMP_LOG(DEBUG, "qat compression message template:", comp_req,
+ sizeof(struct icp_qat_fw_comp_req));
+#endif
+ return 0;
+}
+
+/**
+ * Create driver private_xform data.
+ *
+ * @param dev
+ * Compressdev device
+ * @param xform
+ * xform data from application
+ * @param private_xform
+ * ptr where handle of pmd's private_xform data should be stored
+ * @return
+ * - if successful returns 0
+ * and valid private_xform handle
+ * - <0 in error cases
+ * - Returns -EINVAL if input parameters are invalid.
+ * - Returns -ENOTSUP if comp device does not support the comp transform.
+ * - Returns -ENOMEM if the private_xform could not be allocated.
+ */
+int
+qat_comp_private_xform_create(struct rte_compressdev *dev,
+ const struct rte_comp_xform *xform,
+ void **private_xform)
+{
+ struct qat_comp_dev_private *qat = dev->data->dev_private;
+
+ if (unlikely(private_xform == NULL)) {
+ QAT_LOG(ERR, "QAT: private_xform parameter is NULL");
+ return -EINVAL;
+ }
+ if (unlikely(qat->xformpool == NULL)) {
+ QAT_LOG(ERR, "QAT device has no private_xform mempool");
+ return -ENOMEM;
+ }
+ if (rte_mempool_get(qat->xformpool, private_xform)) {
+ QAT_LOG(ERR, "Couldn't get object from qat xform mempool");
+ return -ENOMEM;
+ }
+
+ struct qat_comp_xform *qat_xform =
+ (struct qat_comp_xform *)*private_xform;
+
+ if (xform->type == RTE_COMP_COMPRESS) {
+ if (xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_FIXED ||
+ ((xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_DEFAULT)
+ && qat->interm_buff_mz == NULL))
+
+ qat_xform->qat_comp_request =
+ QAT_COMP_REQUEST_FIXED_COMP_STATELESS;
+ else if ((xform->compress.deflate.huffman ==
+ RTE_COMP_HUFFMAN_DYNAMIC ||
+ xform->compress.deflate.huffman ==
+ RTE_COMP_HUFFMAN_DEFAULT) &&
+ qat->interm_buff_mz != NULL)
+
+ qat_xform->qat_comp_request =
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS;
+ else {
+ QAT_LOG(ERR,
+ "IM buffers needed for dynamic deflate. Set size in config file");
+ return -EINVAL;
+ }
+
+ } else {
+ qat_xform->qat_comp_request = QAT_COMP_REQUEST_DECOMPRESS;
+ }
+
+ qat_xform->checksum_type = xform->compress.chksum;
+
+ if (qat_comp_create_templates(qat_xform, qat->interm_buff_mz, xform)) {
+ QAT_LOG(ERR, "QAT: Problem with setting compression");
+ return -EINVAL;
+ }
+ return 0;
+}
+
+/**
+ * Free driver private_xform data.
+ *
+ * @param dev
+ * Compressdev device
+ * @param private_xform
+ * handle of pmd's private_xform data
+ * @return
+ * - 0 if successful
+ * - <0 in error cases
+ * - Returns -EINVAL if input parameters are invalid.
+ */
+int
+qat_comp_private_xform_free(struct rte_compressdev *dev __rte_unused,
+ void *private_xform)
+{
+ struct qat_comp_xform *qat_xform =
+ (struct qat_comp_xform *)private_xform;
+
+ if (qat_xform) {
+ memset(qat_xform, 0, qat_comp_xform_size());
+ struct rte_mempool *mp = rte_mempool_from_obj(qat_xform);
+
+ rte_mempool_put(mp, qat_xform);
+ return 0;
+ }
+ return -EINVAL;
+}
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
new file mode 100644
index 0000000..ba3beec
--- /dev/null
+++ b/drivers/compress/qat/qat_comp.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+
+#ifndef _QAT_COMP_H_
+#define _QAT_COMP_H_
+
+#ifdef RTE_LIBRTE_COMPRESSDEV
+
+#include <rte_compressdev.h>
+#include <rte_compressdev_pmd.h>
+
+#include "qat_common.h"
+#include "icp_qat_hw.h"
+#include "icp_qat_fw_comp.h"
+#include "icp_qat_fw_la.h"
+
+/*
+ * This macro rounds up a number to a be a multiple of
+ * the alignment when the alignment is a power of 2
+ */
+#define ALIGN_POW2_ROUNDUP(num, align) \
+ (((num) + (align) - 1) & ~((align) - 1))
+#define QAT_64_BYTE_ALIGN_MASK (~0x3f)
+#define QAT_64_BYTE_ALIGN (64)
+#define QAT_NUM_BUFS_IN_IM_SGL 2
+/* Use correct Deflate terminology */
+#define QAT_COMP_REQUEST_FIXED_COMP_STATELESS QAT_COMP_REQUEST_STATIC_COMP_STATELESS
+
+
+struct array_of_ptrs {
+ phys_addr_t pointer[0];
+};
+
+struct qat_inter_sgl {
+ qat_sgl_hdr;
+ struct qat_flat_buf buffers[QAT_NUM_BUFS_IN_IM_SGL];
+} __rte_packed __rte_cache_aligned;
+
+struct qat_comp_sgl {
+ qat_sgl_hdr;
+ struct qat_flat_buf buffers[RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS];
+} __rte_packed __rte_cache_aligned;
+
+struct qat_comp_op_cookie {
+ struct qat_comp_sgl qat_sgl_src;
+ struct qat_comp_sgl qat_sgl_dst;
+ phys_addr_t qat_sgl_src_phys_addr;
+ phys_addr_t qat_sgl_dst_phys_addr;
+};
+
+struct qat_comp_xform {
+ struct icp_qat_fw_comp_req qat_comp_req_tmpl;
+ enum qat_comp_request qat_comp_request;
+ enum rte_comp_checksum_type checksum_type;
+};
+
+int
+qat_comp_build_request(void *in_op, uint8_t *out_msg, void *op_cookie,
+ enum qat_device_gen qat_dev_gen __rte_unused);
+
+int
+qat_comp_process_response(void **op, uint8_t *resp);
+
+
+int
+qat_comp_private_xform_create(struct rte_compressdev *dev,
+ const struct rte_comp_xform *xform,
+ void **private_xform);
+
+int
+qat_comp_private_xform_free(struct rte_compressdev *dev, void *private_xform);
+
+unsigned int
+qat_comp_xform_size(void);
+
+#endif
+#endif
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
new file mode 100644
index 0000000..6006e03
--- /dev/null
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -0,0 +1,479 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+
+#include <rte_bus_pci.h>
+#include <rte_common.h>
+#include <rte_dev.h>
+#include <rte_malloc.h>
+#include <rte_pci.h>
+
+#include "qat_logs.h"
+#include "qat_comp.h"
+#include "qat_comp_pmd.h"
+
+uint8_t compressdev_qat_driver_id;
+
+static const struct rte_compressdev_capabilities qat_comp_gen_capabilities[] = {
+ {/* COMPRESSION - deflate */
+ .algo = RTE_COMP_ALGO_DEFLATE,
+ .comp_feature_flags = RTE_COMP_FF_MBUF_SCATTER_GATHER |
+ RTE_COMP_FF_MULTI_PKT_CHECKSUM |
+ RTE_COMP_FF_CRC32_ADLER32_CHECKSUM,
+ .window_size = {.min = 15, .max = 15, .increment = 0} },
+ {RTE_COMP_ALGO_LIST_END, 0, {0, 0, 0} } };
+
+static void
+qat_comp_stats_get(struct rte_compressdev *dev,
+ struct rte_compressdev_stats *stats)
+{
+ struct qat_common_stats qat_stats = {0};
+ struct qat_comp_dev_private *qat_priv;
+
+ if (stats == NULL || dev == NULL) {
+ QAT_LOG(ERR, "invalid ptr: stats %p, dev %p", stats, dev);
+ return;
+ }
+ qat_priv = dev->data->dev_private;
+
+ qat_stats_get(qat_priv->qat_dev, &qat_stats, QAT_SERVICE_COMPRESSION);
+ stats->enqueued_count = qat_stats.enqueued_count;
+ stats->dequeued_count = qat_stats.dequeued_count;
+ stats->enqueue_err_count = qat_stats.enqueue_err_count;
+ stats->dequeue_err_count = qat_stats.dequeue_err_count;
+}
+
+static void
+qat_comp_stats_reset(struct rte_compressdev *dev)
+{
+ struct qat_comp_dev_private *qat_priv;
+
+ if (dev == NULL) {
+ QAT_LOG(ERR, "invalid compressdev ptr %p", dev);
+ return;
+ }
+ qat_priv = dev->data->dev_private;
+
+ qat_stats_reset(qat_priv->qat_dev, QAT_SERVICE_COMPRESSION);
+
+}
+
+static int
+qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)
+{
+ struct qat_comp_dev_private *qat_private = dev->data->dev_private;
+
+ QAT_LOG(DEBUG, "Release comp qp %u on device %d",
+ queue_pair_id, dev->data->dev_id);
+
+ qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][queue_pair_id]
+ = NULL;
+
+ return qat_qp_release((struct qat_qp **)
+ &(dev->data->queue_pairs[queue_pair_id]));
+}
+
+static int
+qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
+ uint32_t max_inflight_ops, int socket_id)
+{
+ struct qat_qp *qp;
+ int ret = 0;
+ uint32_t i;
+ struct qat_qp_config qat_qp_conf;
+
+ struct qat_qp **qp_addr =
+ (struct qat_qp **)&(dev->data->queue_pairs[qp_id]);
+ struct qat_comp_dev_private *qat_private = dev->data->dev_private;
+ const struct qat_qp_hw_data *comp_hw_qps =
+ qat_gen_config[qat_private->qat_dev->qat_dev_gen]
+ .qp_hw_data[QAT_SERVICE_COMPRESSION];
+ const struct qat_qp_hw_data *qp_hw_data = comp_hw_qps + qp_id;
+
+ /* If qp is already in use free ring memory and qp metadata. */
+ if (*qp_addr != NULL) {
+ ret = qat_comp_qp_release(dev, qp_id);
+ if (ret < 0)
+ return ret;
+ }
+ if (qp_id >= qat_qps_per_service(comp_hw_qps,
+ QAT_SERVICE_COMPRESSION)) {
+ QAT_LOG(ERR, "qp_id %u invalid for this device", qp_id);
+ return -EINVAL;
+ }
+
+ qat_qp_conf.hw = qp_hw_data;
+ qat_qp_conf.build_request = qat_comp_build_request;
+ qat_qp_conf.cookie_size = sizeof(struct qat_comp_op_cookie);
+ qat_qp_conf.nb_descriptors = max_inflight_ops;
+ qat_qp_conf.socket_id = socket_id;
+ qat_qp_conf.service_str = "comp";
+
+ ret = qat_qp_setup(qat_private->qat_dev, qp_addr, qp_id, &qat_qp_conf);
+ if (ret != 0)
+ return ret;
+
+ /* store a link to the qp in the qat_pci_device */
+ qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][qp_id]
+ = *qp_addr;
+
+ qp = (struct qat_qp *)*qp_addr;
+
+ for (i = 0; i < qp->nb_descriptors; i++) {
+
+ struct qat_comp_op_cookie *cookie =
+ qp->op_cookies[i];
+
+ cookie->qat_sgl_src_phys_addr =
+ rte_mempool_virt2iova(cookie) +
+ offsetof(struct qat_comp_op_cookie,
+ qat_sgl_src);
+
+ cookie->qat_sgl_dst_phys_addr =
+ rte_mempool_virt2iova(cookie) +
+ offsetof(struct qat_comp_op_cookie,
+ qat_sgl_dst);
+ }
+
+ return ret;
+}
+
+static const struct rte_memzone *
+qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev,
+ uint32_t buff_size)
+{
+ char inter_buff_mz_name[RTE_MEMZONE_NAMESIZE];
+ const struct rte_memzone *memzone;
+ uint8_t *mz_start = NULL;
+ phys_addr_t mz_start_phys = 0;
+ struct array_of_ptrs *array_of_pointers;
+ int size_of_ptr_array;
+ uint32_t full_size;
+ uint32_t offset_of_sgls, offset_of_flat_buffs = 0;
+ int i;
+ int num_im_sgls = qat_gen_config[comp_dev->qat_dev->qat_dev_gen].
+ comp_num_im_bufs_required;
+
+ QAT_LOG(DEBUG, "QAT COMP device %s needs %d sgls",
+ comp_dev->qat_dev->name, num_im_sgls);
+ snprintf(inter_buff_mz_name, RTE_MEMZONE_NAMESIZE,
+ "%s_inter_buff", comp_dev->qat_dev->name);
+ memzone = rte_memzone_lookup(inter_buff_mz_name);
+ if (memzone != NULL) {
+ QAT_LOG(DEBUG, "QAT COMP im buffer memzone created already");
+ return memzone;
+ }
+
+ /* Create a memzone to hold intermediate buffers and associated
+ * meta-data needed by the firmware. The memzone contains:
+ * - a list of num_im_sgls physical pointers to sgls
+ * - the num_im_sgl sgl structures, each pointing to 2 flat buffers
+ * - the flat buffers: num_im_sgl * 2
+ * where num_im_sgls depends on the hardware generation of the device
+ */
+
+ size_of_ptr_array = num_im_sgls * sizeof(phys_addr_t);
+ offset_of_sgls = (size_of_ptr_array + (~QAT_64_BYTE_ALIGN_MASK))
+ & QAT_64_BYTE_ALIGN_MASK;
+ offset_of_flat_buffs =
+ offset_of_sgls + num_im_sgls * sizeof(struct qat_inter_sgl);
+ full_size = offset_of_flat_buffs +
+ num_im_sgls * buff_size * QAT_NUM_BUFS_IN_IM_SGL;
+
+ memzone = rte_memzone_reserve_aligned(inter_buff_mz_name, full_size,
+ comp_dev->compressdev->data->socket_id,
+ RTE_MEMZONE_2MB, QAT_64_BYTE_ALIGN);
+ if (memzone == NULL) {
+ QAT_LOG(ERR, "Can't allocate intermediate buffers"
+ " for device %s", comp_dev->qat_dev->name);
+ return NULL;
+ }
+
+ mz_start = (uint8_t *)memzone->addr;
+ mz_start_phys = memzone->phys_addr;
+ QAT_LOG(DEBUG, "Memzone %s: addr = %p, phys = %lx, size required %d,"
+ "size created %ld",
+ inter_buff_mz_name, mz_start, mz_start_phys,
+ full_size, memzone->len);
+
+ array_of_pointers = (struct array_of_ptrs *)mz_start;
+ for (i = 0; i < num_im_sgls; i++) {
+ uint32_t curr_sgl_offset =
+ offset_of_sgls + i * sizeof(struct qat_inter_sgl);
+ struct qat_inter_sgl *sgl =
+ (struct qat_inter_sgl *)(mz_start + curr_sgl_offset);
+ array_of_pointers->pointer[i] = mz_start_phys + curr_sgl_offset;
+
+ sgl->num_bufs = QAT_NUM_BUFS_IN_IM_SGL;
+ sgl->num_mapped_bufs = 0;
+ sgl->resrvd = 0;
+ sgl->buffers[0].addr = mz_start_phys + offset_of_flat_buffs +
+ i * buff_size * QAT_NUM_BUFS_IN_IM_SGL;
+ sgl->buffers[1].addr = mz_start_phys + offset_of_flat_buffs +
+ buff_size * (QAT_NUM_BUFS_IN_IM_SGL * i + 1);
+ sgl->buffers[0].len = sgl->buffers[1].len = buff_size;
+ sgl->buffers[0].resrvd = sgl->buffers[1].resrvd = 0;
+
+ QAT_LOG(DEBUG, " : array_of_pointers->pointer[i]"
+ "= %lx", array_of_pointers->pointer[i]);
+ QAT_LOG(DEBUG, " : sgl[%i] = %p", i, sgl);
+ QAT_LOG(DEBUG, " : sgl->buffers[0].addr = %lx, len=%d",
+ sgl->buffers[0].addr, sgl->buffers[0].len);
+ QAT_LOG(DEBUG, " : sgl->buffers[1].addr = %lx, len=%d",
+ sgl->buffers[1].addr, sgl->buffers[1].len);
+ }
+ return memzone;
+}
+
+static struct rte_mempool *
+qat_comp_create_xform_pool(struct qat_comp_dev_private *comp_dev,
+ uint32_t num_elements)
+{
+ char xform_pool_name[RTE_MEMPOOL_NAMESIZE];
+ struct rte_mempool *mp;
+
+ snprintf(xform_pool_name, RTE_MEMPOOL_NAMESIZE,
+ "%s_xforms", comp_dev->qat_dev->name);
+
+ QAT_LOG(DEBUG, "xformpool: %s", xform_pool_name);
+ mp = rte_mempool_lookup(xform_pool_name);
+
+ if (mp != NULL) {
+ QAT_LOG(DEBUG, "xformpool already created");
+ if (mp->size != num_elements) {
+ QAT_LOG(DEBUG, "xformpool wrong size - delete it");
+ rte_mempool_free(mp);
+ mp = NULL;
+ comp_dev->xformpool = NULL;
+ }
+ }
+
+ if (mp == NULL)
+ mp = rte_mempool_create(xform_pool_name,
+ num_elements,
+ qat_comp_xform_size(), 0, 0,
+ NULL, NULL, NULL, NULL, rte_socket_id(),
+ 0);
+ if (mp == NULL) {
+ QAT_LOG(ERR, "Err creating mempool %s w %d elements of size %d",
+ xform_pool_name, num_elements, qat_comp_xform_size());
+ return NULL;
+ }
+
+ return mp;
+}
+
+static void
+_qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)
+{
+ /* Free intermediate buffers */
+ if (comp_dev->interm_buff_mz) {
+ rte_memzone_free(comp_dev->interm_buff_mz);
+ comp_dev->interm_buff_mz = NULL;
+ }
+ /* Free private_xform pool */
+ if (comp_dev->xformpool) {
+ /* Free internal mempool for private xforms */
+ rte_mempool_free(comp_dev->xformpool);
+ comp_dev->xformpool = NULL;
+ }
+}
+
+static int
+qat_comp_dev_config(struct rte_compressdev *dev,
+ struct rte_compressdev_config *config)
+{
+ struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
+ int ret = 0;
+
+ if (config->max_nb_streams != 0) {
+ QAT_LOG(ERR,
+ "QAT device does not support STATEFUL so max_nb_streams must be 0");
+ return -EINVAL;
+ }
+
+ if (RTE_PMD_QAT_COMP_IM_BUFFER_SIZE == 0) {
+ QAT_LOG(WARNING,
+ "RTE_PMD_QAT_COMP_IM_BUFFER_SIZE = 0 in config file, so"
+ " QAT device can't be used for Dynamic Deflate. "
+ "Did you really intend to do this?");
+ } else {
+ comp_dev->interm_buff_mz =
+ qat_comp_setup_inter_buffers(comp_dev,
+ RTE_PMD_QAT_COMP_IM_BUFFER_SIZE);
+ if (comp_dev->interm_buff_mz == NULL) {
+ ret = -ENOMEM;
+ goto error_out;
+ }
+ }
+
+ comp_dev->xformpool = qat_comp_create_xform_pool(comp_dev,
+ config->max_nb_priv_xforms);
+ if (comp_dev->xformpool == NULL) {
+
+ ret = -ENOMEM;
+ goto error_out;
+ }
+ return 0;
+
+error_out:
+ _qat_comp_dev_config_clear(comp_dev);
+ return ret;
+}
+
+static int
+qat_comp_dev_start(struct rte_compressdev *dev __rte_unused)
+{
+ return 0;
+}
+
+static void
+qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused)
+{
+
+}
+
+static int
+qat_comp_dev_close(struct rte_compressdev *dev)
+{
+ int i;
+ int ret = 0;
+ struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
+
+ for (i = 0; i < dev->data->nb_queue_pairs; i++) {
+ ret = qat_comp_qp_release(dev, i);
+ if (ret < 0)
+ return ret;
+ }
+
+ _qat_comp_dev_config_clear(comp_dev);
+
+ return ret;
+}
+
+static void
+qat_comp_dev_info_get(struct rte_compressdev *dev,
+ struct rte_compressdev_info *info)
+{
+ struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
+ const struct qat_qp_hw_data *comp_hw_qps =
+ qat_gen_config[comp_dev->qat_dev->qat_dev_gen]
+ .qp_hw_data[QAT_SERVICE_COMPRESSION];
+
+ if (info != NULL) {
+ info->max_nb_queue_pairs =
+ qat_qps_per_service(comp_hw_qps,
+ QAT_SERVICE_COMPRESSION);
+ info->feature_flags = dev->feature_flags;
+ info->capabilities = comp_dev->qat_dev_capabilities;
+ }
+}
+
+static uint16_t
+qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops)
+{
+ return qat_enqueue_op_burst(qp, (void **)ops, nb_ops);
+}
+
+static uint16_t
+qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops)
+{
+ return qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
+}
+
+static struct rte_compressdev_ops compress_qat_ops = {
+
+ /* Device related operations */
+ .dev_configure = qat_comp_dev_config,
+ .dev_start = qat_comp_dev_start,
+ .dev_stop = qat_comp_dev_stop,
+ .dev_close = qat_comp_dev_close,
+ .dev_infos_get = qat_comp_dev_info_get,
+
+ .stats_get = qat_comp_stats_get,
+ .stats_reset = qat_comp_stats_reset,
+ .queue_pair_setup = qat_comp_qp_setup,
+ .queue_pair_release = qat_comp_qp_release,
+
+ /* Compression related operations */
+ .private_xform_create = qat_comp_private_xform_create,
+ .private_xform_free = qat_comp_private_xform_free
+};
+
+int
+qat_comp_dev_create(struct qat_pci_device *qat_pci_dev)
+{
+ struct rte_compressdev_pmd_init_params init_params = {
+ .name = "",
+ .socket_id = qat_pci_dev->pci_dev->device.numa_node,
+ };
+ char name[RTE_COMPRESSDEV_NAME_MAX_LEN];
+ struct rte_compressdev *compressdev;
+ struct qat_comp_dev_private *comp_dev;
+
+ snprintf(name, RTE_COMPRESSDEV_NAME_MAX_LEN, "%s_%s",
+ qat_pci_dev->name, "comp");
+ QAT_LOG(DEBUG, "Creating QAT COMP device %s", name);
+
+ compressdev = rte_compressdev_pmd_create(name,
+ &qat_pci_dev->pci_dev->device,
+ sizeof(struct qat_comp_dev_private),
+ &init_params);
+
+ if (compressdev == NULL)
+ return -ENODEV;
+
+ compressdev->driver_id = compressdev_qat_driver_id;
+ compressdev->dev_ops = &compress_qat_ops;
+
+ compressdev->enqueue_burst = qat_comp_pmd_enqueue_op_burst;
+ compressdev->dequeue_burst = qat_comp_pmd_dequeue_op_burst;
+
+ compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
+
+ comp_dev = compressdev->data->dev_private;
+ comp_dev->qat_dev = qat_pci_dev;
+ comp_dev->compressdev = compressdev;
+ qat_pci_dev->comp_dev = comp_dev;
+
+ switch (qat_pci_dev->qat_dev_gen) {
+ case QAT_GEN1:
+ case QAT_GEN2:
+ comp_dev->qat_dev_capabilities = qat_comp_gen_capabilities;
+ break;
+ default:
+ comp_dev->qat_dev_capabilities = qat_comp_gen_capabilities;
+ QAT_LOG(DEBUG,
+ "QAT gen %d capabilities unknown, default to GEN1",
+ qat_pci_dev->qat_dev_gen);
+ break;
+ }
+
+ QAT_LOG(DEBUG,
+ "Created QAT COMP device %s as compressdev instance %d",
+ name, compressdev->data->dev_id);
+ return 0;
+}
+
+int
+qat_comp_dev_destroy(struct qat_pci_device *qat_pci_dev)
+{
+ struct qat_comp_dev_private *comp_dev;
+
+ if (qat_pci_dev == NULL)
+ return -ENODEV;
+
+ comp_dev = qat_pci_dev->comp_dev;
+ if (comp_dev == NULL)
+ return 0;
+
+ /* clean up any resources used by the device */
+ qat_comp_dev_close(comp_dev->compressdev);
+
+ rte_compressdev_pmd_destroy(comp_dev->compressdev);
+ qat_pci_dev->comp_dev = NULL;
+
+ return 0;
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
new file mode 100644
index 0000000..11ea467
--- /dev/null
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+
+#ifndef _QAT_COMP_PMD_H_
+#define _QAT_COMP_PMD_H_
+
+#ifdef RTE_LIBRTE_COMPRESSDEV
+
+#include <rte_compressdev.h>
+#include <rte_compressdev_pmd.h>
+
+#include "qat_device.h"
+
+/**< Intel(R) QAT Compression PMD device name */
+#define COMPRESSDEV_NAME_QAT_PMD comp_qat
+
+/** private data structure for a QAT compression device.
+ * This QAT device is a device offering only a compression service,
+ * there can be one of these on each qat_pci_device (VF).
+ */
+struct qat_comp_dev_private {
+ struct qat_pci_device *qat_dev;
+ /**< The qat pci device hosting the service */
+ struct rte_compressdev *compressdev;
+ /**< The pointer to this compression device structure */
+ const struct rte_compressdev_capabilities *qat_dev_capabilities;
+ /* QAT device compression capabilities */
+ const struct rte_memzone *interm_buff_mz;
+ struct rte_mempool *xformpool;
+};
+
+int
+qat_comp_dev_create(struct qat_pci_device *qat_pci_dev);
+
+int
+qat_comp_dev_destroy(struct qat_pci_device *qat_pci_dev);
+
+#endif
+#endif /* _QAT_COMP_PMD_H_ */
diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c
index 17d63eb..3e3c3ac 100644
--- a/drivers/crypto/qat/qat_sym.c
+++ b/drivers/crypto/qat/qat_sym.c
@@ -495,8 +495,9 @@
ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
QAT_COMN_PTR_TYPE_SGL);
ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
- &cookie->qat_sgl_src,
- qat_req->comn_mid.src_length);
+ &cookie->qat_sgl_src,
+ qat_req->comn_mid.src_length,
+ QAT_SYM_SGL_MAX_NUMBER);
if (unlikely(ret)) {
QAT_DP_LOG(ERR, "QAT PMD Cannot fill sgl array");
@@ -509,9 +510,10 @@
cookie->qat_sgl_src_phys_addr;
else {
ret = qat_sgl_fill_array(op->sym->m_dst,
- dst_buf_start,
- &cookie->qat_sgl_dst,
- qat_req->comn_mid.dst_length);
+ dst_buf_start,
+ &cookie->qat_sgl_dst,
+ qat_req->comn_mid.dst_length,
+ QAT_SYM_SGL_MAX_NUMBER);
if (unlikely(ret)) {
QAT_DP_LOG(ERR, "QAT PMD can't fill sgl array");
diff --git a/drivers/crypto/qat/qat_sym.h b/drivers/crypto/qat/qat_sym.h
index 3c8ec5b..53c3275 100644
--- a/drivers/crypto/qat/qat_sym.h
+++ b/drivers/crypto/qat/qat_sym.h
@@ -22,11 +22,21 @@
*/
#define BPI_MAX_ENCR_IV_LEN ICP_QAT_HW_AES_BLK_SZ
+/*
+ * Maximum number of SGL entries
+ */
+#define QAT_SYM_SGL_MAX_NUMBER 16
+
struct qat_sym_session;
+struct qat_sym_sgl {
+ qat_sgl_hdr;
+ struct qat_flat_buf buffers[QAT_SYM_SGL_MAX_NUMBER];
+} __rte_packed __rte_cache_aligned;
+
struct qat_sym_op_cookie {
- struct qat_sgl qat_sgl_src;
- struct qat_sgl qat_sgl_dst;
+ struct qat_sym_sgl qat_sgl_src;
+ struct qat_sym_sgl qat_sgl_dst;
phys_addr_t qat_sgl_src_phys_addr;
phys_addr_t qat_sgl_dst_phys_addr;
};
--
1.7.0.7
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v2 00/16] compress/qat: add compression PMD
2018-05-23 18:40 [dpdk-dev] [PATCH] compress/qat: add compression PMD Fiona Trahe
@ 2018-07-05 16:05 ` Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 " Fiona Trahe
` (16 more replies)
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 01/16] common/qat: updated firmware headers Fiona Trahe
` (15 subsequent siblings)
16 siblings, 17 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 16:05 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Create compression PMD for Intel QuickAssist devices
Currently only the C62x and c3xxx devices are supported.
The qat comp PMD supports
- stateless compression and
decompression using the Deflate algorithm with Fixed Huffman
encoding. Dynamic huffman encoding is not supported, it
will be added in a later patch.
- checksum generation: Adler32, CRC32 and combined.
The compression service is hosted on a QuickAssist VF PCI
device, which is managed by code in the
drivers/common/qat directory.
This patch is dependent on the cryptodev API patch re Huffman Encoding capability
https://patches.dpdk.org/patch/42286/
v2 changes
- Added check for correct firmware
- Split patchset
- Added documentation
- removed support for scatter-gather-lists and related config flag
- Removed support for Dynamic huffman encoding and related IM buffer config flag
- Removed support for DH895xcc device
Fiona Trahe (16):
common/qat: updated firmware headers
compress/qat: add makefiles for PMD
compress/qat: add meson build
compress/qat: add xform processing
compress/qat: create fw request and process response
compress/qat: check that correct firmware is in use
compress/qat: add stats functions
compress/qat: setup queue-pairs for compression service
compress/qat: add fns to configure and clear device
compress/qat: add fn to return device info
compress/qat: add enqueue/dequeue functions
compress/qat: add device start and stop fns
compress/qat: create and populate the ops structure
compress/qat: add fns to create and destroy the PMD
compress/qat: prevent device usage if incorrect firmware
docs/qat: refactor docs adding compression guide
MAINTAINERS | 4 +
config/common_base | 5 +-
doc/guides/compressdevs/features/qat.ini | 22 ++
doc/guides/compressdevs/index.rst | 1 +
doc/guides/compressdevs/qat_comp.rst | 49 +++
doc/guides/cryptodevs/qat.rst | 183 ++++++----
doc/guides/rel_notes/release_18_08.rst | 5 +
drivers/common/qat/Makefile | 48 ++-
drivers/common/qat/qat_adf/icp_qat_fw.h | 69 +++-
drivers/common/qat/qat_adf/icp_qat_fw_comp.h | 482 +++++++++++++++++++++++++++
drivers/common/qat/qat_adf/icp_qat_hw.h | 130 +++++++-
drivers/common/qat/qat_device.h | 4 +
drivers/common/qat/qat_qp.c | 11 +-
drivers/common/qat/qat_qp.h | 5 +
drivers/compress/meson.build | 2 +-
drivers/compress/qat/meson.build | 18 +
drivers/compress/qat/qat_comp.c | 359 ++++++++++++++++++++
drivers/compress/qat/qat_comp.h | 56 ++++
drivers/compress/qat/qat_comp_pmd.c | 405 ++++++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 39 +++
drivers/compress/qat/rte_pmd_qat_version.map | 3 +
drivers/crypto/qat/meson.build | 10 +-
drivers/crypto/qat/rte_pmd_qat_version.map | 3 -
test/test/test_cryptodev.c | 6 +-
24 files changed, 1804 insertions(+), 115 deletions(-)
create mode 100644 doc/guides/compressdevs/features/qat.ini
create mode 100644 doc/guides/compressdevs/qat_comp.rst
create mode 100644 drivers/common/qat/qat_adf/icp_qat_fw_comp.h
create mode 100644 drivers/compress/qat/meson.build
create mode 100644 drivers/compress/qat/qat_comp.c
create mode 100644 drivers/compress/qat/qat_comp.h
create mode 100644 drivers/compress/qat/qat_comp_pmd.c
create mode 100644 drivers/compress/qat/qat_comp_pmd.h
create mode 100644 drivers/compress/qat/rte_pmd_qat_version.map
delete mode 100644 drivers/crypto/qat/rte_pmd_qat_version.map
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v2 01/16] common/qat: updated firmware headers
2018-05-23 18:40 [dpdk-dev] [PATCH] compress/qat: add compression PMD Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 00/16] " Fiona Trahe
@ 2018-07-05 16:05 ` Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 02/16] compress/qat: add makefiles for PMD Fiona Trahe
` (14 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 16:05 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Updated to latest firmware headers files for QuickAssist devices.
Includes updates for symmetric crypto, PKE and Compression services.
Change-Id: Ia8890f78361852664d555db1a26ecc03ef2c39d2
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
drivers/common/qat/qat_adf/icp_qat_fw.h | 69 +++-
drivers/common/qat/qat_adf/icp_qat_fw_comp.h | 482 +++++++++++++++++++++++++++
drivers/common/qat/qat_adf/icp_qat_hw.h | 130 +++++++-
3 files changed, 654 insertions(+), 27 deletions(-)
create mode 100644 drivers/common/qat/qat_adf/icp_qat_fw_comp.h
diff --git a/drivers/common/qat/qat_adf/icp_qat_fw.h b/drivers/common/qat/qat_adf/icp_qat_fw.h
index ae39b7f..8f7cb37 100644
--- a/drivers/common/qat/qat_adf/icp_qat_fw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_fw.h
@@ -117,6 +117,10 @@ struct icp_qat_fw_comn_resp {
#define ICP_QAT_FW_COMN_VALID_FLAG_BITPOS 7
#define ICP_QAT_FW_COMN_VALID_FLAG_MASK 0x1
#define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK 0x7F
+#define ICP_QAT_FW_COMN_CNV_FLAG_BITPOS 6
+#define ICP_QAT_FW_COMN_CNV_FLAG_MASK 0x1
+#define ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS 5
+#define ICP_QAT_FW_COMN_CNVNR_FLAG_MASK 0x1
#define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \
icp_qat_fw_comn_req_hdr_t.service_type
@@ -133,6 +137,16 @@ struct icp_qat_fw_comn_resp {
#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_GET(hdr_t) \
ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_t.hdr_flags)
+#define ICP_QAT_FW_COMN_HDR_CNVNR_FLAG_GET(hdr_flags) \
+ QAT_FIELD_GET(hdr_flags, \
+ ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS, \
+ ICP_QAT_FW_COMN_CNVNR_FLAG_MASK)
+
+#define ICP_QAT_FW_COMN_HDR_CNV_FLAG_GET(hdr_flags) \
+ QAT_FIELD_GET(hdr_flags, \
+ ICP_QAT_FW_COMN_CNV_FLAG_BITPOS, \
+ ICP_QAT_FW_COMN_CNV_FLAG_MASK)
+
#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_SET(hdr_t, val) \
ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val)
@@ -204,29 +218,44 @@ struct icp_qat_fw_comn_resp {
& ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)); }
+#define ICP_QAT_FW_COMN_NEXT_ID_SET_2(next_curr_id, val) \
+ do { \
+ (next_curr_id) = \
+ (((next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK) | \
+ (((val) << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) & \
+ ICP_QAT_FW_COMN_NEXT_ID_MASK)) \
+ } while (0)
+
+#define ICP_QAT_FW_COMN_CURR_ID_SET_2(next_curr_id, val) \
+ do { \
+ (next_curr_id) = \
+ (((next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
+ ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) \
+ } while (0)
+
#define QAT_COMN_RESP_CRYPTO_STATUS_BITPOS 7
#define QAT_COMN_RESP_CRYPTO_STATUS_MASK 0x1
+#define QAT_COMN_RESP_PKE_STATUS_BITPOS 6
+#define QAT_COMN_RESP_PKE_STATUS_MASK 0x1
#define QAT_COMN_RESP_CMP_STATUS_BITPOS 5
#define QAT_COMN_RESP_CMP_STATUS_MASK 0x1
#define QAT_COMN_RESP_XLAT_STATUS_BITPOS 4
#define QAT_COMN_RESP_XLAT_STATUS_MASK 0x1
#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS 3
#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1
-
-#define ICP_QAT_FW_COMN_RESP_STATUS_BUILD(crypto, comp, xlat, eolb) \
- ((((crypto) & QAT_COMN_RESP_CRYPTO_STATUS_MASK) << \
- QAT_COMN_RESP_CRYPTO_STATUS_BITPOS) | \
- (((comp) & QAT_COMN_RESP_CMP_STATUS_MASK) << \
- QAT_COMN_RESP_CMP_STATUS_BITPOS) | \
- (((xlat) & QAT_COMN_RESP_XLAT_STATUS_MASK) << \
- QAT_COMN_RESP_XLAT_STATUS_BITPOS) | \
- (((eolb) & QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK) << \
- QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS))
+#define QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS 2
+#define QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK 0x1
+#define QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS 0
+#define QAT_COMN_RESP_XLT_WA_APPLIED_MASK 0x1
#define ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(status) \
QAT_FIELD_GET(status, QAT_COMN_RESP_CRYPTO_STATUS_BITPOS, \
QAT_COMN_RESP_CRYPTO_STATUS_MASK)
+#define ICP_QAT_FW_COMN_RESP_PKE_STAT_GET(status) \
+ QAT_FIELD_GET(status, QAT_COMN_RESP_PKE_STATUS_BITPOS, \
+ QAT_COMN_RESP_PKE_STATUS_MASK)
+
#define ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(status) \
QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_STATUS_BITPOS, \
QAT_COMN_RESP_CMP_STATUS_MASK)
@@ -235,10 +264,18 @@ struct icp_qat_fw_comn_resp {
QAT_FIELD_GET(status, QAT_COMN_RESP_XLAT_STATUS_BITPOS, \
QAT_COMN_RESP_XLAT_STATUS_MASK)
+#define ICP_QAT_FW_COMN_RESP_XLT_WA_APPLIED_GET(status) \
+ QAT_FIELD_GET(status, QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS, \
+ QAT_COMN_RESP_XLT_WA_APPLIED_MASK)
+
#define ICP_QAT_FW_COMN_RESP_CMP_END_OF_LAST_BLK_FLAG_GET(status) \
QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS, \
QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK)
+#define ICP_QAT_FW_COMN_RESP_UNSUPPORTED_REQUEST_STAT_GET(status) \
+ QAT_FIELD_GET(status, QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS, \
+ QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK)
+
#define ICP_QAT_FW_COMN_STATUS_FLAG_OK 0
#define ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 1
#define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0
@@ -257,8 +294,16 @@ struct icp_qat_fw_comn_resp {
#define ERR_CODE_OVERFLOW_ERROR -11
#define ERR_CODE_SOFT_ERROR -12
#define ERR_CODE_FATAL_ERROR -13
-#define ERR_CODE_SSM_ERROR -14
-#define ERR_CODE_ENDPOINT_ERROR -15
+#define ERR_CODE_COMP_OUTPUT_CORRUPTION -14
+#define ERR_CODE_HW_INCOMPLETE_FILE -15
+#define ERR_CODE_SSM_ERROR -16
+#define ERR_CODE_ENDPOINT_ERROR -17
+#define ERR_CODE_CNV_ERROR -18
+#define ERR_CODE_EMPTY_DYM_BLOCK -19
+#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_HANDLE -20
+#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_HMAC_FAILED -21
+#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_WRAPPING_ALGO -22
+#define ERR_CODE_KPT_DRNG_SEED_NOT_LOAD -23
enum icp_qat_fw_slice {
ICP_QAT_FW_SLICE_NULL = 0,
diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_comp.h b/drivers/common/qat/qat_adf/icp_qat_fw_comp.h
new file mode 100644
index 0000000..8138177
--- /dev/null
+++ b/drivers/common/qat/qat_adf/icp_qat_fw_comp.h
@@ -0,0 +1,482 @@
+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+#ifndef _ICP_QAT_FW_COMP_H_
+#define _ICP_QAT_FW_COMP_H_
+
+#include "icp_qat_fw.h"
+
+enum icp_qat_fw_comp_cmd_id {
+ ICP_QAT_FW_COMP_CMD_STATIC = 0,
+ /*!< Static Compress Request */
+
+ ICP_QAT_FW_COMP_CMD_DYNAMIC = 1,
+ /*!< Dynamic Compress Request */
+
+ ICP_QAT_FW_COMP_CMD_DECOMPRESS = 2,
+ /*!< Decompress Request */
+
+ ICP_QAT_FW_COMP_CMD_DELIMITER
+ /**< Delimiter type */
+};
+
+/**< Flag usage */
+
+#define ICP_QAT_FW_COMP_STATELESS_SESSION 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that session is stateless
+ */
+
+#define ICP_QAT_FW_COMP_STATEFUL_SESSION 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that session is stateful
+ */
+
+#define ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that autoselectbest is NOT used
+ */
+
+#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that autoselectbest is used
+ */
+
+#define ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is NOT used
+ */
+
+#define ICP_QAT_FW_COMP_ENH_AUTO_SELECT_BEST 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is used
+ */
+
+#define ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is NOT used
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is used
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_USED_AS_INTMD_BUF 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing secure RAM from being used as
+ * an intermediate buffer is DISABLED.
+ */
+
+#define ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing secure RAM from being used as
+ * an intermediate buffer is ENABLED.
+ */
+
+/**< Flag mask & bit position */
+
+#define ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS 2
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the session type
+ */
+
+#define ICP_QAT_FW_COMP_SESSION_TYPE_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask used to determine the session type
+ */
+
+#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS 3
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for auto select best
+ */
+
+#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for auto select best
+ */
+
+#define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS 4
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for enhanced auto select best
+ */
+
+#define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for enhanced auto select best
+ */
+
+#define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS 5
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for disabling type zero header write back
+ * when Enhanced autoselect best is enabled. If set firmware does
+ * not return type0 store block header, only copies src to dest.
+ * (if best output is Type0)
+ */
+
+#define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for auto select best
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS 7
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for flag used to disable secure ram from
+ * being used as an intermediate buffer.
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for disable secure ram for use as an intermediate
+ * buffer.
+ */
+
+#define ICP_QAT_FW_COMP_FLAGS_BUILD(sesstype, autoselect, enhanced_asb, \
+ ret_uncomp, secure_ram) \
+ ((((sesstype)&ICP_QAT_FW_COMP_SESSION_TYPE_MASK) \
+ << ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS) | \
+ (((autoselect)&ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK) \
+ << ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS) | \
+ (((enhanced_asb)&ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK) \
+ << ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS) | \
+ (((ret_uncomp)&ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK) \
+ << ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS) | \
+ (((secure_ram)&ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK) \
+ << ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS))
+
+union icp_qat_fw_comp_req_hdr_cd_pars {
+ /**< LWs 2-5 */
+ struct {
+ uint64_t content_desc_addr;
+ /**< Address of the content descriptor */
+
+ uint16_t content_desc_resrvd1;
+ /**< Content descriptor reserved field */
+
+ uint8_t content_desc_params_sz;
+ /**< Size of the content descriptor parameters in quad words.
+ * These parameters describe the session setup configuration
+ * info for the slices that this request relies upon i.e.
+ * the configuration word and cipher key needed by the cipher
+ * slice if there is a request for cipher processing.
+ */
+
+ uint8_t content_desc_hdr_resrvd2;
+ /**< Content descriptor reserved field */
+
+ uint32_t content_desc_resrvd3;
+ /**< Content descriptor reserved field */
+ } s;
+
+ struct {
+ uint32_t comp_slice_cfg_word[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /* Compression Slice Config Word */
+
+ uint32_t content_desc_resrvd4;
+ /**< Content descriptor reserved field */
+
+ } sl;
+
+};
+
+struct icp_qat_fw_comp_req_params {
+ /**< LW 14 */
+ uint32_t comp_len;
+ /**< Size of input to process in bytes Note: Only EOP requests can be
+ * odd for decompression. IA must set LSB to zero for odd sized
+ * intermediate inputs
+ */
+
+ /**< LW 15 */
+ uint32_t out_buffer_sz;
+ /**< Size of output buffer in bytes */
+
+ /**< LW 16 */
+ uint32_t initial_crc32;
+ /**< CRC of previously processed bytes */
+
+ /**< LW 17 */
+ uint32_t initial_adler;
+ /**< Adler of previously processed bytes */
+
+ /**< LW 18 */
+ uint32_t req_par_flags;
+
+ /**< LW 19 */
+ uint32_t rsrvd;
+};
+
+#define ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(sop, eop, bfinal, cnv, cnvnr) \
+ ((((sop)&ICP_QAT_FW_COMP_SOP_MASK) << ICP_QAT_FW_COMP_SOP_BITPOS) | \
+ (((eop)&ICP_QAT_FW_COMP_EOP_MASK) << ICP_QAT_FW_COMP_EOP_BITPOS) | \
+ (((bfinal)&ICP_QAT_FW_COMP_BFINAL_MASK) \
+ << ICP_QAT_FW_COMP_BFINAL_BITPOS) | \
+ ((cnv & ICP_QAT_FW_COMP_CNV_MASK) << ICP_QAT_FW_COMP_CNV_BITPOS) | \
+ ((cnvnr & ICP_QAT_FW_COMP_CNV_RECOVERY_MASK) \
+ << ICP_QAT_FW_COMP_CNV_RECOVERY_BITPOS))
+
+#define ICP_QAT_FW_COMP_NOT_SOP 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request is NOT Start of Packet
+ */
+
+#define ICP_QAT_FW_COMP_SOP 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request IS Start of Packet
+ */
+
+#define ICP_QAT_FW_COMP_NOT_EOP 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request is NOT Start of Packet
+ */
+
+#define ICP_QAT_FW_COMP_EOP 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request IS End of Packet
+ */
+
+#define ICP_QAT_FW_COMP_NOT_BFINAL 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing to indicate firmware this is not the last block
+ */
+
+#define ICP_QAT_FW_COMP_BFINAL 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing to indicate firmware this is the last block
+ */
+
+#define ICP_QAT_FW_COMP_NO_CNV 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that NO cnv check is to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_CNV 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that a cnv check IS to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_NO_CNV_RECOVERY 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that NO cnv recovery is to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_CNV_RECOVERY 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that a cnv recovery is to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_SOP_BITPOS 0
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for SOP
+ */
+
+#define ICP_QAT_FW_COMP_SOP_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask used to determine SOP
+ */
+
+#define ICP_QAT_FW_COMP_EOP_BITPOS 1
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for EOP
+ */
+
+#define ICP_QAT_FW_COMP_EOP_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask used to determine EOP
+ */
+
+#define ICP_QAT_FW_COMP_BFINAL_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for the bfinal bit
+ */
+
+#define ICP_QAT_FW_COMP_BFINAL_BITPOS 6
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the bfinal bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for the CNV bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_BITPOS 16
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the CNV bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_RECOVERY_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for the CNV Recovery bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_RECOVERY_BITPOS 17
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the CNV Recovery bit
+ */
+
+struct icp_qat_fw_xlt_req_params {
+ /**< LWs 20-21 */
+ uint64_t inter_buff_ptr;
+ /**< This field specifies the physical address of an intermediate
+ * buffer SGL array. The array contains a pair of 64-bit
+ * intermediate buffer pointers to SGL buffer descriptors, one pair
+ * per CPM. Please refer to the CPM1.6 Firmware Interface HLD
+ * specification for more details.
+ */
+};
+
+
+struct icp_qat_fw_comp_cd_hdr {
+ /**< LW 24 */
+ uint16_t ram_bank_flags;
+ /**< Flags to show which ram banks to access */
+
+ uint8_t comp_cfg_offset;
+ /**< Quad word offset from the content descriptor parameters address
+ * to the parameters for the compression processing
+ */
+
+ uint8_t next_curr_id;
+ /**< This field combines the next and current id (each four bits) -
+ * the next id is the most significant nibble.
+ * Next Id: Set to the next slice to pass the compressed data through.
+ * Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through
+ * anymore slices after compression
+ * Current Id: Initialised with the compression slice type
+ */
+
+ /**< LW 25 */
+ uint32_t resrvd;
+ /**< LWs 26-27 */
+
+ uint64_t comp_state_addr;
+ /**< Pointer to compression state */
+
+ /**< LWs 28-29 */
+ uint64_t ram_banks_addr;
+ /**< Pointer to banks */
+
+};
+
+
+struct icp_qat_fw_xlt_cd_hdr {
+ /**< LW 30 */
+ uint16_t resrvd1;
+ /**< Reserved field and assumed set to 0 */
+
+ uint8_t resrvd2;
+ /**< Reserved field and assumed set to 0 */
+
+ uint8_t next_curr_id;
+ /**< This field combines the next and current id (each four bits) -
+ * the next id is the most significant nibble.
+ * Next Id: Set to the next slice to pass the translated data through.
+ * Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through
+ * any more slices after compression
+ * Current Id: Initialised with the translation slice type
+ */
+
+ /**< LW 31 */
+ uint32_t resrvd3;
+ /**< Reserved and should be set to zero, needed for quadword
+ * alignment
+ */
+};
+
+struct icp_qat_fw_comp_req {
+ /**< LWs 0-1 */
+ struct icp_qat_fw_comn_req_hdr comn_hdr;
+ /**< Common request header - for Service Command Id,
+ * use service-specific Compression Command Id.
+ * Service Specific Flags - use Compression Command Flags
+ */
+
+ /**< LWs 2-5 */
+ union icp_qat_fw_comp_req_hdr_cd_pars cd_pars;
+ /**< Compression service-specific content descriptor field which points
+ * either to a content descriptor parameter block or contains the
+ * compression slice config word.
+ */
+
+ /**< LWs 6-13 */
+ struct icp_qat_fw_comn_req_mid comn_mid;
+ /**< Common request middle section */
+
+ /**< LWs 14-19 */
+ struct icp_qat_fw_comp_req_params comp_pars;
+ /**< Compression request Parameters block */
+
+ /**< LWs 20-21 */
+ union {
+ struct icp_qat_fw_xlt_req_params xlt_pars;
+ /**< Translation request Parameters block */
+ uint32_t resrvd1[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /**< Reserved if not used for translation */
+
+ } u1;
+
+ /**< LWs 22-23 */
+ union {
+ uint32_t resrvd2[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /**< Reserved - not used if Batch and Pack is disabled.*/
+
+ uint64_t bnp_res_table_addr;
+ /**< A generic pointer to the unbounded list of
+ * icp_qat_fw_resp_comp_pars members. This pointer is only
+ * used when the Batch and Pack is enabled.
+ */
+ } u3;
+
+ /**< LWs 24-29 */
+ struct icp_qat_fw_comp_cd_hdr comp_cd_ctrl;
+ /**< Compression request content descriptor control block header */
+
+ /**< LWs 30-31 */
+ union {
+ struct icp_qat_fw_xlt_cd_hdr xlt_cd_ctrl;
+ /**< Translation request content descriptor
+ * control block header
+ */
+
+ uint32_t resrvd3[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /**< Reserved if not used for translation */
+ } u2;
+};
+
+struct icp_qat_fw_resp_comp_pars {
+ /**< LW 4 */
+ uint32_t input_byte_counter;
+ /**< Input byte counter */
+
+ /**< LW 5 */
+ uint32_t output_byte_counter;
+ /**< Output byte counter */
+
+ /**< LW 6 & 7*/
+ union {
+ uint64_t curr_chksum;
+ struct {
+ /**< LW 6 */
+ uint32_t curr_crc32;
+ /**< LW 7 */
+ uint32_t curr_adler_32;
+ };
+ };
+};
+
+struct icp_qat_fw_comp_resp {
+ /**< LWs 0-1 */
+ struct icp_qat_fw_comn_resp_hdr comn_resp;
+ /**< Common interface response format see icp_qat_fw.h */
+
+ /**< LWs 2-3 */
+ uint64_t opaque_data;
+ /**< Opaque data passed from the request to the response message */
+
+ /**< LWs 4-7 */
+ struct icp_qat_fw_resp_comp_pars comp_resp_pars;
+ /**< Common response params (checksums and byte counts) */
+};
+
+#endif
diff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h b/drivers/common/qat/qat_adf/icp_qat_hw.h
index 56e3cf7..e7961db 100644
--- a/drivers/common/qat/qat_adf/icp_qat_hw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_hw.h
@@ -72,19 +72,44 @@ struct icp_qat_hw_auth_config {
#define QAT_AUTH_ALGO_MASK 0xF
#define QAT_AUTH_CMP_BITPOS 8
#define QAT_AUTH_CMP_MASK 0x7F
-#define QAT_AUTH_SHA3_PADDING_BITPOS 16
-#define QAT_AUTH_SHA3_PADDING_MASK 0x1
+#define QAT_AUTH_SHA3_PADDING_DISABLE_BITPOS 16
+#define QAT_AUTH_SHA3_PADDING_DISABLE_MASK 0x1
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_BITPOS 17
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_MASK 0x1
#define QAT_AUTH_ALGO_SHA3_BITPOS 22
#define QAT_AUTH_ALGO_SHA3_MASK 0x3
-#define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \
- (((mode & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \
- ((algo & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \
- (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) << \
- QAT_AUTH_ALGO_SHA3_BITPOS) | \
- (((((algo == ICP_QAT_HW_AUTH_ALGO_SHA3_256) || \
- (algo == ICP_QAT_HW_AUTH_ALGO_SHA3_512)) ? 1 : 0) \
- & QAT_AUTH_SHA3_PADDING_MASK) << QAT_AUTH_SHA3_PADDING_BITPOS) | \
- ((cmp_len & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
+#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_BITPOS 16
+#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_MASK 0xF
+#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_BITPOS 24
+#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_MASK 0xFF
+#define QAT_AUTH_SHA3_HW_PADDING_ENABLE 0
+#define QAT_AUTH_SHA3_HW_PADDING_DISABLE 1
+#define QAT_AUTH_SHA3_PADDING_DISABLE_USE_DEFAULT 0
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_USE_DEFAULT 0
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_PROGRAMMABLE 1
+#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_RESERVED 0
+#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_RESERVED 0
+
+#define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \
+ ((((mode) & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \
+ (((algo) & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \
+ (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) \
+ << QAT_AUTH_ALGO_SHA3_BITPOS) | \
+ (((QAT_AUTH_SHA3_PADDING_DISABLE_USE_DEFAULT) & \
+ QAT_AUTH_SHA3_PADDING_DISABLE_MASK) \
+ << QAT_AUTH_SHA3_PADDING_DISABLE_BITPOS) | \
+ (((QAT_AUTH_SHA3_PADDING_OVERRIDE_USE_DEFAULT) & \
+ QAT_AUTH_SHA3_PADDING_OVERRIDE_MASK) \
+ << QAT_AUTH_SHA3_PADDING_OVERRIDE_BITPOS) | \
+ (((cmp_len) & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
+
+#define ICP_QAT_HW_AUTH_CONFIG_BUILD_UPPER \
+ ((((QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_RESERVED) & \
+ QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_MASK) \
+ << QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_BITPOS) | \
+ (((QAT_AUTH_SHA3_PROG_PADDING_PREFIX_RESERVED) & \
+ QAT_AUTH_SHA3_PROG_PADDING_PREFIX_MASK) \
+ << QAT_AUTH_SHA3_PROG_PADDING_PREFIX_BITPOS))
struct icp_qat_hw_auth_counter {
uint32_t counter;
@@ -107,13 +132,13 @@ struct icp_qat_hw_auth_setup {
#define ICP_QAT_HW_MD5_STATE1_SZ 16
#define ICP_QAT_HW_SHA1_STATE1_SZ 20
#define ICP_QAT_HW_SHA224_STATE1_SZ 32
+#define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
#define ICP_QAT_HW_SHA256_STATE1_SZ 32
#define ICP_QAT_HW_SHA3_256_STATE1_SZ 32
#define ICP_QAT_HW_SHA384_STATE1_SZ 64
+#define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
#define ICP_QAT_HW_SHA512_STATE1_SZ 64
#define ICP_QAT_HW_SHA3_512_STATE1_SZ 64
-#define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
-#define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
#define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ 16
#define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ 16
#define ICP_QAT_HW_AES_F9_STATE1_SZ 32
@@ -121,17 +146,18 @@ struct icp_qat_hw_auth_setup {
#define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16
#define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8
#define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8
+
#define ICP_QAT_HW_NULL_STATE2_SZ 32
#define ICP_QAT_HW_MD5_STATE2_SZ 16
#define ICP_QAT_HW_SHA1_STATE2_SZ 20
#define ICP_QAT_HW_SHA224_STATE2_SZ 32
+#define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
#define ICP_QAT_HW_SHA256_STATE2_SZ 32
#define ICP_QAT_HW_SHA3_256_STATE2_SZ 0
#define ICP_QAT_HW_SHA384_STATE2_SZ 64
+#define ICP_QAT_HW_SHA3_384_STATE2_SZ 0
#define ICP_QAT_HW_SHA512_STATE2_SZ 64
#define ICP_QAT_HW_SHA3_512_STATE2_SZ 0
-#define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
-#define ICP_QAT_HW_SHA3_384_STATE2_SZ 0
#define ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ 48
#define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16
#define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16
@@ -154,6 +180,12 @@ struct icp_qat_hw_auth_sha512 {
uint8_t state2[ICP_QAT_HW_SHA512_STATE2_SZ];
};
+struct icp_qat_hw_auth_sha3_512 {
+ struct icp_qat_hw_auth_setup inner_setup;
+ uint8_t state1[ICP_QAT_HW_SHA3_512_STATE1_SZ];
+ struct icp_qat_hw_auth_setup outer_setup;
+};
+
struct icp_qat_hw_auth_algo_blk {
struct icp_qat_hw_auth_sha512 sha;
};
@@ -283,4 +315,72 @@ struct icp_qat_hw_cipher_algo_blk {
uint8_t key[ICP_QAT_HW_CIPHER_MAX_KEY_SZ];
} __rte_cache_aligned;
+/* ========================================================================= */
+/* COMPRESSION SLICE */
+/* ========================================================================= */
+
+enum icp_qat_hw_compression_direction {
+ ICP_QAT_HW_COMPRESSION_DIR_COMPRESS = 0,
+ ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS = 1,
+ ICP_QAT_HW_COMPRESSION_DIR_DELIMITER = 2
+};
+
+enum icp_qat_hw_compression_delayed_match {
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED = 0,
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_ENABLED = 1,
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DELIMITER = 2
+};
+
+enum icp_qat_hw_compression_algo {
+ ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE = 0,
+ ICP_QAT_HW_COMPRESSION_ALGO_LZS = 1,
+ ICP_QAT_HW_COMPRESSION_ALGO_DELIMITER = 2
+};
+
+
+enum icp_qat_hw_compression_depth {
+ ICP_QAT_HW_COMPRESSION_DEPTH_1 = 0,
+ ICP_QAT_HW_COMPRESSION_DEPTH_4 = 1,
+ ICP_QAT_HW_COMPRESSION_DEPTH_8 = 2,
+ ICP_QAT_HW_COMPRESSION_DEPTH_16 = 3,
+ ICP_QAT_HW_COMPRESSION_DEPTH_DELIMITER = 4
+};
+
+enum icp_qat_hw_compression_file_type {
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_0 = 0,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_1 = 1,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_2 = 2,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_3 = 3,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_4 = 4,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_DELIMITER = 5
+};
+
+struct icp_qat_hw_compression_config {
+ uint32_t val;
+ uint32_t reserved;
+};
+
+#define QAT_COMPRESSION_DIR_BITPOS 4
+#define QAT_COMPRESSION_DIR_MASK 0x7
+#define QAT_COMPRESSION_DELAYED_MATCH_BITPOS 16
+#define QAT_COMPRESSION_DELAYED_MATCH_MASK 0x1
+#define QAT_COMPRESSION_ALGO_BITPOS 31
+#define QAT_COMPRESSION_ALGO_MASK 0x1
+#define QAT_COMPRESSION_DEPTH_BITPOS 28
+#define QAT_COMPRESSION_DEPTH_MASK 0x7
+#define QAT_COMPRESSION_FILE_TYPE_BITPOS 24
+#define QAT_COMPRESSION_FILE_TYPE_MASK 0xF
+
+#define ICP_QAT_HW_COMPRESSION_CONFIG_BUILD( \
+ dir, delayed, algo, depth, filetype) \
+ ((((dir) & QAT_COMPRESSION_DIR_MASK) << QAT_COMPRESSION_DIR_BITPOS) | \
+ (((delayed) & QAT_COMPRESSION_DELAYED_MATCH_MASK) \
+ << QAT_COMPRESSION_DELAYED_MATCH_BITPOS) | \
+ (((algo) & QAT_COMPRESSION_ALGO_MASK) \
+ << QAT_COMPRESSION_ALGO_BITPOS) | \
+ (((depth) & QAT_COMPRESSION_DEPTH_MASK) \
+ << QAT_COMPRESSION_DEPTH_BITPOS) | \
+ (((filetype) & QAT_COMPRESSION_FILE_TYPE_MASK) \
+ << QAT_COMPRESSION_FILE_TYPE_BITPOS))
+
#endif
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v2 02/16] compress/qat: add makefiles for PMD
2018-05-23 18:40 [dpdk-dev] [PATCH] compress/qat: add compression PMD Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 00/16] " Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 01/16] common/qat: updated firmware headers Fiona Trahe
@ 2018-07-05 16:05 ` Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 03/16] compress/qat: add meson build Fiona Trahe
` (13 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 16:05 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add Makefiles, directory and empty source files for compression PMD.
Handle cases for building either symmetric crypto PMD
or compression PMD or both and the common files both depend on.
Change-Id: I71c4c6abd1982443cd6f7ff25e03bb161fb3fb16
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
MAINTAINERS | 4 ++++
config/common_base | 3 ++-
drivers/common/qat/Makefile | 48 ++++++++++++++++++++++++++++---------
drivers/compress/qat/qat_comp.c | 5 ++++
drivers/compress/qat/qat_comp.h | 14 +++++++++++
drivers/compress/qat/qat_comp_pmd.c | 5 ++++
drivers/compress/qat/qat_comp_pmd.h | 15 ++++++++++++
test/test/test_cryptodev.c | 6 ++---
8 files changed, 85 insertions(+), 15 deletions(-)
create mode 100644 drivers/compress/qat/qat_comp.c
create mode 100644 drivers/compress/qat/qat_comp.h
create mode 100644 drivers/compress/qat/qat_comp_pmd.c
create mode 100644 drivers/compress/qat/qat_comp_pmd.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 8050b5d..50b2dff 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -852,6 +852,10 @@ F: drivers/compress/isal/
F: doc/guides/compressdevs/isal.rst
F: doc/guides/compressdevs/features/isal.ini
+Intel QuickAssist
+M: Fiona Trahe <fiona.trahe@intel.com>
+F: drivers/compress/qat/
+F: drivers/common/qat/
Eventdev Drivers
----------------
diff --git a/config/common_base b/config/common_base
index 4236e29..93c8857 100644
--- a/config/common_base
+++ b/config/common_base
@@ -484,7 +484,8 @@ CONFIG_RTE_DPAA_SEC_PMD_MAX_NB_SESSIONS=2048
#
# Compile PMD for QuickAssist based devices
#
-CONFIG_RTE_LIBRTE_PMD_QAT=n
+CONFIG_RTE_LIBRTE_PMD_QAT=y
+CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
#
# Max. number of QuickAssist devices, which can be detected and attached
#
diff --git a/drivers/common/qat/Makefile b/drivers/common/qat/Makefile
index 68c7c95..b1a76c1 100644
--- a/drivers/common/qat/Makefile
+++ b/drivers/common/qat/Makefile
@@ -15,35 +15,61 @@ CFLAGS += -O3
# build directories
QAT_CRYPTO_DIR := $(RTE_SDK)/drivers/crypto/qat
+QAT_COMPRESS_DIR := $(RTE_SDK)/drivers/compress/qat
# external library include paths
CFLAGS += -I$(SRCDIR)/qat_adf
CFLAGS += -I$(SRCDIR)
CFLAGS += -I$(QAT_CRYPTO_DIR)
+CFLAGS += -I$(QAT_COMPRESS_DIR)
-# library common source files
-SRCS-y += qat_device.c
-SRCS-y += qat_common.c
-SRCS-y += qat_logs.c
-SRCS-y += qat_qp.c
+
+ifeq ($(CONFIG_RTE_LIBRTE_COMPRESSDEV),y)
+ CFLAGS += -DALLOW_EXPERIMENTAL_API
+ LDLIBS += -lrte_compressdev
+ SRCS-y += $(QAT_COMPRESS_DIR)/qat_comp.c
+ SRCS-y += $(QAT_COMPRESS_DIR)/qat_comp_pmd.c
+ build_qat = yes
+endif
# library symmetric crypto source files
ifeq ($(CONFIG_RTE_LIBRTE_CRYPTODEV),y)
+ifeq ($(CONFIG_RTE_LIBRTE_PMD_QAT_SYM),y)
LDLIBS += -lrte_cryptodev
LDLIBS += -lcrypto
CFLAGS += -DBUILD_QAT_SYM
SRCS-y += $(QAT_CRYPTO_DIR)/qat_sym.c
SRCS-y += $(QAT_CRYPTO_DIR)/qat_sym_session.c
SRCS-y += $(QAT_CRYPTO_DIR)/qat_sym_pmd.c
+ build_qat = yes
endif
+endif
+
+ifdef build_qat
-LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool
-LDLIBS += -lrte_pci -lrte_bus_pci
+ # library name
+ LIB = librte_pmd_qat.a
-# export include files
-SYMLINK-y-include +=
+ # library version
+ LIBABIVER := 1
+ # build flags
+ CFLAGS += $(WERROR_FLAGS)
+ CFLAGS += -O3
-# versioning export map
-EXPORT_MAP := ../../crypto/qat/rte_pmd_qat_version.map
+ # library common source files
+ SRCS-y += qat_device.c
+ SRCS-y += qat_common.c
+ SRCS-y += qat_logs.c
+ SRCS-y += qat_qp.c
+
+ LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool
+ LDLIBS += -lrte_pci -lrte_bus_pci
+
+ # export include files
+ SYMLINK-y-include +=
+
+ # versioning export map
+ EXPORT_MAP := ../../crypto/qat/rte_pmd_qat_version.map
+endif
include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
new file mode 100644
index 0000000..caa1158
--- /dev/null
+++ b/drivers/compress/qat/qat_comp.c
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Intel Corporation
+ */
+
+#include "qat_comp.h"
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
new file mode 100644
index 0000000..89c475e
--- /dev/null
+++ b/drivers/compress/qat/qat_comp.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+
+#ifndef _QAT_COMP_H_
+#define _QAT_COMP_H_
+
+#ifdef RTE_LIBRTE_COMPRESSDEV
+
+#include <rte_compressdev.h>
+#include <rte_compressdev_pmd.h>
+
+#endif
+#endif
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
new file mode 100644
index 0000000..fb035d1
--- /dev/null
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+
+#include "qat_comp_pmd.h"
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
new file mode 100644
index 0000000..9b5b543
--- /dev/null
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+
+#ifndef _QAT_COMP_PMD_H_
+#define _QAT_COMP_PMD_H_
+
+#ifdef RTE_LIBRTE_COMPRESSDEV
+
+#include <rte_compressdev.h>
+#include <rte_compressdev_pmd.h>
+
+
+#endif
+#endif /* _QAT_COMP_PMD_H_ */
diff --git a/test/test/test_cryptodev.c b/test/test/test_cryptodev.c
index 389f796..ec03a98 100644
--- a/test/test/test_cryptodev.c
+++ b/test/test/test_cryptodev.c
@@ -9908,9 +9908,9 @@ test_cryptodev_qat(void /*argv __rte_unused, int argc __rte_unused*/)
RTE_STR(CRYPTODEV_NAME_QAT_SYM_PMD));
if (gbl_driver_id == -1) {
- RTE_LOG(ERR, USER1, "QAT PMD must be loaded. Check if "
- "CONFIG_RTE_LIBRTE_PMD_QAT is enabled "
- "in config file to run this testsuite.\n");
+ RTE_LOG(ERR, USER1, "QAT PMD must be loaded. Check that both "
+ "CONFIG_RTE_LIBRTE_PMD_QAT and CONFIG_RTE_LIBRTE_PMD_QAT_SYM "
+ "are enabled in config file to run this testsuite.\n");
return TEST_SKIPPED;
}
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v2 03/16] compress/qat: add meson build
2018-05-23 18:40 [dpdk-dev] [PATCH] compress/qat: add compression PMD Fiona Trahe
` (2 preceding siblings ...)
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 02/16] compress/qat: add makefiles for PMD Fiona Trahe
@ 2018-07-05 16:05 ` Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 04/16] compress/qat: add xform processing Fiona Trahe
` (12 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 16:05 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add meson build files.
Change-Id: Ia759f56fcc230f90252afcc5e1745c6fb78cefa3
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
drivers/common/qat/Makefile | 2 +-
drivers/compress/meson.build | 2 +-
drivers/compress/qat/meson.build | 18 ++++++++++++++++++
drivers/compress/qat/rte_pmd_qat_version.map | 3 +++
drivers/crypto/qat/meson.build | 10 ++--------
drivers/crypto/qat/rte_pmd_qat_version.map | 3 ---
6 files changed, 25 insertions(+), 13 deletions(-)
create mode 100644 drivers/compress/qat/meson.build
create mode 100644 drivers/compress/qat/rte_pmd_qat_version.map
delete mode 100644 drivers/crypto/qat/rte_pmd_qat_version.map
diff --git a/drivers/common/qat/Makefile b/drivers/common/qat/Makefile
index b1a76c1..bc53652 100644
--- a/drivers/common/qat/Makefile
+++ b/drivers/common/qat/Makefile
@@ -69,7 +69,7 @@ ifdef build_qat
SYMLINK-y-include +=
# versioning export map
- EXPORT_MAP := ../../crypto/qat/rte_pmd_qat_version.map
+ EXPORT_MAP := ../../compress/qat/rte_pmd_qat_version.map
endif
include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/compress/meson.build b/drivers/compress/meson.build
index fb136e1..2352ad5 100644
--- a/drivers/compress/meson.build
+++ b/drivers/compress/meson.build
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2018 Intel Corporation
-drivers = ['isal']
+drivers = ['isal', 'qat']
std_deps = ['compressdev'] # compressdev pulls in all other needed deps
config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'
diff --git a/drivers/compress/qat/meson.build b/drivers/compress/qat/meson.build
new file mode 100644
index 0000000..9d15076
--- /dev/null
+++ b/drivers/compress/qat/meson.build
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2017-2018 Intel Corporation
+
+
+# Add our sources files to the list
+allow_experimental_apis = true
+qat_sources += files('qat_comp_pmd.c',
+ 'qat_comp.c')
+qat_includes += include_directories('.')
+qat_deps += 'compressdev'
+qat_ext_deps += dep
+
+# build the whole driver
+sources += qat_sources
+cflags += qat_cflags
+deps += qat_deps
+ext_deps += qat_ext_deps
+includes += qat_includes
diff --git a/drivers/compress/qat/rte_pmd_qat_version.map b/drivers/compress/qat/rte_pmd_qat_version.map
new file mode 100644
index 0000000..ad6e191
--- /dev/null
+++ b/drivers/compress/qat/rte_pmd_qat_version.map
@@ -0,0 +1,3 @@
+DPDK_18.08 {
+ local: *;
+};
diff --git a/drivers/crypto/qat/meson.build b/drivers/crypto/qat/meson.build
index 2873637..d7cff68 100644
--- a/drivers/crypto/qat/meson.build
+++ b/drivers/crypto/qat/meson.build
@@ -1,6 +1,8 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017-2018 Intel Corporation
+# this does not build the QAT driver, instead that is done in the compression
+# driver which comes later. Here we just add our sources files to the list
build = false
dep = dependency('libcrypto', required: false)
if dep.found()
@@ -13,12 +15,4 @@ if dep.found()
qat_ext_deps += dep
pkgconfig_extra_libs += '-lcrypto'
qat_cflags += '-DBUILD_QAT_SYM'
-
- # build the whole driver
- sources += qat_sources
- cflags += qat_cflags
- deps += qat_deps
- ext_deps += qat_ext_deps
- includes += qat_includes
- build = true
endif
diff --git a/drivers/crypto/qat/rte_pmd_qat_version.map b/drivers/crypto/qat/rte_pmd_qat_version.map
deleted file mode 100644
index bbaf1c8..0000000
--- a/drivers/crypto/qat/rte_pmd_qat_version.map
+++ /dev/null
@@ -1,3 +0,0 @@
-DPDK_2.2 {
- local: *;
-};
\ No newline at end of file
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v2 04/16] compress/qat: add xform processing
2018-05-23 18:40 [dpdk-dev] [PATCH] compress/qat: add compression PMD Fiona Trahe
` (3 preceding siblings ...)
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 03/16] compress/qat: add meson build Fiona Trahe
@ 2018-07-05 16:05 ` Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 05/16] compress/qat: create fw request and process response Fiona Trahe
` (11 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 16:05 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add code to process compressdev rte_comp_xforms, creating
private qat_comp_xforms with prepared firmware message templates.
Change-Id: I8e785d3a6ab3fe196d581413d938244f8143d7bb
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp.c | 239 ++++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp.h | 30 +++++
drivers/compress/qat/qat_comp_pmd.h | 16 +++
3 files changed, 285 insertions(+)
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index caa1158..cb2005a 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -2,4 +2,243 @@
* Copyright(c) 2018 Intel Corporation
*/
+
+#include <rte_mempool.h>
+#include <rte_mbuf.h>
+#include <rte_hexdump.h>
+#include <rte_comp.h>
+#include <rte_bus_pci.h>
+#include <rte_byteorder.h>
+#include <rte_memcpy.h>
+#include <rte_common.h>
+#include <rte_spinlock.h>
+#include <rte_log.h>
+#include <rte_malloc.h>
+
+#include "qat_logs.h"
#include "qat_comp.h"
+#include "qat_comp_pmd.h"
+
+unsigned int
+qat_comp_xform_size(void)
+{
+ return RTE_ALIGN_CEIL(sizeof(struct qat_comp_xform), 8);
+}
+
+static void qat_comp_create_req_hdr(struct icp_qat_fw_comn_req_hdr *header,
+ enum qat_comp_request_type request)
+{
+ if (request == QAT_COMP_REQUEST_FIXED_COMP_STATELESS)
+ header->service_cmd_id = ICP_QAT_FW_COMP_CMD_STATIC;
+ else if (request == QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS)
+ header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DYNAMIC;
+ else if (request == QAT_COMP_REQUEST_DECOMPRESS)
+ header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DECOMPRESS;
+
+ header->service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_COMP;
+ header->hdr_flags =
+ ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
+
+ header->comn_req_flags = ICP_QAT_FW_COMN_FLAGS_BUILD(
+ QAT_COMN_CD_FLD_TYPE_16BYTE_DATA, QAT_COMN_PTR_TYPE_FLAT);
+}
+
+static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,
+ const struct rte_memzone *interm_buff_mz __rte_unused,
+ const struct rte_comp_xform *xform)
+{
+ struct icp_qat_fw_comp_req *comp_req;
+ int comp_level, algo;
+ uint32_t req_par_flags;
+ int direction = ICP_QAT_HW_COMPRESSION_DIR_COMPRESS;
+
+ if (unlikely(qat_xform == NULL)) {
+ QAT_LOG(ERR, "Session was not created for this device");
+ return -EINVAL;
+ }
+
+ if (qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS) {
+ direction = ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS;
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_1;
+ req_par_flags = ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(
+ ICP_QAT_FW_COMP_SOP, ICP_QAT_FW_COMP_EOP,
+ ICP_QAT_FW_COMP_BFINAL, ICP_QAT_FW_COMP_NO_CNV,
+ ICP_QAT_FW_COMP_NO_CNV_RECOVERY);
+
+ } else {
+ if (xform->compress.level == RTE_COMP_LEVEL_PMD_DEFAULT)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_8;
+ else if (xform->compress.level == 1)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_1;
+ else if (xform->compress.level == 2)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_4;
+ else if (xform->compress.level == 3)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_8;
+ else if (xform->compress.level >= 4 &&
+ xform->compress.level <= 9)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_16;
+ else {
+ QAT_LOG(ERR, "compression level not supported");
+ return -EINVAL;
+ }
+ req_par_flags = ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(
+ ICP_QAT_FW_COMP_SOP, ICP_QAT_FW_COMP_EOP,
+ ICP_QAT_FW_COMP_BFINAL, ICP_QAT_FW_COMP_CNV,
+ ICP_QAT_FW_COMP_CNV_RECOVERY);
+ }
+
+ switch (xform->compress.algo) {
+ case RTE_COMP_ALGO_DEFLATE:
+ algo = ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE;
+ break;
+ case RTE_COMP_ALGO_LZS:
+ default:
+ /* RTE_COMP_NULL */
+ QAT_LOG(ERR, "compression algorithm not supported");
+ return -EINVAL;
+ }
+
+ comp_req = &qat_xform->qat_comp_req_tmpl;
+
+ /* Initialize header */
+ qat_comp_create_req_hdr(&comp_req->comn_hdr,
+ qat_xform->qat_comp_request_type);
+
+ comp_req->comn_hdr.serv_specif_flags = ICP_QAT_FW_COMP_FLAGS_BUILD(
+ ICP_QAT_FW_COMP_STATELESS_SESSION,
+ ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST,
+ ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST,
+ ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST,
+ ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_USED_AS_INTMD_BUF);
+
+ comp_req->cd_pars.sl.comp_slice_cfg_word[0] =
+ ICP_QAT_HW_COMPRESSION_CONFIG_BUILD(
+ direction,
+ /* In CPM 1.6 only valid mode ! */
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_ENABLED, algo,
+ /* Translate level to depth */
+ comp_level, ICP_QAT_HW_COMPRESSION_FILE_TYPE_0);
+
+ comp_req->comp_pars.initial_adler = 1;
+ comp_req->comp_pars.initial_crc32 = 0;
+ comp_req->comp_pars.req_par_flags = req_par_flags;
+
+
+ if (qat_xform->qat_comp_request_type ==
+ QAT_COMP_REQUEST_FIXED_COMP_STATELESS ||
+ qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS) {
+ ICP_QAT_FW_COMN_NEXT_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_DRAM_WR);
+ ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_COMP);
+ } else if (qat_xform->qat_comp_request_type ==
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {
+
+ QAT_LOG(ERR, "Dynamic huffman encoding not supported");
+ return -EINVAL;
+ }
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_HEXDUMP_LOG(DEBUG, "qat compression message template:", comp_req,
+ sizeof(struct icp_qat_fw_comp_req));
+#endif
+ return 0;
+}
+
+/**
+ * Create driver private_xform data.
+ *
+ * @param dev
+ * Compressdev device
+ * @param xform
+ * xform data from application
+ * @param private_xform
+ * ptr where handle of pmd's private_xform data should be stored
+ * @return
+ * - if successful returns 0
+ * and valid private_xform handle
+ * - <0 in error cases
+ * - Returns -EINVAL if input parameters are invalid.
+ * - Returns -ENOTSUP if comp device does not support the comp transform.
+ * - Returns -ENOMEM if the private_xform could not be allocated.
+ */
+int
+qat_comp_private_xform_create(struct rte_compressdev *dev,
+ const struct rte_comp_xform *xform,
+ void **private_xform)
+{
+ struct qat_comp_dev_private *qat = dev->data->dev_private;
+
+ if (unlikely(private_xform == NULL)) {
+ QAT_LOG(ERR, "QAT: private_xform parameter is NULL");
+ return -EINVAL;
+ }
+ if (unlikely(qat->xformpool == NULL)) {
+ QAT_LOG(ERR, "QAT device has no private_xform mempool");
+ return -ENOMEM;
+ }
+ if (rte_mempool_get(qat->xformpool, private_xform)) {
+ QAT_LOG(ERR, "Couldn't get object from qat xform mempool");
+ return -ENOMEM;
+ }
+
+ struct qat_comp_xform *qat_xform =
+ (struct qat_comp_xform *)*private_xform;
+
+ if (xform->type == RTE_COMP_COMPRESS) {
+ if (xform->compress.deflate.huffman ==
+ RTE_COMP_HUFFMAN_DYNAMIC) {
+ QAT_LOG(ERR,
+ "QAT device doesn't support dynamic compression");
+ return -ENOTSUP;
+ }
+
+ if (xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_FIXED ||
+ ((xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_DEFAULT)
+ && qat->interm_buff_mz == NULL))
+
+ qat_xform->qat_comp_request_type =
+ QAT_COMP_REQUEST_FIXED_COMP_STATELESS;
+
+
+ } else {
+ qat_xform->qat_comp_request_type = QAT_COMP_REQUEST_DECOMPRESS;
+ }
+
+ qat_xform->checksum_type = xform->compress.chksum;
+
+ if (qat_comp_create_templates(qat_xform, qat->interm_buff_mz, xform)) {
+ QAT_LOG(ERR, "QAT: Problem with setting compression");
+ return -EINVAL;
+ }
+ return 0;
+}
+
+/**
+ * Free driver private_xform data.
+ *
+ * @param dev
+ * Compressdev device
+ * @param private_xform
+ * handle of pmd's private_xform data
+ * @return
+ * - 0 if successful
+ * - <0 in error cases
+ * - Returns -EINVAL if input parameters are invalid.
+ */
+int
+qat_comp_private_xform_free(struct rte_compressdev *dev __rte_unused,
+ void *private_xform)
+{
+ struct qat_comp_xform *qat_xform =
+ (struct qat_comp_xform *)private_xform;
+
+ if (qat_xform) {
+ memset(qat_xform, 0, qat_comp_xform_size());
+ struct rte_mempool *mp = rte_mempool_from_obj(qat_xform);
+
+ rte_mempool_put(mp, qat_xform);
+ return 0;
+ }
+ return -EINVAL;
+}
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 89c475e..0f58a76 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -10,5 +10,35 @@
#include <rte_compressdev.h>
#include <rte_compressdev_pmd.h>
+#include "icp_qat_hw.h"
+#include "icp_qat_fw_comp.h"
+#include "icp_qat_fw_la.h"
+
+enum qat_comp_request_type {
+ QAT_COMP_REQUEST_FIXED_COMP_STATELESS,
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS,
+ QAT_COMP_REQUEST_DECOMPRESS,
+ REQ_COMP_END
+};
+
+
+struct qat_comp_xform {
+ struct icp_qat_fw_comp_req qat_comp_req_tmpl;
+ enum qat_comp_request_type qat_comp_request_type;
+ enum rte_comp_checksum_type checksum_type;
+};
+
+
+int
+qat_comp_private_xform_create(struct rte_compressdev *dev,
+ const struct rte_comp_xform *xform,
+ void **private_xform);
+
+int
+qat_comp_private_xform_free(struct rte_compressdev *dev, void *private_xform);
+
+unsigned int
+qat_comp_xform_size(void);
+
#endif
#endif
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 9b5b543..fd97cbf 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -11,5 +11,21 @@
#include <rte_compressdev_pmd.h>
+/** private data structure for a QAT compression device.
+ * This QAT device is a device offering only a compression service,
+ * there can be one of these on each qat_pci_device (VF).
+ */
+struct qat_comp_dev_private {
+ struct qat_pci_device *qat_dev;
+ /**< The qat pci device hosting the service */
+ struct rte_compressdev *compressdev;
+ /**< The pointer to this compression device structure */
+ const struct rte_memzone *interm_buff_mz;
+ /**< The device's memory for intermediate buffers */
+ struct rte_mempool *xformpool;
+ /**< The device's pool for qat_comp_xforms */
+
+};
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v2 05/16] compress/qat: create fw request and process response
2018-05-23 18:40 [dpdk-dev] [PATCH] compress/qat: add compression PMD Fiona Trahe
` (4 preceding siblings ...)
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 04/16] compress/qat: add xform processing Fiona Trahe
@ 2018-07-05 16:05 ` Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 06/16] compress/qat: check that correct firmware is in use Fiona Trahe
` (10 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 16:05 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add functions to create the request message to send to
firmware and to process the firmware response.
Change-Id: Ie03a6ba3de3741f237e2247d543f2e7101c7435d
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp.c | 101 ++++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp.h | 8 +++
drivers/compress/qat/qat_comp_pmd.h | 1 +
3 files changed, 110 insertions(+)
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index cb2005a..a32d6ef 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -19,6 +19,107 @@
#include "qat_comp.h"
#include "qat_comp_pmd.h"
+
+int
+qat_comp_build_request(void *in_op, uint8_t *out_msg,
+ void *op_cookie __rte_unused,
+ enum qat_device_gen qat_dev_gen __rte_unused)
+{
+ struct rte_comp_op *op = in_op;
+ struct qat_comp_xform *qat_xform = op->private_xform;
+ const uint8_t *tmpl = (uint8_t *)&qat_xform->qat_comp_req_tmpl;
+ struct icp_qat_fw_comp_req *comp_req =
+ (struct icp_qat_fw_comp_req *)out_msg;
+
+ if (unlikely(op->op_type != RTE_COMP_OP_STATELESS)) {
+ QAT_DP_LOG(ERR, "QAT PMD only supports stateless compression "
+ "operation requests, op (%p) is not a "
+ "stateless operation.", op);
+ return -EINVAL;
+ }
+
+ rte_mov128(out_msg, tmpl);
+ comp_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
+
+ /* common for sgl and flat buffers */
+ comp_req->comp_pars.comp_len = op->src.length;
+ comp_req->comp_pars.out_buffer_sz = rte_pktmbuf_pkt_len(op->m_dst);
+
+ /* sgl */
+ if (op->m_src->next != NULL || op->m_dst->next != NULL) {
+ QAT_DP_LOG(ERR, "QAT PMD doesn't support scatter gather");
+ return -EINVAL;
+
+ } else {
+ ICP_QAT_FW_COMN_PTR_TYPE_SET(comp_req->comn_hdr.comn_req_flags,
+ QAT_COMN_PTR_TYPE_FLAT);
+ comp_req->comn_mid.src_length = rte_pktmbuf_data_len(op->m_src);
+ comp_req->comn_mid.dst_length = rte_pktmbuf_data_len(op->m_dst);
+
+ comp_req->comn_mid.src_data_addr =
+ rte_pktmbuf_mtophys_offset(op->m_src, op->src.offset);
+ comp_req->comn_mid.dest_data_addr =
+ rte_pktmbuf_mtophys_offset(op->m_dst, op->dst.offset);
+ }
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_LOG(DEBUG, "Direction: %s",
+ qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS ?
+ "decompression" : "compression");
+ QAT_DP_HEXDUMP_LOG(DEBUG, "qat compression message:", comp_req,
+ sizeof(struct icp_qat_fw_comp_req));
+#endif
+ return 0;
+}
+
+int
+qat_comp_process_response(void **op, uint8_t *resp)
+{
+ struct icp_qat_fw_comp_resp *resp_msg =
+ (struct icp_qat_fw_comp_resp *)resp;
+ struct rte_comp_op *rx_op = (struct rte_comp_op *)(uintptr_t)
+ (resp_msg->opaque_data);
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_LOG(DEBUG, "Direction: %s",
+ qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS ?
+ "decompression" : "compression");
+ QAT_DP_HEXDUMP_LOG(DEBUG, "qat_response:", (uint8_t *)resp_msg,
+ sizeof(struct icp_qat_fw_comp_resp));
+#endif
+
+ if ((ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(resp_msg->comn_resp.comn_status)
+ | ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(
+ resp_msg->comn_resp.comn_status)) !=
+ ICP_QAT_FW_COMN_STATUS_FLAG_OK) {
+
+ rx_op->status = RTE_COMP_OP_STATUS_ERROR;
+ rx_op->debug_status =
+ *((uint16_t *)(&resp_msg->comn_resp.comn_error));
+ } else {
+ struct qat_comp_xform *qat_xform = rx_op->private_xform;
+ struct icp_qat_fw_resp_comp_pars *comp_resp =
+ (struct icp_qat_fw_resp_comp_pars *)&resp_msg->comp_resp_pars;
+
+ rx_op->status = RTE_COMP_OP_STATUS_SUCCESS;
+ rx_op->consumed = comp_resp->input_byte_counter;
+ rx_op->produced = comp_resp->output_byte_counter;
+
+ if (qat_xform->checksum_type != RTE_COMP_CHECKSUM_NONE) {
+ if (qat_xform->checksum_type == RTE_COMP_CHECKSUM_CRC32)
+ rx_op->output_chksum = comp_resp->curr_crc32;
+ else if (qat_xform->checksum_type ==
+ RTE_COMP_CHECKSUM_ADLER32)
+ rx_op->output_chksum = comp_resp->curr_adler_32;
+ else
+ rx_op->output_chksum = comp_resp->curr_chksum;
+ }
+ }
+ *op = (void *)rx_op;
+
+ return 0;
+}
+
unsigned int
qat_comp_xform_size(void)
{
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 0f58a76..46105b4 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -10,6 +10,7 @@
#include <rte_compressdev.h>
#include <rte_compressdev_pmd.h>
+#include "qat_common.h"
#include "icp_qat_hw.h"
#include "icp_qat_fw_comp.h"
#include "icp_qat_fw_la.h"
@@ -28,6 +29,13 @@ struct qat_comp_xform {
enum rte_comp_checksum_type checksum_type;
};
+int
+qat_comp_build_request(void *in_op, uint8_t *out_msg, void *op_cookie,
+ enum qat_device_gen qat_dev_gen __rte_unused);
+
+int
+qat_comp_process_response(void **op, uint8_t *resp);
+
int
qat_comp_private_xform_create(struct rte_compressdev *dev,
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index fd97cbf..cd04f11 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -10,6 +10,7 @@
#include <rte_compressdev.h>
#include <rte_compressdev_pmd.h>
+#include "qat_device.h"
/** private data structure for a QAT compression device.
* This QAT device is a device offering only a compression service,
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v2 06/16] compress/qat: check that correct firmware is in use
2018-05-23 18:40 [dpdk-dev] [PATCH] compress/qat: add compression PMD Fiona Trahe
` (5 preceding siblings ...)
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 05/16] compress/qat: create fw request and process response Fiona Trahe
@ 2018-07-05 16:05 ` Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 07/16] compress/qat: add stats functions Fiona Trahe
` (9 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 16:05 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Check bit in response message to verify that correct firmware
is in use for compression. If not return an error.
Change-Id: I0d1a6ba3a27380226e60491e66aef3284e49de67
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp.c | 16 +++++++++++++++-
drivers/compress/qat/qat_comp.h | 2 ++
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index a32d6ef..e8019eb 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -2,7 +2,6 @@
* Copyright(c) 2018 Intel Corporation
*/
-
#include <rte_mempool.h>
#include <rte_mbuf.h>
#include <rte_hexdump.h>
@@ -79,6 +78,8 @@ qat_comp_process_response(void **op, uint8_t *resp)
(struct icp_qat_fw_comp_resp *)resp;
struct rte_comp_op *rx_op = (struct rte_comp_op *)(uintptr_t)
(resp_msg->opaque_data);
+ struct qat_comp_xform *qat_xform = (struct qat_comp_xform *)
+ (rx_op->private_xform);
#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
QAT_DP_LOG(DEBUG, "Direction: %s",
@@ -88,6 +89,19 @@ qat_comp_process_response(void **op, uint8_t *resp)
sizeof(struct icp_qat_fw_comp_resp));
#endif
+ if (likely(qat_xform->qat_comp_request_type
+ != QAT_COMP_REQUEST_DECOMPRESS)) {
+ if (unlikely(ICP_QAT_FW_COMN_HDR_CNV_FLAG_GET(
+ resp_msg->comn_resp.hdr_flags)
+ == ICP_QAT_FW_COMP_NO_CNV)) {
+ rx_op->status = RTE_COMP_OP_STATUS_ERROR;
+ rx_op->debug_status = ERR_CODE_QAT_COMP_WRONG_FW;
+ *op = (void *)rx_op;
+ QAT_DP_LOG(ERR, "QAT has wrong firmware");
+ return 0;
+ }
+ }
+
if ((ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(resp_msg->comn_resp.comn_status)
| ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(
resp_msg->comn_resp.comn_status)) !=
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 46105b4..937f3c8 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -15,6 +15,8 @@
#include "icp_qat_fw_comp.h"
#include "icp_qat_fw_la.h"
+#define ERR_CODE_QAT_COMP_WRONG_FW -99
+
enum qat_comp_request_type {
QAT_COMP_REQUEST_FIXED_COMP_STATELESS,
QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS,
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v2 07/16] compress/qat: add stats functions
2018-05-23 18:40 [dpdk-dev] [PATCH] compress/qat: add compression PMD Fiona Trahe
` (6 preceding siblings ...)
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 06/16] compress/qat: check that correct firmware is in use Fiona Trahe
@ 2018-07-05 16:05 ` Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 08/16] compress/qat: setup queue-pairs for compression service Fiona Trahe
` (8 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 16:05 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add fns to get and clear compression queue-pair stats.
Change-Id: I22cbf2425c96850472410da11a18be64727f5d17
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 35 +++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 7 +++++++
2 files changed, 42 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index fb035d1..6feffb7 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -3,3 +3,38 @@
*/
#include "qat_comp_pmd.h"
+
+void
+qat_comp_stats_get(struct rte_compressdev *dev,
+ struct rte_compressdev_stats *stats)
+{
+ struct qat_common_stats qat_stats = {0};
+ struct qat_comp_dev_private *qat_priv;
+
+ if (stats == NULL || dev == NULL) {
+ QAT_LOG(ERR, "invalid ptr: stats %p, dev %p", stats, dev);
+ return;
+ }
+ qat_priv = dev->data->dev_private;
+
+ qat_stats_get(qat_priv->qat_dev, &qat_stats, QAT_SERVICE_COMPRESSION);
+ stats->enqueued_count = qat_stats.enqueued_count;
+ stats->dequeued_count = qat_stats.dequeued_count;
+ stats->enqueue_err_count = qat_stats.enqueue_err_count;
+ stats->dequeue_err_count = qat_stats.dequeue_err_count;
+}
+
+void
+qat_comp_stats_reset(struct rte_compressdev *dev)
+{
+ struct qat_comp_dev_private *qat_priv;
+
+ if (dev == NULL) {
+ QAT_LOG(ERR, "invalid compressdev ptr %p", dev);
+ return;
+ }
+ qat_priv = dev->data->dev_private;
+
+ qat_stats_reset(qat_priv->qat_dev, QAT_SERVICE_COMPRESSION);
+
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index cd04f11..27d84c8 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -28,5 +28,12 @@ struct qat_comp_dev_private {
};
+void
+qat_comp_stats_reset(struct rte_compressdev *dev);
+
+void
+qat_comp_stats_get(struct rte_compressdev *dev,
+ struct rte_compressdev_stats *stats);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v2 08/16] compress/qat: setup queue-pairs for compression service
2018-05-23 18:40 [dpdk-dev] [PATCH] compress/qat: add compression PMD Fiona Trahe
` (7 preceding siblings ...)
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 07/16] compress/qat: add stats functions Fiona Trahe
@ 2018-07-05 16:05 ` Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 09/16] compress/qat: add fns to configure and clear device Fiona Trahe
` (7 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 16:05 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Setup and clear queue-pairs for handling compression
requests and responses.
Change-Id: Id9e517eb7bfcbbd3a79cae8f6757c91cc46d4de6
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp.h | 2 ++
drivers/compress/qat/qat_comp_pmd.c | 62 +++++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 6 ++++
3 files changed, 70 insertions(+)
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 937f3c8..9e6861b 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -24,6 +24,8 @@ enum qat_comp_request_type {
REQ_COMP_END
};
+struct qat_comp_op_cookie {
+};
struct qat_comp_xform {
struct icp_qat_fw_comp_req qat_comp_req_tmpl;
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 6feffb7..e7252b2 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -2,6 +2,7 @@
* Copyright(c) 2015-2018 Intel Corporation
*/
+#include "qat_comp.h"
#include "qat_comp_pmd.h"
void
@@ -38,3 +39,64 @@ qat_comp_stats_reset(struct rte_compressdev *dev)
qat_stats_reset(qat_priv->qat_dev, QAT_SERVICE_COMPRESSION);
}
+
+int
+qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)
+{
+ struct qat_comp_dev_private *qat_private = dev->data->dev_private;
+
+ QAT_LOG(DEBUG, "Release comp qp %u on device %d",
+ queue_pair_id, dev->data->dev_id);
+
+ qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][queue_pair_id]
+ = NULL;
+
+ return qat_qp_release((struct qat_qp **)
+ &(dev->data->queue_pairs[queue_pair_id]));
+}
+
+int
+qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
+ uint32_t max_inflight_ops, int socket_id)
+{
+ int ret = 0;
+ struct qat_qp_config qat_qp_conf;
+
+ struct qat_qp **qp_addr =
+ (struct qat_qp **)&(dev->data->queue_pairs[qp_id]);
+ struct qat_comp_dev_private *qat_private = dev->data->dev_private;
+ const struct qat_qp_hw_data *comp_hw_qps =
+ qat_gen_config[qat_private->qat_dev->qat_dev_gen]
+ .qp_hw_data[QAT_SERVICE_COMPRESSION];
+ const struct qat_qp_hw_data *qp_hw_data = comp_hw_qps + qp_id;
+
+ /* If qp is already in use free ring memory and qp metadata. */
+ if (*qp_addr != NULL) {
+ ret = qat_comp_qp_release(dev, qp_id);
+ if (ret < 0)
+ return ret;
+ }
+ if (qp_id >= qat_qps_per_service(comp_hw_qps,
+ QAT_SERVICE_COMPRESSION)) {
+ QAT_LOG(ERR, "qp_id %u invalid for this device", qp_id);
+ return -EINVAL;
+ }
+
+ qat_qp_conf.hw = qp_hw_data;
+ qat_qp_conf.build_request = qat_comp_build_request;
+ qat_qp_conf.cookie_size = sizeof(struct qat_comp_op_cookie);
+ qat_qp_conf.nb_descriptors = max_inflight_ops;
+ qat_qp_conf.socket_id = socket_id;
+ qat_qp_conf.service_str = "comp";
+
+ ret = qat_qp_setup(qat_private->qat_dev, qp_addr, qp_id, &qat_qp_conf);
+ if (ret != 0)
+ return ret;
+
+ /* store a link to the qp in the qat_pci_device */
+ qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][qp_id]
+ = *qp_addr;
+
+ return ret;
+}
+
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 27d84c8..5a4bc31 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -34,6 +34,12 @@ qat_comp_stats_reset(struct rte_compressdev *dev);
void
qat_comp_stats_get(struct rte_compressdev *dev,
struct rte_compressdev_stats *stats);
+int
+qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id);
+
+int
+qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
+ uint32_t max_inflight_ops, int socket_id);
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v2 09/16] compress/qat: add fns to configure and clear device
2018-05-23 18:40 [dpdk-dev] [PATCH] compress/qat: add compression PMD Fiona Trahe
` (8 preceding siblings ...)
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 08/16] compress/qat: setup queue-pairs for compression service Fiona Trahe
@ 2018-07-05 16:05 ` Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 10/16] compress/qat: add fn to return device info Fiona Trahe
` (6 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 16:05 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add functions to configure and clear the qat comp device,
including the creation and freeing of the xform pool
and the freeing of queue-pairs.
Change-Id: I24d75b20141ae9bda3917dda0c9c2accf874cf88
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 96 +++++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 7 +++
2 files changed, 103 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index e7252b2..dfdb373 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -100,3 +100,99 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
return ret;
}
+
+static struct rte_mempool *
+qat_comp_create_xform_pool(struct qat_comp_dev_private *comp_dev,
+ uint32_t num_elements)
+{
+ char xform_pool_name[RTE_MEMPOOL_NAMESIZE];
+ struct rte_mempool *mp;
+
+ snprintf(xform_pool_name, RTE_MEMPOOL_NAMESIZE,
+ "%s_xforms", comp_dev->qat_dev->name);
+
+ QAT_LOG(DEBUG, "xformpool: %s", xform_pool_name);
+ mp = rte_mempool_lookup(xform_pool_name);
+
+ if (mp != NULL) {
+ QAT_LOG(DEBUG, "xformpool already created");
+ if (mp->size != num_elements) {
+ QAT_LOG(DEBUG, "xformpool wrong size - delete it");
+ rte_mempool_free(mp);
+ mp = NULL;
+ comp_dev->xformpool = NULL;
+ }
+ }
+
+ if (mp == NULL)
+ mp = rte_mempool_create(xform_pool_name,
+ num_elements,
+ qat_comp_xform_size(), 0, 0,
+ NULL, NULL, NULL, NULL, rte_socket_id(),
+ 0);
+ if (mp == NULL) {
+ QAT_LOG(ERR, "Err creating mempool %s w %d elements of size %d",
+ xform_pool_name, num_elements, qat_comp_xform_size());
+ return NULL;
+ }
+
+ return mp;
+}
+
+static void
+_qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)
+{
+ /* Free private_xform pool */
+ if (comp_dev->xformpool) {
+ /* Free internal mempool for private xforms */
+ rte_mempool_free(comp_dev->xformpool);
+ comp_dev->xformpool = NULL;
+ }
+}
+
+int
+qat_comp_dev_config(struct rte_compressdev *dev,
+ struct rte_compressdev_config *config)
+{
+ struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
+ int ret = 0;
+
+ if (config->max_nb_streams != 0) {
+ QAT_LOG(ERR,
+ "QAT device does not support STATEFUL so max_nb_streams must be 0");
+ return -EINVAL;
+ }
+
+ comp_dev->xformpool = qat_comp_create_xform_pool(comp_dev,
+ config->max_nb_priv_xforms);
+ if (comp_dev->xformpool == NULL) {
+
+ ret = -ENOMEM;
+ goto error_out;
+ }
+ return 0;
+
+error_out:
+ _qat_comp_dev_config_clear(comp_dev);
+ return ret;
+}
+
+
+int
+qat_comp_dev_close(struct rte_compressdev *dev)
+{
+ int i;
+ int ret = 0;
+ struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
+
+ for (i = 0; i < dev->data->nb_queue_pairs; i++) {
+ ret = qat_comp_qp_release(dev, i);
+ if (ret < 0)
+ return ret;
+ }
+
+ _qat_comp_dev_config_clear(comp_dev);
+
+ return ret;
+}
+
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 5a4bc31..b10a66f 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -41,5 +41,12 @@ int
qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
uint32_t max_inflight_ops, int socket_id);
+int
+qat_comp_dev_config(struct rte_compressdev *dev,
+ struct rte_compressdev_config *config);
+
+int
+qat_comp_dev_close(struct rte_compressdev *dev);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v2 10/16] compress/qat: add fn to return device info
2018-05-23 18:40 [dpdk-dev] [PATCH] compress/qat: add compression PMD Fiona Trahe
` (9 preceding siblings ...)
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 09/16] compress/qat: add fns to configure and clear device Fiona Trahe
@ 2018-07-05 16:05 ` Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 11/16] compress/qat: add enqueue/dequeue functions Fiona Trahe
` (5 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 16:05 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add capabilities ptr to internal qat comp device
and function to return this and other info.
Change-Id: Ic0bf5375e0fbf6338d90fb10e7b9ae1454c93792
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 18 ++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 6 ++++++
2 files changed, 24 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index dfdb373..2b64130 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -196,3 +196,21 @@ qat_comp_dev_close(struct rte_compressdev *dev)
return ret;
}
+
+void
+qat_comp_dev_info_get(struct rte_compressdev *dev,
+ struct rte_compressdev_info *info)
+{
+ struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
+ const struct qat_qp_hw_data *comp_hw_qps =
+ qat_gen_config[comp_dev->qat_dev->qat_dev_gen]
+ .qp_hw_data[QAT_SERVICE_COMPRESSION];
+
+ if (info != NULL) {
+ info->max_nb_queue_pairs =
+ qat_qps_per_service(comp_hw_qps,
+ QAT_SERVICE_COMPRESSION);
+ info->feature_flags = dev->feature_flags;
+ info->capabilities = comp_dev->qat_dev_capabilities;
+ }
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index b10a66f..22576f4 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -21,6 +21,8 @@ struct qat_comp_dev_private {
/**< The qat pci device hosting the service */
struct rte_compressdev *compressdev;
/**< The pointer to this compression device structure */
+ const struct rte_compressdev_capabilities *qat_dev_capabilities;
+ /* QAT device compression capabilities */
const struct rte_memzone *interm_buff_mz;
/**< The device's memory for intermediate buffers */
struct rte_mempool *xformpool;
@@ -48,5 +50,9 @@ qat_comp_dev_config(struct rte_compressdev *dev,
int
qat_comp_dev_close(struct rte_compressdev *dev);
+void
+qat_comp_dev_info_get(struct rte_compressdev *dev,
+ struct rte_compressdev_info *info);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v2 11/16] compress/qat: add enqueue/dequeue functions
2018-05-23 18:40 [dpdk-dev] [PATCH] compress/qat: add compression PMD Fiona Trahe
` (10 preceding siblings ...)
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 10/16] compress/qat: add fn to return device info Fiona Trahe
@ 2018-07-05 16:05 ` Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 12/16] compress/qat: add device start and stop fns Fiona Trahe
` (4 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 16:05 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Wrap generic qat enqueue/dequeue functions with
compressdev enqueue and dequeue fns.
Change-Id: Ie2fd918f17b29fd97f52ce9773966d231f4c7a33
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 14 ++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 8 ++++++++
2 files changed, 22 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 2b64130..fc99cca 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -214,3 +214,17 @@ qat_comp_dev_info_get(struct rte_compressdev *dev,
info->capabilities = comp_dev->qat_dev_capabilities;
}
}
+
+uint16_t
+qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops)
+{
+ return qat_enqueue_op_burst(qp, (void **)ops, nb_ops);
+}
+
+uint16_t
+qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops)
+{
+ return qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 22576f4..f360c29 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -54,5 +54,13 @@ void
qat_comp_dev_info_get(struct rte_compressdev *dev,
struct rte_compressdev_info *info);
+uint16_t
+qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops);
+
+uint16_t
+qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v2 12/16] compress/qat: add device start and stop fns
2018-05-23 18:40 [dpdk-dev] [PATCH] compress/qat: add compression PMD Fiona Trahe
` (11 preceding siblings ...)
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 11/16] compress/qat: add enqueue/dequeue functions Fiona Trahe
@ 2018-07-05 16:05 ` Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 13/16] compress/qat: create and populate the ops structure Fiona Trahe
` (3 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 16:05 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
There are no specific actions needed to start/stop a QAT comp device
so these are just trivial fns to satisfy the pmd API.
Change-Id: I09288ffee58614ee68acf54f031b0eadb991b266
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 11 +++++++++++
drivers/compress/qat/qat_comp_pmd.h | 6 ++++++
2 files changed, 17 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index fc99cca..bf07989 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -177,6 +177,17 @@ qat_comp_dev_config(struct rte_compressdev *dev,
return ret;
}
+int
+qat_comp_dev_start(struct rte_compressdev *dev __rte_unused)
+{
+ return 0;
+}
+
+void
+qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused)
+{
+
+}
int
qat_comp_dev_close(struct rte_compressdev *dev)
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index f360c29..22cbefb 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -62,5 +62,11 @@ uint16_t
qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops);
+int
+qat_comp_dev_start(struct rte_compressdev *dev __rte_unused);
+
+void
+qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v2 13/16] compress/qat: create and populate the ops structure
2018-05-23 18:40 [dpdk-dev] [PATCH] compress/qat: add compression PMD Fiona Trahe
` (12 preceding siblings ...)
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 12/16] compress/qat: add device start and stop fns Fiona Trahe
@ 2018-07-05 16:05 ` Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 14/16] compress/qat: add fns to create and destroy the PMD Fiona Trahe
` (2 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 16:05 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Create an ops structure and populate it with the
qat-specific finctions.
Change-Id: I4fec917df598b983b889e4e07e5aa110774e446d
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 38 ++++++++++++++++++++++++++++---------
drivers/compress/qat/qat_comp_pmd.h | 30 -----------------------------
2 files changed, 29 insertions(+), 39 deletions(-)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index bf07989..41946af 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -5,7 +5,7 @@
#include "qat_comp.h"
#include "qat_comp_pmd.h"
-void
+static void
qat_comp_stats_get(struct rte_compressdev *dev,
struct rte_compressdev_stats *stats)
{
@@ -25,7 +25,7 @@ qat_comp_stats_get(struct rte_compressdev *dev,
stats->dequeue_err_count = qat_stats.dequeue_err_count;
}
-void
+static void
qat_comp_stats_reset(struct rte_compressdev *dev)
{
struct qat_comp_dev_private *qat_priv;
@@ -40,7 +40,7 @@ qat_comp_stats_reset(struct rte_compressdev *dev)
}
-int
+static int
qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)
{
struct qat_comp_dev_private *qat_private = dev->data->dev_private;
@@ -55,7 +55,7 @@ qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)
&(dev->data->queue_pairs[queue_pair_id]));
}
-int
+static int
qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
uint32_t max_inflight_ops, int socket_id)
{
@@ -150,7 +150,7 @@ _qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)
}
}
-int
+static int
qat_comp_dev_config(struct rte_compressdev *dev,
struct rte_compressdev_config *config)
{
@@ -177,19 +177,19 @@ qat_comp_dev_config(struct rte_compressdev *dev,
return ret;
}
-int
+static int
qat_comp_dev_start(struct rte_compressdev *dev __rte_unused)
{
return 0;
}
-void
+static void
qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused)
{
}
-int
+static int
qat_comp_dev_close(struct rte_compressdev *dev)
{
int i;
@@ -208,7 +208,7 @@ qat_comp_dev_close(struct rte_compressdev *dev)
}
-void
+static void
qat_comp_dev_info_get(struct rte_compressdev *dev,
struct rte_compressdev_info *info)
{
@@ -239,3 +239,23 @@ qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
{
return qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
}
+
+
+struct rte_compressdev_ops compress_qat_ops = {
+
+ /* Device related operations */
+ .dev_configure = qat_comp_dev_config,
+ .dev_start = qat_comp_dev_start,
+ .dev_stop = qat_comp_dev_stop,
+ .dev_close = qat_comp_dev_close,
+ .dev_infos_get = qat_comp_dev_info_get,
+
+ .stats_get = qat_comp_stats_get,
+ .stats_reset = qat_comp_stats_reset,
+ .queue_pair_setup = qat_comp_qp_setup,
+ .queue_pair_release = qat_comp_qp_release,
+
+ /* Compression related operations */
+ .private_xform_create = qat_comp_private_xform_create,
+ .private_xform_free = qat_comp_private_xform_free
+};
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 22cbefb..7ba1b8d 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -30,30 +30,6 @@ struct qat_comp_dev_private {
};
-void
-qat_comp_stats_reset(struct rte_compressdev *dev);
-
-void
-qat_comp_stats_get(struct rte_compressdev *dev,
- struct rte_compressdev_stats *stats);
-int
-qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id);
-
-int
-qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
- uint32_t max_inflight_ops, int socket_id);
-
-int
-qat_comp_dev_config(struct rte_compressdev *dev,
- struct rte_compressdev_config *config);
-
-int
-qat_comp_dev_close(struct rte_compressdev *dev);
-
-void
-qat_comp_dev_info_get(struct rte_compressdev *dev,
- struct rte_compressdev_info *info);
-
uint16_t
qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops);
@@ -62,11 +38,5 @@ uint16_t
qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops);
-int
-qat_comp_dev_start(struct rte_compressdev *dev __rte_unused);
-
-void
-qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused);
-
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v2 14/16] compress/qat: add fns to create and destroy the PMD
2018-05-23 18:40 [dpdk-dev] [PATCH] compress/qat: add compression PMD Fiona Trahe
` (13 preceding siblings ...)
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 13/16] compress/qat: create and populate the ops structure Fiona Trahe
@ 2018-07-05 16:05 ` Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 15/16] compress/qat: prevent device usage if incorrect firmware Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 16/16] docs/qat: refactor docs adding compression guide Fiona Trahe
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 16:05 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Now that all the device operations are available,
add the functions to create and destroy the pmd.
Called on probe and remove of the qat pci device, these
register the device with the compressdev API
and plug in all the device functionality.
Change-Id: I288fe781a5ea4a8595bc00754089921af89c2f50
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/common/qat/qat_device.h | 4 ++
drivers/common/qat/qat_qp.c | 11 ++++-
drivers/common/qat/qat_qp.h | 5 ++
drivers/compress/qat/qat_comp_pmd.c | 95 +++++++++++++++++++++++++++++++++++--
drivers/compress/qat/qat_comp_pmd.h | 11 ++---
5 files changed, 114 insertions(+), 12 deletions(-)
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index 0cb370c..9599fc5 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -25,6 +25,8 @@
* - runtime data
*/
struct qat_sym_dev_private;
+struct qat_comp_dev_private;
+
struct qat_pci_device {
/* Data used by all services */
@@ -55,6 +57,8 @@ struct qat_pci_device {
*/
/* Data relating to compression service */
+ struct qat_comp_dev_private *comp_dev;
+ /**< link back to compressdev private data */
/* Data relating to asymmetric crypto service */
diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c
index 32c1759..7ca7a45 100644
--- a/drivers/common/qat/qat_qp.c
+++ b/drivers/common/qat/qat_qp.c
@@ -15,6 +15,7 @@
#include "qat_device.h"
#include "qat_qp.h"
#include "qat_sym.h"
+#include "qat_comp.h"
#include "adf_transport_access_macros.h"
@@ -606,8 +607,8 @@ qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
if (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC)
qat_sym_process_response(ops, resp_msg);
- /* add qat_asym_process_response here */
- /* add qat_comp_process_response here */
+ else if (tmp_qp->service_type == QAT_SERVICE_COMPRESSION)
+ qat_comp_process_response(ops, resp_msg);
head = adf_modulo(head + rx_queue->msg_size,
rx_queue->modulo_mask);
@@ -633,3 +634,9 @@ qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
}
return resp_counter;
}
+
+__attribute__((weak)) int
+qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused)
+{
+ return 0;
+}
diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h
index 59db945..69f8a61 100644
--- a/drivers/common/qat/qat_qp.h
+++ b/drivers/common/qat/qat_qp.h
@@ -103,4 +103,9 @@ qat_qp_setup(struct qat_pci_device *qat_dev,
int
qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,
enum qat_service_type service);
+
+/* Needed for weak function*/
+int
+qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused);
+
#endif /* _QAT_QP_H_ */
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 41946af..4ff1518 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -5,6 +5,15 @@
#include "qat_comp.h"
#include "qat_comp_pmd.h"
+static const struct rte_compressdev_capabilities qat_comp_gen_capabilities[] = {
+ {/* COMPRESSION - deflate */
+ .algo = RTE_COMP_ALGO_DEFLATE,
+ .comp_feature_flags = RTE_COMP_FF_MULTI_PKT_CHECKSUM |
+ RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
+ RTE_COMP_FF_HUFFMAN_FIXED,
+ .window_size = {.min = 15, .max = 15, .increment = 0} },
+ {RTE_COMP_ALGO_LIST_END, 0, {0, 0, 0} } };
+
static void
qat_comp_stats_get(struct rte_compressdev *dev,
struct rte_compressdev_stats *stats)
@@ -226,14 +235,14 @@ qat_comp_dev_info_get(struct rte_compressdev *dev,
}
}
-uint16_t
+static uint16_t
qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops)
{
return qat_enqueue_op_burst(qp, (void **)ops, nb_ops);
}
-uint16_t
+static uint16_t
qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops)
{
@@ -241,7 +250,7 @@ qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
}
-struct rte_compressdev_ops compress_qat_ops = {
+static struct rte_compressdev_ops compress_qat_ops = {
/* Device related operations */
.dev_configure = qat_comp_dev_config,
@@ -259,3 +268,83 @@ struct rte_compressdev_ops compress_qat_ops = {
.private_xform_create = qat_comp_private_xform_create,
.private_xform_free = qat_comp_private_xform_free
};
+
+int
+qat_comp_dev_create(struct qat_pci_device *qat_pci_dev)
+{
+ if (qat_pci_dev->qat_dev_gen == QAT_GEN1) {
+ QAT_LOG(ERR, "Compression PMD not supported on QAT dh895xcc");
+ return 0;
+ }
+
+ struct rte_compressdev_pmd_init_params init_params = {
+ .name = "",
+ .socket_id = qat_pci_dev->pci_dev->device.numa_node,
+ };
+ char name[RTE_COMPRESSDEV_NAME_MAX_LEN];
+ struct rte_compressdev *compressdev;
+ struct qat_comp_dev_private *comp_dev;
+
+ snprintf(name, RTE_COMPRESSDEV_NAME_MAX_LEN, "%s_%s",
+ qat_pci_dev->name, "comp");
+ QAT_LOG(DEBUG, "Creating QAT COMP device %s", name);
+
+ compressdev = rte_compressdev_pmd_create(name,
+ &qat_pci_dev->pci_dev->device,
+ sizeof(struct qat_comp_dev_private),
+ &init_params);
+
+ if (compressdev == NULL)
+ return -ENODEV;
+
+ compressdev->dev_ops = &compress_qat_ops;
+
+ compressdev->enqueue_burst = qat_comp_pmd_enqueue_op_burst;
+ compressdev->dequeue_burst = qat_comp_pmd_dequeue_op_burst;
+
+ compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
+
+ comp_dev = compressdev->data->dev_private;
+ comp_dev->qat_dev = qat_pci_dev;
+ comp_dev->compressdev = compressdev;
+ qat_pci_dev->comp_dev = comp_dev;
+
+ switch (qat_pci_dev->qat_dev_gen) {
+ case QAT_GEN1:
+ case QAT_GEN2:
+ comp_dev->qat_dev_capabilities = qat_comp_gen_capabilities;
+ break;
+ default:
+ comp_dev->qat_dev_capabilities = qat_comp_gen_capabilities;
+ QAT_LOG(DEBUG,
+ "QAT gen %d capabilities unknown, default to GEN1",
+ qat_pci_dev->qat_dev_gen);
+ break;
+ }
+
+ QAT_LOG(DEBUG,
+ "Created QAT COMP device %s as compressdev instance %d",
+ name, compressdev->data->dev_id);
+ return 0;
+}
+
+int
+qat_comp_dev_destroy(struct qat_pci_device *qat_pci_dev)
+{
+ struct qat_comp_dev_private *comp_dev;
+
+ if (qat_pci_dev == NULL)
+ return -ENODEV;
+
+ comp_dev = qat_pci_dev->comp_dev;
+ if (comp_dev == NULL)
+ return 0;
+
+ /* clean up any resources used by the device */
+ qat_comp_dev_close(comp_dev->compressdev);
+
+ rte_compressdev_pmd_destroy(comp_dev->compressdev);
+ qat_pci_dev->comp_dev = NULL;
+
+ return 0;
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 7ba1b8d..9ad2a28 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -27,16 +27,13 @@ struct qat_comp_dev_private {
/**< The device's memory for intermediate buffers */
struct rte_mempool *xformpool;
/**< The device's pool for qat_comp_xforms */
-
};
-uint16_t
-qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
- uint16_t nb_ops);
+int
+qat_comp_dev_create(struct qat_pci_device *qat_pci_dev);
-uint16_t
-qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
- uint16_t nb_ops);
+int
+qat_comp_dev_destroy(struct qat_pci_device *qat_pci_dev);
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v2 15/16] compress/qat: prevent device usage if incorrect firmware
2018-05-23 18:40 [dpdk-dev] [PATCH] compress/qat: add compression PMD Fiona Trahe
` (14 preceding siblings ...)
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 14/16] compress/qat: add fns to create and destroy the PMD Fiona Trahe
@ 2018-07-05 16:05 ` Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 16/16] docs/qat: refactor docs adding compression guide Fiona Trahe
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 16:05 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Previous check only causes op to fail on dequeue.
This extends so once first fail is detected, application can
no longer enqueue ops to the device and will also get an
appropriate error if
trying to reconfigure or setup the device.
Change-Id: Ie196fbaa0ab09ecdf5dfb8e4c3059b3d437a53a6
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 57 ++++++++++++++++++++++++++++++++++++-
1 file changed, 56 insertions(+), 1 deletion(-)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 4ff1518..89b7ad6 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -250,6 +250,61 @@ qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
}
+static uint16_t
+qat_comp_pmd_enq_deq_dummy_op_burst(void *qp __rte_unused,
+ struct rte_comp_op **ops __rte_unused,
+ uint16_t nb_ops __rte_unused)
+{
+ QAT_DP_LOG(ERR, "QAT PMD detected wrong FW version !");
+ return 0;
+}
+
+static struct rte_compressdev_ops compress_qat_dummy_ops = {
+
+ /* Device related operations */
+ .dev_configure = NULL,
+ .dev_start = NULL,
+ .dev_stop = qat_comp_dev_stop,
+ .dev_close = qat_comp_dev_close,
+ .dev_infos_get = NULL,
+
+ .stats_get = NULL,
+ .stats_reset = qat_comp_stats_reset,
+ .queue_pair_setup = NULL,
+ .queue_pair_release = qat_comp_qp_release,
+
+ /* Compression related operations */
+ .private_xform_create = NULL,
+ .private_xform_free = qat_comp_private_xform_free
+};
+
+static uint16_t
+qat_comp_pmd_dequeue_frst_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops)
+{
+ uint16_t ret = qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
+ struct qat_qp *tmp_qp = (struct qat_qp *)qp;
+
+ if (ret) {
+ if ((*ops)->debug_status ==
+ (uint64_t)ERR_CODE_QAT_COMP_WRONG_FW) {
+ tmp_qp->qat_dev->comp_dev->compressdev->enqueue_burst =
+ qat_comp_pmd_enq_deq_dummy_op_burst;
+ tmp_qp->qat_dev->comp_dev->compressdev->dequeue_burst =
+ qat_comp_pmd_enq_deq_dummy_op_burst;
+
+ tmp_qp->qat_dev->comp_dev->compressdev->dev_ops =
+ &compress_qat_dummy_ops;
+ QAT_LOG(ERR, "QAT PMD detected wrong FW version !");
+
+ } else {
+ tmp_qp->qat_dev->comp_dev->compressdev->dequeue_burst =
+ qat_comp_pmd_dequeue_op_burst;
+ }
+ }
+ return ret;
+}
+
static struct rte_compressdev_ops compress_qat_ops = {
/* Device related operations */
@@ -300,7 +355,7 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev)
compressdev->dev_ops = &compress_qat_ops;
compressdev->enqueue_burst = qat_comp_pmd_enqueue_op_burst;
- compressdev->dequeue_burst = qat_comp_pmd_dequeue_op_burst;
+ compressdev->dequeue_burst = qat_comp_pmd_dequeue_frst_op_burst;
compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v2 16/16] docs/qat: refactor docs adding compression guide
2018-05-23 18:40 [dpdk-dev] [PATCH] compress/qat: add compression PMD Fiona Trahe
` (15 preceding siblings ...)
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 15/16] compress/qat: prevent device usage if incorrect firmware Fiona Trahe
@ 2018-07-05 16:05 ` Fiona Trahe
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 16:05 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Extend QAT guide to cover crypto and compression and common
informationi, particularly about kernel driver.
Update release note.
Update compression feature ist for qat.
Change-Id: I7d9bde8b71d23e5e160170243ae4705aaa4cff3d
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
config/common_base | 2 +-
doc/guides/compressdevs/features/qat.ini | 22 ++++
doc/guides/compressdevs/index.rst | 1 +
doc/guides/compressdevs/qat_comp.rst | 49 +++++++++
doc/guides/cryptodevs/qat.rst | 183 +++++++++++++++++++++----------
doc/guides/rel_notes/release_18_08.rst | 5 +
6 files changed, 203 insertions(+), 59 deletions(-)
create mode 100644 doc/guides/compressdevs/features/qat.ini
create mode 100644 doc/guides/compressdevs/qat_comp.rst
diff --git a/config/common_base b/config/common_base
index 93c8857..402231d 100644
--- a/config/common_base
+++ b/config/common_base
@@ -482,7 +482,7 @@ CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4
CONFIG_RTE_DPAA_SEC_PMD_MAX_NB_SESSIONS=2048
#
-# Compile PMD for QuickAssist based devices
+# Compile PMD for QuickAssist based devices - see docs for details
#
CONFIG_RTE_LIBRTE_PMD_QAT=y
CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
diff --git a/doc/guides/compressdevs/features/qat.ini b/doc/guides/compressdevs/features/qat.ini
new file mode 100644
index 0000000..68f36c8
--- /dev/null
+++ b/doc/guides/compressdevs/features/qat.ini
@@ -0,0 +1,22 @@
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+; Supported features of 'QAT' compression driver.
+;
+[Features]
+HW Accelerated = Y
+CPU SSE =
+CPU AVX =
+CPU AVX2 =
+CPU AVX512 =
+CPU NEON =
+Stateful =
+By-Pass =
+Chained mbufs =
+Deflate = Y
+LZS =
+Adler32 = Y
+Crc32 = Y
+Adler32&Crc32 = Y
+Fixed = Y
+Dynamic =
diff --git a/doc/guides/compressdevs/index.rst b/doc/guides/compressdevs/index.rst
index bc59ce8..4228768 100644
--- a/doc/guides/compressdevs/index.rst
+++ b/doc/guides/compressdevs/index.rst
@@ -11,3 +11,4 @@ Compression Device Drivers
overview
isal
+ qat_comp
diff --git a/doc/guides/compressdevs/qat_comp.rst b/doc/guides/compressdevs/qat_comp.rst
new file mode 100644
index 0000000..167f816
--- /dev/null
+++ b/doc/guides/compressdevs/qat_comp.rst
@@ -0,0 +1,49 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+ Copyright(c) 2018 Intel Corporation.
+
+Intel(R) QuickAssist (QAT) Compression Poll Mode Driver
+=======================================================
+
+The QAT compression PMD provides poll mode compression & decompression driver
+support for the following hardware accelerator devices:
+
+* ``Intel QuickAssist Technology C62x``
+* ``Intel QuickAssist Technology C3xxx``
+
+
+Features
+--------
+
+QAT compression PMD has support for:
+
+Compression/Decompression algorithm:
+
+ * DEFLATE
+
+Huffman code type:
+
+ * FIXED
+
+Window size support:
+
+ * 32K
+
+Checksum generation:
+
+ * CRC32, Adler and combined checksum
+
+Limitations
+-----------
+
+* Chained mbufs are not yet supported, therefore max data size which can be passed to the PMD in a single mbuf is 64K - 1. If data is larger than this it will need to be split up and sent as multiple operations.
+
+* Compressdev level 0, no compression, is not supported.
+
+* Dynamic Huffman encoding is not yet supported.
+
+Installation
+------------
+
+The QAT compression PMD is built by default with a standard DPDK build.
+
+It depends on a QAT kernel driver, see :ref:`qat_kernel_installation`.
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index b899985..bdc58eb 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -68,12 +68,32 @@ Limitations
* Queue pairs are not thread-safe (that is, within a single queue pair, RX and TX from different lcores is not supported).
-Installation
-------------
+Extra notes on KASUMI F9
+------------------------
+
+When using KASUMI F9 authentication algorithm, the input buffer must be
+constructed according to the 3GPP KASUMI specifications (section 4.4, page 13):
+`<http://cryptome.org/3gpp/35201-900.pdf>`_.
+Input buffer has to have COUNT (4 bytes), FRESH (4 bytes), MESSAGE and DIRECTION (1 bit)
+concatenated. After the DIRECTION bit, a single '1' bit is appended, followed by
+between 0 and 7 '0' bits, so that the total length of the buffer is multiple of 8 bits.
+Note that the actual message can be any length, specified in bits.
-To enable QAT in DPDK, follow the instructions for modifying the compile-time
+Once this buffer is passed this way, when creating the crypto operation,
+length of data to authenticate (op.sym.auth.data.length) must be the length
+of all the items described above, including the padding at the end.
+Also, offset of data to authenticate (op.sym.auth.data.offset)
+must be such that points at the start of the COUNT bytes.
+
+
+Building the DPDK QAT cryptodev PMD
+-----------------------------------
+
+
+To enable QAT crypto in DPDK, follow the instructions for modifying the compile-time
configuration file as described `here <http://dpdk.org/doc/guides/linux_gsg/build_dpdk.html>`_.
+
Quick instructions are as follows:
.. code-block:: console
@@ -81,29 +101,95 @@ Quick instructions are as follows:
cd to the top-level DPDK directory
make config T=x86_64-native-linuxapp-gcc
sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT\)=n,\1=y,' build/.config
+ sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT_SYM\)=n,\1=y,' build/.config
make
-To use the DPDK QAT PMD an SRIOV-enabled QAT kernel driver is required. The VF
-devices exposed by this driver will be used by the QAT PMD. The devices and
-available kernel drivers and device ids are :
+
+.. _qat_kernel_installation:
+
+Dependency on the QAT kernel driver
+-----------------------------------
+
+To use the QAT PMD an SRIOV-enabled QAT kernel driver is required. The VF
+devices created and initialised by this driver will be used by the QAT PMD.
+
+Instructions for installation are below, but first an explanation of the
+relationships between the PF/VF devices and the PMDs visible to
+DPDK applications.
+
+
+Acceleration services - cryptography and compression - are provided to DPDK
+applications via PMDs which register to implement the corresponding
+cryptodev and compressdev APIs.
+
+Each QuickAssist VF device can expose one cryptodev PMD and/or one compressdev PMD.
+These QAT PMDs share the same underlying device and pci-mgmt code, but are
+enumerated independently on their respective APIs and appear as independent
+devices to applications.
+
+.. Note::
+
+ Each VF can only be used by one DPDK process. It is not possible to share
+ the same VF across multiple processes, even if these processes are using
+ different acceleration services.
+
+ Conversely one DPDK process can use one or more QAT VFs and can expose both
+ cryptodev and compressdev instances on each of those VFs.
+
+
+
+Device and driver naming
+------------------------
+
+* The qat cryptodev driver name is "crypto_qat".
+ The rte_cryptodev_devices_get() returns the devices exposed by this driver.
+
+* Each qat crypto device has a unique name, in format
+ <pci bdf>_<service>, e.g. "0000:41:01.0_qat_sym".
+ This name can be passed to rte_cryptodev_get_dev_id() to get the device_id.
+
+.. Note::
+
+ The qat crypto driver name is passed to the dpdk-test-crypto-perf tool in the -devtype parameter.
+
+ The qat crypto device name is in the format of the slave parameter passed to the crypto scheduler.
+
+* The qat compressdev driver name is "comp_qat".
+ The rte_compressdev_devices_get() returns the devices exposed by this driver.
+
+* Each qat compression device has a unique name, in format
+ <pci bdf>_<service>, e.g. "0000:41:01.0_qat_comp".
+ This name can be passed to rte_compressdev_get_dev_id() to get the device_id.
+
+
+Available kernel drivers
+------------------------
+
+Kernel drivers for each device are listed in the following table. Scroll right
+to check that the driver and device supports the servic you require.
+
.. _table_qat_pmds_drivers:
.. table:: QAT device generations, devices and drivers
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | Gen | Device | Driver | Kernel Module | Pci Driver | PF Did | #PFs | Vf Did | VFs/PF |
- +=====+==========+========+===============+============+========+======+========+========+
- | 1 | DH895xCC | 01.org | icp_qa_al | n/a | 435 | 1 | 443 | 32 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | 1 | DH895xCC | 4.4+ | qat_dh895xcc | dh895xcc | 435 | 1 | 443 | 32 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | 2 | C62x | 4.5+ | qat_c62x | c6xx | 37c8 | 3 | 37c9 | 16 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | 2 | C3xxx | 4.5+ | qat_c3xxx | c3xxx | 19e2 | 1 | 19e3 | 16 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | 2 | D15xx | p | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | Gen | Device | Driver/ver | Kernel Module | Pci Driver | PF Did | #PFs | VF Did | VFs/PF | cryptodev | compressdev |
+ +=====+==========+===============+===============+============+========+======+========+========+===========+=============+
+ | 1 | DH895xCC | linux/4.4+ | qat_dh895xcc | dh895xcc | 435 | 1 | 443 | 32 | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | 2 | C62x | linux/4.5+ | qat_c62x | c6xx | 37c8 | 3 | 37c9 | 16 | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | Yes | Yes |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | 2 | C3xxx | linux/4.5+ | qat_c3xxx | c3xxx | 19e2 | 1 | 19e3 | 16 | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | Yes | Yes |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | 2 | D15xx | p | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
The ``Driver`` column indicates either the Linux kernel version in which
@@ -196,9 +282,9 @@ Consult the *Getting Started Guide* at the same URL for further information.
The steps below assume you are:
-* Building on a platform with one ``DH895xCC`` device.
-* Using package ``qatmux.l.2.3.0-34.tgz``.
-* On Fedora21 kernel ``3.17.4-301.fc21.x86_64``.
+* Building on a platform with one ``C62x`` device.
+* Using package ``qat1.7.l.4.2.0-000xx.tar.gz``.
+* On Fedora26 kernel ``4.11.11-300.fc26.x86_64``.
In the BIOS ensure that SRIOV is enabled and VT-d is disabled.
@@ -206,21 +292,30 @@ Uninstall any existing QAT driver, for example by running:
* ``./installer.sh uninstall`` in the directory where originally installed.
-* or ``rmmod qat_dh895xcc; rmmod intel_qat``.
Build and install the SRIOV-enabled QAT driver::
mkdir /QAT
cd /QAT
- # Copy qatmux.l.2.3.0-34.tgz to this location
- tar zxof qatmux.l.2.3.0-34.tgz
+ # Copy the package to this location and unpack
+ tar zxof qat1.7.l.4.2.0-000xx.tar.gz
- export ICP_WITHOUT_IOMMU=1
- ./installer.sh install QAT1.6 host
+ ./configure --enable-icp-sriov=host
+ make install
+
+You can use ``cat /sys/kernel/debug/qat<your device type and bdf>/version/fw`` to confirm the driver is correctly installed and is using firmware version 4.2.0.
+You can use ``lspci -d:37c9`` to confirm the presence of the 16 VF devices available per ``C62x`` PF.
+
+Confirm the driver is correctly installed and is using firmware version 4.2.0::
+
+ cat /sys/kernel/debug/qat<your device type and bdf>/version/fw
+
+
+Confirm the presence of 48 VF devices - 16 per PF::
+
+ lspci -d:37c9
-You can use ``cat /proc/icp_dh895xcc_dev0/version`` to confirm the driver is correctly installed.
-You can use ``lspci -d:443`` to confirm the of the 32 VF devices available per ``DH895xCC`` device.
To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_.
@@ -261,6 +356,7 @@ To complete the installation - follow instructions in `Binding the available VFs
sudo yum install zlib-devel
sudo yum install openssl-devel
+ sudo yum install libudev-devel
.. Note::
@@ -343,35 +439,6 @@ Another way to bind the VFs to the DPDK UIO driver is by using the
./usertools/dpdk-devbind.py -b igb_uio 0000:03:01.1
-Extra notes on KASUMI F9
-------------------------
-
-When using KASUMI F9 authentication algorithm, the input buffer must be
-constructed according to the 3GPP KASUMI specifications (section 4.4, page 13):
-`<http://cryptome.org/3gpp/35201-900.pdf>`_.
-Input buffer has to have COUNT (4 bytes), FRESH (4 bytes), MESSAGE and DIRECTION (1 bit)
-concatenated. After the DIRECTION bit, a single '1' bit is appended, followed by
-between 0 and 7 '0' bits, so that the total length of the buffer is multiple of 8 bits.
-Note that the actual message can be any length, specified in bits.
-
-Once this buffer is passed this way, when creating the crypto operation,
-length of data to authenticate (op.sym.auth.data.length) must be the length
-of all the items described above, including the padding at the end.
-Also, offset of data to authenticate (op.sym.auth.data.offset)
-must be such that points at the start of the COUNT bytes.
-
-Device and driver naming
-------------------------
-
-The qat crypto driver name is "crypto_qat".
-This name is passed to the dpdk-test-crypto-perf tool in the -devtype parameter.
-The rte_cryptodev_devices_get() can return the devices exposed by a driver.
-
-Each qat crypto device has a unique name, in format
-<pci bdf>_<service>, e.g. "0000:41:01.0_qat_sym".
-This name can be passed to rte_cryptodev_get_dev_id() to get the device_id.
-This is also the format of the slave parameter passed to the crypto scheduler.
-
Debugging
----------------------------------------
diff --git a/doc/guides/rel_notes/release_18_08.rst b/doc/guides/rel_notes/release_18_08.rst
index bc01242..2230d3e 100644
--- a/doc/guides/rel_notes/release_18_08.rst
+++ b/doc/guides/rel_notes/release_18_08.rst
@@ -46,6 +46,11 @@ New Features
Flow API support has been added to CXGBE Poll Mode Driver to offload
flows to Chelsio T5/T6 NICs.
+* **Added a new compression PMD using Intel's QuickAssist (QAT) device family.**
+
+ Added the new ``QAT`` compression driver, for compression and decompression
+ operations in software. See the :doc:`../compressdevs/qat_comp` compression
+ driver guide for details on this new driver.
API Changes
-----------
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v3 00/16] compress/qat: add compression PMD
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 00/16] " Fiona Trahe
@ 2018-07-05 17:32 ` Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 " Fiona Trahe
` (16 more replies)
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 01/16] common/qat: updated firmware headers Fiona Trahe
` (15 subsequent siblings)
16 siblings, 17 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 17:32 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Create compression PMD for Intel QuickAssist devices
Currently only the C62x and c3xxx devices are supported.
The qat comp PMD supports
- stateless compression and
decompression using the Deflate algorithm with Fixed Huffman
encoding. Dynamic huffman encoding is not supported, it
will be added in a later patch.
- checksum generation: Adler32, CRC32 and combined.
The compression service is hosted on a QuickAssist VF PCI
device, which is managed by code in the
drivers/common/qat directory.
This patch is dependent on the cryptodev API patch re Huffman Encoding capability
https://patches.dpdk.org/patch/42286/
v3 changes:
- only commit message changes, i.e. removed ChangeId and fixed typos
v2 changes:
- Added check for correct firmware
- Split patchset
- Added documentation
- removed support for scatter-gather-lists and related config flag
- Removed support for Dynamic huffman encoding and related IM buffer config flag
- Removed support for DH895xcc device
Fiona Trahe (16):
common/qat: updated firmware headers
compress/qat: add makefiles for PMD
compress/qat: add meson build
compress/qat: add xform processing
compress/qat: create fw request and process response
compress/qat: check that correct firmware is in use
compress/qat: add stats functions
compress/qat: setup queue-pairs for compression service
compress/qat: add fns to configure and clear device
compress/qat: add fn to return device info
compress/qat: add enqueue/dequeue functions
compress/qat: add device start and stop fns
compress/qat: create and populate the ops structure
compress/qat: add fns to create and destroy the PMD
compress/qat: prevent device usage if incorrect firmware
docs/qat: refactor docs adding compression guide
MAINTAINERS | 4 +
config/common_base | 5 +-
doc/guides/compressdevs/features/qat.ini | 22 ++
doc/guides/compressdevs/index.rst | 1 +
doc/guides/compressdevs/qat_comp.rst | 49 +++
doc/guides/cryptodevs/qat.rst | 183 ++++++----
doc/guides/rel_notes/release_18_08.rst | 5 +
drivers/common/qat/Makefile | 48 ++-
drivers/common/qat/qat_adf/icp_qat_fw.h | 69 +++-
drivers/common/qat/qat_adf/icp_qat_fw_comp.h | 482 +++++++++++++++++++++++++++
drivers/common/qat/qat_adf/icp_qat_hw.h | 130 +++++++-
drivers/common/qat/qat_device.h | 4 +
drivers/common/qat/qat_qp.c | 11 +-
drivers/common/qat/qat_qp.h | 5 +
drivers/compress/meson.build | 2 +-
drivers/compress/qat/meson.build | 18 +
drivers/compress/qat/qat_comp.c | 359 ++++++++++++++++++++
drivers/compress/qat/qat_comp.h | 56 ++++
drivers/compress/qat/qat_comp_pmd.c | 405 ++++++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 39 +++
drivers/compress/qat/rte_pmd_qat_version.map | 3 +
drivers/crypto/qat/meson.build | 10 +-
drivers/crypto/qat/rte_pmd_qat_version.map | 3 -
test/test/test_cryptodev.c | 6 +-
24 files changed, 1804 insertions(+), 115 deletions(-)
create mode 100644 doc/guides/compressdevs/features/qat.ini
create mode 100644 doc/guides/compressdevs/qat_comp.rst
create mode 100644 drivers/common/qat/qat_adf/icp_qat_fw_comp.h
create mode 100644 drivers/compress/qat/meson.build
create mode 100644 drivers/compress/qat/qat_comp.c
create mode 100644 drivers/compress/qat/qat_comp.h
create mode 100644 drivers/compress/qat/qat_comp_pmd.c
create mode 100644 drivers/compress/qat/qat_comp_pmd.h
create mode 100644 drivers/compress/qat/rte_pmd_qat_version.map
delete mode 100644 drivers/crypto/qat/rte_pmd_qat_version.map
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v3 01/16] common/qat: updated firmware headers
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 00/16] " Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 " Fiona Trahe
@ 2018-07-05 17:32 ` Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 02/16] compress/qat: add makefiles for PMD Fiona Trahe
` (14 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 17:32 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Updated to latest firmware headers files for QuickAssist devices.
Includes updates for symmetric crypto, PKE and Compression services.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
drivers/common/qat/qat_adf/icp_qat_fw.h | 69 +++-
drivers/common/qat/qat_adf/icp_qat_fw_comp.h | 482 +++++++++++++++++++++++++++
drivers/common/qat/qat_adf/icp_qat_hw.h | 130 +++++++-
3 files changed, 654 insertions(+), 27 deletions(-)
create mode 100644 drivers/common/qat/qat_adf/icp_qat_fw_comp.h
diff --git a/drivers/common/qat/qat_adf/icp_qat_fw.h b/drivers/common/qat/qat_adf/icp_qat_fw.h
index ae39b7f..8f7cb37 100644
--- a/drivers/common/qat/qat_adf/icp_qat_fw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_fw.h
@@ -117,6 +117,10 @@ struct icp_qat_fw_comn_resp {
#define ICP_QAT_FW_COMN_VALID_FLAG_BITPOS 7
#define ICP_QAT_FW_COMN_VALID_FLAG_MASK 0x1
#define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK 0x7F
+#define ICP_QAT_FW_COMN_CNV_FLAG_BITPOS 6
+#define ICP_QAT_FW_COMN_CNV_FLAG_MASK 0x1
+#define ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS 5
+#define ICP_QAT_FW_COMN_CNVNR_FLAG_MASK 0x1
#define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \
icp_qat_fw_comn_req_hdr_t.service_type
@@ -133,6 +137,16 @@ struct icp_qat_fw_comn_resp {
#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_GET(hdr_t) \
ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_t.hdr_flags)
+#define ICP_QAT_FW_COMN_HDR_CNVNR_FLAG_GET(hdr_flags) \
+ QAT_FIELD_GET(hdr_flags, \
+ ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS, \
+ ICP_QAT_FW_COMN_CNVNR_FLAG_MASK)
+
+#define ICP_QAT_FW_COMN_HDR_CNV_FLAG_GET(hdr_flags) \
+ QAT_FIELD_GET(hdr_flags, \
+ ICP_QAT_FW_COMN_CNV_FLAG_BITPOS, \
+ ICP_QAT_FW_COMN_CNV_FLAG_MASK)
+
#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_SET(hdr_t, val) \
ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val)
@@ -204,29 +218,44 @@ struct icp_qat_fw_comn_resp {
& ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)); }
+#define ICP_QAT_FW_COMN_NEXT_ID_SET_2(next_curr_id, val) \
+ do { \
+ (next_curr_id) = \
+ (((next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK) | \
+ (((val) << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) & \
+ ICP_QAT_FW_COMN_NEXT_ID_MASK)) \
+ } while (0)
+
+#define ICP_QAT_FW_COMN_CURR_ID_SET_2(next_curr_id, val) \
+ do { \
+ (next_curr_id) = \
+ (((next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
+ ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) \
+ } while (0)
+
#define QAT_COMN_RESP_CRYPTO_STATUS_BITPOS 7
#define QAT_COMN_RESP_CRYPTO_STATUS_MASK 0x1
+#define QAT_COMN_RESP_PKE_STATUS_BITPOS 6
+#define QAT_COMN_RESP_PKE_STATUS_MASK 0x1
#define QAT_COMN_RESP_CMP_STATUS_BITPOS 5
#define QAT_COMN_RESP_CMP_STATUS_MASK 0x1
#define QAT_COMN_RESP_XLAT_STATUS_BITPOS 4
#define QAT_COMN_RESP_XLAT_STATUS_MASK 0x1
#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS 3
#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1
-
-#define ICP_QAT_FW_COMN_RESP_STATUS_BUILD(crypto, comp, xlat, eolb) \
- ((((crypto) & QAT_COMN_RESP_CRYPTO_STATUS_MASK) << \
- QAT_COMN_RESP_CRYPTO_STATUS_BITPOS) | \
- (((comp) & QAT_COMN_RESP_CMP_STATUS_MASK) << \
- QAT_COMN_RESP_CMP_STATUS_BITPOS) | \
- (((xlat) & QAT_COMN_RESP_XLAT_STATUS_MASK) << \
- QAT_COMN_RESP_XLAT_STATUS_BITPOS) | \
- (((eolb) & QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK) << \
- QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS))
+#define QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS 2
+#define QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK 0x1
+#define QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS 0
+#define QAT_COMN_RESP_XLT_WA_APPLIED_MASK 0x1
#define ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(status) \
QAT_FIELD_GET(status, QAT_COMN_RESP_CRYPTO_STATUS_BITPOS, \
QAT_COMN_RESP_CRYPTO_STATUS_MASK)
+#define ICP_QAT_FW_COMN_RESP_PKE_STAT_GET(status) \
+ QAT_FIELD_GET(status, QAT_COMN_RESP_PKE_STATUS_BITPOS, \
+ QAT_COMN_RESP_PKE_STATUS_MASK)
+
#define ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(status) \
QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_STATUS_BITPOS, \
QAT_COMN_RESP_CMP_STATUS_MASK)
@@ -235,10 +264,18 @@ struct icp_qat_fw_comn_resp {
QAT_FIELD_GET(status, QAT_COMN_RESP_XLAT_STATUS_BITPOS, \
QAT_COMN_RESP_XLAT_STATUS_MASK)
+#define ICP_QAT_FW_COMN_RESP_XLT_WA_APPLIED_GET(status) \
+ QAT_FIELD_GET(status, QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS, \
+ QAT_COMN_RESP_XLT_WA_APPLIED_MASK)
+
#define ICP_QAT_FW_COMN_RESP_CMP_END_OF_LAST_BLK_FLAG_GET(status) \
QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS, \
QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK)
+#define ICP_QAT_FW_COMN_RESP_UNSUPPORTED_REQUEST_STAT_GET(status) \
+ QAT_FIELD_GET(status, QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS, \
+ QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK)
+
#define ICP_QAT_FW_COMN_STATUS_FLAG_OK 0
#define ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 1
#define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0
@@ -257,8 +294,16 @@ struct icp_qat_fw_comn_resp {
#define ERR_CODE_OVERFLOW_ERROR -11
#define ERR_CODE_SOFT_ERROR -12
#define ERR_CODE_FATAL_ERROR -13
-#define ERR_CODE_SSM_ERROR -14
-#define ERR_CODE_ENDPOINT_ERROR -15
+#define ERR_CODE_COMP_OUTPUT_CORRUPTION -14
+#define ERR_CODE_HW_INCOMPLETE_FILE -15
+#define ERR_CODE_SSM_ERROR -16
+#define ERR_CODE_ENDPOINT_ERROR -17
+#define ERR_CODE_CNV_ERROR -18
+#define ERR_CODE_EMPTY_DYM_BLOCK -19
+#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_HANDLE -20
+#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_HMAC_FAILED -21
+#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_WRAPPING_ALGO -22
+#define ERR_CODE_KPT_DRNG_SEED_NOT_LOAD -23
enum icp_qat_fw_slice {
ICP_QAT_FW_SLICE_NULL = 0,
diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_comp.h b/drivers/common/qat/qat_adf/icp_qat_fw_comp.h
new file mode 100644
index 0000000..8138177
--- /dev/null
+++ b/drivers/common/qat/qat_adf/icp_qat_fw_comp.h
@@ -0,0 +1,482 @@
+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+#ifndef _ICP_QAT_FW_COMP_H_
+#define _ICP_QAT_FW_COMP_H_
+
+#include "icp_qat_fw.h"
+
+enum icp_qat_fw_comp_cmd_id {
+ ICP_QAT_FW_COMP_CMD_STATIC = 0,
+ /*!< Static Compress Request */
+
+ ICP_QAT_FW_COMP_CMD_DYNAMIC = 1,
+ /*!< Dynamic Compress Request */
+
+ ICP_QAT_FW_COMP_CMD_DECOMPRESS = 2,
+ /*!< Decompress Request */
+
+ ICP_QAT_FW_COMP_CMD_DELIMITER
+ /**< Delimiter type */
+};
+
+/**< Flag usage */
+
+#define ICP_QAT_FW_COMP_STATELESS_SESSION 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that session is stateless
+ */
+
+#define ICP_QAT_FW_COMP_STATEFUL_SESSION 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that session is stateful
+ */
+
+#define ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that autoselectbest is NOT used
+ */
+
+#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that autoselectbest is used
+ */
+
+#define ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is NOT used
+ */
+
+#define ICP_QAT_FW_COMP_ENH_AUTO_SELECT_BEST 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is used
+ */
+
+#define ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is NOT used
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is used
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_USED_AS_INTMD_BUF 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing secure RAM from being used as
+ * an intermediate buffer is DISABLED.
+ */
+
+#define ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing secure RAM from being used as
+ * an intermediate buffer is ENABLED.
+ */
+
+/**< Flag mask & bit position */
+
+#define ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS 2
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the session type
+ */
+
+#define ICP_QAT_FW_COMP_SESSION_TYPE_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask used to determine the session type
+ */
+
+#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS 3
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for auto select best
+ */
+
+#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for auto select best
+ */
+
+#define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS 4
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for enhanced auto select best
+ */
+
+#define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for enhanced auto select best
+ */
+
+#define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS 5
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for disabling type zero header write back
+ * when Enhanced autoselect best is enabled. If set firmware does
+ * not return type0 store block header, only copies src to dest.
+ * (if best output is Type0)
+ */
+
+#define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for auto select best
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS 7
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for flag used to disable secure ram from
+ * being used as an intermediate buffer.
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for disable secure ram for use as an intermediate
+ * buffer.
+ */
+
+#define ICP_QAT_FW_COMP_FLAGS_BUILD(sesstype, autoselect, enhanced_asb, \
+ ret_uncomp, secure_ram) \
+ ((((sesstype)&ICP_QAT_FW_COMP_SESSION_TYPE_MASK) \
+ << ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS) | \
+ (((autoselect)&ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK) \
+ << ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS) | \
+ (((enhanced_asb)&ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK) \
+ << ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS) | \
+ (((ret_uncomp)&ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK) \
+ << ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS) | \
+ (((secure_ram)&ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK) \
+ << ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS))
+
+union icp_qat_fw_comp_req_hdr_cd_pars {
+ /**< LWs 2-5 */
+ struct {
+ uint64_t content_desc_addr;
+ /**< Address of the content descriptor */
+
+ uint16_t content_desc_resrvd1;
+ /**< Content descriptor reserved field */
+
+ uint8_t content_desc_params_sz;
+ /**< Size of the content descriptor parameters in quad words.
+ * These parameters describe the session setup configuration
+ * info for the slices that this request relies upon i.e.
+ * the configuration word and cipher key needed by the cipher
+ * slice if there is a request for cipher processing.
+ */
+
+ uint8_t content_desc_hdr_resrvd2;
+ /**< Content descriptor reserved field */
+
+ uint32_t content_desc_resrvd3;
+ /**< Content descriptor reserved field */
+ } s;
+
+ struct {
+ uint32_t comp_slice_cfg_word[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /* Compression Slice Config Word */
+
+ uint32_t content_desc_resrvd4;
+ /**< Content descriptor reserved field */
+
+ } sl;
+
+};
+
+struct icp_qat_fw_comp_req_params {
+ /**< LW 14 */
+ uint32_t comp_len;
+ /**< Size of input to process in bytes Note: Only EOP requests can be
+ * odd for decompression. IA must set LSB to zero for odd sized
+ * intermediate inputs
+ */
+
+ /**< LW 15 */
+ uint32_t out_buffer_sz;
+ /**< Size of output buffer in bytes */
+
+ /**< LW 16 */
+ uint32_t initial_crc32;
+ /**< CRC of previously processed bytes */
+
+ /**< LW 17 */
+ uint32_t initial_adler;
+ /**< Adler of previously processed bytes */
+
+ /**< LW 18 */
+ uint32_t req_par_flags;
+
+ /**< LW 19 */
+ uint32_t rsrvd;
+};
+
+#define ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(sop, eop, bfinal, cnv, cnvnr) \
+ ((((sop)&ICP_QAT_FW_COMP_SOP_MASK) << ICP_QAT_FW_COMP_SOP_BITPOS) | \
+ (((eop)&ICP_QAT_FW_COMP_EOP_MASK) << ICP_QAT_FW_COMP_EOP_BITPOS) | \
+ (((bfinal)&ICP_QAT_FW_COMP_BFINAL_MASK) \
+ << ICP_QAT_FW_COMP_BFINAL_BITPOS) | \
+ ((cnv & ICP_QAT_FW_COMP_CNV_MASK) << ICP_QAT_FW_COMP_CNV_BITPOS) | \
+ ((cnvnr & ICP_QAT_FW_COMP_CNV_RECOVERY_MASK) \
+ << ICP_QAT_FW_COMP_CNV_RECOVERY_BITPOS))
+
+#define ICP_QAT_FW_COMP_NOT_SOP 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request is NOT Start of Packet
+ */
+
+#define ICP_QAT_FW_COMP_SOP 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request IS Start of Packet
+ */
+
+#define ICP_QAT_FW_COMP_NOT_EOP 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request is NOT Start of Packet
+ */
+
+#define ICP_QAT_FW_COMP_EOP 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request IS End of Packet
+ */
+
+#define ICP_QAT_FW_COMP_NOT_BFINAL 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing to indicate firmware this is not the last block
+ */
+
+#define ICP_QAT_FW_COMP_BFINAL 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing to indicate firmware this is the last block
+ */
+
+#define ICP_QAT_FW_COMP_NO_CNV 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that NO cnv check is to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_CNV 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that a cnv check IS to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_NO_CNV_RECOVERY 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that NO cnv recovery is to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_CNV_RECOVERY 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that a cnv recovery is to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_SOP_BITPOS 0
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for SOP
+ */
+
+#define ICP_QAT_FW_COMP_SOP_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask used to determine SOP
+ */
+
+#define ICP_QAT_FW_COMP_EOP_BITPOS 1
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for EOP
+ */
+
+#define ICP_QAT_FW_COMP_EOP_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask used to determine EOP
+ */
+
+#define ICP_QAT_FW_COMP_BFINAL_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for the bfinal bit
+ */
+
+#define ICP_QAT_FW_COMP_BFINAL_BITPOS 6
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the bfinal bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for the CNV bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_BITPOS 16
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the CNV bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_RECOVERY_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for the CNV Recovery bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_RECOVERY_BITPOS 17
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the CNV Recovery bit
+ */
+
+struct icp_qat_fw_xlt_req_params {
+ /**< LWs 20-21 */
+ uint64_t inter_buff_ptr;
+ /**< This field specifies the physical address of an intermediate
+ * buffer SGL array. The array contains a pair of 64-bit
+ * intermediate buffer pointers to SGL buffer descriptors, one pair
+ * per CPM. Please refer to the CPM1.6 Firmware Interface HLD
+ * specification for more details.
+ */
+};
+
+
+struct icp_qat_fw_comp_cd_hdr {
+ /**< LW 24 */
+ uint16_t ram_bank_flags;
+ /**< Flags to show which ram banks to access */
+
+ uint8_t comp_cfg_offset;
+ /**< Quad word offset from the content descriptor parameters address
+ * to the parameters for the compression processing
+ */
+
+ uint8_t next_curr_id;
+ /**< This field combines the next and current id (each four bits) -
+ * the next id is the most significant nibble.
+ * Next Id: Set to the next slice to pass the compressed data through.
+ * Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through
+ * anymore slices after compression
+ * Current Id: Initialised with the compression slice type
+ */
+
+ /**< LW 25 */
+ uint32_t resrvd;
+ /**< LWs 26-27 */
+
+ uint64_t comp_state_addr;
+ /**< Pointer to compression state */
+
+ /**< LWs 28-29 */
+ uint64_t ram_banks_addr;
+ /**< Pointer to banks */
+
+};
+
+
+struct icp_qat_fw_xlt_cd_hdr {
+ /**< LW 30 */
+ uint16_t resrvd1;
+ /**< Reserved field and assumed set to 0 */
+
+ uint8_t resrvd2;
+ /**< Reserved field and assumed set to 0 */
+
+ uint8_t next_curr_id;
+ /**< This field combines the next and current id (each four bits) -
+ * the next id is the most significant nibble.
+ * Next Id: Set to the next slice to pass the translated data through.
+ * Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through
+ * any more slices after compression
+ * Current Id: Initialised with the translation slice type
+ */
+
+ /**< LW 31 */
+ uint32_t resrvd3;
+ /**< Reserved and should be set to zero, needed for quadword
+ * alignment
+ */
+};
+
+struct icp_qat_fw_comp_req {
+ /**< LWs 0-1 */
+ struct icp_qat_fw_comn_req_hdr comn_hdr;
+ /**< Common request header - for Service Command Id,
+ * use service-specific Compression Command Id.
+ * Service Specific Flags - use Compression Command Flags
+ */
+
+ /**< LWs 2-5 */
+ union icp_qat_fw_comp_req_hdr_cd_pars cd_pars;
+ /**< Compression service-specific content descriptor field which points
+ * either to a content descriptor parameter block or contains the
+ * compression slice config word.
+ */
+
+ /**< LWs 6-13 */
+ struct icp_qat_fw_comn_req_mid comn_mid;
+ /**< Common request middle section */
+
+ /**< LWs 14-19 */
+ struct icp_qat_fw_comp_req_params comp_pars;
+ /**< Compression request Parameters block */
+
+ /**< LWs 20-21 */
+ union {
+ struct icp_qat_fw_xlt_req_params xlt_pars;
+ /**< Translation request Parameters block */
+ uint32_t resrvd1[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /**< Reserved if not used for translation */
+
+ } u1;
+
+ /**< LWs 22-23 */
+ union {
+ uint32_t resrvd2[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /**< Reserved - not used if Batch and Pack is disabled.*/
+
+ uint64_t bnp_res_table_addr;
+ /**< A generic pointer to the unbounded list of
+ * icp_qat_fw_resp_comp_pars members. This pointer is only
+ * used when the Batch and Pack is enabled.
+ */
+ } u3;
+
+ /**< LWs 24-29 */
+ struct icp_qat_fw_comp_cd_hdr comp_cd_ctrl;
+ /**< Compression request content descriptor control block header */
+
+ /**< LWs 30-31 */
+ union {
+ struct icp_qat_fw_xlt_cd_hdr xlt_cd_ctrl;
+ /**< Translation request content descriptor
+ * control block header
+ */
+
+ uint32_t resrvd3[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /**< Reserved if not used for translation */
+ } u2;
+};
+
+struct icp_qat_fw_resp_comp_pars {
+ /**< LW 4 */
+ uint32_t input_byte_counter;
+ /**< Input byte counter */
+
+ /**< LW 5 */
+ uint32_t output_byte_counter;
+ /**< Output byte counter */
+
+ /**< LW 6 & 7*/
+ union {
+ uint64_t curr_chksum;
+ struct {
+ /**< LW 6 */
+ uint32_t curr_crc32;
+ /**< LW 7 */
+ uint32_t curr_adler_32;
+ };
+ };
+};
+
+struct icp_qat_fw_comp_resp {
+ /**< LWs 0-1 */
+ struct icp_qat_fw_comn_resp_hdr comn_resp;
+ /**< Common interface response format see icp_qat_fw.h */
+
+ /**< LWs 2-3 */
+ uint64_t opaque_data;
+ /**< Opaque data passed from the request to the response message */
+
+ /**< LWs 4-7 */
+ struct icp_qat_fw_resp_comp_pars comp_resp_pars;
+ /**< Common response params (checksums and byte counts) */
+};
+
+#endif
diff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h b/drivers/common/qat/qat_adf/icp_qat_hw.h
index 56e3cf7..e7961db 100644
--- a/drivers/common/qat/qat_adf/icp_qat_hw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_hw.h
@@ -72,19 +72,44 @@ struct icp_qat_hw_auth_config {
#define QAT_AUTH_ALGO_MASK 0xF
#define QAT_AUTH_CMP_BITPOS 8
#define QAT_AUTH_CMP_MASK 0x7F
-#define QAT_AUTH_SHA3_PADDING_BITPOS 16
-#define QAT_AUTH_SHA3_PADDING_MASK 0x1
+#define QAT_AUTH_SHA3_PADDING_DISABLE_BITPOS 16
+#define QAT_AUTH_SHA3_PADDING_DISABLE_MASK 0x1
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_BITPOS 17
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_MASK 0x1
#define QAT_AUTH_ALGO_SHA3_BITPOS 22
#define QAT_AUTH_ALGO_SHA3_MASK 0x3
-#define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \
- (((mode & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \
- ((algo & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \
- (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) << \
- QAT_AUTH_ALGO_SHA3_BITPOS) | \
- (((((algo == ICP_QAT_HW_AUTH_ALGO_SHA3_256) || \
- (algo == ICP_QAT_HW_AUTH_ALGO_SHA3_512)) ? 1 : 0) \
- & QAT_AUTH_SHA3_PADDING_MASK) << QAT_AUTH_SHA3_PADDING_BITPOS) | \
- ((cmp_len & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
+#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_BITPOS 16
+#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_MASK 0xF
+#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_BITPOS 24
+#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_MASK 0xFF
+#define QAT_AUTH_SHA3_HW_PADDING_ENABLE 0
+#define QAT_AUTH_SHA3_HW_PADDING_DISABLE 1
+#define QAT_AUTH_SHA3_PADDING_DISABLE_USE_DEFAULT 0
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_USE_DEFAULT 0
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_PROGRAMMABLE 1
+#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_RESERVED 0
+#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_RESERVED 0
+
+#define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \
+ ((((mode) & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \
+ (((algo) & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \
+ (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) \
+ << QAT_AUTH_ALGO_SHA3_BITPOS) | \
+ (((QAT_AUTH_SHA3_PADDING_DISABLE_USE_DEFAULT) & \
+ QAT_AUTH_SHA3_PADDING_DISABLE_MASK) \
+ << QAT_AUTH_SHA3_PADDING_DISABLE_BITPOS) | \
+ (((QAT_AUTH_SHA3_PADDING_OVERRIDE_USE_DEFAULT) & \
+ QAT_AUTH_SHA3_PADDING_OVERRIDE_MASK) \
+ << QAT_AUTH_SHA3_PADDING_OVERRIDE_BITPOS) | \
+ (((cmp_len) & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
+
+#define ICP_QAT_HW_AUTH_CONFIG_BUILD_UPPER \
+ ((((QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_RESERVED) & \
+ QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_MASK) \
+ << QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_BITPOS) | \
+ (((QAT_AUTH_SHA3_PROG_PADDING_PREFIX_RESERVED) & \
+ QAT_AUTH_SHA3_PROG_PADDING_PREFIX_MASK) \
+ << QAT_AUTH_SHA3_PROG_PADDING_PREFIX_BITPOS))
struct icp_qat_hw_auth_counter {
uint32_t counter;
@@ -107,13 +132,13 @@ struct icp_qat_hw_auth_setup {
#define ICP_QAT_HW_MD5_STATE1_SZ 16
#define ICP_QAT_HW_SHA1_STATE1_SZ 20
#define ICP_QAT_HW_SHA224_STATE1_SZ 32
+#define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
#define ICP_QAT_HW_SHA256_STATE1_SZ 32
#define ICP_QAT_HW_SHA3_256_STATE1_SZ 32
#define ICP_QAT_HW_SHA384_STATE1_SZ 64
+#define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
#define ICP_QAT_HW_SHA512_STATE1_SZ 64
#define ICP_QAT_HW_SHA3_512_STATE1_SZ 64
-#define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
-#define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
#define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ 16
#define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ 16
#define ICP_QAT_HW_AES_F9_STATE1_SZ 32
@@ -121,17 +146,18 @@ struct icp_qat_hw_auth_setup {
#define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16
#define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8
#define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8
+
#define ICP_QAT_HW_NULL_STATE2_SZ 32
#define ICP_QAT_HW_MD5_STATE2_SZ 16
#define ICP_QAT_HW_SHA1_STATE2_SZ 20
#define ICP_QAT_HW_SHA224_STATE2_SZ 32
+#define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
#define ICP_QAT_HW_SHA256_STATE2_SZ 32
#define ICP_QAT_HW_SHA3_256_STATE2_SZ 0
#define ICP_QAT_HW_SHA384_STATE2_SZ 64
+#define ICP_QAT_HW_SHA3_384_STATE2_SZ 0
#define ICP_QAT_HW_SHA512_STATE2_SZ 64
#define ICP_QAT_HW_SHA3_512_STATE2_SZ 0
-#define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
-#define ICP_QAT_HW_SHA3_384_STATE2_SZ 0
#define ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ 48
#define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16
#define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16
@@ -154,6 +180,12 @@ struct icp_qat_hw_auth_sha512 {
uint8_t state2[ICP_QAT_HW_SHA512_STATE2_SZ];
};
+struct icp_qat_hw_auth_sha3_512 {
+ struct icp_qat_hw_auth_setup inner_setup;
+ uint8_t state1[ICP_QAT_HW_SHA3_512_STATE1_SZ];
+ struct icp_qat_hw_auth_setup outer_setup;
+};
+
struct icp_qat_hw_auth_algo_blk {
struct icp_qat_hw_auth_sha512 sha;
};
@@ -283,4 +315,72 @@ struct icp_qat_hw_cipher_algo_blk {
uint8_t key[ICP_QAT_HW_CIPHER_MAX_KEY_SZ];
} __rte_cache_aligned;
+/* ========================================================================= */
+/* COMPRESSION SLICE */
+/* ========================================================================= */
+
+enum icp_qat_hw_compression_direction {
+ ICP_QAT_HW_COMPRESSION_DIR_COMPRESS = 0,
+ ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS = 1,
+ ICP_QAT_HW_COMPRESSION_DIR_DELIMITER = 2
+};
+
+enum icp_qat_hw_compression_delayed_match {
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED = 0,
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_ENABLED = 1,
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DELIMITER = 2
+};
+
+enum icp_qat_hw_compression_algo {
+ ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE = 0,
+ ICP_QAT_HW_COMPRESSION_ALGO_LZS = 1,
+ ICP_QAT_HW_COMPRESSION_ALGO_DELIMITER = 2
+};
+
+
+enum icp_qat_hw_compression_depth {
+ ICP_QAT_HW_COMPRESSION_DEPTH_1 = 0,
+ ICP_QAT_HW_COMPRESSION_DEPTH_4 = 1,
+ ICP_QAT_HW_COMPRESSION_DEPTH_8 = 2,
+ ICP_QAT_HW_COMPRESSION_DEPTH_16 = 3,
+ ICP_QAT_HW_COMPRESSION_DEPTH_DELIMITER = 4
+};
+
+enum icp_qat_hw_compression_file_type {
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_0 = 0,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_1 = 1,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_2 = 2,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_3 = 3,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_4 = 4,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_DELIMITER = 5
+};
+
+struct icp_qat_hw_compression_config {
+ uint32_t val;
+ uint32_t reserved;
+};
+
+#define QAT_COMPRESSION_DIR_BITPOS 4
+#define QAT_COMPRESSION_DIR_MASK 0x7
+#define QAT_COMPRESSION_DELAYED_MATCH_BITPOS 16
+#define QAT_COMPRESSION_DELAYED_MATCH_MASK 0x1
+#define QAT_COMPRESSION_ALGO_BITPOS 31
+#define QAT_COMPRESSION_ALGO_MASK 0x1
+#define QAT_COMPRESSION_DEPTH_BITPOS 28
+#define QAT_COMPRESSION_DEPTH_MASK 0x7
+#define QAT_COMPRESSION_FILE_TYPE_BITPOS 24
+#define QAT_COMPRESSION_FILE_TYPE_MASK 0xF
+
+#define ICP_QAT_HW_COMPRESSION_CONFIG_BUILD( \
+ dir, delayed, algo, depth, filetype) \
+ ((((dir) & QAT_COMPRESSION_DIR_MASK) << QAT_COMPRESSION_DIR_BITPOS) | \
+ (((delayed) & QAT_COMPRESSION_DELAYED_MATCH_MASK) \
+ << QAT_COMPRESSION_DELAYED_MATCH_BITPOS) | \
+ (((algo) & QAT_COMPRESSION_ALGO_MASK) \
+ << QAT_COMPRESSION_ALGO_BITPOS) | \
+ (((depth) & QAT_COMPRESSION_DEPTH_MASK) \
+ << QAT_COMPRESSION_DEPTH_BITPOS) | \
+ (((filetype) & QAT_COMPRESSION_FILE_TYPE_MASK) \
+ << QAT_COMPRESSION_FILE_TYPE_BITPOS))
+
#endif
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v3 02/16] compress/qat: add makefiles for PMD
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 00/16] " Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 " Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 01/16] common/qat: updated firmware headers Fiona Trahe
@ 2018-07-05 17:32 ` Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 03/16] compress/qat: add meson build Fiona Trahe
` (13 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 17:32 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add Makefiles, directory and empty source files for compression PMD.
Handle cases for building either symmetric crypto PMD
or compression PMD or both and the common files both depend on.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
MAINTAINERS | 4 ++++
config/common_base | 3 ++-
drivers/common/qat/Makefile | 48 ++++++++++++++++++++++++++++---------
drivers/compress/qat/qat_comp.c | 5 ++++
drivers/compress/qat/qat_comp.h | 14 +++++++++++
drivers/compress/qat/qat_comp_pmd.c | 5 ++++
drivers/compress/qat/qat_comp_pmd.h | 15 ++++++++++++
test/test/test_cryptodev.c | 6 ++---
8 files changed, 85 insertions(+), 15 deletions(-)
create mode 100644 drivers/compress/qat/qat_comp.c
create mode 100644 drivers/compress/qat/qat_comp.h
create mode 100644 drivers/compress/qat/qat_comp_pmd.c
create mode 100644 drivers/compress/qat/qat_comp_pmd.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 8050b5d..50b2dff 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -852,6 +852,10 @@ F: drivers/compress/isal/
F: doc/guides/compressdevs/isal.rst
F: doc/guides/compressdevs/features/isal.ini
+Intel QuickAssist
+M: Fiona Trahe <fiona.trahe@intel.com>
+F: drivers/compress/qat/
+F: drivers/common/qat/
Eventdev Drivers
----------------
diff --git a/config/common_base b/config/common_base
index 4236e29..93c8857 100644
--- a/config/common_base
+++ b/config/common_base
@@ -484,7 +484,8 @@ CONFIG_RTE_DPAA_SEC_PMD_MAX_NB_SESSIONS=2048
#
# Compile PMD for QuickAssist based devices
#
-CONFIG_RTE_LIBRTE_PMD_QAT=n
+CONFIG_RTE_LIBRTE_PMD_QAT=y
+CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
#
# Max. number of QuickAssist devices, which can be detected and attached
#
diff --git a/drivers/common/qat/Makefile b/drivers/common/qat/Makefile
index 68c7c95..b1a76c1 100644
--- a/drivers/common/qat/Makefile
+++ b/drivers/common/qat/Makefile
@@ -15,35 +15,61 @@ CFLAGS += -O3
# build directories
QAT_CRYPTO_DIR := $(RTE_SDK)/drivers/crypto/qat
+QAT_COMPRESS_DIR := $(RTE_SDK)/drivers/compress/qat
# external library include paths
CFLAGS += -I$(SRCDIR)/qat_adf
CFLAGS += -I$(SRCDIR)
CFLAGS += -I$(QAT_CRYPTO_DIR)
+CFLAGS += -I$(QAT_COMPRESS_DIR)
-# library common source files
-SRCS-y += qat_device.c
-SRCS-y += qat_common.c
-SRCS-y += qat_logs.c
-SRCS-y += qat_qp.c
+
+ifeq ($(CONFIG_RTE_LIBRTE_COMPRESSDEV),y)
+ CFLAGS += -DALLOW_EXPERIMENTAL_API
+ LDLIBS += -lrte_compressdev
+ SRCS-y += $(QAT_COMPRESS_DIR)/qat_comp.c
+ SRCS-y += $(QAT_COMPRESS_DIR)/qat_comp_pmd.c
+ build_qat = yes
+endif
# library symmetric crypto source files
ifeq ($(CONFIG_RTE_LIBRTE_CRYPTODEV),y)
+ifeq ($(CONFIG_RTE_LIBRTE_PMD_QAT_SYM),y)
LDLIBS += -lrte_cryptodev
LDLIBS += -lcrypto
CFLAGS += -DBUILD_QAT_SYM
SRCS-y += $(QAT_CRYPTO_DIR)/qat_sym.c
SRCS-y += $(QAT_CRYPTO_DIR)/qat_sym_session.c
SRCS-y += $(QAT_CRYPTO_DIR)/qat_sym_pmd.c
+ build_qat = yes
endif
+endif
+
+ifdef build_qat
-LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool
-LDLIBS += -lrte_pci -lrte_bus_pci
+ # library name
+ LIB = librte_pmd_qat.a
-# export include files
-SYMLINK-y-include +=
+ # library version
+ LIBABIVER := 1
+ # build flags
+ CFLAGS += $(WERROR_FLAGS)
+ CFLAGS += -O3
-# versioning export map
-EXPORT_MAP := ../../crypto/qat/rte_pmd_qat_version.map
+ # library common source files
+ SRCS-y += qat_device.c
+ SRCS-y += qat_common.c
+ SRCS-y += qat_logs.c
+ SRCS-y += qat_qp.c
+
+ LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool
+ LDLIBS += -lrte_pci -lrte_bus_pci
+
+ # export include files
+ SYMLINK-y-include +=
+
+ # versioning export map
+ EXPORT_MAP := ../../crypto/qat/rte_pmd_qat_version.map
+endif
include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
new file mode 100644
index 0000000..caa1158
--- /dev/null
+++ b/drivers/compress/qat/qat_comp.c
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Intel Corporation
+ */
+
+#include "qat_comp.h"
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
new file mode 100644
index 0000000..89c475e
--- /dev/null
+++ b/drivers/compress/qat/qat_comp.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+
+#ifndef _QAT_COMP_H_
+#define _QAT_COMP_H_
+
+#ifdef RTE_LIBRTE_COMPRESSDEV
+
+#include <rte_compressdev.h>
+#include <rte_compressdev_pmd.h>
+
+#endif
+#endif
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
new file mode 100644
index 0000000..fb035d1
--- /dev/null
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+
+#include "qat_comp_pmd.h"
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
new file mode 100644
index 0000000..9b5b543
--- /dev/null
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+
+#ifndef _QAT_COMP_PMD_H_
+#define _QAT_COMP_PMD_H_
+
+#ifdef RTE_LIBRTE_COMPRESSDEV
+
+#include <rte_compressdev.h>
+#include <rte_compressdev_pmd.h>
+
+
+#endif
+#endif /* _QAT_COMP_PMD_H_ */
diff --git a/test/test/test_cryptodev.c b/test/test/test_cryptodev.c
index 389f796..ec03a98 100644
--- a/test/test/test_cryptodev.c
+++ b/test/test/test_cryptodev.c
@@ -9908,9 +9908,9 @@ test_cryptodev_qat(void /*argv __rte_unused, int argc __rte_unused*/)
RTE_STR(CRYPTODEV_NAME_QAT_SYM_PMD));
if (gbl_driver_id == -1) {
- RTE_LOG(ERR, USER1, "QAT PMD must be loaded. Check if "
- "CONFIG_RTE_LIBRTE_PMD_QAT is enabled "
- "in config file to run this testsuite.\n");
+ RTE_LOG(ERR, USER1, "QAT PMD must be loaded. Check that both "
+ "CONFIG_RTE_LIBRTE_PMD_QAT and CONFIG_RTE_LIBRTE_PMD_QAT_SYM "
+ "are enabled in config file to run this testsuite.\n");
return TEST_SKIPPED;
}
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v3 03/16] compress/qat: add meson build
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 00/16] " Fiona Trahe
` (2 preceding siblings ...)
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 02/16] compress/qat: add makefiles for PMD Fiona Trahe
@ 2018-07-05 17:32 ` Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 04/16] compress/qat: add xform processing Fiona Trahe
` (12 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 17:32 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add meson build files.
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
drivers/common/qat/Makefile | 2 +-
drivers/compress/meson.build | 2 +-
drivers/compress/qat/meson.build | 18 ++++++++++++++++++
drivers/compress/qat/rte_pmd_qat_version.map | 3 +++
drivers/crypto/qat/meson.build | 10 ++--------
drivers/crypto/qat/rte_pmd_qat_version.map | 3 ---
6 files changed, 25 insertions(+), 13 deletions(-)
create mode 100644 drivers/compress/qat/meson.build
create mode 100644 drivers/compress/qat/rte_pmd_qat_version.map
delete mode 100644 drivers/crypto/qat/rte_pmd_qat_version.map
diff --git a/drivers/common/qat/Makefile b/drivers/common/qat/Makefile
index b1a76c1..bc53652 100644
--- a/drivers/common/qat/Makefile
+++ b/drivers/common/qat/Makefile
@@ -69,7 +69,7 @@ ifdef build_qat
SYMLINK-y-include +=
# versioning export map
- EXPORT_MAP := ../../crypto/qat/rte_pmd_qat_version.map
+ EXPORT_MAP := ../../compress/qat/rte_pmd_qat_version.map
endif
include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/compress/meson.build b/drivers/compress/meson.build
index fb136e1..2352ad5 100644
--- a/drivers/compress/meson.build
+++ b/drivers/compress/meson.build
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2018 Intel Corporation
-drivers = ['isal']
+drivers = ['isal', 'qat']
std_deps = ['compressdev'] # compressdev pulls in all other needed deps
config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'
diff --git a/drivers/compress/qat/meson.build b/drivers/compress/qat/meson.build
new file mode 100644
index 0000000..9d15076
--- /dev/null
+++ b/drivers/compress/qat/meson.build
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2017-2018 Intel Corporation
+
+
+# Add our sources files to the list
+allow_experimental_apis = true
+qat_sources += files('qat_comp_pmd.c',
+ 'qat_comp.c')
+qat_includes += include_directories('.')
+qat_deps += 'compressdev'
+qat_ext_deps += dep
+
+# build the whole driver
+sources += qat_sources
+cflags += qat_cflags
+deps += qat_deps
+ext_deps += qat_ext_deps
+includes += qat_includes
diff --git a/drivers/compress/qat/rte_pmd_qat_version.map b/drivers/compress/qat/rte_pmd_qat_version.map
new file mode 100644
index 0000000..ad6e191
--- /dev/null
+++ b/drivers/compress/qat/rte_pmd_qat_version.map
@@ -0,0 +1,3 @@
+DPDK_18.08 {
+ local: *;
+};
diff --git a/drivers/crypto/qat/meson.build b/drivers/crypto/qat/meson.build
index 2873637..d7cff68 100644
--- a/drivers/crypto/qat/meson.build
+++ b/drivers/crypto/qat/meson.build
@@ -1,6 +1,8 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017-2018 Intel Corporation
+# this does not build the QAT driver, instead that is done in the compression
+# driver which comes later. Here we just add our sources files to the list
build = false
dep = dependency('libcrypto', required: false)
if dep.found()
@@ -13,12 +15,4 @@ if dep.found()
qat_ext_deps += dep
pkgconfig_extra_libs += '-lcrypto'
qat_cflags += '-DBUILD_QAT_SYM'
-
- # build the whole driver
- sources += qat_sources
- cflags += qat_cflags
- deps += qat_deps
- ext_deps += qat_ext_deps
- includes += qat_includes
- build = true
endif
diff --git a/drivers/crypto/qat/rte_pmd_qat_version.map b/drivers/crypto/qat/rte_pmd_qat_version.map
deleted file mode 100644
index bbaf1c8..0000000
--- a/drivers/crypto/qat/rte_pmd_qat_version.map
+++ /dev/null
@@ -1,3 +0,0 @@
-DPDK_2.2 {
- local: *;
-};
\ No newline at end of file
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v3 04/16] compress/qat: add xform processing
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 00/16] " Fiona Trahe
` (3 preceding siblings ...)
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 03/16] compress/qat: add meson build Fiona Trahe
@ 2018-07-05 17:32 ` Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 05/16] compress/qat: create fw request and process response Fiona Trahe
` (11 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 17:32 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add code to process compressdev rte_comp_xforms, creating
private qat_comp_xforms with prepared firmware message templates.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp.c | 239 ++++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp.h | 30 +++++
drivers/compress/qat/qat_comp_pmd.h | 16 +++
3 files changed, 285 insertions(+)
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index caa1158..cb2005a 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -2,4 +2,243 @@
* Copyright(c) 2018 Intel Corporation
*/
+
+#include <rte_mempool.h>
+#include <rte_mbuf.h>
+#include <rte_hexdump.h>
+#include <rte_comp.h>
+#include <rte_bus_pci.h>
+#include <rte_byteorder.h>
+#include <rte_memcpy.h>
+#include <rte_common.h>
+#include <rte_spinlock.h>
+#include <rte_log.h>
+#include <rte_malloc.h>
+
+#include "qat_logs.h"
#include "qat_comp.h"
+#include "qat_comp_pmd.h"
+
+unsigned int
+qat_comp_xform_size(void)
+{
+ return RTE_ALIGN_CEIL(sizeof(struct qat_comp_xform), 8);
+}
+
+static void qat_comp_create_req_hdr(struct icp_qat_fw_comn_req_hdr *header,
+ enum qat_comp_request_type request)
+{
+ if (request == QAT_COMP_REQUEST_FIXED_COMP_STATELESS)
+ header->service_cmd_id = ICP_QAT_FW_COMP_CMD_STATIC;
+ else if (request == QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS)
+ header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DYNAMIC;
+ else if (request == QAT_COMP_REQUEST_DECOMPRESS)
+ header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DECOMPRESS;
+
+ header->service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_COMP;
+ header->hdr_flags =
+ ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
+
+ header->comn_req_flags = ICP_QAT_FW_COMN_FLAGS_BUILD(
+ QAT_COMN_CD_FLD_TYPE_16BYTE_DATA, QAT_COMN_PTR_TYPE_FLAT);
+}
+
+static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,
+ const struct rte_memzone *interm_buff_mz __rte_unused,
+ const struct rte_comp_xform *xform)
+{
+ struct icp_qat_fw_comp_req *comp_req;
+ int comp_level, algo;
+ uint32_t req_par_flags;
+ int direction = ICP_QAT_HW_COMPRESSION_DIR_COMPRESS;
+
+ if (unlikely(qat_xform == NULL)) {
+ QAT_LOG(ERR, "Session was not created for this device");
+ return -EINVAL;
+ }
+
+ if (qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS) {
+ direction = ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS;
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_1;
+ req_par_flags = ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(
+ ICP_QAT_FW_COMP_SOP, ICP_QAT_FW_COMP_EOP,
+ ICP_QAT_FW_COMP_BFINAL, ICP_QAT_FW_COMP_NO_CNV,
+ ICP_QAT_FW_COMP_NO_CNV_RECOVERY);
+
+ } else {
+ if (xform->compress.level == RTE_COMP_LEVEL_PMD_DEFAULT)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_8;
+ else if (xform->compress.level == 1)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_1;
+ else if (xform->compress.level == 2)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_4;
+ else if (xform->compress.level == 3)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_8;
+ else if (xform->compress.level >= 4 &&
+ xform->compress.level <= 9)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_16;
+ else {
+ QAT_LOG(ERR, "compression level not supported");
+ return -EINVAL;
+ }
+ req_par_flags = ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(
+ ICP_QAT_FW_COMP_SOP, ICP_QAT_FW_COMP_EOP,
+ ICP_QAT_FW_COMP_BFINAL, ICP_QAT_FW_COMP_CNV,
+ ICP_QAT_FW_COMP_CNV_RECOVERY);
+ }
+
+ switch (xform->compress.algo) {
+ case RTE_COMP_ALGO_DEFLATE:
+ algo = ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE;
+ break;
+ case RTE_COMP_ALGO_LZS:
+ default:
+ /* RTE_COMP_NULL */
+ QAT_LOG(ERR, "compression algorithm not supported");
+ return -EINVAL;
+ }
+
+ comp_req = &qat_xform->qat_comp_req_tmpl;
+
+ /* Initialize header */
+ qat_comp_create_req_hdr(&comp_req->comn_hdr,
+ qat_xform->qat_comp_request_type);
+
+ comp_req->comn_hdr.serv_specif_flags = ICP_QAT_FW_COMP_FLAGS_BUILD(
+ ICP_QAT_FW_COMP_STATELESS_SESSION,
+ ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST,
+ ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST,
+ ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST,
+ ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_USED_AS_INTMD_BUF);
+
+ comp_req->cd_pars.sl.comp_slice_cfg_word[0] =
+ ICP_QAT_HW_COMPRESSION_CONFIG_BUILD(
+ direction,
+ /* In CPM 1.6 only valid mode ! */
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_ENABLED, algo,
+ /* Translate level to depth */
+ comp_level, ICP_QAT_HW_COMPRESSION_FILE_TYPE_0);
+
+ comp_req->comp_pars.initial_adler = 1;
+ comp_req->comp_pars.initial_crc32 = 0;
+ comp_req->comp_pars.req_par_flags = req_par_flags;
+
+
+ if (qat_xform->qat_comp_request_type ==
+ QAT_COMP_REQUEST_FIXED_COMP_STATELESS ||
+ qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS) {
+ ICP_QAT_FW_COMN_NEXT_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_DRAM_WR);
+ ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_COMP);
+ } else if (qat_xform->qat_comp_request_type ==
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {
+
+ QAT_LOG(ERR, "Dynamic huffman encoding not supported");
+ return -EINVAL;
+ }
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_HEXDUMP_LOG(DEBUG, "qat compression message template:", comp_req,
+ sizeof(struct icp_qat_fw_comp_req));
+#endif
+ return 0;
+}
+
+/**
+ * Create driver private_xform data.
+ *
+ * @param dev
+ * Compressdev device
+ * @param xform
+ * xform data from application
+ * @param private_xform
+ * ptr where handle of pmd's private_xform data should be stored
+ * @return
+ * - if successful returns 0
+ * and valid private_xform handle
+ * - <0 in error cases
+ * - Returns -EINVAL if input parameters are invalid.
+ * - Returns -ENOTSUP if comp device does not support the comp transform.
+ * - Returns -ENOMEM if the private_xform could not be allocated.
+ */
+int
+qat_comp_private_xform_create(struct rte_compressdev *dev,
+ const struct rte_comp_xform *xform,
+ void **private_xform)
+{
+ struct qat_comp_dev_private *qat = dev->data->dev_private;
+
+ if (unlikely(private_xform == NULL)) {
+ QAT_LOG(ERR, "QAT: private_xform parameter is NULL");
+ return -EINVAL;
+ }
+ if (unlikely(qat->xformpool == NULL)) {
+ QAT_LOG(ERR, "QAT device has no private_xform mempool");
+ return -ENOMEM;
+ }
+ if (rte_mempool_get(qat->xformpool, private_xform)) {
+ QAT_LOG(ERR, "Couldn't get object from qat xform mempool");
+ return -ENOMEM;
+ }
+
+ struct qat_comp_xform *qat_xform =
+ (struct qat_comp_xform *)*private_xform;
+
+ if (xform->type == RTE_COMP_COMPRESS) {
+ if (xform->compress.deflate.huffman ==
+ RTE_COMP_HUFFMAN_DYNAMIC) {
+ QAT_LOG(ERR,
+ "QAT device doesn't support dynamic compression");
+ return -ENOTSUP;
+ }
+
+ if (xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_FIXED ||
+ ((xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_DEFAULT)
+ && qat->interm_buff_mz == NULL))
+
+ qat_xform->qat_comp_request_type =
+ QAT_COMP_REQUEST_FIXED_COMP_STATELESS;
+
+
+ } else {
+ qat_xform->qat_comp_request_type = QAT_COMP_REQUEST_DECOMPRESS;
+ }
+
+ qat_xform->checksum_type = xform->compress.chksum;
+
+ if (qat_comp_create_templates(qat_xform, qat->interm_buff_mz, xform)) {
+ QAT_LOG(ERR, "QAT: Problem with setting compression");
+ return -EINVAL;
+ }
+ return 0;
+}
+
+/**
+ * Free driver private_xform data.
+ *
+ * @param dev
+ * Compressdev device
+ * @param private_xform
+ * handle of pmd's private_xform data
+ * @return
+ * - 0 if successful
+ * - <0 in error cases
+ * - Returns -EINVAL if input parameters are invalid.
+ */
+int
+qat_comp_private_xform_free(struct rte_compressdev *dev __rte_unused,
+ void *private_xform)
+{
+ struct qat_comp_xform *qat_xform =
+ (struct qat_comp_xform *)private_xform;
+
+ if (qat_xform) {
+ memset(qat_xform, 0, qat_comp_xform_size());
+ struct rte_mempool *mp = rte_mempool_from_obj(qat_xform);
+
+ rte_mempool_put(mp, qat_xform);
+ return 0;
+ }
+ return -EINVAL;
+}
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 89c475e..0f58a76 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -10,5 +10,35 @@
#include <rte_compressdev.h>
#include <rte_compressdev_pmd.h>
+#include "icp_qat_hw.h"
+#include "icp_qat_fw_comp.h"
+#include "icp_qat_fw_la.h"
+
+enum qat_comp_request_type {
+ QAT_COMP_REQUEST_FIXED_COMP_STATELESS,
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS,
+ QAT_COMP_REQUEST_DECOMPRESS,
+ REQ_COMP_END
+};
+
+
+struct qat_comp_xform {
+ struct icp_qat_fw_comp_req qat_comp_req_tmpl;
+ enum qat_comp_request_type qat_comp_request_type;
+ enum rte_comp_checksum_type checksum_type;
+};
+
+
+int
+qat_comp_private_xform_create(struct rte_compressdev *dev,
+ const struct rte_comp_xform *xform,
+ void **private_xform);
+
+int
+qat_comp_private_xform_free(struct rte_compressdev *dev, void *private_xform);
+
+unsigned int
+qat_comp_xform_size(void);
+
#endif
#endif
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 9b5b543..fd97cbf 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -11,5 +11,21 @@
#include <rte_compressdev_pmd.h>
+/** private data structure for a QAT compression device.
+ * This QAT device is a device offering only a compression service,
+ * there can be one of these on each qat_pci_device (VF).
+ */
+struct qat_comp_dev_private {
+ struct qat_pci_device *qat_dev;
+ /**< The qat pci device hosting the service */
+ struct rte_compressdev *compressdev;
+ /**< The pointer to this compression device structure */
+ const struct rte_memzone *interm_buff_mz;
+ /**< The device's memory for intermediate buffers */
+ struct rte_mempool *xformpool;
+ /**< The device's pool for qat_comp_xforms */
+
+};
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v3 05/16] compress/qat: create fw request and process response
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 00/16] " Fiona Trahe
` (4 preceding siblings ...)
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 04/16] compress/qat: add xform processing Fiona Trahe
@ 2018-07-05 17:32 ` Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 06/16] compress/qat: check that correct firmware is in use Fiona Trahe
` (10 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 17:32 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add functions to create the request message to send to
firmware and to process the firmware response.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp.c | 101 ++++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp.h | 8 +++
drivers/compress/qat/qat_comp_pmd.h | 1 +
3 files changed, 110 insertions(+)
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index cb2005a..a32d6ef 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -19,6 +19,107 @@
#include "qat_comp.h"
#include "qat_comp_pmd.h"
+
+int
+qat_comp_build_request(void *in_op, uint8_t *out_msg,
+ void *op_cookie __rte_unused,
+ enum qat_device_gen qat_dev_gen __rte_unused)
+{
+ struct rte_comp_op *op = in_op;
+ struct qat_comp_xform *qat_xform = op->private_xform;
+ const uint8_t *tmpl = (uint8_t *)&qat_xform->qat_comp_req_tmpl;
+ struct icp_qat_fw_comp_req *comp_req =
+ (struct icp_qat_fw_comp_req *)out_msg;
+
+ if (unlikely(op->op_type != RTE_COMP_OP_STATELESS)) {
+ QAT_DP_LOG(ERR, "QAT PMD only supports stateless compression "
+ "operation requests, op (%p) is not a "
+ "stateless operation.", op);
+ return -EINVAL;
+ }
+
+ rte_mov128(out_msg, tmpl);
+ comp_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
+
+ /* common for sgl and flat buffers */
+ comp_req->comp_pars.comp_len = op->src.length;
+ comp_req->comp_pars.out_buffer_sz = rte_pktmbuf_pkt_len(op->m_dst);
+
+ /* sgl */
+ if (op->m_src->next != NULL || op->m_dst->next != NULL) {
+ QAT_DP_LOG(ERR, "QAT PMD doesn't support scatter gather");
+ return -EINVAL;
+
+ } else {
+ ICP_QAT_FW_COMN_PTR_TYPE_SET(comp_req->comn_hdr.comn_req_flags,
+ QAT_COMN_PTR_TYPE_FLAT);
+ comp_req->comn_mid.src_length = rte_pktmbuf_data_len(op->m_src);
+ comp_req->comn_mid.dst_length = rte_pktmbuf_data_len(op->m_dst);
+
+ comp_req->comn_mid.src_data_addr =
+ rte_pktmbuf_mtophys_offset(op->m_src, op->src.offset);
+ comp_req->comn_mid.dest_data_addr =
+ rte_pktmbuf_mtophys_offset(op->m_dst, op->dst.offset);
+ }
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_LOG(DEBUG, "Direction: %s",
+ qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS ?
+ "decompression" : "compression");
+ QAT_DP_HEXDUMP_LOG(DEBUG, "qat compression message:", comp_req,
+ sizeof(struct icp_qat_fw_comp_req));
+#endif
+ return 0;
+}
+
+int
+qat_comp_process_response(void **op, uint8_t *resp)
+{
+ struct icp_qat_fw_comp_resp *resp_msg =
+ (struct icp_qat_fw_comp_resp *)resp;
+ struct rte_comp_op *rx_op = (struct rte_comp_op *)(uintptr_t)
+ (resp_msg->opaque_data);
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_LOG(DEBUG, "Direction: %s",
+ qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS ?
+ "decompression" : "compression");
+ QAT_DP_HEXDUMP_LOG(DEBUG, "qat_response:", (uint8_t *)resp_msg,
+ sizeof(struct icp_qat_fw_comp_resp));
+#endif
+
+ if ((ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(resp_msg->comn_resp.comn_status)
+ | ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(
+ resp_msg->comn_resp.comn_status)) !=
+ ICP_QAT_FW_COMN_STATUS_FLAG_OK) {
+
+ rx_op->status = RTE_COMP_OP_STATUS_ERROR;
+ rx_op->debug_status =
+ *((uint16_t *)(&resp_msg->comn_resp.comn_error));
+ } else {
+ struct qat_comp_xform *qat_xform = rx_op->private_xform;
+ struct icp_qat_fw_resp_comp_pars *comp_resp =
+ (struct icp_qat_fw_resp_comp_pars *)&resp_msg->comp_resp_pars;
+
+ rx_op->status = RTE_COMP_OP_STATUS_SUCCESS;
+ rx_op->consumed = comp_resp->input_byte_counter;
+ rx_op->produced = comp_resp->output_byte_counter;
+
+ if (qat_xform->checksum_type != RTE_COMP_CHECKSUM_NONE) {
+ if (qat_xform->checksum_type == RTE_COMP_CHECKSUM_CRC32)
+ rx_op->output_chksum = comp_resp->curr_crc32;
+ else if (qat_xform->checksum_type ==
+ RTE_COMP_CHECKSUM_ADLER32)
+ rx_op->output_chksum = comp_resp->curr_adler_32;
+ else
+ rx_op->output_chksum = comp_resp->curr_chksum;
+ }
+ }
+ *op = (void *)rx_op;
+
+ return 0;
+}
+
unsigned int
qat_comp_xform_size(void)
{
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 0f58a76..46105b4 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -10,6 +10,7 @@
#include <rte_compressdev.h>
#include <rte_compressdev_pmd.h>
+#include "qat_common.h"
#include "icp_qat_hw.h"
#include "icp_qat_fw_comp.h"
#include "icp_qat_fw_la.h"
@@ -28,6 +29,13 @@ struct qat_comp_xform {
enum rte_comp_checksum_type checksum_type;
};
+int
+qat_comp_build_request(void *in_op, uint8_t *out_msg, void *op_cookie,
+ enum qat_device_gen qat_dev_gen __rte_unused);
+
+int
+qat_comp_process_response(void **op, uint8_t *resp);
+
int
qat_comp_private_xform_create(struct rte_compressdev *dev,
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index fd97cbf..cd04f11 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -10,6 +10,7 @@
#include <rte_compressdev.h>
#include <rte_compressdev_pmd.h>
+#include "qat_device.h"
/** private data structure for a QAT compression device.
* This QAT device is a device offering only a compression service,
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v3 06/16] compress/qat: check that correct firmware is in use
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 00/16] " Fiona Trahe
` (5 preceding siblings ...)
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 05/16] compress/qat: create fw request and process response Fiona Trahe
@ 2018-07-05 17:32 ` Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 07/16] compress/qat: add stats functions Fiona Trahe
` (9 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 17:32 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Check bit in response message to verify that correct firmware
is in use for compression. If not return an error.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp.c | 16 +++++++++++++++-
drivers/compress/qat/qat_comp.h | 2 ++
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index a32d6ef..e8019eb 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -2,7 +2,6 @@
* Copyright(c) 2018 Intel Corporation
*/
-
#include <rte_mempool.h>
#include <rte_mbuf.h>
#include <rte_hexdump.h>
@@ -79,6 +78,8 @@ qat_comp_process_response(void **op, uint8_t *resp)
(struct icp_qat_fw_comp_resp *)resp;
struct rte_comp_op *rx_op = (struct rte_comp_op *)(uintptr_t)
(resp_msg->opaque_data);
+ struct qat_comp_xform *qat_xform = (struct qat_comp_xform *)
+ (rx_op->private_xform);
#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
QAT_DP_LOG(DEBUG, "Direction: %s",
@@ -88,6 +89,19 @@ qat_comp_process_response(void **op, uint8_t *resp)
sizeof(struct icp_qat_fw_comp_resp));
#endif
+ if (likely(qat_xform->qat_comp_request_type
+ != QAT_COMP_REQUEST_DECOMPRESS)) {
+ if (unlikely(ICP_QAT_FW_COMN_HDR_CNV_FLAG_GET(
+ resp_msg->comn_resp.hdr_flags)
+ == ICP_QAT_FW_COMP_NO_CNV)) {
+ rx_op->status = RTE_COMP_OP_STATUS_ERROR;
+ rx_op->debug_status = ERR_CODE_QAT_COMP_WRONG_FW;
+ *op = (void *)rx_op;
+ QAT_DP_LOG(ERR, "QAT has wrong firmware");
+ return 0;
+ }
+ }
+
if ((ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(resp_msg->comn_resp.comn_status)
| ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(
resp_msg->comn_resp.comn_status)) !=
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 46105b4..937f3c8 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -15,6 +15,8 @@
#include "icp_qat_fw_comp.h"
#include "icp_qat_fw_la.h"
+#define ERR_CODE_QAT_COMP_WRONG_FW -99
+
enum qat_comp_request_type {
QAT_COMP_REQUEST_FIXED_COMP_STATELESS,
QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS,
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v3 07/16] compress/qat: add stats functions
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 00/16] " Fiona Trahe
` (6 preceding siblings ...)
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 06/16] compress/qat: check that correct firmware is in use Fiona Trahe
@ 2018-07-05 17:32 ` Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 08/16] compress/qat: setup queue-pairs for compression service Fiona Trahe
` (8 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 17:32 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add functions to get and clear compression queue-pair statistics.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 35 +++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 7 +++++++
2 files changed, 42 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index fb035d1..6feffb7 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -3,3 +3,38 @@
*/
#include "qat_comp_pmd.h"
+
+void
+qat_comp_stats_get(struct rte_compressdev *dev,
+ struct rte_compressdev_stats *stats)
+{
+ struct qat_common_stats qat_stats = {0};
+ struct qat_comp_dev_private *qat_priv;
+
+ if (stats == NULL || dev == NULL) {
+ QAT_LOG(ERR, "invalid ptr: stats %p, dev %p", stats, dev);
+ return;
+ }
+ qat_priv = dev->data->dev_private;
+
+ qat_stats_get(qat_priv->qat_dev, &qat_stats, QAT_SERVICE_COMPRESSION);
+ stats->enqueued_count = qat_stats.enqueued_count;
+ stats->dequeued_count = qat_stats.dequeued_count;
+ stats->enqueue_err_count = qat_stats.enqueue_err_count;
+ stats->dequeue_err_count = qat_stats.dequeue_err_count;
+}
+
+void
+qat_comp_stats_reset(struct rte_compressdev *dev)
+{
+ struct qat_comp_dev_private *qat_priv;
+
+ if (dev == NULL) {
+ QAT_LOG(ERR, "invalid compressdev ptr %p", dev);
+ return;
+ }
+ qat_priv = dev->data->dev_private;
+
+ qat_stats_reset(qat_priv->qat_dev, QAT_SERVICE_COMPRESSION);
+
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index cd04f11..27d84c8 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -28,5 +28,12 @@ struct qat_comp_dev_private {
};
+void
+qat_comp_stats_reset(struct rte_compressdev *dev);
+
+void
+qat_comp_stats_get(struct rte_compressdev *dev,
+ struct rte_compressdev_stats *stats);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v3 08/16] compress/qat: setup queue-pairs for compression service
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 00/16] " Fiona Trahe
` (7 preceding siblings ...)
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 07/16] compress/qat: add stats functions Fiona Trahe
@ 2018-07-05 17:32 ` Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 09/16] compress/qat: add fns to configure and clear device Fiona Trahe
` (7 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 17:32 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Setup and clear queue-pairs for handling compression
requests and responses.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp.h | 2 ++
drivers/compress/qat/qat_comp_pmd.c | 62 +++++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 6 ++++
3 files changed, 70 insertions(+)
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 937f3c8..9e6861b 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -24,6 +24,8 @@ enum qat_comp_request_type {
REQ_COMP_END
};
+struct qat_comp_op_cookie {
+};
struct qat_comp_xform {
struct icp_qat_fw_comp_req qat_comp_req_tmpl;
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 6feffb7..e7252b2 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -2,6 +2,7 @@
* Copyright(c) 2015-2018 Intel Corporation
*/
+#include "qat_comp.h"
#include "qat_comp_pmd.h"
void
@@ -38,3 +39,64 @@ qat_comp_stats_reset(struct rte_compressdev *dev)
qat_stats_reset(qat_priv->qat_dev, QAT_SERVICE_COMPRESSION);
}
+
+int
+qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)
+{
+ struct qat_comp_dev_private *qat_private = dev->data->dev_private;
+
+ QAT_LOG(DEBUG, "Release comp qp %u on device %d",
+ queue_pair_id, dev->data->dev_id);
+
+ qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][queue_pair_id]
+ = NULL;
+
+ return qat_qp_release((struct qat_qp **)
+ &(dev->data->queue_pairs[queue_pair_id]));
+}
+
+int
+qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
+ uint32_t max_inflight_ops, int socket_id)
+{
+ int ret = 0;
+ struct qat_qp_config qat_qp_conf;
+
+ struct qat_qp **qp_addr =
+ (struct qat_qp **)&(dev->data->queue_pairs[qp_id]);
+ struct qat_comp_dev_private *qat_private = dev->data->dev_private;
+ const struct qat_qp_hw_data *comp_hw_qps =
+ qat_gen_config[qat_private->qat_dev->qat_dev_gen]
+ .qp_hw_data[QAT_SERVICE_COMPRESSION];
+ const struct qat_qp_hw_data *qp_hw_data = comp_hw_qps + qp_id;
+
+ /* If qp is already in use free ring memory and qp metadata. */
+ if (*qp_addr != NULL) {
+ ret = qat_comp_qp_release(dev, qp_id);
+ if (ret < 0)
+ return ret;
+ }
+ if (qp_id >= qat_qps_per_service(comp_hw_qps,
+ QAT_SERVICE_COMPRESSION)) {
+ QAT_LOG(ERR, "qp_id %u invalid for this device", qp_id);
+ return -EINVAL;
+ }
+
+ qat_qp_conf.hw = qp_hw_data;
+ qat_qp_conf.build_request = qat_comp_build_request;
+ qat_qp_conf.cookie_size = sizeof(struct qat_comp_op_cookie);
+ qat_qp_conf.nb_descriptors = max_inflight_ops;
+ qat_qp_conf.socket_id = socket_id;
+ qat_qp_conf.service_str = "comp";
+
+ ret = qat_qp_setup(qat_private->qat_dev, qp_addr, qp_id, &qat_qp_conf);
+ if (ret != 0)
+ return ret;
+
+ /* store a link to the qp in the qat_pci_device */
+ qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][qp_id]
+ = *qp_addr;
+
+ return ret;
+}
+
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 27d84c8..5a4bc31 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -34,6 +34,12 @@ qat_comp_stats_reset(struct rte_compressdev *dev);
void
qat_comp_stats_get(struct rte_compressdev *dev,
struct rte_compressdev_stats *stats);
+int
+qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id);
+
+int
+qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
+ uint32_t max_inflight_ops, int socket_id);
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v3 09/16] compress/qat: add fns to configure and clear device
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 00/16] " Fiona Trahe
` (8 preceding siblings ...)
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 08/16] compress/qat: setup queue-pairs for compression service Fiona Trahe
@ 2018-07-05 17:32 ` Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 10/16] compress/qat: add fn to return device info Fiona Trahe
` (6 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 17:32 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add functions to configure and clear the qat comp device,
including the creation and freeing of the xform pool
and the freeing of queue-pairs.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 96 +++++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 7 +++
2 files changed, 103 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index e7252b2..dfdb373 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -100,3 +100,99 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
return ret;
}
+
+static struct rte_mempool *
+qat_comp_create_xform_pool(struct qat_comp_dev_private *comp_dev,
+ uint32_t num_elements)
+{
+ char xform_pool_name[RTE_MEMPOOL_NAMESIZE];
+ struct rte_mempool *mp;
+
+ snprintf(xform_pool_name, RTE_MEMPOOL_NAMESIZE,
+ "%s_xforms", comp_dev->qat_dev->name);
+
+ QAT_LOG(DEBUG, "xformpool: %s", xform_pool_name);
+ mp = rte_mempool_lookup(xform_pool_name);
+
+ if (mp != NULL) {
+ QAT_LOG(DEBUG, "xformpool already created");
+ if (mp->size != num_elements) {
+ QAT_LOG(DEBUG, "xformpool wrong size - delete it");
+ rte_mempool_free(mp);
+ mp = NULL;
+ comp_dev->xformpool = NULL;
+ }
+ }
+
+ if (mp == NULL)
+ mp = rte_mempool_create(xform_pool_name,
+ num_elements,
+ qat_comp_xform_size(), 0, 0,
+ NULL, NULL, NULL, NULL, rte_socket_id(),
+ 0);
+ if (mp == NULL) {
+ QAT_LOG(ERR, "Err creating mempool %s w %d elements of size %d",
+ xform_pool_name, num_elements, qat_comp_xform_size());
+ return NULL;
+ }
+
+ return mp;
+}
+
+static void
+_qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)
+{
+ /* Free private_xform pool */
+ if (comp_dev->xformpool) {
+ /* Free internal mempool for private xforms */
+ rte_mempool_free(comp_dev->xformpool);
+ comp_dev->xformpool = NULL;
+ }
+}
+
+int
+qat_comp_dev_config(struct rte_compressdev *dev,
+ struct rte_compressdev_config *config)
+{
+ struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
+ int ret = 0;
+
+ if (config->max_nb_streams != 0) {
+ QAT_LOG(ERR,
+ "QAT device does not support STATEFUL so max_nb_streams must be 0");
+ return -EINVAL;
+ }
+
+ comp_dev->xformpool = qat_comp_create_xform_pool(comp_dev,
+ config->max_nb_priv_xforms);
+ if (comp_dev->xformpool == NULL) {
+
+ ret = -ENOMEM;
+ goto error_out;
+ }
+ return 0;
+
+error_out:
+ _qat_comp_dev_config_clear(comp_dev);
+ return ret;
+}
+
+
+int
+qat_comp_dev_close(struct rte_compressdev *dev)
+{
+ int i;
+ int ret = 0;
+ struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
+
+ for (i = 0; i < dev->data->nb_queue_pairs; i++) {
+ ret = qat_comp_qp_release(dev, i);
+ if (ret < 0)
+ return ret;
+ }
+
+ _qat_comp_dev_config_clear(comp_dev);
+
+ return ret;
+}
+
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 5a4bc31..b10a66f 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -41,5 +41,12 @@ int
qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
uint32_t max_inflight_ops, int socket_id);
+int
+qat_comp_dev_config(struct rte_compressdev *dev,
+ struct rte_compressdev_config *config);
+
+int
+qat_comp_dev_close(struct rte_compressdev *dev);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v3 10/16] compress/qat: add fn to return device info
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 00/16] " Fiona Trahe
` (9 preceding siblings ...)
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 09/16] compress/qat: add fns to configure and clear device Fiona Trahe
@ 2018-07-05 17:32 ` Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 11/16] compress/qat: add enqueue/dequeue functions Fiona Trahe
` (5 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 17:32 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add capabilities pointer to internal qat comp device
and function to return this and other info.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 18 ++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 6 ++++++
2 files changed, 24 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index dfdb373..2b64130 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -196,3 +196,21 @@ qat_comp_dev_close(struct rte_compressdev *dev)
return ret;
}
+
+void
+qat_comp_dev_info_get(struct rte_compressdev *dev,
+ struct rte_compressdev_info *info)
+{
+ struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
+ const struct qat_qp_hw_data *comp_hw_qps =
+ qat_gen_config[comp_dev->qat_dev->qat_dev_gen]
+ .qp_hw_data[QAT_SERVICE_COMPRESSION];
+
+ if (info != NULL) {
+ info->max_nb_queue_pairs =
+ qat_qps_per_service(comp_hw_qps,
+ QAT_SERVICE_COMPRESSION);
+ info->feature_flags = dev->feature_flags;
+ info->capabilities = comp_dev->qat_dev_capabilities;
+ }
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index b10a66f..22576f4 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -21,6 +21,8 @@ struct qat_comp_dev_private {
/**< The qat pci device hosting the service */
struct rte_compressdev *compressdev;
/**< The pointer to this compression device structure */
+ const struct rte_compressdev_capabilities *qat_dev_capabilities;
+ /* QAT device compression capabilities */
const struct rte_memzone *interm_buff_mz;
/**< The device's memory for intermediate buffers */
struct rte_mempool *xformpool;
@@ -48,5 +50,9 @@ qat_comp_dev_config(struct rte_compressdev *dev,
int
qat_comp_dev_close(struct rte_compressdev *dev);
+void
+qat_comp_dev_info_get(struct rte_compressdev *dev,
+ struct rte_compressdev_info *info);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v3 11/16] compress/qat: add enqueue/dequeue functions
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 00/16] " Fiona Trahe
` (10 preceding siblings ...)
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 10/16] compress/qat: add fn to return device info Fiona Trahe
@ 2018-07-05 17:32 ` Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 12/16] compress/qat: add device start and stop fns Fiona Trahe
` (4 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 17:32 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Wrap generic qat enqueue/dequeue functions with
compressdev enqueue and dequeue fns.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 14 ++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 8 ++++++++
2 files changed, 22 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 2b64130..fc99cca 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -214,3 +214,17 @@ qat_comp_dev_info_get(struct rte_compressdev *dev,
info->capabilities = comp_dev->qat_dev_capabilities;
}
}
+
+uint16_t
+qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops)
+{
+ return qat_enqueue_op_burst(qp, (void **)ops, nb_ops);
+}
+
+uint16_t
+qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops)
+{
+ return qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 22576f4..f360c29 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -54,5 +54,13 @@ void
qat_comp_dev_info_get(struct rte_compressdev *dev,
struct rte_compressdev_info *info);
+uint16_t
+qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops);
+
+uint16_t
+qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v3 12/16] compress/qat: add device start and stop fns
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 00/16] " Fiona Trahe
` (11 preceding siblings ...)
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 11/16] compress/qat: add enqueue/dequeue functions Fiona Trahe
@ 2018-07-05 17:32 ` Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 13/16] compress/qat: create and populate the ops structure Fiona Trahe
` (3 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 17:32 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
There are no specific actions needed to start/stop a QAT comp device
so these are just trivial fns to satisfy the pmd API.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 11 +++++++++++
drivers/compress/qat/qat_comp_pmd.h | 6 ++++++
2 files changed, 17 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index fc99cca..bf07989 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -177,6 +177,17 @@ qat_comp_dev_config(struct rte_compressdev *dev,
return ret;
}
+int
+qat_comp_dev_start(struct rte_compressdev *dev __rte_unused)
+{
+ return 0;
+}
+
+void
+qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused)
+{
+
+}
int
qat_comp_dev_close(struct rte_compressdev *dev)
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index f360c29..22cbefb 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -62,5 +62,11 @@ uint16_t
qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops);
+int
+qat_comp_dev_start(struct rte_compressdev *dev __rte_unused);
+
+void
+qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v3 13/16] compress/qat: create and populate the ops structure
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 00/16] " Fiona Trahe
` (12 preceding siblings ...)
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 12/16] compress/qat: add device start and stop fns Fiona Trahe
@ 2018-07-05 17:32 ` Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 14/16] compress/qat: add fns to create and destroy the PMD Fiona Trahe
` (2 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 17:32 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Create an ops structure and populate it with the
qat-specific functions.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 38 ++++++++++++++++++++++++++++---------
drivers/compress/qat/qat_comp_pmd.h | 30 -----------------------------
2 files changed, 29 insertions(+), 39 deletions(-)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index bf07989..41946af 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -5,7 +5,7 @@
#include "qat_comp.h"
#include "qat_comp_pmd.h"
-void
+static void
qat_comp_stats_get(struct rte_compressdev *dev,
struct rte_compressdev_stats *stats)
{
@@ -25,7 +25,7 @@ qat_comp_stats_get(struct rte_compressdev *dev,
stats->dequeue_err_count = qat_stats.dequeue_err_count;
}
-void
+static void
qat_comp_stats_reset(struct rte_compressdev *dev)
{
struct qat_comp_dev_private *qat_priv;
@@ -40,7 +40,7 @@ qat_comp_stats_reset(struct rte_compressdev *dev)
}
-int
+static int
qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)
{
struct qat_comp_dev_private *qat_private = dev->data->dev_private;
@@ -55,7 +55,7 @@ qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)
&(dev->data->queue_pairs[queue_pair_id]));
}
-int
+static int
qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
uint32_t max_inflight_ops, int socket_id)
{
@@ -150,7 +150,7 @@ _qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)
}
}
-int
+static int
qat_comp_dev_config(struct rte_compressdev *dev,
struct rte_compressdev_config *config)
{
@@ -177,19 +177,19 @@ qat_comp_dev_config(struct rte_compressdev *dev,
return ret;
}
-int
+static int
qat_comp_dev_start(struct rte_compressdev *dev __rte_unused)
{
return 0;
}
-void
+static void
qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused)
{
}
-int
+static int
qat_comp_dev_close(struct rte_compressdev *dev)
{
int i;
@@ -208,7 +208,7 @@ qat_comp_dev_close(struct rte_compressdev *dev)
}
-void
+static void
qat_comp_dev_info_get(struct rte_compressdev *dev,
struct rte_compressdev_info *info)
{
@@ -239,3 +239,23 @@ qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
{
return qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
}
+
+
+struct rte_compressdev_ops compress_qat_ops = {
+
+ /* Device related operations */
+ .dev_configure = qat_comp_dev_config,
+ .dev_start = qat_comp_dev_start,
+ .dev_stop = qat_comp_dev_stop,
+ .dev_close = qat_comp_dev_close,
+ .dev_infos_get = qat_comp_dev_info_get,
+
+ .stats_get = qat_comp_stats_get,
+ .stats_reset = qat_comp_stats_reset,
+ .queue_pair_setup = qat_comp_qp_setup,
+ .queue_pair_release = qat_comp_qp_release,
+
+ /* Compression related operations */
+ .private_xform_create = qat_comp_private_xform_create,
+ .private_xform_free = qat_comp_private_xform_free
+};
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 22cbefb..7ba1b8d 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -30,30 +30,6 @@ struct qat_comp_dev_private {
};
-void
-qat_comp_stats_reset(struct rte_compressdev *dev);
-
-void
-qat_comp_stats_get(struct rte_compressdev *dev,
- struct rte_compressdev_stats *stats);
-int
-qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id);
-
-int
-qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
- uint32_t max_inflight_ops, int socket_id);
-
-int
-qat_comp_dev_config(struct rte_compressdev *dev,
- struct rte_compressdev_config *config);
-
-int
-qat_comp_dev_close(struct rte_compressdev *dev);
-
-void
-qat_comp_dev_info_get(struct rte_compressdev *dev,
- struct rte_compressdev_info *info);
-
uint16_t
qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops);
@@ -62,11 +38,5 @@ uint16_t
qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops);
-int
-qat_comp_dev_start(struct rte_compressdev *dev __rte_unused);
-
-void
-qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused);
-
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v3 14/16] compress/qat: add fns to create and destroy the PMD
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 00/16] " Fiona Trahe
` (13 preceding siblings ...)
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 13/16] compress/qat: create and populate the ops structure Fiona Trahe
@ 2018-07-05 17:32 ` Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 15/16] compress/qat: prevent device usage if incorrect firmware Fiona Trahe
2018-07-05 17:33 ` [dpdk-dev] [PATCH v3 16/16] docs/qat: refactor docs adding compression guide Fiona Trahe
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 17:32 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Now that all the device operations are available,
add the functions to create and destroy the pmd.
Called on probe and remove of the qat pci device, these
register the device with the compressdev API
and plug in all the device functionality.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/common/qat/qat_device.h | 4 ++
drivers/common/qat/qat_qp.c | 11 ++++-
drivers/common/qat/qat_qp.h | 5 ++
drivers/compress/qat/qat_comp_pmd.c | 95 +++++++++++++++++++++++++++++++++++--
drivers/compress/qat/qat_comp_pmd.h | 11 ++---
5 files changed, 114 insertions(+), 12 deletions(-)
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index 0cb370c..9599fc5 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -25,6 +25,8 @@
* - runtime data
*/
struct qat_sym_dev_private;
+struct qat_comp_dev_private;
+
struct qat_pci_device {
/* Data used by all services */
@@ -55,6 +57,8 @@ struct qat_pci_device {
*/
/* Data relating to compression service */
+ struct qat_comp_dev_private *comp_dev;
+ /**< link back to compressdev private data */
/* Data relating to asymmetric crypto service */
diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c
index 32c1759..7ca7a45 100644
--- a/drivers/common/qat/qat_qp.c
+++ b/drivers/common/qat/qat_qp.c
@@ -15,6 +15,7 @@
#include "qat_device.h"
#include "qat_qp.h"
#include "qat_sym.h"
+#include "qat_comp.h"
#include "adf_transport_access_macros.h"
@@ -606,8 +607,8 @@ qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
if (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC)
qat_sym_process_response(ops, resp_msg);
- /* add qat_asym_process_response here */
- /* add qat_comp_process_response here */
+ else if (tmp_qp->service_type == QAT_SERVICE_COMPRESSION)
+ qat_comp_process_response(ops, resp_msg);
head = adf_modulo(head + rx_queue->msg_size,
rx_queue->modulo_mask);
@@ -633,3 +634,9 @@ qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
}
return resp_counter;
}
+
+__attribute__((weak)) int
+qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused)
+{
+ return 0;
+}
diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h
index 59db945..69f8a61 100644
--- a/drivers/common/qat/qat_qp.h
+++ b/drivers/common/qat/qat_qp.h
@@ -103,4 +103,9 @@ qat_qp_setup(struct qat_pci_device *qat_dev,
int
qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,
enum qat_service_type service);
+
+/* Needed for weak function*/
+int
+qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused);
+
#endif /* _QAT_QP_H_ */
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 41946af..4ff1518 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -5,6 +5,15 @@
#include "qat_comp.h"
#include "qat_comp_pmd.h"
+static const struct rte_compressdev_capabilities qat_comp_gen_capabilities[] = {
+ {/* COMPRESSION - deflate */
+ .algo = RTE_COMP_ALGO_DEFLATE,
+ .comp_feature_flags = RTE_COMP_FF_MULTI_PKT_CHECKSUM |
+ RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
+ RTE_COMP_FF_HUFFMAN_FIXED,
+ .window_size = {.min = 15, .max = 15, .increment = 0} },
+ {RTE_COMP_ALGO_LIST_END, 0, {0, 0, 0} } };
+
static void
qat_comp_stats_get(struct rte_compressdev *dev,
struct rte_compressdev_stats *stats)
@@ -226,14 +235,14 @@ qat_comp_dev_info_get(struct rte_compressdev *dev,
}
}
-uint16_t
+static uint16_t
qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops)
{
return qat_enqueue_op_burst(qp, (void **)ops, nb_ops);
}
-uint16_t
+static uint16_t
qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops)
{
@@ -241,7 +250,7 @@ qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
}
-struct rte_compressdev_ops compress_qat_ops = {
+static struct rte_compressdev_ops compress_qat_ops = {
/* Device related operations */
.dev_configure = qat_comp_dev_config,
@@ -259,3 +268,83 @@ struct rte_compressdev_ops compress_qat_ops = {
.private_xform_create = qat_comp_private_xform_create,
.private_xform_free = qat_comp_private_xform_free
};
+
+int
+qat_comp_dev_create(struct qat_pci_device *qat_pci_dev)
+{
+ if (qat_pci_dev->qat_dev_gen == QAT_GEN1) {
+ QAT_LOG(ERR, "Compression PMD not supported on QAT dh895xcc");
+ return 0;
+ }
+
+ struct rte_compressdev_pmd_init_params init_params = {
+ .name = "",
+ .socket_id = qat_pci_dev->pci_dev->device.numa_node,
+ };
+ char name[RTE_COMPRESSDEV_NAME_MAX_LEN];
+ struct rte_compressdev *compressdev;
+ struct qat_comp_dev_private *comp_dev;
+
+ snprintf(name, RTE_COMPRESSDEV_NAME_MAX_LEN, "%s_%s",
+ qat_pci_dev->name, "comp");
+ QAT_LOG(DEBUG, "Creating QAT COMP device %s", name);
+
+ compressdev = rte_compressdev_pmd_create(name,
+ &qat_pci_dev->pci_dev->device,
+ sizeof(struct qat_comp_dev_private),
+ &init_params);
+
+ if (compressdev == NULL)
+ return -ENODEV;
+
+ compressdev->dev_ops = &compress_qat_ops;
+
+ compressdev->enqueue_burst = qat_comp_pmd_enqueue_op_burst;
+ compressdev->dequeue_burst = qat_comp_pmd_dequeue_op_burst;
+
+ compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
+
+ comp_dev = compressdev->data->dev_private;
+ comp_dev->qat_dev = qat_pci_dev;
+ comp_dev->compressdev = compressdev;
+ qat_pci_dev->comp_dev = comp_dev;
+
+ switch (qat_pci_dev->qat_dev_gen) {
+ case QAT_GEN1:
+ case QAT_GEN2:
+ comp_dev->qat_dev_capabilities = qat_comp_gen_capabilities;
+ break;
+ default:
+ comp_dev->qat_dev_capabilities = qat_comp_gen_capabilities;
+ QAT_LOG(DEBUG,
+ "QAT gen %d capabilities unknown, default to GEN1",
+ qat_pci_dev->qat_dev_gen);
+ break;
+ }
+
+ QAT_LOG(DEBUG,
+ "Created QAT COMP device %s as compressdev instance %d",
+ name, compressdev->data->dev_id);
+ return 0;
+}
+
+int
+qat_comp_dev_destroy(struct qat_pci_device *qat_pci_dev)
+{
+ struct qat_comp_dev_private *comp_dev;
+
+ if (qat_pci_dev == NULL)
+ return -ENODEV;
+
+ comp_dev = qat_pci_dev->comp_dev;
+ if (comp_dev == NULL)
+ return 0;
+
+ /* clean up any resources used by the device */
+ qat_comp_dev_close(comp_dev->compressdev);
+
+ rte_compressdev_pmd_destroy(comp_dev->compressdev);
+ qat_pci_dev->comp_dev = NULL;
+
+ return 0;
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 7ba1b8d..9ad2a28 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -27,16 +27,13 @@ struct qat_comp_dev_private {
/**< The device's memory for intermediate buffers */
struct rte_mempool *xformpool;
/**< The device's pool for qat_comp_xforms */
-
};
-uint16_t
-qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
- uint16_t nb_ops);
+int
+qat_comp_dev_create(struct qat_pci_device *qat_pci_dev);
-uint16_t
-qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
- uint16_t nb_ops);
+int
+qat_comp_dev_destroy(struct qat_pci_device *qat_pci_dev);
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v3 15/16] compress/qat: prevent device usage if incorrect firmware
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 00/16] " Fiona Trahe
` (14 preceding siblings ...)
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 14/16] compress/qat: add fns to create and destroy the PMD Fiona Trahe
@ 2018-07-05 17:32 ` Fiona Trahe
2018-07-05 17:33 ` [dpdk-dev] [PATCH v3 16/16] docs/qat: refactor docs adding compression guide Fiona Trahe
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 17:32 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Previous check only causes op to fail on dequeue.
This extends so once first fail is detected, application can
no longer enqueue ops to the device and will also get an
appropriate error if trying to reconfigure or setup the device.
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 57 ++++++++++++++++++++++++++++++++++++-
1 file changed, 56 insertions(+), 1 deletion(-)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 4ff1518..89b7ad6 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -250,6 +250,61 @@ qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
}
+static uint16_t
+qat_comp_pmd_enq_deq_dummy_op_burst(void *qp __rte_unused,
+ struct rte_comp_op **ops __rte_unused,
+ uint16_t nb_ops __rte_unused)
+{
+ QAT_DP_LOG(ERR, "QAT PMD detected wrong FW version !");
+ return 0;
+}
+
+static struct rte_compressdev_ops compress_qat_dummy_ops = {
+
+ /* Device related operations */
+ .dev_configure = NULL,
+ .dev_start = NULL,
+ .dev_stop = qat_comp_dev_stop,
+ .dev_close = qat_comp_dev_close,
+ .dev_infos_get = NULL,
+
+ .stats_get = NULL,
+ .stats_reset = qat_comp_stats_reset,
+ .queue_pair_setup = NULL,
+ .queue_pair_release = qat_comp_qp_release,
+
+ /* Compression related operations */
+ .private_xform_create = NULL,
+ .private_xform_free = qat_comp_private_xform_free
+};
+
+static uint16_t
+qat_comp_pmd_dequeue_frst_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops)
+{
+ uint16_t ret = qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
+ struct qat_qp *tmp_qp = (struct qat_qp *)qp;
+
+ if (ret) {
+ if ((*ops)->debug_status ==
+ (uint64_t)ERR_CODE_QAT_COMP_WRONG_FW) {
+ tmp_qp->qat_dev->comp_dev->compressdev->enqueue_burst =
+ qat_comp_pmd_enq_deq_dummy_op_burst;
+ tmp_qp->qat_dev->comp_dev->compressdev->dequeue_burst =
+ qat_comp_pmd_enq_deq_dummy_op_burst;
+
+ tmp_qp->qat_dev->comp_dev->compressdev->dev_ops =
+ &compress_qat_dummy_ops;
+ QAT_LOG(ERR, "QAT PMD detected wrong FW version !");
+
+ } else {
+ tmp_qp->qat_dev->comp_dev->compressdev->dequeue_burst =
+ qat_comp_pmd_dequeue_op_burst;
+ }
+ }
+ return ret;
+}
+
static struct rte_compressdev_ops compress_qat_ops = {
/* Device related operations */
@@ -300,7 +355,7 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev)
compressdev->dev_ops = &compress_qat_ops;
compressdev->enqueue_burst = qat_comp_pmd_enqueue_op_burst;
- compressdev->dequeue_burst = qat_comp_pmd_dequeue_op_burst;
+ compressdev->dequeue_burst = qat_comp_pmd_dequeue_frst_op_burst;
compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v3 16/16] docs/qat: refactor docs adding compression guide
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 00/16] " Fiona Trahe
` (15 preceding siblings ...)
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 15/16] compress/qat: prevent device usage if incorrect firmware Fiona Trahe
@ 2018-07-05 17:33 ` Fiona Trahe
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-05 17:33 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Extend QAT guide to cover crypto and compression and common
information, particularly about kernel driver dependency.
Update release note.
Update compression feature list for qat.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
config/common_base | 2 +-
doc/guides/compressdevs/features/qat.ini | 22 ++++
doc/guides/compressdevs/index.rst | 1 +
doc/guides/compressdevs/qat_comp.rst | 49 +++++++++
doc/guides/cryptodevs/qat.rst | 183 +++++++++++++++++++++----------
doc/guides/rel_notes/release_18_08.rst | 5 +
6 files changed, 203 insertions(+), 59 deletions(-)
create mode 100644 doc/guides/compressdevs/features/qat.ini
create mode 100644 doc/guides/compressdevs/qat_comp.rst
diff --git a/config/common_base b/config/common_base
index 93c8857..402231d 100644
--- a/config/common_base
+++ b/config/common_base
@@ -482,7 +482,7 @@ CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4
CONFIG_RTE_DPAA_SEC_PMD_MAX_NB_SESSIONS=2048
#
-# Compile PMD for QuickAssist based devices
+# Compile PMD for QuickAssist based devices - see docs for details
#
CONFIG_RTE_LIBRTE_PMD_QAT=y
CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
diff --git a/doc/guides/compressdevs/features/qat.ini b/doc/guides/compressdevs/features/qat.ini
new file mode 100644
index 0000000..68f36c8
--- /dev/null
+++ b/doc/guides/compressdevs/features/qat.ini
@@ -0,0 +1,22 @@
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+; Supported features of 'QAT' compression driver.
+;
+[Features]
+HW Accelerated = Y
+CPU SSE =
+CPU AVX =
+CPU AVX2 =
+CPU AVX512 =
+CPU NEON =
+Stateful =
+By-Pass =
+Chained mbufs =
+Deflate = Y
+LZS =
+Adler32 = Y
+Crc32 = Y
+Adler32&Crc32 = Y
+Fixed = Y
+Dynamic =
diff --git a/doc/guides/compressdevs/index.rst b/doc/guides/compressdevs/index.rst
index bc59ce8..4228768 100644
--- a/doc/guides/compressdevs/index.rst
+++ b/doc/guides/compressdevs/index.rst
@@ -11,3 +11,4 @@ Compression Device Drivers
overview
isal
+ qat_comp
diff --git a/doc/guides/compressdevs/qat_comp.rst b/doc/guides/compressdevs/qat_comp.rst
new file mode 100644
index 0000000..167f816
--- /dev/null
+++ b/doc/guides/compressdevs/qat_comp.rst
@@ -0,0 +1,49 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+ Copyright(c) 2018 Intel Corporation.
+
+Intel(R) QuickAssist (QAT) Compression Poll Mode Driver
+=======================================================
+
+The QAT compression PMD provides poll mode compression & decompression driver
+support for the following hardware accelerator devices:
+
+* ``Intel QuickAssist Technology C62x``
+* ``Intel QuickAssist Technology C3xxx``
+
+
+Features
+--------
+
+QAT compression PMD has support for:
+
+Compression/Decompression algorithm:
+
+ * DEFLATE
+
+Huffman code type:
+
+ * FIXED
+
+Window size support:
+
+ * 32K
+
+Checksum generation:
+
+ * CRC32, Adler and combined checksum
+
+Limitations
+-----------
+
+* Chained mbufs are not yet supported, therefore max data size which can be passed to the PMD in a single mbuf is 64K - 1. If data is larger than this it will need to be split up and sent as multiple operations.
+
+* Compressdev level 0, no compression, is not supported.
+
+* Dynamic Huffman encoding is not yet supported.
+
+Installation
+------------
+
+The QAT compression PMD is built by default with a standard DPDK build.
+
+It depends on a QAT kernel driver, see :ref:`qat_kernel_installation`.
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index b899985..bdc58eb 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -68,12 +68,32 @@ Limitations
* Queue pairs are not thread-safe (that is, within a single queue pair, RX and TX from different lcores is not supported).
-Installation
-------------
+Extra notes on KASUMI F9
+------------------------
+
+When using KASUMI F9 authentication algorithm, the input buffer must be
+constructed according to the 3GPP KASUMI specifications (section 4.4, page 13):
+`<http://cryptome.org/3gpp/35201-900.pdf>`_.
+Input buffer has to have COUNT (4 bytes), FRESH (4 bytes), MESSAGE and DIRECTION (1 bit)
+concatenated. After the DIRECTION bit, a single '1' bit is appended, followed by
+between 0 and 7 '0' bits, so that the total length of the buffer is multiple of 8 bits.
+Note that the actual message can be any length, specified in bits.
-To enable QAT in DPDK, follow the instructions for modifying the compile-time
+Once this buffer is passed this way, when creating the crypto operation,
+length of data to authenticate (op.sym.auth.data.length) must be the length
+of all the items described above, including the padding at the end.
+Also, offset of data to authenticate (op.sym.auth.data.offset)
+must be such that points at the start of the COUNT bytes.
+
+
+Building the DPDK QAT cryptodev PMD
+-----------------------------------
+
+
+To enable QAT crypto in DPDK, follow the instructions for modifying the compile-time
configuration file as described `here <http://dpdk.org/doc/guides/linux_gsg/build_dpdk.html>`_.
+
Quick instructions are as follows:
.. code-block:: console
@@ -81,29 +101,95 @@ Quick instructions are as follows:
cd to the top-level DPDK directory
make config T=x86_64-native-linuxapp-gcc
sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT\)=n,\1=y,' build/.config
+ sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT_SYM\)=n,\1=y,' build/.config
make
-To use the DPDK QAT PMD an SRIOV-enabled QAT kernel driver is required. The VF
-devices exposed by this driver will be used by the QAT PMD. The devices and
-available kernel drivers and device ids are :
+
+.. _qat_kernel_installation:
+
+Dependency on the QAT kernel driver
+-----------------------------------
+
+To use the QAT PMD an SRIOV-enabled QAT kernel driver is required. The VF
+devices created and initialised by this driver will be used by the QAT PMD.
+
+Instructions for installation are below, but first an explanation of the
+relationships between the PF/VF devices and the PMDs visible to
+DPDK applications.
+
+
+Acceleration services - cryptography and compression - are provided to DPDK
+applications via PMDs which register to implement the corresponding
+cryptodev and compressdev APIs.
+
+Each QuickAssist VF device can expose one cryptodev PMD and/or one compressdev PMD.
+These QAT PMDs share the same underlying device and pci-mgmt code, but are
+enumerated independently on their respective APIs and appear as independent
+devices to applications.
+
+.. Note::
+
+ Each VF can only be used by one DPDK process. It is not possible to share
+ the same VF across multiple processes, even if these processes are using
+ different acceleration services.
+
+ Conversely one DPDK process can use one or more QAT VFs and can expose both
+ cryptodev and compressdev instances on each of those VFs.
+
+
+
+Device and driver naming
+------------------------
+
+* The qat cryptodev driver name is "crypto_qat".
+ The rte_cryptodev_devices_get() returns the devices exposed by this driver.
+
+* Each qat crypto device has a unique name, in format
+ <pci bdf>_<service>, e.g. "0000:41:01.0_qat_sym".
+ This name can be passed to rte_cryptodev_get_dev_id() to get the device_id.
+
+.. Note::
+
+ The qat crypto driver name is passed to the dpdk-test-crypto-perf tool in the -devtype parameter.
+
+ The qat crypto device name is in the format of the slave parameter passed to the crypto scheduler.
+
+* The qat compressdev driver name is "comp_qat".
+ The rte_compressdev_devices_get() returns the devices exposed by this driver.
+
+* Each qat compression device has a unique name, in format
+ <pci bdf>_<service>, e.g. "0000:41:01.0_qat_comp".
+ This name can be passed to rte_compressdev_get_dev_id() to get the device_id.
+
+
+Available kernel drivers
+------------------------
+
+Kernel drivers for each device are listed in the following table. Scroll right
+to check that the driver and device supports the servic you require.
+
.. _table_qat_pmds_drivers:
.. table:: QAT device generations, devices and drivers
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | Gen | Device | Driver | Kernel Module | Pci Driver | PF Did | #PFs | Vf Did | VFs/PF |
- +=====+==========+========+===============+============+========+======+========+========+
- | 1 | DH895xCC | 01.org | icp_qa_al | n/a | 435 | 1 | 443 | 32 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | 1 | DH895xCC | 4.4+ | qat_dh895xcc | dh895xcc | 435 | 1 | 443 | 32 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | 2 | C62x | 4.5+ | qat_c62x | c6xx | 37c8 | 3 | 37c9 | 16 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | 2 | C3xxx | 4.5+ | qat_c3xxx | c3xxx | 19e2 | 1 | 19e3 | 16 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | 2 | D15xx | p | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | Gen | Device | Driver/ver | Kernel Module | Pci Driver | PF Did | #PFs | VF Did | VFs/PF | cryptodev | compressdev |
+ +=====+==========+===============+===============+============+========+======+========+========+===========+=============+
+ | 1 | DH895xCC | linux/4.4+ | qat_dh895xcc | dh895xcc | 435 | 1 | 443 | 32 | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | 2 | C62x | linux/4.5+ | qat_c62x | c6xx | 37c8 | 3 | 37c9 | 16 | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | Yes | Yes |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | 2 | C3xxx | linux/4.5+ | qat_c3xxx | c3xxx | 19e2 | 1 | 19e3 | 16 | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | Yes | Yes |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | 2 | D15xx | p | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
The ``Driver`` column indicates either the Linux kernel version in which
@@ -196,9 +282,9 @@ Consult the *Getting Started Guide* at the same URL for further information.
The steps below assume you are:
-* Building on a platform with one ``DH895xCC`` device.
-* Using package ``qatmux.l.2.3.0-34.tgz``.
-* On Fedora21 kernel ``3.17.4-301.fc21.x86_64``.
+* Building on a platform with one ``C62x`` device.
+* Using package ``qat1.7.l.4.2.0-000xx.tar.gz``.
+* On Fedora26 kernel ``4.11.11-300.fc26.x86_64``.
In the BIOS ensure that SRIOV is enabled and VT-d is disabled.
@@ -206,21 +292,30 @@ Uninstall any existing QAT driver, for example by running:
* ``./installer.sh uninstall`` in the directory where originally installed.
-* or ``rmmod qat_dh895xcc; rmmod intel_qat``.
Build and install the SRIOV-enabled QAT driver::
mkdir /QAT
cd /QAT
- # Copy qatmux.l.2.3.0-34.tgz to this location
- tar zxof qatmux.l.2.3.0-34.tgz
+ # Copy the package to this location and unpack
+ tar zxof qat1.7.l.4.2.0-000xx.tar.gz
- export ICP_WITHOUT_IOMMU=1
- ./installer.sh install QAT1.6 host
+ ./configure --enable-icp-sriov=host
+ make install
+
+You can use ``cat /sys/kernel/debug/qat<your device type and bdf>/version/fw`` to confirm the driver is correctly installed and is using firmware version 4.2.0.
+You can use ``lspci -d:37c9`` to confirm the presence of the 16 VF devices available per ``C62x`` PF.
+
+Confirm the driver is correctly installed and is using firmware version 4.2.0::
+
+ cat /sys/kernel/debug/qat<your device type and bdf>/version/fw
+
+
+Confirm the presence of 48 VF devices - 16 per PF::
+
+ lspci -d:37c9
-You can use ``cat /proc/icp_dh895xcc_dev0/version`` to confirm the driver is correctly installed.
-You can use ``lspci -d:443`` to confirm the of the 32 VF devices available per ``DH895xCC`` device.
To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_.
@@ -261,6 +356,7 @@ To complete the installation - follow instructions in `Binding the available VFs
sudo yum install zlib-devel
sudo yum install openssl-devel
+ sudo yum install libudev-devel
.. Note::
@@ -343,35 +439,6 @@ Another way to bind the VFs to the DPDK UIO driver is by using the
./usertools/dpdk-devbind.py -b igb_uio 0000:03:01.1
-Extra notes on KASUMI F9
-------------------------
-
-When using KASUMI F9 authentication algorithm, the input buffer must be
-constructed according to the 3GPP KASUMI specifications (section 4.4, page 13):
-`<http://cryptome.org/3gpp/35201-900.pdf>`_.
-Input buffer has to have COUNT (4 bytes), FRESH (4 bytes), MESSAGE and DIRECTION (1 bit)
-concatenated. After the DIRECTION bit, a single '1' bit is appended, followed by
-between 0 and 7 '0' bits, so that the total length of the buffer is multiple of 8 bits.
-Note that the actual message can be any length, specified in bits.
-
-Once this buffer is passed this way, when creating the crypto operation,
-length of data to authenticate (op.sym.auth.data.length) must be the length
-of all the items described above, including the padding at the end.
-Also, offset of data to authenticate (op.sym.auth.data.offset)
-must be such that points at the start of the COUNT bytes.
-
-Device and driver naming
-------------------------
-
-The qat crypto driver name is "crypto_qat".
-This name is passed to the dpdk-test-crypto-perf tool in the -devtype parameter.
-The rte_cryptodev_devices_get() can return the devices exposed by a driver.
-
-Each qat crypto device has a unique name, in format
-<pci bdf>_<service>, e.g. "0000:41:01.0_qat_sym".
-This name can be passed to rte_cryptodev_get_dev_id() to get the device_id.
-This is also the format of the slave parameter passed to the crypto scheduler.
-
Debugging
----------------------------------------
diff --git a/doc/guides/rel_notes/release_18_08.rst b/doc/guides/rel_notes/release_18_08.rst
index bc01242..2230d3e 100644
--- a/doc/guides/rel_notes/release_18_08.rst
+++ b/doc/guides/rel_notes/release_18_08.rst
@@ -46,6 +46,11 @@ New Features
Flow API support has been added to CXGBE Poll Mode Driver to offload
flows to Chelsio T5/T6 NICs.
+* **Added a new compression PMD using Intel's QuickAssist (QAT) device family.**
+
+ Added the new ``QAT`` compression driver, for compression and decompression
+ operations in software. See the :doc:`../compressdevs/qat_comp` compression
+ driver guide for details on this new driver.
API Changes
-----------
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v4 00/16] compress/qat: add compression PMD
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 " Fiona Trahe
@ 2018-07-10 0:41 ` Fiona Trahe
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 " Fiona Trahe
` (16 more replies)
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 01/16] common/qat: updated firmware headers Fiona Trahe
` (15 subsequent siblings)
16 siblings, 17 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-10 0:41 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Create compression PMD for Intel QuickAssist devices
Currently only the C62x and c3xxx devices are supported.
The qat comp PMD supports
- stateless compression and
decompression using the Deflate algorithm with Fixed Huffman
encoding. Dynamic huffman encoding is not supported, it
will be added in a later patch.
- checksum generation: Adler32, CRC32 and combined.
The compression service is hosted on a QuickAssist VF PCI
device, which is managed by code in the
drivers/common/qat directory.
v4 changes:
- corrected capabilities
v3 changes:
- only commit message changes, i.e. removed ChangeId and fixed typos
v2 changes:
- Added check for correct firmware
- Split patchset
- Added documentation
- removed support for scatter-gather-lists and related config flag
- Removed support for Dynamic huffman encoding and related IM buffer config flag
- Removed support for DH895xcc device
Fiona Trahe (16):
common/qat: updated firmware headers
compress/qat: add makefiles for PMD
compress/qat: add meson build
compress/qat: add xform processing
compress/qat: create fw request and process response
compress/qat: check that correct firmware is in use
compress/qat: add stats functions
compress/qat: setup queue-pairs for compression service
compress/qat: add fns to configure and clear device
compress/qat: add fn to return device info
compress/qat: add enqueue/dequeue functions
compress/qat: add device start and stop fns
compress/qat: create and populate the ops structure
compress/qat: add fns to create and destroy the PMD
compress/qat: prevent device usage if incorrect firmware
docs/qat: refactor docs adding compression guide
MAINTAINERS | 4 +
config/common_base | 5 +-
doc/guides/compressdevs/features/qat.ini | 22 ++
doc/guides/compressdevs/index.rst | 1 +
doc/guides/compressdevs/qat_comp.rst | 49 +++
doc/guides/cryptodevs/qat.rst | 183 ++++++----
doc/guides/rel_notes/release_18_08.rst | 5 +
drivers/common/qat/Makefile | 48 ++-
drivers/common/qat/qat_adf/icp_qat_fw.h | 69 +++-
drivers/common/qat/qat_adf/icp_qat_fw_comp.h | 482 +++++++++++++++++++++++++++
drivers/common/qat/qat_adf/icp_qat_hw.h | 130 +++++++-
drivers/common/qat/qat_device.h | 4 +
drivers/common/qat/qat_qp.c | 11 +-
drivers/common/qat/qat_qp.h | 5 +
drivers/compress/meson.build | 2 +-
drivers/compress/qat/meson.build | 18 +
drivers/compress/qat/qat_comp.c | 359 ++++++++++++++++++++
drivers/compress/qat/qat_comp.h | 56 ++++
drivers/compress/qat/qat_comp_pmd.c | 407 ++++++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 39 +++
drivers/compress/qat/rte_pmd_qat_version.map | 3 +
drivers/crypto/qat/meson.build | 10 +-
drivers/crypto/qat/rte_pmd_qat_version.map | 3 -
test/test/test_cryptodev.c | 6 +-
24 files changed, 1806 insertions(+), 115 deletions(-)
create mode 100644 doc/guides/compressdevs/features/qat.ini
create mode 100644 doc/guides/compressdevs/qat_comp.rst
create mode 100644 drivers/common/qat/qat_adf/icp_qat_fw_comp.h
create mode 100644 drivers/compress/qat/meson.build
create mode 100644 drivers/compress/qat/qat_comp.c
create mode 100644 drivers/compress/qat/qat_comp.h
create mode 100644 drivers/compress/qat/qat_comp_pmd.c
create mode 100644 drivers/compress/qat/qat_comp_pmd.h
create mode 100644 drivers/compress/qat/rte_pmd_qat_version.map
delete mode 100644 drivers/crypto/qat/rte_pmd_qat_version.map
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v4 01/16] common/qat: updated firmware headers
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 " Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 " Fiona Trahe
@ 2018-07-10 0:41 ` Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 02/16] compress/qat: add makefiles for PMD Fiona Trahe
` (14 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-10 0:41 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Updated to latest firmware headers files for QuickAssist devices.
Includes updates for symmetric crypto, PKE and Compression services.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
drivers/common/qat/qat_adf/icp_qat_fw.h | 69 +++-
drivers/common/qat/qat_adf/icp_qat_fw_comp.h | 482 +++++++++++++++++++++++++++
drivers/common/qat/qat_adf/icp_qat_hw.h | 130 +++++++-
3 files changed, 654 insertions(+), 27 deletions(-)
create mode 100644 drivers/common/qat/qat_adf/icp_qat_fw_comp.h
diff --git a/drivers/common/qat/qat_adf/icp_qat_fw.h b/drivers/common/qat/qat_adf/icp_qat_fw.h
index ae39b7f..8f7cb37 100644
--- a/drivers/common/qat/qat_adf/icp_qat_fw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_fw.h
@@ -117,6 +117,10 @@ struct icp_qat_fw_comn_resp {
#define ICP_QAT_FW_COMN_VALID_FLAG_BITPOS 7
#define ICP_QAT_FW_COMN_VALID_FLAG_MASK 0x1
#define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK 0x7F
+#define ICP_QAT_FW_COMN_CNV_FLAG_BITPOS 6
+#define ICP_QAT_FW_COMN_CNV_FLAG_MASK 0x1
+#define ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS 5
+#define ICP_QAT_FW_COMN_CNVNR_FLAG_MASK 0x1
#define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \
icp_qat_fw_comn_req_hdr_t.service_type
@@ -133,6 +137,16 @@ struct icp_qat_fw_comn_resp {
#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_GET(hdr_t) \
ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_t.hdr_flags)
+#define ICP_QAT_FW_COMN_HDR_CNVNR_FLAG_GET(hdr_flags) \
+ QAT_FIELD_GET(hdr_flags, \
+ ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS, \
+ ICP_QAT_FW_COMN_CNVNR_FLAG_MASK)
+
+#define ICP_QAT_FW_COMN_HDR_CNV_FLAG_GET(hdr_flags) \
+ QAT_FIELD_GET(hdr_flags, \
+ ICP_QAT_FW_COMN_CNV_FLAG_BITPOS, \
+ ICP_QAT_FW_COMN_CNV_FLAG_MASK)
+
#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_SET(hdr_t, val) \
ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val)
@@ -204,29 +218,44 @@ struct icp_qat_fw_comn_resp {
& ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)); }
+#define ICP_QAT_FW_COMN_NEXT_ID_SET_2(next_curr_id, val) \
+ do { \
+ (next_curr_id) = \
+ (((next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK) | \
+ (((val) << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) & \
+ ICP_QAT_FW_COMN_NEXT_ID_MASK)) \
+ } while (0)
+
+#define ICP_QAT_FW_COMN_CURR_ID_SET_2(next_curr_id, val) \
+ do { \
+ (next_curr_id) = \
+ (((next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
+ ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) \
+ } while (0)
+
#define QAT_COMN_RESP_CRYPTO_STATUS_BITPOS 7
#define QAT_COMN_RESP_CRYPTO_STATUS_MASK 0x1
+#define QAT_COMN_RESP_PKE_STATUS_BITPOS 6
+#define QAT_COMN_RESP_PKE_STATUS_MASK 0x1
#define QAT_COMN_RESP_CMP_STATUS_BITPOS 5
#define QAT_COMN_RESP_CMP_STATUS_MASK 0x1
#define QAT_COMN_RESP_XLAT_STATUS_BITPOS 4
#define QAT_COMN_RESP_XLAT_STATUS_MASK 0x1
#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS 3
#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1
-
-#define ICP_QAT_FW_COMN_RESP_STATUS_BUILD(crypto, comp, xlat, eolb) \
- ((((crypto) & QAT_COMN_RESP_CRYPTO_STATUS_MASK) << \
- QAT_COMN_RESP_CRYPTO_STATUS_BITPOS) | \
- (((comp) & QAT_COMN_RESP_CMP_STATUS_MASK) << \
- QAT_COMN_RESP_CMP_STATUS_BITPOS) | \
- (((xlat) & QAT_COMN_RESP_XLAT_STATUS_MASK) << \
- QAT_COMN_RESP_XLAT_STATUS_BITPOS) | \
- (((eolb) & QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK) << \
- QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS))
+#define QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS 2
+#define QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK 0x1
+#define QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS 0
+#define QAT_COMN_RESP_XLT_WA_APPLIED_MASK 0x1
#define ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(status) \
QAT_FIELD_GET(status, QAT_COMN_RESP_CRYPTO_STATUS_BITPOS, \
QAT_COMN_RESP_CRYPTO_STATUS_MASK)
+#define ICP_QAT_FW_COMN_RESP_PKE_STAT_GET(status) \
+ QAT_FIELD_GET(status, QAT_COMN_RESP_PKE_STATUS_BITPOS, \
+ QAT_COMN_RESP_PKE_STATUS_MASK)
+
#define ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(status) \
QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_STATUS_BITPOS, \
QAT_COMN_RESP_CMP_STATUS_MASK)
@@ -235,10 +264,18 @@ struct icp_qat_fw_comn_resp {
QAT_FIELD_GET(status, QAT_COMN_RESP_XLAT_STATUS_BITPOS, \
QAT_COMN_RESP_XLAT_STATUS_MASK)
+#define ICP_QAT_FW_COMN_RESP_XLT_WA_APPLIED_GET(status) \
+ QAT_FIELD_GET(status, QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS, \
+ QAT_COMN_RESP_XLT_WA_APPLIED_MASK)
+
#define ICP_QAT_FW_COMN_RESP_CMP_END_OF_LAST_BLK_FLAG_GET(status) \
QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS, \
QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK)
+#define ICP_QAT_FW_COMN_RESP_UNSUPPORTED_REQUEST_STAT_GET(status) \
+ QAT_FIELD_GET(status, QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS, \
+ QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK)
+
#define ICP_QAT_FW_COMN_STATUS_FLAG_OK 0
#define ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 1
#define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0
@@ -257,8 +294,16 @@ struct icp_qat_fw_comn_resp {
#define ERR_CODE_OVERFLOW_ERROR -11
#define ERR_CODE_SOFT_ERROR -12
#define ERR_CODE_FATAL_ERROR -13
-#define ERR_CODE_SSM_ERROR -14
-#define ERR_CODE_ENDPOINT_ERROR -15
+#define ERR_CODE_COMP_OUTPUT_CORRUPTION -14
+#define ERR_CODE_HW_INCOMPLETE_FILE -15
+#define ERR_CODE_SSM_ERROR -16
+#define ERR_CODE_ENDPOINT_ERROR -17
+#define ERR_CODE_CNV_ERROR -18
+#define ERR_CODE_EMPTY_DYM_BLOCK -19
+#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_HANDLE -20
+#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_HMAC_FAILED -21
+#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_WRAPPING_ALGO -22
+#define ERR_CODE_KPT_DRNG_SEED_NOT_LOAD -23
enum icp_qat_fw_slice {
ICP_QAT_FW_SLICE_NULL = 0,
diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_comp.h b/drivers/common/qat/qat_adf/icp_qat_fw_comp.h
new file mode 100644
index 0000000..8138177
--- /dev/null
+++ b/drivers/common/qat/qat_adf/icp_qat_fw_comp.h
@@ -0,0 +1,482 @@
+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+#ifndef _ICP_QAT_FW_COMP_H_
+#define _ICP_QAT_FW_COMP_H_
+
+#include "icp_qat_fw.h"
+
+enum icp_qat_fw_comp_cmd_id {
+ ICP_QAT_FW_COMP_CMD_STATIC = 0,
+ /*!< Static Compress Request */
+
+ ICP_QAT_FW_COMP_CMD_DYNAMIC = 1,
+ /*!< Dynamic Compress Request */
+
+ ICP_QAT_FW_COMP_CMD_DECOMPRESS = 2,
+ /*!< Decompress Request */
+
+ ICP_QAT_FW_COMP_CMD_DELIMITER
+ /**< Delimiter type */
+};
+
+/**< Flag usage */
+
+#define ICP_QAT_FW_COMP_STATELESS_SESSION 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that session is stateless
+ */
+
+#define ICP_QAT_FW_COMP_STATEFUL_SESSION 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that session is stateful
+ */
+
+#define ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that autoselectbest is NOT used
+ */
+
+#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that autoselectbest is used
+ */
+
+#define ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is NOT used
+ */
+
+#define ICP_QAT_FW_COMP_ENH_AUTO_SELECT_BEST 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is used
+ */
+
+#define ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is NOT used
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is used
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_USED_AS_INTMD_BUF 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing secure RAM from being used as
+ * an intermediate buffer is DISABLED.
+ */
+
+#define ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing secure RAM from being used as
+ * an intermediate buffer is ENABLED.
+ */
+
+/**< Flag mask & bit position */
+
+#define ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS 2
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the session type
+ */
+
+#define ICP_QAT_FW_COMP_SESSION_TYPE_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask used to determine the session type
+ */
+
+#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS 3
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for auto select best
+ */
+
+#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for auto select best
+ */
+
+#define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS 4
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for enhanced auto select best
+ */
+
+#define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for enhanced auto select best
+ */
+
+#define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS 5
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for disabling type zero header write back
+ * when Enhanced autoselect best is enabled. If set firmware does
+ * not return type0 store block header, only copies src to dest.
+ * (if best output is Type0)
+ */
+
+#define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for auto select best
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS 7
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for flag used to disable secure ram from
+ * being used as an intermediate buffer.
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for disable secure ram for use as an intermediate
+ * buffer.
+ */
+
+#define ICP_QAT_FW_COMP_FLAGS_BUILD(sesstype, autoselect, enhanced_asb, \
+ ret_uncomp, secure_ram) \
+ ((((sesstype)&ICP_QAT_FW_COMP_SESSION_TYPE_MASK) \
+ << ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS) | \
+ (((autoselect)&ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK) \
+ << ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS) | \
+ (((enhanced_asb)&ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK) \
+ << ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS) | \
+ (((ret_uncomp)&ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK) \
+ << ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS) | \
+ (((secure_ram)&ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK) \
+ << ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS))
+
+union icp_qat_fw_comp_req_hdr_cd_pars {
+ /**< LWs 2-5 */
+ struct {
+ uint64_t content_desc_addr;
+ /**< Address of the content descriptor */
+
+ uint16_t content_desc_resrvd1;
+ /**< Content descriptor reserved field */
+
+ uint8_t content_desc_params_sz;
+ /**< Size of the content descriptor parameters in quad words.
+ * These parameters describe the session setup configuration
+ * info for the slices that this request relies upon i.e.
+ * the configuration word and cipher key needed by the cipher
+ * slice if there is a request for cipher processing.
+ */
+
+ uint8_t content_desc_hdr_resrvd2;
+ /**< Content descriptor reserved field */
+
+ uint32_t content_desc_resrvd3;
+ /**< Content descriptor reserved field */
+ } s;
+
+ struct {
+ uint32_t comp_slice_cfg_word[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /* Compression Slice Config Word */
+
+ uint32_t content_desc_resrvd4;
+ /**< Content descriptor reserved field */
+
+ } sl;
+
+};
+
+struct icp_qat_fw_comp_req_params {
+ /**< LW 14 */
+ uint32_t comp_len;
+ /**< Size of input to process in bytes Note: Only EOP requests can be
+ * odd for decompression. IA must set LSB to zero for odd sized
+ * intermediate inputs
+ */
+
+ /**< LW 15 */
+ uint32_t out_buffer_sz;
+ /**< Size of output buffer in bytes */
+
+ /**< LW 16 */
+ uint32_t initial_crc32;
+ /**< CRC of previously processed bytes */
+
+ /**< LW 17 */
+ uint32_t initial_adler;
+ /**< Adler of previously processed bytes */
+
+ /**< LW 18 */
+ uint32_t req_par_flags;
+
+ /**< LW 19 */
+ uint32_t rsrvd;
+};
+
+#define ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(sop, eop, bfinal, cnv, cnvnr) \
+ ((((sop)&ICP_QAT_FW_COMP_SOP_MASK) << ICP_QAT_FW_COMP_SOP_BITPOS) | \
+ (((eop)&ICP_QAT_FW_COMP_EOP_MASK) << ICP_QAT_FW_COMP_EOP_BITPOS) | \
+ (((bfinal)&ICP_QAT_FW_COMP_BFINAL_MASK) \
+ << ICP_QAT_FW_COMP_BFINAL_BITPOS) | \
+ ((cnv & ICP_QAT_FW_COMP_CNV_MASK) << ICP_QAT_FW_COMP_CNV_BITPOS) | \
+ ((cnvnr & ICP_QAT_FW_COMP_CNV_RECOVERY_MASK) \
+ << ICP_QAT_FW_COMP_CNV_RECOVERY_BITPOS))
+
+#define ICP_QAT_FW_COMP_NOT_SOP 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request is NOT Start of Packet
+ */
+
+#define ICP_QAT_FW_COMP_SOP 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request IS Start of Packet
+ */
+
+#define ICP_QAT_FW_COMP_NOT_EOP 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request is NOT Start of Packet
+ */
+
+#define ICP_QAT_FW_COMP_EOP 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request IS End of Packet
+ */
+
+#define ICP_QAT_FW_COMP_NOT_BFINAL 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing to indicate firmware this is not the last block
+ */
+
+#define ICP_QAT_FW_COMP_BFINAL 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing to indicate firmware this is the last block
+ */
+
+#define ICP_QAT_FW_COMP_NO_CNV 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that NO cnv check is to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_CNV 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that a cnv check IS to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_NO_CNV_RECOVERY 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that NO cnv recovery is to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_CNV_RECOVERY 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that a cnv recovery is to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_SOP_BITPOS 0
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for SOP
+ */
+
+#define ICP_QAT_FW_COMP_SOP_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask used to determine SOP
+ */
+
+#define ICP_QAT_FW_COMP_EOP_BITPOS 1
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for EOP
+ */
+
+#define ICP_QAT_FW_COMP_EOP_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask used to determine EOP
+ */
+
+#define ICP_QAT_FW_COMP_BFINAL_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for the bfinal bit
+ */
+
+#define ICP_QAT_FW_COMP_BFINAL_BITPOS 6
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the bfinal bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for the CNV bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_BITPOS 16
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the CNV bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_RECOVERY_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for the CNV Recovery bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_RECOVERY_BITPOS 17
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the CNV Recovery bit
+ */
+
+struct icp_qat_fw_xlt_req_params {
+ /**< LWs 20-21 */
+ uint64_t inter_buff_ptr;
+ /**< This field specifies the physical address of an intermediate
+ * buffer SGL array. The array contains a pair of 64-bit
+ * intermediate buffer pointers to SGL buffer descriptors, one pair
+ * per CPM. Please refer to the CPM1.6 Firmware Interface HLD
+ * specification for more details.
+ */
+};
+
+
+struct icp_qat_fw_comp_cd_hdr {
+ /**< LW 24 */
+ uint16_t ram_bank_flags;
+ /**< Flags to show which ram banks to access */
+
+ uint8_t comp_cfg_offset;
+ /**< Quad word offset from the content descriptor parameters address
+ * to the parameters for the compression processing
+ */
+
+ uint8_t next_curr_id;
+ /**< This field combines the next and current id (each four bits) -
+ * the next id is the most significant nibble.
+ * Next Id: Set to the next slice to pass the compressed data through.
+ * Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through
+ * anymore slices after compression
+ * Current Id: Initialised with the compression slice type
+ */
+
+ /**< LW 25 */
+ uint32_t resrvd;
+ /**< LWs 26-27 */
+
+ uint64_t comp_state_addr;
+ /**< Pointer to compression state */
+
+ /**< LWs 28-29 */
+ uint64_t ram_banks_addr;
+ /**< Pointer to banks */
+
+};
+
+
+struct icp_qat_fw_xlt_cd_hdr {
+ /**< LW 30 */
+ uint16_t resrvd1;
+ /**< Reserved field and assumed set to 0 */
+
+ uint8_t resrvd2;
+ /**< Reserved field and assumed set to 0 */
+
+ uint8_t next_curr_id;
+ /**< This field combines the next and current id (each four bits) -
+ * the next id is the most significant nibble.
+ * Next Id: Set to the next slice to pass the translated data through.
+ * Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through
+ * any more slices after compression
+ * Current Id: Initialised with the translation slice type
+ */
+
+ /**< LW 31 */
+ uint32_t resrvd3;
+ /**< Reserved and should be set to zero, needed for quadword
+ * alignment
+ */
+};
+
+struct icp_qat_fw_comp_req {
+ /**< LWs 0-1 */
+ struct icp_qat_fw_comn_req_hdr comn_hdr;
+ /**< Common request header - for Service Command Id,
+ * use service-specific Compression Command Id.
+ * Service Specific Flags - use Compression Command Flags
+ */
+
+ /**< LWs 2-5 */
+ union icp_qat_fw_comp_req_hdr_cd_pars cd_pars;
+ /**< Compression service-specific content descriptor field which points
+ * either to a content descriptor parameter block or contains the
+ * compression slice config word.
+ */
+
+ /**< LWs 6-13 */
+ struct icp_qat_fw_comn_req_mid comn_mid;
+ /**< Common request middle section */
+
+ /**< LWs 14-19 */
+ struct icp_qat_fw_comp_req_params comp_pars;
+ /**< Compression request Parameters block */
+
+ /**< LWs 20-21 */
+ union {
+ struct icp_qat_fw_xlt_req_params xlt_pars;
+ /**< Translation request Parameters block */
+ uint32_t resrvd1[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /**< Reserved if not used for translation */
+
+ } u1;
+
+ /**< LWs 22-23 */
+ union {
+ uint32_t resrvd2[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /**< Reserved - not used if Batch and Pack is disabled.*/
+
+ uint64_t bnp_res_table_addr;
+ /**< A generic pointer to the unbounded list of
+ * icp_qat_fw_resp_comp_pars members. This pointer is only
+ * used when the Batch and Pack is enabled.
+ */
+ } u3;
+
+ /**< LWs 24-29 */
+ struct icp_qat_fw_comp_cd_hdr comp_cd_ctrl;
+ /**< Compression request content descriptor control block header */
+
+ /**< LWs 30-31 */
+ union {
+ struct icp_qat_fw_xlt_cd_hdr xlt_cd_ctrl;
+ /**< Translation request content descriptor
+ * control block header
+ */
+
+ uint32_t resrvd3[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /**< Reserved if not used for translation */
+ } u2;
+};
+
+struct icp_qat_fw_resp_comp_pars {
+ /**< LW 4 */
+ uint32_t input_byte_counter;
+ /**< Input byte counter */
+
+ /**< LW 5 */
+ uint32_t output_byte_counter;
+ /**< Output byte counter */
+
+ /**< LW 6 & 7*/
+ union {
+ uint64_t curr_chksum;
+ struct {
+ /**< LW 6 */
+ uint32_t curr_crc32;
+ /**< LW 7 */
+ uint32_t curr_adler_32;
+ };
+ };
+};
+
+struct icp_qat_fw_comp_resp {
+ /**< LWs 0-1 */
+ struct icp_qat_fw_comn_resp_hdr comn_resp;
+ /**< Common interface response format see icp_qat_fw.h */
+
+ /**< LWs 2-3 */
+ uint64_t opaque_data;
+ /**< Opaque data passed from the request to the response message */
+
+ /**< LWs 4-7 */
+ struct icp_qat_fw_resp_comp_pars comp_resp_pars;
+ /**< Common response params (checksums and byte counts) */
+};
+
+#endif
diff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h b/drivers/common/qat/qat_adf/icp_qat_hw.h
index 56e3cf7..e7961db 100644
--- a/drivers/common/qat/qat_adf/icp_qat_hw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_hw.h
@@ -72,19 +72,44 @@ struct icp_qat_hw_auth_config {
#define QAT_AUTH_ALGO_MASK 0xF
#define QAT_AUTH_CMP_BITPOS 8
#define QAT_AUTH_CMP_MASK 0x7F
-#define QAT_AUTH_SHA3_PADDING_BITPOS 16
-#define QAT_AUTH_SHA3_PADDING_MASK 0x1
+#define QAT_AUTH_SHA3_PADDING_DISABLE_BITPOS 16
+#define QAT_AUTH_SHA3_PADDING_DISABLE_MASK 0x1
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_BITPOS 17
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_MASK 0x1
#define QAT_AUTH_ALGO_SHA3_BITPOS 22
#define QAT_AUTH_ALGO_SHA3_MASK 0x3
-#define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \
- (((mode & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \
- ((algo & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \
- (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) << \
- QAT_AUTH_ALGO_SHA3_BITPOS) | \
- (((((algo == ICP_QAT_HW_AUTH_ALGO_SHA3_256) || \
- (algo == ICP_QAT_HW_AUTH_ALGO_SHA3_512)) ? 1 : 0) \
- & QAT_AUTH_SHA3_PADDING_MASK) << QAT_AUTH_SHA3_PADDING_BITPOS) | \
- ((cmp_len & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
+#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_BITPOS 16
+#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_MASK 0xF
+#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_BITPOS 24
+#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_MASK 0xFF
+#define QAT_AUTH_SHA3_HW_PADDING_ENABLE 0
+#define QAT_AUTH_SHA3_HW_PADDING_DISABLE 1
+#define QAT_AUTH_SHA3_PADDING_DISABLE_USE_DEFAULT 0
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_USE_DEFAULT 0
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_PROGRAMMABLE 1
+#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_RESERVED 0
+#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_RESERVED 0
+
+#define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \
+ ((((mode) & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \
+ (((algo) & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \
+ (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) \
+ << QAT_AUTH_ALGO_SHA3_BITPOS) | \
+ (((QAT_AUTH_SHA3_PADDING_DISABLE_USE_DEFAULT) & \
+ QAT_AUTH_SHA3_PADDING_DISABLE_MASK) \
+ << QAT_AUTH_SHA3_PADDING_DISABLE_BITPOS) | \
+ (((QAT_AUTH_SHA3_PADDING_OVERRIDE_USE_DEFAULT) & \
+ QAT_AUTH_SHA3_PADDING_OVERRIDE_MASK) \
+ << QAT_AUTH_SHA3_PADDING_OVERRIDE_BITPOS) | \
+ (((cmp_len) & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
+
+#define ICP_QAT_HW_AUTH_CONFIG_BUILD_UPPER \
+ ((((QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_RESERVED) & \
+ QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_MASK) \
+ << QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_BITPOS) | \
+ (((QAT_AUTH_SHA3_PROG_PADDING_PREFIX_RESERVED) & \
+ QAT_AUTH_SHA3_PROG_PADDING_PREFIX_MASK) \
+ << QAT_AUTH_SHA3_PROG_PADDING_PREFIX_BITPOS))
struct icp_qat_hw_auth_counter {
uint32_t counter;
@@ -107,13 +132,13 @@ struct icp_qat_hw_auth_setup {
#define ICP_QAT_HW_MD5_STATE1_SZ 16
#define ICP_QAT_HW_SHA1_STATE1_SZ 20
#define ICP_QAT_HW_SHA224_STATE1_SZ 32
+#define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
#define ICP_QAT_HW_SHA256_STATE1_SZ 32
#define ICP_QAT_HW_SHA3_256_STATE1_SZ 32
#define ICP_QAT_HW_SHA384_STATE1_SZ 64
+#define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
#define ICP_QAT_HW_SHA512_STATE1_SZ 64
#define ICP_QAT_HW_SHA3_512_STATE1_SZ 64
-#define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
-#define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
#define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ 16
#define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ 16
#define ICP_QAT_HW_AES_F9_STATE1_SZ 32
@@ -121,17 +146,18 @@ struct icp_qat_hw_auth_setup {
#define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16
#define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8
#define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8
+
#define ICP_QAT_HW_NULL_STATE2_SZ 32
#define ICP_QAT_HW_MD5_STATE2_SZ 16
#define ICP_QAT_HW_SHA1_STATE2_SZ 20
#define ICP_QAT_HW_SHA224_STATE2_SZ 32
+#define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
#define ICP_QAT_HW_SHA256_STATE2_SZ 32
#define ICP_QAT_HW_SHA3_256_STATE2_SZ 0
#define ICP_QAT_HW_SHA384_STATE2_SZ 64
+#define ICP_QAT_HW_SHA3_384_STATE2_SZ 0
#define ICP_QAT_HW_SHA512_STATE2_SZ 64
#define ICP_QAT_HW_SHA3_512_STATE2_SZ 0
-#define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
-#define ICP_QAT_HW_SHA3_384_STATE2_SZ 0
#define ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ 48
#define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16
#define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16
@@ -154,6 +180,12 @@ struct icp_qat_hw_auth_sha512 {
uint8_t state2[ICP_QAT_HW_SHA512_STATE2_SZ];
};
+struct icp_qat_hw_auth_sha3_512 {
+ struct icp_qat_hw_auth_setup inner_setup;
+ uint8_t state1[ICP_QAT_HW_SHA3_512_STATE1_SZ];
+ struct icp_qat_hw_auth_setup outer_setup;
+};
+
struct icp_qat_hw_auth_algo_blk {
struct icp_qat_hw_auth_sha512 sha;
};
@@ -283,4 +315,72 @@ struct icp_qat_hw_cipher_algo_blk {
uint8_t key[ICP_QAT_HW_CIPHER_MAX_KEY_SZ];
} __rte_cache_aligned;
+/* ========================================================================= */
+/* COMPRESSION SLICE */
+/* ========================================================================= */
+
+enum icp_qat_hw_compression_direction {
+ ICP_QAT_HW_COMPRESSION_DIR_COMPRESS = 0,
+ ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS = 1,
+ ICP_QAT_HW_COMPRESSION_DIR_DELIMITER = 2
+};
+
+enum icp_qat_hw_compression_delayed_match {
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED = 0,
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_ENABLED = 1,
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DELIMITER = 2
+};
+
+enum icp_qat_hw_compression_algo {
+ ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE = 0,
+ ICP_QAT_HW_COMPRESSION_ALGO_LZS = 1,
+ ICP_QAT_HW_COMPRESSION_ALGO_DELIMITER = 2
+};
+
+
+enum icp_qat_hw_compression_depth {
+ ICP_QAT_HW_COMPRESSION_DEPTH_1 = 0,
+ ICP_QAT_HW_COMPRESSION_DEPTH_4 = 1,
+ ICP_QAT_HW_COMPRESSION_DEPTH_8 = 2,
+ ICP_QAT_HW_COMPRESSION_DEPTH_16 = 3,
+ ICP_QAT_HW_COMPRESSION_DEPTH_DELIMITER = 4
+};
+
+enum icp_qat_hw_compression_file_type {
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_0 = 0,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_1 = 1,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_2 = 2,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_3 = 3,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_4 = 4,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_DELIMITER = 5
+};
+
+struct icp_qat_hw_compression_config {
+ uint32_t val;
+ uint32_t reserved;
+};
+
+#define QAT_COMPRESSION_DIR_BITPOS 4
+#define QAT_COMPRESSION_DIR_MASK 0x7
+#define QAT_COMPRESSION_DELAYED_MATCH_BITPOS 16
+#define QAT_COMPRESSION_DELAYED_MATCH_MASK 0x1
+#define QAT_COMPRESSION_ALGO_BITPOS 31
+#define QAT_COMPRESSION_ALGO_MASK 0x1
+#define QAT_COMPRESSION_DEPTH_BITPOS 28
+#define QAT_COMPRESSION_DEPTH_MASK 0x7
+#define QAT_COMPRESSION_FILE_TYPE_BITPOS 24
+#define QAT_COMPRESSION_FILE_TYPE_MASK 0xF
+
+#define ICP_QAT_HW_COMPRESSION_CONFIG_BUILD( \
+ dir, delayed, algo, depth, filetype) \
+ ((((dir) & QAT_COMPRESSION_DIR_MASK) << QAT_COMPRESSION_DIR_BITPOS) | \
+ (((delayed) & QAT_COMPRESSION_DELAYED_MATCH_MASK) \
+ << QAT_COMPRESSION_DELAYED_MATCH_BITPOS) | \
+ (((algo) & QAT_COMPRESSION_ALGO_MASK) \
+ << QAT_COMPRESSION_ALGO_BITPOS) | \
+ (((depth) & QAT_COMPRESSION_DEPTH_MASK) \
+ << QAT_COMPRESSION_DEPTH_BITPOS) | \
+ (((filetype) & QAT_COMPRESSION_FILE_TYPE_MASK) \
+ << QAT_COMPRESSION_FILE_TYPE_BITPOS))
+
#endif
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v4 02/16] compress/qat: add makefiles for PMD
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 " Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 " Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 01/16] common/qat: updated firmware headers Fiona Trahe
@ 2018-07-10 0:41 ` Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 03/16] compress/qat: add meson build Fiona Trahe
` (13 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-10 0:41 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add Makefiles, directory and empty source files for compression PMD.
Handle cases for building either symmetric crypto PMD
or compression PMD or both and the common files both depend on.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
MAINTAINERS | 4 ++++
config/common_base | 3 ++-
drivers/common/qat/Makefile | 48 ++++++++++++++++++++++++++++---------
drivers/compress/qat/qat_comp.c | 5 ++++
drivers/compress/qat/qat_comp.h | 14 +++++++++++
drivers/compress/qat/qat_comp_pmd.c | 5 ++++
drivers/compress/qat/qat_comp_pmd.h | 15 ++++++++++++
test/test/test_cryptodev.c | 6 ++---
8 files changed, 85 insertions(+), 15 deletions(-)
create mode 100644 drivers/compress/qat/qat_comp.c
create mode 100644 drivers/compress/qat/qat_comp.h
create mode 100644 drivers/compress/qat/qat_comp_pmd.c
create mode 100644 drivers/compress/qat/qat_comp_pmd.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 8050b5d..50b2dff 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -852,6 +852,10 @@ F: drivers/compress/isal/
F: doc/guides/compressdevs/isal.rst
F: doc/guides/compressdevs/features/isal.ini
+Intel QuickAssist
+M: Fiona Trahe <fiona.trahe@intel.com>
+F: drivers/compress/qat/
+F: drivers/common/qat/
Eventdev Drivers
----------------
diff --git a/config/common_base b/config/common_base
index 4236e29..93c8857 100644
--- a/config/common_base
+++ b/config/common_base
@@ -484,7 +484,8 @@ CONFIG_RTE_DPAA_SEC_PMD_MAX_NB_SESSIONS=2048
#
# Compile PMD for QuickAssist based devices
#
-CONFIG_RTE_LIBRTE_PMD_QAT=n
+CONFIG_RTE_LIBRTE_PMD_QAT=y
+CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
#
# Max. number of QuickAssist devices, which can be detected and attached
#
diff --git a/drivers/common/qat/Makefile b/drivers/common/qat/Makefile
index 68c7c95..b1a76c1 100644
--- a/drivers/common/qat/Makefile
+++ b/drivers/common/qat/Makefile
@@ -15,35 +15,61 @@ CFLAGS += -O3
# build directories
QAT_CRYPTO_DIR := $(RTE_SDK)/drivers/crypto/qat
+QAT_COMPRESS_DIR := $(RTE_SDK)/drivers/compress/qat
# external library include paths
CFLAGS += -I$(SRCDIR)/qat_adf
CFLAGS += -I$(SRCDIR)
CFLAGS += -I$(QAT_CRYPTO_DIR)
+CFLAGS += -I$(QAT_COMPRESS_DIR)
-# library common source files
-SRCS-y += qat_device.c
-SRCS-y += qat_common.c
-SRCS-y += qat_logs.c
-SRCS-y += qat_qp.c
+
+ifeq ($(CONFIG_RTE_LIBRTE_COMPRESSDEV),y)
+ CFLAGS += -DALLOW_EXPERIMENTAL_API
+ LDLIBS += -lrte_compressdev
+ SRCS-y += $(QAT_COMPRESS_DIR)/qat_comp.c
+ SRCS-y += $(QAT_COMPRESS_DIR)/qat_comp_pmd.c
+ build_qat = yes
+endif
# library symmetric crypto source files
ifeq ($(CONFIG_RTE_LIBRTE_CRYPTODEV),y)
+ifeq ($(CONFIG_RTE_LIBRTE_PMD_QAT_SYM),y)
LDLIBS += -lrte_cryptodev
LDLIBS += -lcrypto
CFLAGS += -DBUILD_QAT_SYM
SRCS-y += $(QAT_CRYPTO_DIR)/qat_sym.c
SRCS-y += $(QAT_CRYPTO_DIR)/qat_sym_session.c
SRCS-y += $(QAT_CRYPTO_DIR)/qat_sym_pmd.c
+ build_qat = yes
endif
+endif
+
+ifdef build_qat
-LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool
-LDLIBS += -lrte_pci -lrte_bus_pci
+ # library name
+ LIB = librte_pmd_qat.a
-# export include files
-SYMLINK-y-include +=
+ # library version
+ LIBABIVER := 1
+ # build flags
+ CFLAGS += $(WERROR_FLAGS)
+ CFLAGS += -O3
-# versioning export map
-EXPORT_MAP := ../../crypto/qat/rte_pmd_qat_version.map
+ # library common source files
+ SRCS-y += qat_device.c
+ SRCS-y += qat_common.c
+ SRCS-y += qat_logs.c
+ SRCS-y += qat_qp.c
+
+ LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool
+ LDLIBS += -lrte_pci -lrte_bus_pci
+
+ # export include files
+ SYMLINK-y-include +=
+
+ # versioning export map
+ EXPORT_MAP := ../../crypto/qat/rte_pmd_qat_version.map
+endif
include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
new file mode 100644
index 0000000..caa1158
--- /dev/null
+++ b/drivers/compress/qat/qat_comp.c
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Intel Corporation
+ */
+
+#include "qat_comp.h"
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
new file mode 100644
index 0000000..89c475e
--- /dev/null
+++ b/drivers/compress/qat/qat_comp.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+
+#ifndef _QAT_COMP_H_
+#define _QAT_COMP_H_
+
+#ifdef RTE_LIBRTE_COMPRESSDEV
+
+#include <rte_compressdev.h>
+#include <rte_compressdev_pmd.h>
+
+#endif
+#endif
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
new file mode 100644
index 0000000..fb035d1
--- /dev/null
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+
+#include "qat_comp_pmd.h"
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
new file mode 100644
index 0000000..9b5b543
--- /dev/null
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+
+#ifndef _QAT_COMP_PMD_H_
+#define _QAT_COMP_PMD_H_
+
+#ifdef RTE_LIBRTE_COMPRESSDEV
+
+#include <rte_compressdev.h>
+#include <rte_compressdev_pmd.h>
+
+
+#endif
+#endif /* _QAT_COMP_PMD_H_ */
diff --git a/test/test/test_cryptodev.c b/test/test/test_cryptodev.c
index e252fee..bb20d07 100644
--- a/test/test/test_cryptodev.c
+++ b/test/test/test_cryptodev.c
@@ -9908,9 +9908,9 @@ test_cryptodev_qat(void /*argv __rte_unused, int argc __rte_unused*/)
RTE_STR(CRYPTODEV_NAME_QAT_SYM_PMD));
if (gbl_driver_id == -1) {
- RTE_LOG(ERR, USER1, "QAT PMD must be loaded. Check if "
- "CONFIG_RTE_LIBRTE_PMD_QAT is enabled "
- "in config file to run this testsuite.\n");
+ RTE_LOG(ERR, USER1, "QAT PMD must be loaded. Check that both "
+ "CONFIG_RTE_LIBRTE_PMD_QAT and CONFIG_RTE_LIBRTE_PMD_QAT_SYM "
+ "are enabled in config file to run this testsuite.\n");
return TEST_SKIPPED;
}
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v4 03/16] compress/qat: add meson build
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 " Fiona Trahe
` (2 preceding siblings ...)
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 02/16] compress/qat: add makefiles for PMD Fiona Trahe
@ 2018-07-10 0:41 ` Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 04/16] compress/qat: add xform processing Fiona Trahe
` (12 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-10 0:41 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add meson build files.
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
drivers/common/qat/Makefile | 2 +-
drivers/compress/meson.build | 2 +-
drivers/compress/qat/meson.build | 18 ++++++++++++++++++
drivers/compress/qat/rte_pmd_qat_version.map | 3 +++
drivers/crypto/qat/meson.build | 10 ++--------
drivers/crypto/qat/rte_pmd_qat_version.map | 3 ---
6 files changed, 25 insertions(+), 13 deletions(-)
create mode 100644 drivers/compress/qat/meson.build
create mode 100644 drivers/compress/qat/rte_pmd_qat_version.map
delete mode 100644 drivers/crypto/qat/rte_pmd_qat_version.map
diff --git a/drivers/common/qat/Makefile b/drivers/common/qat/Makefile
index b1a76c1..bc53652 100644
--- a/drivers/common/qat/Makefile
+++ b/drivers/common/qat/Makefile
@@ -69,7 +69,7 @@ ifdef build_qat
SYMLINK-y-include +=
# versioning export map
- EXPORT_MAP := ../../crypto/qat/rte_pmd_qat_version.map
+ EXPORT_MAP := ../../compress/qat/rte_pmd_qat_version.map
endif
include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/compress/meson.build b/drivers/compress/meson.build
index fb136e1..2352ad5 100644
--- a/drivers/compress/meson.build
+++ b/drivers/compress/meson.build
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2018 Intel Corporation
-drivers = ['isal']
+drivers = ['isal', 'qat']
std_deps = ['compressdev'] # compressdev pulls in all other needed deps
config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'
diff --git a/drivers/compress/qat/meson.build b/drivers/compress/qat/meson.build
new file mode 100644
index 0000000..9d15076
--- /dev/null
+++ b/drivers/compress/qat/meson.build
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2017-2018 Intel Corporation
+
+
+# Add our sources files to the list
+allow_experimental_apis = true
+qat_sources += files('qat_comp_pmd.c',
+ 'qat_comp.c')
+qat_includes += include_directories('.')
+qat_deps += 'compressdev'
+qat_ext_deps += dep
+
+# build the whole driver
+sources += qat_sources
+cflags += qat_cflags
+deps += qat_deps
+ext_deps += qat_ext_deps
+includes += qat_includes
diff --git a/drivers/compress/qat/rte_pmd_qat_version.map b/drivers/compress/qat/rte_pmd_qat_version.map
new file mode 100644
index 0000000..ad6e191
--- /dev/null
+++ b/drivers/compress/qat/rte_pmd_qat_version.map
@@ -0,0 +1,3 @@
+DPDK_18.08 {
+ local: *;
+};
diff --git a/drivers/crypto/qat/meson.build b/drivers/crypto/qat/meson.build
index 2873637..d7cff68 100644
--- a/drivers/crypto/qat/meson.build
+++ b/drivers/crypto/qat/meson.build
@@ -1,6 +1,8 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017-2018 Intel Corporation
+# this does not build the QAT driver, instead that is done in the compression
+# driver which comes later. Here we just add our sources files to the list
build = false
dep = dependency('libcrypto', required: false)
if dep.found()
@@ -13,12 +15,4 @@ if dep.found()
qat_ext_deps += dep
pkgconfig_extra_libs += '-lcrypto'
qat_cflags += '-DBUILD_QAT_SYM'
-
- # build the whole driver
- sources += qat_sources
- cflags += qat_cflags
- deps += qat_deps
- ext_deps += qat_ext_deps
- includes += qat_includes
- build = true
endif
diff --git a/drivers/crypto/qat/rte_pmd_qat_version.map b/drivers/crypto/qat/rte_pmd_qat_version.map
deleted file mode 100644
index bbaf1c8..0000000
--- a/drivers/crypto/qat/rte_pmd_qat_version.map
+++ /dev/null
@@ -1,3 +0,0 @@
-DPDK_2.2 {
- local: *;
-};
\ No newline at end of file
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v4 04/16] compress/qat: add xform processing
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 " Fiona Trahe
` (3 preceding siblings ...)
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 03/16] compress/qat: add meson build Fiona Trahe
@ 2018-07-10 0:41 ` Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 05/16] compress/qat: create fw request and process response Fiona Trahe
` (11 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-10 0:41 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add code to process compressdev rte_comp_xforms, creating
private qat_comp_xforms with prepared firmware message templates.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp.c | 239 ++++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp.h | 30 +++++
drivers/compress/qat/qat_comp_pmd.h | 16 +++
3 files changed, 285 insertions(+)
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index caa1158..cb2005a 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -2,4 +2,243 @@
* Copyright(c) 2018 Intel Corporation
*/
+
+#include <rte_mempool.h>
+#include <rte_mbuf.h>
+#include <rte_hexdump.h>
+#include <rte_comp.h>
+#include <rte_bus_pci.h>
+#include <rte_byteorder.h>
+#include <rte_memcpy.h>
+#include <rte_common.h>
+#include <rte_spinlock.h>
+#include <rte_log.h>
+#include <rte_malloc.h>
+
+#include "qat_logs.h"
#include "qat_comp.h"
+#include "qat_comp_pmd.h"
+
+unsigned int
+qat_comp_xform_size(void)
+{
+ return RTE_ALIGN_CEIL(sizeof(struct qat_comp_xform), 8);
+}
+
+static void qat_comp_create_req_hdr(struct icp_qat_fw_comn_req_hdr *header,
+ enum qat_comp_request_type request)
+{
+ if (request == QAT_COMP_REQUEST_FIXED_COMP_STATELESS)
+ header->service_cmd_id = ICP_QAT_FW_COMP_CMD_STATIC;
+ else if (request == QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS)
+ header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DYNAMIC;
+ else if (request == QAT_COMP_REQUEST_DECOMPRESS)
+ header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DECOMPRESS;
+
+ header->service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_COMP;
+ header->hdr_flags =
+ ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
+
+ header->comn_req_flags = ICP_QAT_FW_COMN_FLAGS_BUILD(
+ QAT_COMN_CD_FLD_TYPE_16BYTE_DATA, QAT_COMN_PTR_TYPE_FLAT);
+}
+
+static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,
+ const struct rte_memzone *interm_buff_mz __rte_unused,
+ const struct rte_comp_xform *xform)
+{
+ struct icp_qat_fw_comp_req *comp_req;
+ int comp_level, algo;
+ uint32_t req_par_flags;
+ int direction = ICP_QAT_HW_COMPRESSION_DIR_COMPRESS;
+
+ if (unlikely(qat_xform == NULL)) {
+ QAT_LOG(ERR, "Session was not created for this device");
+ return -EINVAL;
+ }
+
+ if (qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS) {
+ direction = ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS;
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_1;
+ req_par_flags = ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(
+ ICP_QAT_FW_COMP_SOP, ICP_QAT_FW_COMP_EOP,
+ ICP_QAT_FW_COMP_BFINAL, ICP_QAT_FW_COMP_NO_CNV,
+ ICP_QAT_FW_COMP_NO_CNV_RECOVERY);
+
+ } else {
+ if (xform->compress.level == RTE_COMP_LEVEL_PMD_DEFAULT)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_8;
+ else if (xform->compress.level == 1)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_1;
+ else if (xform->compress.level == 2)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_4;
+ else if (xform->compress.level == 3)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_8;
+ else if (xform->compress.level >= 4 &&
+ xform->compress.level <= 9)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_16;
+ else {
+ QAT_LOG(ERR, "compression level not supported");
+ return -EINVAL;
+ }
+ req_par_flags = ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(
+ ICP_QAT_FW_COMP_SOP, ICP_QAT_FW_COMP_EOP,
+ ICP_QAT_FW_COMP_BFINAL, ICP_QAT_FW_COMP_CNV,
+ ICP_QAT_FW_COMP_CNV_RECOVERY);
+ }
+
+ switch (xform->compress.algo) {
+ case RTE_COMP_ALGO_DEFLATE:
+ algo = ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE;
+ break;
+ case RTE_COMP_ALGO_LZS:
+ default:
+ /* RTE_COMP_NULL */
+ QAT_LOG(ERR, "compression algorithm not supported");
+ return -EINVAL;
+ }
+
+ comp_req = &qat_xform->qat_comp_req_tmpl;
+
+ /* Initialize header */
+ qat_comp_create_req_hdr(&comp_req->comn_hdr,
+ qat_xform->qat_comp_request_type);
+
+ comp_req->comn_hdr.serv_specif_flags = ICP_QAT_FW_COMP_FLAGS_BUILD(
+ ICP_QAT_FW_COMP_STATELESS_SESSION,
+ ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST,
+ ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST,
+ ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST,
+ ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_USED_AS_INTMD_BUF);
+
+ comp_req->cd_pars.sl.comp_slice_cfg_word[0] =
+ ICP_QAT_HW_COMPRESSION_CONFIG_BUILD(
+ direction,
+ /* In CPM 1.6 only valid mode ! */
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_ENABLED, algo,
+ /* Translate level to depth */
+ comp_level, ICP_QAT_HW_COMPRESSION_FILE_TYPE_0);
+
+ comp_req->comp_pars.initial_adler = 1;
+ comp_req->comp_pars.initial_crc32 = 0;
+ comp_req->comp_pars.req_par_flags = req_par_flags;
+
+
+ if (qat_xform->qat_comp_request_type ==
+ QAT_COMP_REQUEST_FIXED_COMP_STATELESS ||
+ qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS) {
+ ICP_QAT_FW_COMN_NEXT_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_DRAM_WR);
+ ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_COMP);
+ } else if (qat_xform->qat_comp_request_type ==
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {
+
+ QAT_LOG(ERR, "Dynamic huffman encoding not supported");
+ return -EINVAL;
+ }
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_HEXDUMP_LOG(DEBUG, "qat compression message template:", comp_req,
+ sizeof(struct icp_qat_fw_comp_req));
+#endif
+ return 0;
+}
+
+/**
+ * Create driver private_xform data.
+ *
+ * @param dev
+ * Compressdev device
+ * @param xform
+ * xform data from application
+ * @param private_xform
+ * ptr where handle of pmd's private_xform data should be stored
+ * @return
+ * - if successful returns 0
+ * and valid private_xform handle
+ * - <0 in error cases
+ * - Returns -EINVAL if input parameters are invalid.
+ * - Returns -ENOTSUP if comp device does not support the comp transform.
+ * - Returns -ENOMEM if the private_xform could not be allocated.
+ */
+int
+qat_comp_private_xform_create(struct rte_compressdev *dev,
+ const struct rte_comp_xform *xform,
+ void **private_xform)
+{
+ struct qat_comp_dev_private *qat = dev->data->dev_private;
+
+ if (unlikely(private_xform == NULL)) {
+ QAT_LOG(ERR, "QAT: private_xform parameter is NULL");
+ return -EINVAL;
+ }
+ if (unlikely(qat->xformpool == NULL)) {
+ QAT_LOG(ERR, "QAT device has no private_xform mempool");
+ return -ENOMEM;
+ }
+ if (rte_mempool_get(qat->xformpool, private_xform)) {
+ QAT_LOG(ERR, "Couldn't get object from qat xform mempool");
+ return -ENOMEM;
+ }
+
+ struct qat_comp_xform *qat_xform =
+ (struct qat_comp_xform *)*private_xform;
+
+ if (xform->type == RTE_COMP_COMPRESS) {
+ if (xform->compress.deflate.huffman ==
+ RTE_COMP_HUFFMAN_DYNAMIC) {
+ QAT_LOG(ERR,
+ "QAT device doesn't support dynamic compression");
+ return -ENOTSUP;
+ }
+
+ if (xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_FIXED ||
+ ((xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_DEFAULT)
+ && qat->interm_buff_mz == NULL))
+
+ qat_xform->qat_comp_request_type =
+ QAT_COMP_REQUEST_FIXED_COMP_STATELESS;
+
+
+ } else {
+ qat_xform->qat_comp_request_type = QAT_COMP_REQUEST_DECOMPRESS;
+ }
+
+ qat_xform->checksum_type = xform->compress.chksum;
+
+ if (qat_comp_create_templates(qat_xform, qat->interm_buff_mz, xform)) {
+ QAT_LOG(ERR, "QAT: Problem with setting compression");
+ return -EINVAL;
+ }
+ return 0;
+}
+
+/**
+ * Free driver private_xform data.
+ *
+ * @param dev
+ * Compressdev device
+ * @param private_xform
+ * handle of pmd's private_xform data
+ * @return
+ * - 0 if successful
+ * - <0 in error cases
+ * - Returns -EINVAL if input parameters are invalid.
+ */
+int
+qat_comp_private_xform_free(struct rte_compressdev *dev __rte_unused,
+ void *private_xform)
+{
+ struct qat_comp_xform *qat_xform =
+ (struct qat_comp_xform *)private_xform;
+
+ if (qat_xform) {
+ memset(qat_xform, 0, qat_comp_xform_size());
+ struct rte_mempool *mp = rte_mempool_from_obj(qat_xform);
+
+ rte_mempool_put(mp, qat_xform);
+ return 0;
+ }
+ return -EINVAL;
+}
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 89c475e..0f58a76 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -10,5 +10,35 @@
#include <rte_compressdev.h>
#include <rte_compressdev_pmd.h>
+#include "icp_qat_hw.h"
+#include "icp_qat_fw_comp.h"
+#include "icp_qat_fw_la.h"
+
+enum qat_comp_request_type {
+ QAT_COMP_REQUEST_FIXED_COMP_STATELESS,
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS,
+ QAT_COMP_REQUEST_DECOMPRESS,
+ REQ_COMP_END
+};
+
+
+struct qat_comp_xform {
+ struct icp_qat_fw_comp_req qat_comp_req_tmpl;
+ enum qat_comp_request_type qat_comp_request_type;
+ enum rte_comp_checksum_type checksum_type;
+};
+
+
+int
+qat_comp_private_xform_create(struct rte_compressdev *dev,
+ const struct rte_comp_xform *xform,
+ void **private_xform);
+
+int
+qat_comp_private_xform_free(struct rte_compressdev *dev, void *private_xform);
+
+unsigned int
+qat_comp_xform_size(void);
+
#endif
#endif
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 9b5b543..fd97cbf 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -11,5 +11,21 @@
#include <rte_compressdev_pmd.h>
+/** private data structure for a QAT compression device.
+ * This QAT device is a device offering only a compression service,
+ * there can be one of these on each qat_pci_device (VF).
+ */
+struct qat_comp_dev_private {
+ struct qat_pci_device *qat_dev;
+ /**< The qat pci device hosting the service */
+ struct rte_compressdev *compressdev;
+ /**< The pointer to this compression device structure */
+ const struct rte_memzone *interm_buff_mz;
+ /**< The device's memory for intermediate buffers */
+ struct rte_mempool *xformpool;
+ /**< The device's pool for qat_comp_xforms */
+
+};
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v4 05/16] compress/qat: create fw request and process response
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 " Fiona Trahe
` (4 preceding siblings ...)
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 04/16] compress/qat: add xform processing Fiona Trahe
@ 2018-07-10 0:41 ` Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 06/16] compress/qat: check that correct firmware is in use Fiona Trahe
` (10 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-10 0:41 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add functions to create the request message to send to
firmware and to process the firmware response.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp.c | 101 ++++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp.h | 8 +++
drivers/compress/qat/qat_comp_pmd.h | 1 +
3 files changed, 110 insertions(+)
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index cb2005a..a32d6ef 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -19,6 +19,107 @@
#include "qat_comp.h"
#include "qat_comp_pmd.h"
+
+int
+qat_comp_build_request(void *in_op, uint8_t *out_msg,
+ void *op_cookie __rte_unused,
+ enum qat_device_gen qat_dev_gen __rte_unused)
+{
+ struct rte_comp_op *op = in_op;
+ struct qat_comp_xform *qat_xform = op->private_xform;
+ const uint8_t *tmpl = (uint8_t *)&qat_xform->qat_comp_req_tmpl;
+ struct icp_qat_fw_comp_req *comp_req =
+ (struct icp_qat_fw_comp_req *)out_msg;
+
+ if (unlikely(op->op_type != RTE_COMP_OP_STATELESS)) {
+ QAT_DP_LOG(ERR, "QAT PMD only supports stateless compression "
+ "operation requests, op (%p) is not a "
+ "stateless operation.", op);
+ return -EINVAL;
+ }
+
+ rte_mov128(out_msg, tmpl);
+ comp_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
+
+ /* common for sgl and flat buffers */
+ comp_req->comp_pars.comp_len = op->src.length;
+ comp_req->comp_pars.out_buffer_sz = rte_pktmbuf_pkt_len(op->m_dst);
+
+ /* sgl */
+ if (op->m_src->next != NULL || op->m_dst->next != NULL) {
+ QAT_DP_LOG(ERR, "QAT PMD doesn't support scatter gather");
+ return -EINVAL;
+
+ } else {
+ ICP_QAT_FW_COMN_PTR_TYPE_SET(comp_req->comn_hdr.comn_req_flags,
+ QAT_COMN_PTR_TYPE_FLAT);
+ comp_req->comn_mid.src_length = rte_pktmbuf_data_len(op->m_src);
+ comp_req->comn_mid.dst_length = rte_pktmbuf_data_len(op->m_dst);
+
+ comp_req->comn_mid.src_data_addr =
+ rte_pktmbuf_mtophys_offset(op->m_src, op->src.offset);
+ comp_req->comn_mid.dest_data_addr =
+ rte_pktmbuf_mtophys_offset(op->m_dst, op->dst.offset);
+ }
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_LOG(DEBUG, "Direction: %s",
+ qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS ?
+ "decompression" : "compression");
+ QAT_DP_HEXDUMP_LOG(DEBUG, "qat compression message:", comp_req,
+ sizeof(struct icp_qat_fw_comp_req));
+#endif
+ return 0;
+}
+
+int
+qat_comp_process_response(void **op, uint8_t *resp)
+{
+ struct icp_qat_fw_comp_resp *resp_msg =
+ (struct icp_qat_fw_comp_resp *)resp;
+ struct rte_comp_op *rx_op = (struct rte_comp_op *)(uintptr_t)
+ (resp_msg->opaque_data);
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_LOG(DEBUG, "Direction: %s",
+ qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS ?
+ "decompression" : "compression");
+ QAT_DP_HEXDUMP_LOG(DEBUG, "qat_response:", (uint8_t *)resp_msg,
+ sizeof(struct icp_qat_fw_comp_resp));
+#endif
+
+ if ((ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(resp_msg->comn_resp.comn_status)
+ | ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(
+ resp_msg->comn_resp.comn_status)) !=
+ ICP_QAT_FW_COMN_STATUS_FLAG_OK) {
+
+ rx_op->status = RTE_COMP_OP_STATUS_ERROR;
+ rx_op->debug_status =
+ *((uint16_t *)(&resp_msg->comn_resp.comn_error));
+ } else {
+ struct qat_comp_xform *qat_xform = rx_op->private_xform;
+ struct icp_qat_fw_resp_comp_pars *comp_resp =
+ (struct icp_qat_fw_resp_comp_pars *)&resp_msg->comp_resp_pars;
+
+ rx_op->status = RTE_COMP_OP_STATUS_SUCCESS;
+ rx_op->consumed = comp_resp->input_byte_counter;
+ rx_op->produced = comp_resp->output_byte_counter;
+
+ if (qat_xform->checksum_type != RTE_COMP_CHECKSUM_NONE) {
+ if (qat_xform->checksum_type == RTE_COMP_CHECKSUM_CRC32)
+ rx_op->output_chksum = comp_resp->curr_crc32;
+ else if (qat_xform->checksum_type ==
+ RTE_COMP_CHECKSUM_ADLER32)
+ rx_op->output_chksum = comp_resp->curr_adler_32;
+ else
+ rx_op->output_chksum = comp_resp->curr_chksum;
+ }
+ }
+ *op = (void *)rx_op;
+
+ return 0;
+}
+
unsigned int
qat_comp_xform_size(void)
{
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 0f58a76..46105b4 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -10,6 +10,7 @@
#include <rte_compressdev.h>
#include <rte_compressdev_pmd.h>
+#include "qat_common.h"
#include "icp_qat_hw.h"
#include "icp_qat_fw_comp.h"
#include "icp_qat_fw_la.h"
@@ -28,6 +29,13 @@ struct qat_comp_xform {
enum rte_comp_checksum_type checksum_type;
};
+int
+qat_comp_build_request(void *in_op, uint8_t *out_msg, void *op_cookie,
+ enum qat_device_gen qat_dev_gen __rte_unused);
+
+int
+qat_comp_process_response(void **op, uint8_t *resp);
+
int
qat_comp_private_xform_create(struct rte_compressdev *dev,
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index fd97cbf..cd04f11 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -10,6 +10,7 @@
#include <rte_compressdev.h>
#include <rte_compressdev_pmd.h>
+#include "qat_device.h"
/** private data structure for a QAT compression device.
* This QAT device is a device offering only a compression service,
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v4 06/16] compress/qat: check that correct firmware is in use
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 " Fiona Trahe
` (5 preceding siblings ...)
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 05/16] compress/qat: create fw request and process response Fiona Trahe
@ 2018-07-10 0:41 ` Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 07/16] compress/qat: add stats functions Fiona Trahe
` (9 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-10 0:41 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Check bit in response message to verify that correct firmware
is in use for compression. If not return an error.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp.c | 16 +++++++++++++++-
drivers/compress/qat/qat_comp.h | 2 ++
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index a32d6ef..e8019eb 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -2,7 +2,6 @@
* Copyright(c) 2018 Intel Corporation
*/
-
#include <rte_mempool.h>
#include <rte_mbuf.h>
#include <rte_hexdump.h>
@@ -79,6 +78,8 @@ qat_comp_process_response(void **op, uint8_t *resp)
(struct icp_qat_fw_comp_resp *)resp;
struct rte_comp_op *rx_op = (struct rte_comp_op *)(uintptr_t)
(resp_msg->opaque_data);
+ struct qat_comp_xform *qat_xform = (struct qat_comp_xform *)
+ (rx_op->private_xform);
#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
QAT_DP_LOG(DEBUG, "Direction: %s",
@@ -88,6 +89,19 @@ qat_comp_process_response(void **op, uint8_t *resp)
sizeof(struct icp_qat_fw_comp_resp));
#endif
+ if (likely(qat_xform->qat_comp_request_type
+ != QAT_COMP_REQUEST_DECOMPRESS)) {
+ if (unlikely(ICP_QAT_FW_COMN_HDR_CNV_FLAG_GET(
+ resp_msg->comn_resp.hdr_flags)
+ == ICP_QAT_FW_COMP_NO_CNV)) {
+ rx_op->status = RTE_COMP_OP_STATUS_ERROR;
+ rx_op->debug_status = ERR_CODE_QAT_COMP_WRONG_FW;
+ *op = (void *)rx_op;
+ QAT_DP_LOG(ERR, "QAT has wrong firmware");
+ return 0;
+ }
+ }
+
if ((ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(resp_msg->comn_resp.comn_status)
| ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(
resp_msg->comn_resp.comn_status)) !=
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 46105b4..937f3c8 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -15,6 +15,8 @@
#include "icp_qat_fw_comp.h"
#include "icp_qat_fw_la.h"
+#define ERR_CODE_QAT_COMP_WRONG_FW -99
+
enum qat_comp_request_type {
QAT_COMP_REQUEST_FIXED_COMP_STATELESS,
QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS,
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v4 07/16] compress/qat: add stats functions
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 " Fiona Trahe
` (6 preceding siblings ...)
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 06/16] compress/qat: check that correct firmware is in use Fiona Trahe
@ 2018-07-10 0:41 ` Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 08/16] compress/qat: setup queue-pairs for compression service Fiona Trahe
` (8 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-10 0:41 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add functions to get and clear compression queue-pair statistics.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 35 +++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 7 +++++++
2 files changed, 42 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index fb035d1..6feffb7 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -3,3 +3,38 @@
*/
#include "qat_comp_pmd.h"
+
+void
+qat_comp_stats_get(struct rte_compressdev *dev,
+ struct rte_compressdev_stats *stats)
+{
+ struct qat_common_stats qat_stats = {0};
+ struct qat_comp_dev_private *qat_priv;
+
+ if (stats == NULL || dev == NULL) {
+ QAT_LOG(ERR, "invalid ptr: stats %p, dev %p", stats, dev);
+ return;
+ }
+ qat_priv = dev->data->dev_private;
+
+ qat_stats_get(qat_priv->qat_dev, &qat_stats, QAT_SERVICE_COMPRESSION);
+ stats->enqueued_count = qat_stats.enqueued_count;
+ stats->dequeued_count = qat_stats.dequeued_count;
+ stats->enqueue_err_count = qat_stats.enqueue_err_count;
+ stats->dequeue_err_count = qat_stats.dequeue_err_count;
+}
+
+void
+qat_comp_stats_reset(struct rte_compressdev *dev)
+{
+ struct qat_comp_dev_private *qat_priv;
+
+ if (dev == NULL) {
+ QAT_LOG(ERR, "invalid compressdev ptr %p", dev);
+ return;
+ }
+ qat_priv = dev->data->dev_private;
+
+ qat_stats_reset(qat_priv->qat_dev, QAT_SERVICE_COMPRESSION);
+
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index cd04f11..27d84c8 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -28,5 +28,12 @@ struct qat_comp_dev_private {
};
+void
+qat_comp_stats_reset(struct rte_compressdev *dev);
+
+void
+qat_comp_stats_get(struct rte_compressdev *dev,
+ struct rte_compressdev_stats *stats);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v4 08/16] compress/qat: setup queue-pairs for compression service
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 " Fiona Trahe
` (7 preceding siblings ...)
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 07/16] compress/qat: add stats functions Fiona Trahe
@ 2018-07-10 0:41 ` Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 09/16] compress/qat: add fns to configure and clear device Fiona Trahe
` (7 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-10 0:41 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Setup and clear queue-pairs for handling compression
requests and responses.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp.h | 2 ++
drivers/compress/qat/qat_comp_pmd.c | 61 +++++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 6 ++++
3 files changed, 69 insertions(+)
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 937f3c8..9e6861b 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -24,6 +24,8 @@ enum qat_comp_request_type {
REQ_COMP_END
};
+struct qat_comp_op_cookie {
+};
struct qat_comp_xform {
struct icp_qat_fw_comp_req qat_comp_req_tmpl;
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 6feffb7..5ae6caf 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -2,6 +2,7 @@
* Copyright(c) 2015-2018 Intel Corporation
*/
+#include "qat_comp.h"
#include "qat_comp_pmd.h"
void
@@ -38,3 +39,63 @@ qat_comp_stats_reset(struct rte_compressdev *dev)
qat_stats_reset(qat_priv->qat_dev, QAT_SERVICE_COMPRESSION);
}
+
+int
+qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)
+{
+ struct qat_comp_dev_private *qat_private = dev->data->dev_private;
+
+ QAT_LOG(DEBUG, "Release comp qp %u on device %d",
+ queue_pair_id, dev->data->dev_id);
+
+ qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][queue_pair_id]
+ = NULL;
+
+ return qat_qp_release((struct qat_qp **)
+ &(dev->data->queue_pairs[queue_pair_id]));
+}
+
+int
+qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
+ uint32_t max_inflight_ops, int socket_id)
+{
+ int ret = 0;
+ struct qat_qp_config qat_qp_conf;
+
+ struct qat_qp **qp_addr =
+ (struct qat_qp **)&(dev->data->queue_pairs[qp_id]);
+ struct qat_comp_dev_private *qat_private = dev->data->dev_private;
+ const struct qat_qp_hw_data *comp_hw_qps =
+ qat_gen_config[qat_private->qat_dev->qat_dev_gen]
+ .qp_hw_data[QAT_SERVICE_COMPRESSION];
+ const struct qat_qp_hw_data *qp_hw_data = comp_hw_qps + qp_id;
+
+ /* If qp is already in use free ring memory and qp metadata. */
+ if (*qp_addr != NULL) {
+ ret = qat_comp_qp_release(dev, qp_id);
+ if (ret < 0)
+ return ret;
+ }
+ if (qp_id >= qat_qps_per_service(comp_hw_qps,
+ QAT_SERVICE_COMPRESSION)) {
+ QAT_LOG(ERR, "qp_id %u invalid for this device", qp_id);
+ return -EINVAL;
+ }
+
+ qat_qp_conf.hw = qp_hw_data;
+ qat_qp_conf.build_request = qat_comp_build_request;
+ qat_qp_conf.cookie_size = sizeof(struct qat_comp_op_cookie);
+ qat_qp_conf.nb_descriptors = max_inflight_ops;
+ qat_qp_conf.socket_id = socket_id;
+ qat_qp_conf.service_str = "comp";
+
+ ret = qat_qp_setup(qat_private->qat_dev, qp_addr, qp_id, &qat_qp_conf);
+ if (ret != 0)
+ return ret;
+
+ /* store a link to the qp in the qat_pci_device */
+ qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][qp_id]
+ = *qp_addr;
+
+ return ret;
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 27d84c8..5a4bc31 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -34,6 +34,12 @@ qat_comp_stats_reset(struct rte_compressdev *dev);
void
qat_comp_stats_get(struct rte_compressdev *dev,
struct rte_compressdev_stats *stats);
+int
+qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id);
+
+int
+qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
+ uint32_t max_inflight_ops, int socket_id);
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v4 09/16] compress/qat: add fns to configure and clear device
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 " Fiona Trahe
` (8 preceding siblings ...)
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 08/16] compress/qat: setup queue-pairs for compression service Fiona Trahe
@ 2018-07-10 0:41 ` Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 10/16] compress/qat: add fn to return device info Fiona Trahe
` (6 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-10 0:41 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add functions to configure and clear the qat comp device,
including the creation and freeing of the xform pool
and the freeing of queue-pairs.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 95 +++++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 7 +++
2 files changed, 102 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 5ae6caf..beab6e3 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -99,3 +99,98 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
return ret;
}
+
+static struct rte_mempool *
+qat_comp_create_xform_pool(struct qat_comp_dev_private *comp_dev,
+ uint32_t num_elements)
+{
+ char xform_pool_name[RTE_MEMPOOL_NAMESIZE];
+ struct rte_mempool *mp;
+
+ snprintf(xform_pool_name, RTE_MEMPOOL_NAMESIZE,
+ "%s_xforms", comp_dev->qat_dev->name);
+
+ QAT_LOG(DEBUG, "xformpool: %s", xform_pool_name);
+ mp = rte_mempool_lookup(xform_pool_name);
+
+ if (mp != NULL) {
+ QAT_LOG(DEBUG, "xformpool already created");
+ if (mp->size != num_elements) {
+ QAT_LOG(DEBUG, "xformpool wrong size - delete it");
+ rte_mempool_free(mp);
+ mp = NULL;
+ comp_dev->xformpool = NULL;
+ }
+ }
+
+ if (mp == NULL)
+ mp = rte_mempool_create(xform_pool_name,
+ num_elements,
+ qat_comp_xform_size(), 0, 0,
+ NULL, NULL, NULL, NULL, rte_socket_id(),
+ 0);
+ if (mp == NULL) {
+ QAT_LOG(ERR, "Err creating mempool %s w %d elements of size %d",
+ xform_pool_name, num_elements, qat_comp_xform_size());
+ return NULL;
+ }
+
+ return mp;
+}
+
+static void
+_qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)
+{
+ /* Free private_xform pool */
+ if (comp_dev->xformpool) {
+ /* Free internal mempool for private xforms */
+ rte_mempool_free(comp_dev->xformpool);
+ comp_dev->xformpool = NULL;
+ }
+}
+
+int
+qat_comp_dev_config(struct rte_compressdev *dev,
+ struct rte_compressdev_config *config)
+{
+ struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
+ int ret = 0;
+
+ if (config->max_nb_streams != 0) {
+ QAT_LOG(ERR,
+ "QAT device does not support STATEFUL so max_nb_streams must be 0");
+ return -EINVAL;
+ }
+
+ comp_dev->xformpool = qat_comp_create_xform_pool(comp_dev,
+ config->max_nb_priv_xforms);
+ if (comp_dev->xformpool == NULL) {
+
+ ret = -ENOMEM;
+ goto error_out;
+ }
+ return 0;
+
+error_out:
+ _qat_comp_dev_config_clear(comp_dev);
+ return ret;
+}
+
+
+int
+qat_comp_dev_close(struct rte_compressdev *dev)
+{
+ int i;
+ int ret = 0;
+ struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
+
+ for (i = 0; i < dev->data->nb_queue_pairs; i++) {
+ ret = qat_comp_qp_release(dev, i);
+ if (ret < 0)
+ return ret;
+ }
+
+ _qat_comp_dev_config_clear(comp_dev);
+
+ return ret;
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 5a4bc31..b10a66f 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -41,5 +41,12 @@ int
qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
uint32_t max_inflight_ops, int socket_id);
+int
+qat_comp_dev_config(struct rte_compressdev *dev,
+ struct rte_compressdev_config *config);
+
+int
+qat_comp_dev_close(struct rte_compressdev *dev);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v4 10/16] compress/qat: add fn to return device info
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 " Fiona Trahe
` (9 preceding siblings ...)
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 09/16] compress/qat: add fns to configure and clear device Fiona Trahe
@ 2018-07-10 0:41 ` Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 11/16] compress/qat: add enqueue/dequeue functions Fiona Trahe
` (5 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-10 0:41 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add capabilities pointer to internal qat comp device
and function to return this and other info.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 19 +++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 6 ++++++
2 files changed, 25 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index beab6e3..482ebd1 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -194,3 +194,22 @@ qat_comp_dev_close(struct rte_compressdev *dev)
return ret;
}
+
+
+void
+qat_comp_dev_info_get(struct rte_compressdev *dev,
+ struct rte_compressdev_info *info)
+{
+ struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
+ const struct qat_qp_hw_data *comp_hw_qps =
+ qat_gen_config[comp_dev->qat_dev->qat_dev_gen]
+ .qp_hw_data[QAT_SERVICE_COMPRESSION];
+
+ if (info != NULL) {
+ info->max_nb_queue_pairs =
+ qat_qps_per_service(comp_hw_qps,
+ QAT_SERVICE_COMPRESSION);
+ info->feature_flags = dev->feature_flags;
+ info->capabilities = comp_dev->qat_dev_capabilities;
+ }
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index b10a66f..22576f4 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -21,6 +21,8 @@ struct qat_comp_dev_private {
/**< The qat pci device hosting the service */
struct rte_compressdev *compressdev;
/**< The pointer to this compression device structure */
+ const struct rte_compressdev_capabilities *qat_dev_capabilities;
+ /* QAT device compression capabilities */
const struct rte_memzone *interm_buff_mz;
/**< The device's memory for intermediate buffers */
struct rte_mempool *xformpool;
@@ -48,5 +50,9 @@ qat_comp_dev_config(struct rte_compressdev *dev,
int
qat_comp_dev_close(struct rte_compressdev *dev);
+void
+qat_comp_dev_info_get(struct rte_compressdev *dev,
+ struct rte_compressdev_info *info);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v4 11/16] compress/qat: add enqueue/dequeue functions
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 " Fiona Trahe
` (10 preceding siblings ...)
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 10/16] compress/qat: add fn to return device info Fiona Trahe
@ 2018-07-10 0:41 ` Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 12/16] compress/qat: add device start and stop fns Fiona Trahe
` (4 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-10 0:41 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Wrap generic qat enqueue/dequeue functions with
compressdev enqueue and dequeue fns.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 14 ++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 8 ++++++++
2 files changed, 22 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 482ebd1..086b6cf 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -213,3 +213,17 @@ qat_comp_dev_info_get(struct rte_compressdev *dev,
info->capabilities = comp_dev->qat_dev_capabilities;
}
}
+
+uint16_t
+qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops)
+{
+ return qat_enqueue_op_burst(qp, (void **)ops, nb_ops);
+}
+
+uint16_t
+qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops)
+{
+ return qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 22576f4..f360c29 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -54,5 +54,13 @@ void
qat_comp_dev_info_get(struct rte_compressdev *dev,
struct rte_compressdev_info *info);
+uint16_t
+qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops);
+
+uint16_t
+qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v4 12/16] compress/qat: add device start and stop fns
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 " Fiona Trahe
` (11 preceding siblings ...)
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 11/16] compress/qat: add enqueue/dequeue functions Fiona Trahe
@ 2018-07-10 0:41 ` Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 13/16] compress/qat: create and populate the ops structure Fiona Trahe
` (3 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-10 0:41 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
There are no specific actions needed to start/stop a QAT comp device
so these are just trivial fns to satisfy the pmd API.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 11 +++++++++++
drivers/compress/qat/qat_comp_pmd.h | 6 ++++++
2 files changed, 17 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 086b6cf..1ab5cf7 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -176,6 +176,17 @@ qat_comp_dev_config(struct rte_compressdev *dev,
return ret;
}
+int
+qat_comp_dev_start(struct rte_compressdev *dev __rte_unused)
+{
+ return 0;
+}
+
+void
+qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused)
+{
+
+}
int
qat_comp_dev_close(struct rte_compressdev *dev)
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index f360c29..22cbefb 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -62,5 +62,11 @@ uint16_t
qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops);
+int
+qat_comp_dev_start(struct rte_compressdev *dev __rte_unused);
+
+void
+qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v4 13/16] compress/qat: create and populate the ops structure
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 " Fiona Trahe
` (12 preceding siblings ...)
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 12/16] compress/qat: add device start and stop fns Fiona Trahe
@ 2018-07-10 0:41 ` Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 14/16] compress/qat: add fns to create and destroy the PMD Fiona Trahe
` (2 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-10 0:41 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Create an ops structure and populate it with the
qat-specific functions.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 38 ++++++++++++++++++++++++++++---------
drivers/compress/qat/qat_comp_pmd.h | 30 -----------------------------
2 files changed, 29 insertions(+), 39 deletions(-)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 1ab5cf7..013ff6e 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -5,7 +5,7 @@
#include "qat_comp.h"
#include "qat_comp_pmd.h"
-void
+static void
qat_comp_stats_get(struct rte_compressdev *dev,
struct rte_compressdev_stats *stats)
{
@@ -25,7 +25,7 @@ qat_comp_stats_get(struct rte_compressdev *dev,
stats->dequeue_err_count = qat_stats.dequeue_err_count;
}
-void
+static void
qat_comp_stats_reset(struct rte_compressdev *dev)
{
struct qat_comp_dev_private *qat_priv;
@@ -40,7 +40,7 @@ qat_comp_stats_reset(struct rte_compressdev *dev)
}
-int
+static int
qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)
{
struct qat_comp_dev_private *qat_private = dev->data->dev_private;
@@ -55,7 +55,7 @@ qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)
&(dev->data->queue_pairs[queue_pair_id]));
}
-int
+static int
qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
uint32_t max_inflight_ops, int socket_id)
{
@@ -149,7 +149,7 @@ _qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)
}
}
-int
+static int
qat_comp_dev_config(struct rte_compressdev *dev,
struct rte_compressdev_config *config)
{
@@ -176,19 +176,19 @@ qat_comp_dev_config(struct rte_compressdev *dev,
return ret;
}
-int
+static int
qat_comp_dev_start(struct rte_compressdev *dev __rte_unused)
{
return 0;
}
-void
+static void
qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused)
{
}
-int
+static int
qat_comp_dev_close(struct rte_compressdev *dev)
{
int i;
@@ -207,7 +207,7 @@ qat_comp_dev_close(struct rte_compressdev *dev)
}
-void
+static void
qat_comp_dev_info_get(struct rte_compressdev *dev,
struct rte_compressdev_info *info)
{
@@ -238,3 +238,23 @@ qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
{
return qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
}
+
+
+struct rte_compressdev_ops compress_qat_ops = {
+
+ /* Device related operations */
+ .dev_configure = qat_comp_dev_config,
+ .dev_start = qat_comp_dev_start,
+ .dev_stop = qat_comp_dev_stop,
+ .dev_close = qat_comp_dev_close,
+ .dev_infos_get = qat_comp_dev_info_get,
+
+ .stats_get = qat_comp_stats_get,
+ .stats_reset = qat_comp_stats_reset,
+ .queue_pair_setup = qat_comp_qp_setup,
+ .queue_pair_release = qat_comp_qp_release,
+
+ /* Compression related operations */
+ .private_xform_create = qat_comp_private_xform_create,
+ .private_xform_free = qat_comp_private_xform_free
+};
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 22cbefb..7ba1b8d 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -30,30 +30,6 @@ struct qat_comp_dev_private {
};
-void
-qat_comp_stats_reset(struct rte_compressdev *dev);
-
-void
-qat_comp_stats_get(struct rte_compressdev *dev,
- struct rte_compressdev_stats *stats);
-int
-qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id);
-
-int
-qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
- uint32_t max_inflight_ops, int socket_id);
-
-int
-qat_comp_dev_config(struct rte_compressdev *dev,
- struct rte_compressdev_config *config);
-
-int
-qat_comp_dev_close(struct rte_compressdev *dev);
-
-void
-qat_comp_dev_info_get(struct rte_compressdev *dev,
- struct rte_compressdev_info *info);
-
uint16_t
qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops);
@@ -62,11 +38,5 @@ uint16_t
qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops);
-int
-qat_comp_dev_start(struct rte_compressdev *dev __rte_unused);
-
-void
-qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused);
-
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v4 14/16] compress/qat: add fns to create and destroy the PMD
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 " Fiona Trahe
` (13 preceding siblings ...)
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 13/16] compress/qat: create and populate the ops structure Fiona Trahe
@ 2018-07-10 0:41 ` Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 15/16] compress/qat: prevent device usage if incorrect firmware Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 16/16] docs/qat: refactor docs adding compression guide Fiona Trahe
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-10 0:41 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Now that all the device operations are available,
add the functions to create and destroy the pmd.
Called on probe and remove of the qat pci device, these
register the device with the compressdev API
and plug in all the device functionality.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/common/qat/qat_device.h | 4 ++
drivers/common/qat/qat_qp.c | 11 ++++-
drivers/common/qat/qat_qp.h | 5 ++
drivers/compress/qat/qat_comp_pmd.c | 98 +++++++++++++++++++++++++++++++++++--
drivers/compress/qat/qat_comp_pmd.h | 11 ++---
5 files changed, 117 insertions(+), 12 deletions(-)
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index 0cb370c..9599fc5 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -25,6 +25,8 @@
* - runtime data
*/
struct qat_sym_dev_private;
+struct qat_comp_dev_private;
+
struct qat_pci_device {
/* Data used by all services */
@@ -55,6 +57,8 @@ struct qat_pci_device {
*/
/* Data relating to compression service */
+ struct qat_comp_dev_private *comp_dev;
+ /**< link back to compressdev private data */
/* Data relating to asymmetric crypto service */
diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c
index 32c1759..7ca7a45 100644
--- a/drivers/common/qat/qat_qp.c
+++ b/drivers/common/qat/qat_qp.c
@@ -15,6 +15,7 @@
#include "qat_device.h"
#include "qat_qp.h"
#include "qat_sym.h"
+#include "qat_comp.h"
#include "adf_transport_access_macros.h"
@@ -606,8 +607,8 @@ qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
if (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC)
qat_sym_process_response(ops, resp_msg);
- /* add qat_asym_process_response here */
- /* add qat_comp_process_response here */
+ else if (tmp_qp->service_type == QAT_SERVICE_COMPRESSION)
+ qat_comp_process_response(ops, resp_msg);
head = adf_modulo(head + rx_queue->msg_size,
rx_queue->modulo_mask);
@@ -633,3 +634,9 @@ qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
}
return resp_counter;
}
+
+__attribute__((weak)) int
+qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused)
+{
+ return 0;
+}
diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h
index 59db945..69f8a61 100644
--- a/drivers/common/qat/qat_qp.h
+++ b/drivers/common/qat/qat_qp.h
@@ -103,4 +103,9 @@ qat_qp_setup(struct qat_pci_device *qat_dev,
int
qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,
enum qat_service_type service);
+
+/* Needed for weak function*/
+int
+qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused);
+
#endif /* _QAT_QP_H_ */
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 013ff6e..9bb9897 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -5,6 +5,18 @@
#include "qat_comp.h"
#include "qat_comp_pmd.h"
+static const struct rte_compressdev_capabilities qat_comp_gen_capabilities[] = {
+ {/* COMPRESSION - deflate */
+ .algo = RTE_COMP_ALGO_DEFLATE,
+ .comp_feature_flags = RTE_COMP_FF_MULTI_PKT_CHECKSUM |
+ RTE_COMP_FF_CRC32_CHECKSUM |
+ RTE_COMP_FF_ADLER32_CHECKSUM |
+ RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
+ RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
+ RTE_COMP_FF_HUFFMAN_FIXED,
+ .window_size = {.min = 15, .max = 15, .increment = 0} },
+ {RTE_COMP_ALGO_LIST_END, 0, {0, 0, 0} } };
+
static void
qat_comp_stats_get(struct rte_compressdev *dev,
struct rte_compressdev_stats *stats)
@@ -225,14 +237,14 @@ qat_comp_dev_info_get(struct rte_compressdev *dev,
}
}
-uint16_t
+static uint16_t
qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops)
{
return qat_enqueue_op_burst(qp, (void **)ops, nb_ops);
}
-uint16_t
+static uint16_t
qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops)
{
@@ -240,7 +252,7 @@ qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
}
-struct rte_compressdev_ops compress_qat_ops = {
+static struct rte_compressdev_ops compress_qat_ops = {
/* Device related operations */
.dev_configure = qat_comp_dev_config,
@@ -258,3 +270,83 @@ struct rte_compressdev_ops compress_qat_ops = {
.private_xform_create = qat_comp_private_xform_create,
.private_xform_free = qat_comp_private_xform_free
};
+
+int
+qat_comp_dev_create(struct qat_pci_device *qat_pci_dev)
+{
+ if (qat_pci_dev->qat_dev_gen == QAT_GEN1) {
+ QAT_LOG(ERR, "Compression PMD not supported on QAT dh895xcc");
+ return 0;
+ }
+
+ struct rte_compressdev_pmd_init_params init_params = {
+ .name = "",
+ .socket_id = qat_pci_dev->pci_dev->device.numa_node,
+ };
+ char name[RTE_COMPRESSDEV_NAME_MAX_LEN];
+ struct rte_compressdev *compressdev;
+ struct qat_comp_dev_private *comp_dev;
+
+ snprintf(name, RTE_COMPRESSDEV_NAME_MAX_LEN, "%s_%s",
+ qat_pci_dev->name, "comp");
+ QAT_LOG(DEBUG, "Creating QAT COMP device %s", name);
+
+ compressdev = rte_compressdev_pmd_create(name,
+ &qat_pci_dev->pci_dev->device,
+ sizeof(struct qat_comp_dev_private),
+ &init_params);
+
+ if (compressdev == NULL)
+ return -ENODEV;
+
+ compressdev->dev_ops = &compress_qat_ops;
+
+ compressdev->enqueue_burst = qat_comp_pmd_enqueue_op_burst;
+ compressdev->dequeue_burst = qat_comp_pmd_dequeue_op_burst;
+
+ compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
+
+ comp_dev = compressdev->data->dev_private;
+ comp_dev->qat_dev = qat_pci_dev;
+ comp_dev->compressdev = compressdev;
+ qat_pci_dev->comp_dev = comp_dev;
+
+ switch (qat_pci_dev->qat_dev_gen) {
+ case QAT_GEN1:
+ case QAT_GEN2:
+ comp_dev->qat_dev_capabilities = qat_comp_gen_capabilities;
+ break;
+ default:
+ comp_dev->qat_dev_capabilities = qat_comp_gen_capabilities;
+ QAT_LOG(DEBUG,
+ "QAT gen %d capabilities unknown, default to GEN1",
+ qat_pci_dev->qat_dev_gen);
+ break;
+ }
+
+ QAT_LOG(DEBUG,
+ "Created QAT COMP device %s as compressdev instance %d",
+ name, compressdev->data->dev_id);
+ return 0;
+}
+
+int
+qat_comp_dev_destroy(struct qat_pci_device *qat_pci_dev)
+{
+ struct qat_comp_dev_private *comp_dev;
+
+ if (qat_pci_dev == NULL)
+ return -ENODEV;
+
+ comp_dev = qat_pci_dev->comp_dev;
+ if (comp_dev == NULL)
+ return 0;
+
+ /* clean up any resources used by the device */
+ qat_comp_dev_close(comp_dev->compressdev);
+
+ rte_compressdev_pmd_destroy(comp_dev->compressdev);
+ qat_pci_dev->comp_dev = NULL;
+
+ return 0;
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 7ba1b8d..9ad2a28 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -27,16 +27,13 @@ struct qat_comp_dev_private {
/**< The device's memory for intermediate buffers */
struct rte_mempool *xformpool;
/**< The device's pool for qat_comp_xforms */
-
};
-uint16_t
-qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
- uint16_t nb_ops);
+int
+qat_comp_dev_create(struct qat_pci_device *qat_pci_dev);
-uint16_t
-qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
- uint16_t nb_ops);
+int
+qat_comp_dev_destroy(struct qat_pci_device *qat_pci_dev);
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v4 15/16] compress/qat: prevent device usage if incorrect firmware
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 " Fiona Trahe
` (14 preceding siblings ...)
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 14/16] compress/qat: add fns to create and destroy the PMD Fiona Trahe
@ 2018-07-10 0:41 ` Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 16/16] docs/qat: refactor docs adding compression guide Fiona Trahe
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-10 0:41 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Previous check only causes op to fail on dequeue.
This extends so once first fail is detected, application can
no longer enqueue ops to the device and will also get an
appropriate error if trying to reconfigure or setup the device.
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 57 ++++++++++++++++++++++++++++++++++++-
1 file changed, 56 insertions(+), 1 deletion(-)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 9bb9897..0a571b3 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -252,6 +252,61 @@ qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
}
+static uint16_t
+qat_comp_pmd_enq_deq_dummy_op_burst(void *qp __rte_unused,
+ struct rte_comp_op **ops __rte_unused,
+ uint16_t nb_ops __rte_unused)
+{
+ QAT_DP_LOG(ERR, "QAT PMD detected wrong FW version !");
+ return 0;
+}
+
+static struct rte_compressdev_ops compress_qat_dummy_ops = {
+
+ /* Device related operations */
+ .dev_configure = NULL,
+ .dev_start = NULL,
+ .dev_stop = qat_comp_dev_stop,
+ .dev_close = qat_comp_dev_close,
+ .dev_infos_get = NULL,
+
+ .stats_get = NULL,
+ .stats_reset = qat_comp_stats_reset,
+ .queue_pair_setup = NULL,
+ .queue_pair_release = qat_comp_qp_release,
+
+ /* Compression related operations */
+ .private_xform_create = NULL,
+ .private_xform_free = qat_comp_private_xform_free
+};
+
+static uint16_t
+qat_comp_pmd_dequeue_frst_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops)
+{
+ uint16_t ret = qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
+ struct qat_qp *tmp_qp = (struct qat_qp *)qp;
+
+ if (ret) {
+ if ((*ops)->debug_status ==
+ (uint64_t)ERR_CODE_QAT_COMP_WRONG_FW) {
+ tmp_qp->qat_dev->comp_dev->compressdev->enqueue_burst =
+ qat_comp_pmd_enq_deq_dummy_op_burst;
+ tmp_qp->qat_dev->comp_dev->compressdev->dequeue_burst =
+ qat_comp_pmd_enq_deq_dummy_op_burst;
+
+ tmp_qp->qat_dev->comp_dev->compressdev->dev_ops =
+ &compress_qat_dummy_ops;
+ QAT_LOG(ERR, "QAT PMD detected wrong FW version !");
+
+ } else {
+ tmp_qp->qat_dev->comp_dev->compressdev->dequeue_burst =
+ qat_comp_pmd_dequeue_op_burst;
+ }
+ }
+ return ret;
+}
+
static struct rte_compressdev_ops compress_qat_ops = {
/* Device related operations */
@@ -302,7 +357,7 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev)
compressdev->dev_ops = &compress_qat_ops;
compressdev->enqueue_burst = qat_comp_pmd_enqueue_op_burst;
- compressdev->dequeue_burst = qat_comp_pmd_dequeue_op_burst;
+ compressdev->dequeue_burst = qat_comp_pmd_dequeue_frst_op_burst;
compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v4 16/16] docs/qat: refactor docs adding compression guide
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 " Fiona Trahe
` (15 preceding siblings ...)
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 15/16] compress/qat: prevent device usage if incorrect firmware Fiona Trahe
@ 2018-07-10 0:41 ` Fiona Trahe
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-10 0:41 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Extend QAT guide to cover crypto and compression and common
information, particularly about kernel driver dependency.
Update release note.
Update compression feature list for qat.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
config/common_base | 2 +-
doc/guides/compressdevs/features/qat.ini | 22 ++++
doc/guides/compressdevs/index.rst | 1 +
doc/guides/compressdevs/qat_comp.rst | 49 +++++++++
doc/guides/cryptodevs/qat.rst | 183 +++++++++++++++++++++----------
doc/guides/rel_notes/release_18_08.rst | 5 +
6 files changed, 203 insertions(+), 59 deletions(-)
create mode 100644 doc/guides/compressdevs/features/qat.ini
create mode 100644 doc/guides/compressdevs/qat_comp.rst
diff --git a/config/common_base b/config/common_base
index 93c8857..402231d 100644
--- a/config/common_base
+++ b/config/common_base
@@ -482,7 +482,7 @@ CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4
CONFIG_RTE_DPAA_SEC_PMD_MAX_NB_SESSIONS=2048
#
-# Compile PMD for QuickAssist based devices
+# Compile PMD for QuickAssist based devices - see docs for details
#
CONFIG_RTE_LIBRTE_PMD_QAT=y
CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
diff --git a/doc/guides/compressdevs/features/qat.ini b/doc/guides/compressdevs/features/qat.ini
new file mode 100644
index 0000000..68f36c8
--- /dev/null
+++ b/doc/guides/compressdevs/features/qat.ini
@@ -0,0 +1,22 @@
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+; Supported features of 'QAT' compression driver.
+;
+[Features]
+HW Accelerated = Y
+CPU SSE =
+CPU AVX =
+CPU AVX2 =
+CPU AVX512 =
+CPU NEON =
+Stateful =
+By-Pass =
+Chained mbufs =
+Deflate = Y
+LZS =
+Adler32 = Y
+Crc32 = Y
+Adler32&Crc32 = Y
+Fixed = Y
+Dynamic =
diff --git a/doc/guides/compressdevs/index.rst b/doc/guides/compressdevs/index.rst
index bc59ce8..4228768 100644
--- a/doc/guides/compressdevs/index.rst
+++ b/doc/guides/compressdevs/index.rst
@@ -11,3 +11,4 @@ Compression Device Drivers
overview
isal
+ qat_comp
diff --git a/doc/guides/compressdevs/qat_comp.rst b/doc/guides/compressdevs/qat_comp.rst
new file mode 100644
index 0000000..167f816
--- /dev/null
+++ b/doc/guides/compressdevs/qat_comp.rst
@@ -0,0 +1,49 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+ Copyright(c) 2018 Intel Corporation.
+
+Intel(R) QuickAssist (QAT) Compression Poll Mode Driver
+=======================================================
+
+The QAT compression PMD provides poll mode compression & decompression driver
+support for the following hardware accelerator devices:
+
+* ``Intel QuickAssist Technology C62x``
+* ``Intel QuickAssist Technology C3xxx``
+
+
+Features
+--------
+
+QAT compression PMD has support for:
+
+Compression/Decompression algorithm:
+
+ * DEFLATE
+
+Huffman code type:
+
+ * FIXED
+
+Window size support:
+
+ * 32K
+
+Checksum generation:
+
+ * CRC32, Adler and combined checksum
+
+Limitations
+-----------
+
+* Chained mbufs are not yet supported, therefore max data size which can be passed to the PMD in a single mbuf is 64K - 1. If data is larger than this it will need to be split up and sent as multiple operations.
+
+* Compressdev level 0, no compression, is not supported.
+
+* Dynamic Huffman encoding is not yet supported.
+
+Installation
+------------
+
+The QAT compression PMD is built by default with a standard DPDK build.
+
+It depends on a QAT kernel driver, see :ref:`qat_kernel_installation`.
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index b899985..bdc58eb 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -68,12 +68,32 @@ Limitations
* Queue pairs are not thread-safe (that is, within a single queue pair, RX and TX from different lcores is not supported).
-Installation
-------------
+Extra notes on KASUMI F9
+------------------------
+
+When using KASUMI F9 authentication algorithm, the input buffer must be
+constructed according to the 3GPP KASUMI specifications (section 4.4, page 13):
+`<http://cryptome.org/3gpp/35201-900.pdf>`_.
+Input buffer has to have COUNT (4 bytes), FRESH (4 bytes), MESSAGE and DIRECTION (1 bit)
+concatenated. After the DIRECTION bit, a single '1' bit is appended, followed by
+between 0 and 7 '0' bits, so that the total length of the buffer is multiple of 8 bits.
+Note that the actual message can be any length, specified in bits.
-To enable QAT in DPDK, follow the instructions for modifying the compile-time
+Once this buffer is passed this way, when creating the crypto operation,
+length of data to authenticate (op.sym.auth.data.length) must be the length
+of all the items described above, including the padding at the end.
+Also, offset of data to authenticate (op.sym.auth.data.offset)
+must be such that points at the start of the COUNT bytes.
+
+
+Building the DPDK QAT cryptodev PMD
+-----------------------------------
+
+
+To enable QAT crypto in DPDK, follow the instructions for modifying the compile-time
configuration file as described `here <http://dpdk.org/doc/guides/linux_gsg/build_dpdk.html>`_.
+
Quick instructions are as follows:
.. code-block:: console
@@ -81,29 +101,95 @@ Quick instructions are as follows:
cd to the top-level DPDK directory
make config T=x86_64-native-linuxapp-gcc
sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT\)=n,\1=y,' build/.config
+ sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT_SYM\)=n,\1=y,' build/.config
make
-To use the DPDK QAT PMD an SRIOV-enabled QAT kernel driver is required. The VF
-devices exposed by this driver will be used by the QAT PMD. The devices and
-available kernel drivers and device ids are :
+
+.. _qat_kernel_installation:
+
+Dependency on the QAT kernel driver
+-----------------------------------
+
+To use the QAT PMD an SRIOV-enabled QAT kernel driver is required. The VF
+devices created and initialised by this driver will be used by the QAT PMD.
+
+Instructions for installation are below, but first an explanation of the
+relationships between the PF/VF devices and the PMDs visible to
+DPDK applications.
+
+
+Acceleration services - cryptography and compression - are provided to DPDK
+applications via PMDs which register to implement the corresponding
+cryptodev and compressdev APIs.
+
+Each QuickAssist VF device can expose one cryptodev PMD and/or one compressdev PMD.
+These QAT PMDs share the same underlying device and pci-mgmt code, but are
+enumerated independently on their respective APIs and appear as independent
+devices to applications.
+
+.. Note::
+
+ Each VF can only be used by one DPDK process. It is not possible to share
+ the same VF across multiple processes, even if these processes are using
+ different acceleration services.
+
+ Conversely one DPDK process can use one or more QAT VFs and can expose both
+ cryptodev and compressdev instances on each of those VFs.
+
+
+
+Device and driver naming
+------------------------
+
+* The qat cryptodev driver name is "crypto_qat".
+ The rte_cryptodev_devices_get() returns the devices exposed by this driver.
+
+* Each qat crypto device has a unique name, in format
+ <pci bdf>_<service>, e.g. "0000:41:01.0_qat_sym".
+ This name can be passed to rte_cryptodev_get_dev_id() to get the device_id.
+
+.. Note::
+
+ The qat crypto driver name is passed to the dpdk-test-crypto-perf tool in the -devtype parameter.
+
+ The qat crypto device name is in the format of the slave parameter passed to the crypto scheduler.
+
+* The qat compressdev driver name is "comp_qat".
+ The rte_compressdev_devices_get() returns the devices exposed by this driver.
+
+* Each qat compression device has a unique name, in format
+ <pci bdf>_<service>, e.g. "0000:41:01.0_qat_comp".
+ This name can be passed to rte_compressdev_get_dev_id() to get the device_id.
+
+
+Available kernel drivers
+------------------------
+
+Kernel drivers for each device are listed in the following table. Scroll right
+to check that the driver and device supports the servic you require.
+
.. _table_qat_pmds_drivers:
.. table:: QAT device generations, devices and drivers
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | Gen | Device | Driver | Kernel Module | Pci Driver | PF Did | #PFs | Vf Did | VFs/PF |
- +=====+==========+========+===============+============+========+======+========+========+
- | 1 | DH895xCC | 01.org | icp_qa_al | n/a | 435 | 1 | 443 | 32 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | 1 | DH895xCC | 4.4+ | qat_dh895xcc | dh895xcc | 435 | 1 | 443 | 32 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | 2 | C62x | 4.5+ | qat_c62x | c6xx | 37c8 | 3 | 37c9 | 16 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | 2 | C3xxx | 4.5+ | qat_c3xxx | c3xxx | 19e2 | 1 | 19e3 | 16 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | 2 | D15xx | p | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | Gen | Device | Driver/ver | Kernel Module | Pci Driver | PF Did | #PFs | VF Did | VFs/PF | cryptodev | compressdev |
+ +=====+==========+===============+===============+============+========+======+========+========+===========+=============+
+ | 1 | DH895xCC | linux/4.4+ | qat_dh895xcc | dh895xcc | 435 | 1 | 443 | 32 | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | 2 | C62x | linux/4.5+ | qat_c62x | c6xx | 37c8 | 3 | 37c9 | 16 | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | Yes | Yes |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | 2 | C3xxx | linux/4.5+ | qat_c3xxx | c3xxx | 19e2 | 1 | 19e3 | 16 | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | Yes | Yes |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | 2 | D15xx | p | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
The ``Driver`` column indicates either the Linux kernel version in which
@@ -196,9 +282,9 @@ Consult the *Getting Started Guide* at the same URL for further information.
The steps below assume you are:
-* Building on a platform with one ``DH895xCC`` device.
-* Using package ``qatmux.l.2.3.0-34.tgz``.
-* On Fedora21 kernel ``3.17.4-301.fc21.x86_64``.
+* Building on a platform with one ``C62x`` device.
+* Using package ``qat1.7.l.4.2.0-000xx.tar.gz``.
+* On Fedora26 kernel ``4.11.11-300.fc26.x86_64``.
In the BIOS ensure that SRIOV is enabled and VT-d is disabled.
@@ -206,21 +292,30 @@ Uninstall any existing QAT driver, for example by running:
* ``./installer.sh uninstall`` in the directory where originally installed.
-* or ``rmmod qat_dh895xcc; rmmod intel_qat``.
Build and install the SRIOV-enabled QAT driver::
mkdir /QAT
cd /QAT
- # Copy qatmux.l.2.3.0-34.tgz to this location
- tar zxof qatmux.l.2.3.0-34.tgz
+ # Copy the package to this location and unpack
+ tar zxof qat1.7.l.4.2.0-000xx.tar.gz
- export ICP_WITHOUT_IOMMU=1
- ./installer.sh install QAT1.6 host
+ ./configure --enable-icp-sriov=host
+ make install
+
+You can use ``cat /sys/kernel/debug/qat<your device type and bdf>/version/fw`` to confirm the driver is correctly installed and is using firmware version 4.2.0.
+You can use ``lspci -d:37c9`` to confirm the presence of the 16 VF devices available per ``C62x`` PF.
+
+Confirm the driver is correctly installed and is using firmware version 4.2.0::
+
+ cat /sys/kernel/debug/qat<your device type and bdf>/version/fw
+
+
+Confirm the presence of 48 VF devices - 16 per PF::
+
+ lspci -d:37c9
-You can use ``cat /proc/icp_dh895xcc_dev0/version`` to confirm the driver is correctly installed.
-You can use ``lspci -d:443`` to confirm the of the 32 VF devices available per ``DH895xCC`` device.
To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_.
@@ -261,6 +356,7 @@ To complete the installation - follow instructions in `Binding the available VFs
sudo yum install zlib-devel
sudo yum install openssl-devel
+ sudo yum install libudev-devel
.. Note::
@@ -343,35 +439,6 @@ Another way to bind the VFs to the DPDK UIO driver is by using the
./usertools/dpdk-devbind.py -b igb_uio 0000:03:01.1
-Extra notes on KASUMI F9
-------------------------
-
-When using KASUMI F9 authentication algorithm, the input buffer must be
-constructed according to the 3GPP KASUMI specifications (section 4.4, page 13):
-`<http://cryptome.org/3gpp/35201-900.pdf>`_.
-Input buffer has to have COUNT (4 bytes), FRESH (4 bytes), MESSAGE and DIRECTION (1 bit)
-concatenated. After the DIRECTION bit, a single '1' bit is appended, followed by
-between 0 and 7 '0' bits, so that the total length of the buffer is multiple of 8 bits.
-Note that the actual message can be any length, specified in bits.
-
-Once this buffer is passed this way, when creating the crypto operation,
-length of data to authenticate (op.sym.auth.data.length) must be the length
-of all the items described above, including the padding at the end.
-Also, offset of data to authenticate (op.sym.auth.data.offset)
-must be such that points at the start of the COUNT bytes.
-
-Device and driver naming
-------------------------
-
-The qat crypto driver name is "crypto_qat".
-This name is passed to the dpdk-test-crypto-perf tool in the -devtype parameter.
-The rte_cryptodev_devices_get() can return the devices exposed by a driver.
-
-Each qat crypto device has a unique name, in format
-<pci bdf>_<service>, e.g. "0000:41:01.0_qat_sym".
-This name can be passed to rte_cryptodev_get_dev_id() to get the device_id.
-This is also the format of the slave parameter passed to the crypto scheduler.
-
Debugging
----------------------------------------
diff --git a/doc/guides/rel_notes/release_18_08.rst b/doc/guides/rel_notes/release_18_08.rst
index 3487e3f..799971a 100644
--- a/doc/guides/rel_notes/release_18_08.rst
+++ b/doc/guides/rel_notes/release_18_08.rst
@@ -46,6 +46,11 @@ New Features
Flow API support has been added to CXGBE Poll Mode Driver to offload
flows to Chelsio T5/T6 NICs.
+* **Added a new compression PMD using Intel's QuickAssist (QAT) device family.**
+
+ Added the new ``QAT`` compression driver, for compression and decompression
+ operations in software. See the :doc:`../compressdevs/qat_comp` compression
+ driver guide for details on this new driver.
API Changes
-----------
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v5 00/16] compress/qat: add compression PMD
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 " Fiona Trahe
@ 2018-07-11 11:56 ` Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 " Fiona Trahe
` (16 more replies)
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 01/16] common/qat: updated firmware headers Fiona Trahe
` (15 subsequent siblings)
16 siblings, 17 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-11 11:56 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Create compression PMD for Intel QuickAssist devices
Currently only the C62x and c3xxx devices are supported.
The qat comp PMD supports
- stateless compression and
decompression using the Deflate algorithm with Fixed Huffman
encoding. Dynamic huffman encoding is not supported, it
will be added in a later patch.
- checksum generation: Adler32, CRC32 and combined.
The compression service is hosted on a QuickAssist VF PCI
device, which is managed by code in the
drivers/common/qat directory.
v5 changes:
- rebased against latest r/n and features/default.ini
- fixed common/qat/Makefile so no build output files
left hanging around in compress/qat src dir.
v4 changes:
- corrected capabilities
v3 changes:
- only commit message changes, i.e. removed ChangeId and fixed typos
v2 changes:
- Added check for correct firmware
- Split patchset
- Added documentation
- removed support for scatter-gather-lists and related config flag
- Removed support for Dynamic huffman encoding and related IM buffer config flag
- Removed support for DH895xcc device
Fiona Trahe (16):
common/qat: updated firmware headers
compress/qat: add makefiles for PMD
compress/qat: add meson build
compress/qat: add xform processing
compress/qat: create fw request and process response
compress/qat: check that correct firmware is in use
compress/qat: add stats functions
compress/qat: setup queue-pairs for compression service
compress/qat: add fns to configure and clear device
compress/qat: add fn to return device info
compress/qat: add enqueue/dequeue functions
compress/qat: add device start and stop fns
compress/qat: create and populate the ops structure
compress/qat: add fns to create and destroy the PMD
compress/qat: prevent device usage if incorrect firmware
docs/qat: refactor docs adding compression guide
MAINTAINERS | 4 +
config/common_base | 5 +-
doc/guides/compressdevs/features/qat.ini | 24 ++
doc/guides/compressdevs/index.rst | 1 +
doc/guides/compressdevs/qat_comp.rst | 49 +++
doc/guides/cryptodevs/qat.rst | 183 ++++++----
doc/guides/rel_notes/release_18_08.rst | 5 +
drivers/common/qat/Makefile | 60 ++--
drivers/common/qat/qat_adf/icp_qat_fw.h | 69 +++-
drivers/common/qat/qat_adf/icp_qat_fw_comp.h | 482 +++++++++++++++++++++++++++
drivers/common/qat/qat_adf/icp_qat_hw.h | 130 +++++++-
drivers/common/qat/qat_device.h | 4 +
drivers/common/qat/qat_qp.c | 11 +-
drivers/common/qat/qat_qp.h | 5 +
drivers/compress/meson.build | 2 +-
drivers/compress/qat/meson.build | 18 +
drivers/compress/qat/qat_comp.c | 359 ++++++++++++++++++++
drivers/compress/qat/qat_comp.h | 56 ++++
drivers/compress/qat/qat_comp_pmd.c | 407 ++++++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 39 +++
drivers/compress/qat/rte_pmd_qat_version.map | 3 +
drivers/crypto/qat/meson.build | 10 +-
drivers/crypto/qat/rte_pmd_qat_version.map | 3 -
test/test/test_cryptodev.c | 6 +-
24 files changed, 1809 insertions(+), 126 deletions(-)
create mode 100644 doc/guides/compressdevs/features/qat.ini
create mode 100644 doc/guides/compressdevs/qat_comp.rst
create mode 100644 drivers/common/qat/qat_adf/icp_qat_fw_comp.h
create mode 100644 drivers/compress/qat/meson.build
create mode 100644 drivers/compress/qat/qat_comp.c
create mode 100644 drivers/compress/qat/qat_comp.h
create mode 100644 drivers/compress/qat/qat_comp_pmd.c
create mode 100644 drivers/compress/qat/qat_comp_pmd.h
create mode 100644 drivers/compress/qat/rte_pmd_qat_version.map
delete mode 100644 drivers/crypto/qat/rte_pmd_qat_version.map
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v5 01/16] common/qat: updated firmware headers
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 " Fiona Trahe
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 " Fiona Trahe
@ 2018-07-11 11:56 ` Fiona Trahe
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 02/16] compress/qat: add makefiles for PMD Fiona Trahe
` (14 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-11 11:56 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Updated to latest firmware headers files for QuickAssist devices.
Includes updates for symmetric crypto, PKE and Compression services.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
drivers/common/qat/qat_adf/icp_qat_fw.h | 69 +++-
drivers/common/qat/qat_adf/icp_qat_fw_comp.h | 482 +++++++++++++++++++++++++++
drivers/common/qat/qat_adf/icp_qat_hw.h | 130 +++++++-
3 files changed, 654 insertions(+), 27 deletions(-)
create mode 100644 drivers/common/qat/qat_adf/icp_qat_fw_comp.h
diff --git a/drivers/common/qat/qat_adf/icp_qat_fw.h b/drivers/common/qat/qat_adf/icp_qat_fw.h
index ae39b7f..8f7cb37 100644
--- a/drivers/common/qat/qat_adf/icp_qat_fw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_fw.h
@@ -117,6 +117,10 @@ struct icp_qat_fw_comn_resp {
#define ICP_QAT_FW_COMN_VALID_FLAG_BITPOS 7
#define ICP_QAT_FW_COMN_VALID_FLAG_MASK 0x1
#define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK 0x7F
+#define ICP_QAT_FW_COMN_CNV_FLAG_BITPOS 6
+#define ICP_QAT_FW_COMN_CNV_FLAG_MASK 0x1
+#define ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS 5
+#define ICP_QAT_FW_COMN_CNVNR_FLAG_MASK 0x1
#define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \
icp_qat_fw_comn_req_hdr_t.service_type
@@ -133,6 +137,16 @@ struct icp_qat_fw_comn_resp {
#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_GET(hdr_t) \
ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_t.hdr_flags)
+#define ICP_QAT_FW_COMN_HDR_CNVNR_FLAG_GET(hdr_flags) \
+ QAT_FIELD_GET(hdr_flags, \
+ ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS, \
+ ICP_QAT_FW_COMN_CNVNR_FLAG_MASK)
+
+#define ICP_QAT_FW_COMN_HDR_CNV_FLAG_GET(hdr_flags) \
+ QAT_FIELD_GET(hdr_flags, \
+ ICP_QAT_FW_COMN_CNV_FLAG_BITPOS, \
+ ICP_QAT_FW_COMN_CNV_FLAG_MASK)
+
#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_SET(hdr_t, val) \
ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val)
@@ -204,29 +218,44 @@ struct icp_qat_fw_comn_resp {
& ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)); }
+#define ICP_QAT_FW_COMN_NEXT_ID_SET_2(next_curr_id, val) \
+ do { \
+ (next_curr_id) = \
+ (((next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK) | \
+ (((val) << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) & \
+ ICP_QAT_FW_COMN_NEXT_ID_MASK)) \
+ } while (0)
+
+#define ICP_QAT_FW_COMN_CURR_ID_SET_2(next_curr_id, val) \
+ do { \
+ (next_curr_id) = \
+ (((next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
+ ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) \
+ } while (0)
+
#define QAT_COMN_RESP_CRYPTO_STATUS_BITPOS 7
#define QAT_COMN_RESP_CRYPTO_STATUS_MASK 0x1
+#define QAT_COMN_RESP_PKE_STATUS_BITPOS 6
+#define QAT_COMN_RESP_PKE_STATUS_MASK 0x1
#define QAT_COMN_RESP_CMP_STATUS_BITPOS 5
#define QAT_COMN_RESP_CMP_STATUS_MASK 0x1
#define QAT_COMN_RESP_XLAT_STATUS_BITPOS 4
#define QAT_COMN_RESP_XLAT_STATUS_MASK 0x1
#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS 3
#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1
-
-#define ICP_QAT_FW_COMN_RESP_STATUS_BUILD(crypto, comp, xlat, eolb) \
- ((((crypto) & QAT_COMN_RESP_CRYPTO_STATUS_MASK) << \
- QAT_COMN_RESP_CRYPTO_STATUS_BITPOS) | \
- (((comp) & QAT_COMN_RESP_CMP_STATUS_MASK) << \
- QAT_COMN_RESP_CMP_STATUS_BITPOS) | \
- (((xlat) & QAT_COMN_RESP_XLAT_STATUS_MASK) << \
- QAT_COMN_RESP_XLAT_STATUS_BITPOS) | \
- (((eolb) & QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK) << \
- QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS))
+#define QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS 2
+#define QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK 0x1
+#define QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS 0
+#define QAT_COMN_RESP_XLT_WA_APPLIED_MASK 0x1
#define ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(status) \
QAT_FIELD_GET(status, QAT_COMN_RESP_CRYPTO_STATUS_BITPOS, \
QAT_COMN_RESP_CRYPTO_STATUS_MASK)
+#define ICP_QAT_FW_COMN_RESP_PKE_STAT_GET(status) \
+ QAT_FIELD_GET(status, QAT_COMN_RESP_PKE_STATUS_BITPOS, \
+ QAT_COMN_RESP_PKE_STATUS_MASK)
+
#define ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(status) \
QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_STATUS_BITPOS, \
QAT_COMN_RESP_CMP_STATUS_MASK)
@@ -235,10 +264,18 @@ struct icp_qat_fw_comn_resp {
QAT_FIELD_GET(status, QAT_COMN_RESP_XLAT_STATUS_BITPOS, \
QAT_COMN_RESP_XLAT_STATUS_MASK)
+#define ICP_QAT_FW_COMN_RESP_XLT_WA_APPLIED_GET(status) \
+ QAT_FIELD_GET(status, QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS, \
+ QAT_COMN_RESP_XLT_WA_APPLIED_MASK)
+
#define ICP_QAT_FW_COMN_RESP_CMP_END_OF_LAST_BLK_FLAG_GET(status) \
QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS, \
QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK)
+#define ICP_QAT_FW_COMN_RESP_UNSUPPORTED_REQUEST_STAT_GET(status) \
+ QAT_FIELD_GET(status, QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS, \
+ QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK)
+
#define ICP_QAT_FW_COMN_STATUS_FLAG_OK 0
#define ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 1
#define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0
@@ -257,8 +294,16 @@ struct icp_qat_fw_comn_resp {
#define ERR_CODE_OVERFLOW_ERROR -11
#define ERR_CODE_SOFT_ERROR -12
#define ERR_CODE_FATAL_ERROR -13
-#define ERR_CODE_SSM_ERROR -14
-#define ERR_CODE_ENDPOINT_ERROR -15
+#define ERR_CODE_COMP_OUTPUT_CORRUPTION -14
+#define ERR_CODE_HW_INCOMPLETE_FILE -15
+#define ERR_CODE_SSM_ERROR -16
+#define ERR_CODE_ENDPOINT_ERROR -17
+#define ERR_CODE_CNV_ERROR -18
+#define ERR_CODE_EMPTY_DYM_BLOCK -19
+#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_HANDLE -20
+#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_HMAC_FAILED -21
+#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_WRAPPING_ALGO -22
+#define ERR_CODE_KPT_DRNG_SEED_NOT_LOAD -23
enum icp_qat_fw_slice {
ICP_QAT_FW_SLICE_NULL = 0,
diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_comp.h b/drivers/common/qat/qat_adf/icp_qat_fw_comp.h
new file mode 100644
index 0000000..8138177
--- /dev/null
+++ b/drivers/common/qat/qat_adf/icp_qat_fw_comp.h
@@ -0,0 +1,482 @@
+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+#ifndef _ICP_QAT_FW_COMP_H_
+#define _ICP_QAT_FW_COMP_H_
+
+#include "icp_qat_fw.h"
+
+enum icp_qat_fw_comp_cmd_id {
+ ICP_QAT_FW_COMP_CMD_STATIC = 0,
+ /*!< Static Compress Request */
+
+ ICP_QAT_FW_COMP_CMD_DYNAMIC = 1,
+ /*!< Dynamic Compress Request */
+
+ ICP_QAT_FW_COMP_CMD_DECOMPRESS = 2,
+ /*!< Decompress Request */
+
+ ICP_QAT_FW_COMP_CMD_DELIMITER
+ /**< Delimiter type */
+};
+
+/**< Flag usage */
+
+#define ICP_QAT_FW_COMP_STATELESS_SESSION 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that session is stateless
+ */
+
+#define ICP_QAT_FW_COMP_STATEFUL_SESSION 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that session is stateful
+ */
+
+#define ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that autoselectbest is NOT used
+ */
+
+#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that autoselectbest is used
+ */
+
+#define ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is NOT used
+ */
+
+#define ICP_QAT_FW_COMP_ENH_AUTO_SELECT_BEST 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is used
+ */
+
+#define ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is NOT used
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is used
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_USED_AS_INTMD_BUF 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing secure RAM from being used as
+ * an intermediate buffer is DISABLED.
+ */
+
+#define ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing secure RAM from being used as
+ * an intermediate buffer is ENABLED.
+ */
+
+/**< Flag mask & bit position */
+
+#define ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS 2
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the session type
+ */
+
+#define ICP_QAT_FW_COMP_SESSION_TYPE_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask used to determine the session type
+ */
+
+#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS 3
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for auto select best
+ */
+
+#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for auto select best
+ */
+
+#define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS 4
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for enhanced auto select best
+ */
+
+#define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for enhanced auto select best
+ */
+
+#define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS 5
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for disabling type zero header write back
+ * when Enhanced autoselect best is enabled. If set firmware does
+ * not return type0 store block header, only copies src to dest.
+ * (if best output is Type0)
+ */
+
+#define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for auto select best
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS 7
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for flag used to disable secure ram from
+ * being used as an intermediate buffer.
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for disable secure ram for use as an intermediate
+ * buffer.
+ */
+
+#define ICP_QAT_FW_COMP_FLAGS_BUILD(sesstype, autoselect, enhanced_asb, \
+ ret_uncomp, secure_ram) \
+ ((((sesstype)&ICP_QAT_FW_COMP_SESSION_TYPE_MASK) \
+ << ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS) | \
+ (((autoselect)&ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK) \
+ << ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS) | \
+ (((enhanced_asb)&ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK) \
+ << ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS) | \
+ (((ret_uncomp)&ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK) \
+ << ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS) | \
+ (((secure_ram)&ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK) \
+ << ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS))
+
+union icp_qat_fw_comp_req_hdr_cd_pars {
+ /**< LWs 2-5 */
+ struct {
+ uint64_t content_desc_addr;
+ /**< Address of the content descriptor */
+
+ uint16_t content_desc_resrvd1;
+ /**< Content descriptor reserved field */
+
+ uint8_t content_desc_params_sz;
+ /**< Size of the content descriptor parameters in quad words.
+ * These parameters describe the session setup configuration
+ * info for the slices that this request relies upon i.e.
+ * the configuration word and cipher key needed by the cipher
+ * slice if there is a request for cipher processing.
+ */
+
+ uint8_t content_desc_hdr_resrvd2;
+ /**< Content descriptor reserved field */
+
+ uint32_t content_desc_resrvd3;
+ /**< Content descriptor reserved field */
+ } s;
+
+ struct {
+ uint32_t comp_slice_cfg_word[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /* Compression Slice Config Word */
+
+ uint32_t content_desc_resrvd4;
+ /**< Content descriptor reserved field */
+
+ } sl;
+
+};
+
+struct icp_qat_fw_comp_req_params {
+ /**< LW 14 */
+ uint32_t comp_len;
+ /**< Size of input to process in bytes Note: Only EOP requests can be
+ * odd for decompression. IA must set LSB to zero for odd sized
+ * intermediate inputs
+ */
+
+ /**< LW 15 */
+ uint32_t out_buffer_sz;
+ /**< Size of output buffer in bytes */
+
+ /**< LW 16 */
+ uint32_t initial_crc32;
+ /**< CRC of previously processed bytes */
+
+ /**< LW 17 */
+ uint32_t initial_adler;
+ /**< Adler of previously processed bytes */
+
+ /**< LW 18 */
+ uint32_t req_par_flags;
+
+ /**< LW 19 */
+ uint32_t rsrvd;
+};
+
+#define ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(sop, eop, bfinal, cnv, cnvnr) \
+ ((((sop)&ICP_QAT_FW_COMP_SOP_MASK) << ICP_QAT_FW_COMP_SOP_BITPOS) | \
+ (((eop)&ICP_QAT_FW_COMP_EOP_MASK) << ICP_QAT_FW_COMP_EOP_BITPOS) | \
+ (((bfinal)&ICP_QAT_FW_COMP_BFINAL_MASK) \
+ << ICP_QAT_FW_COMP_BFINAL_BITPOS) | \
+ ((cnv & ICP_QAT_FW_COMP_CNV_MASK) << ICP_QAT_FW_COMP_CNV_BITPOS) | \
+ ((cnvnr & ICP_QAT_FW_COMP_CNV_RECOVERY_MASK) \
+ << ICP_QAT_FW_COMP_CNV_RECOVERY_BITPOS))
+
+#define ICP_QAT_FW_COMP_NOT_SOP 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request is NOT Start of Packet
+ */
+
+#define ICP_QAT_FW_COMP_SOP 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request IS Start of Packet
+ */
+
+#define ICP_QAT_FW_COMP_NOT_EOP 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request is NOT Start of Packet
+ */
+
+#define ICP_QAT_FW_COMP_EOP 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request IS End of Packet
+ */
+
+#define ICP_QAT_FW_COMP_NOT_BFINAL 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing to indicate firmware this is not the last block
+ */
+
+#define ICP_QAT_FW_COMP_BFINAL 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing to indicate firmware this is the last block
+ */
+
+#define ICP_QAT_FW_COMP_NO_CNV 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that NO cnv check is to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_CNV 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that a cnv check IS to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_NO_CNV_RECOVERY 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that NO cnv recovery is to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_CNV_RECOVERY 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that a cnv recovery is to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_SOP_BITPOS 0
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for SOP
+ */
+
+#define ICP_QAT_FW_COMP_SOP_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask used to determine SOP
+ */
+
+#define ICP_QAT_FW_COMP_EOP_BITPOS 1
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for EOP
+ */
+
+#define ICP_QAT_FW_COMP_EOP_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask used to determine EOP
+ */
+
+#define ICP_QAT_FW_COMP_BFINAL_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for the bfinal bit
+ */
+
+#define ICP_QAT_FW_COMP_BFINAL_BITPOS 6
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the bfinal bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for the CNV bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_BITPOS 16
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the CNV bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_RECOVERY_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for the CNV Recovery bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_RECOVERY_BITPOS 17
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the CNV Recovery bit
+ */
+
+struct icp_qat_fw_xlt_req_params {
+ /**< LWs 20-21 */
+ uint64_t inter_buff_ptr;
+ /**< This field specifies the physical address of an intermediate
+ * buffer SGL array. The array contains a pair of 64-bit
+ * intermediate buffer pointers to SGL buffer descriptors, one pair
+ * per CPM. Please refer to the CPM1.6 Firmware Interface HLD
+ * specification for more details.
+ */
+};
+
+
+struct icp_qat_fw_comp_cd_hdr {
+ /**< LW 24 */
+ uint16_t ram_bank_flags;
+ /**< Flags to show which ram banks to access */
+
+ uint8_t comp_cfg_offset;
+ /**< Quad word offset from the content descriptor parameters address
+ * to the parameters for the compression processing
+ */
+
+ uint8_t next_curr_id;
+ /**< This field combines the next and current id (each four bits) -
+ * the next id is the most significant nibble.
+ * Next Id: Set to the next slice to pass the compressed data through.
+ * Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through
+ * anymore slices after compression
+ * Current Id: Initialised with the compression slice type
+ */
+
+ /**< LW 25 */
+ uint32_t resrvd;
+ /**< LWs 26-27 */
+
+ uint64_t comp_state_addr;
+ /**< Pointer to compression state */
+
+ /**< LWs 28-29 */
+ uint64_t ram_banks_addr;
+ /**< Pointer to banks */
+
+};
+
+
+struct icp_qat_fw_xlt_cd_hdr {
+ /**< LW 30 */
+ uint16_t resrvd1;
+ /**< Reserved field and assumed set to 0 */
+
+ uint8_t resrvd2;
+ /**< Reserved field and assumed set to 0 */
+
+ uint8_t next_curr_id;
+ /**< This field combines the next and current id (each four bits) -
+ * the next id is the most significant nibble.
+ * Next Id: Set to the next slice to pass the translated data through.
+ * Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through
+ * any more slices after compression
+ * Current Id: Initialised with the translation slice type
+ */
+
+ /**< LW 31 */
+ uint32_t resrvd3;
+ /**< Reserved and should be set to zero, needed for quadword
+ * alignment
+ */
+};
+
+struct icp_qat_fw_comp_req {
+ /**< LWs 0-1 */
+ struct icp_qat_fw_comn_req_hdr comn_hdr;
+ /**< Common request header - for Service Command Id,
+ * use service-specific Compression Command Id.
+ * Service Specific Flags - use Compression Command Flags
+ */
+
+ /**< LWs 2-5 */
+ union icp_qat_fw_comp_req_hdr_cd_pars cd_pars;
+ /**< Compression service-specific content descriptor field which points
+ * either to a content descriptor parameter block or contains the
+ * compression slice config word.
+ */
+
+ /**< LWs 6-13 */
+ struct icp_qat_fw_comn_req_mid comn_mid;
+ /**< Common request middle section */
+
+ /**< LWs 14-19 */
+ struct icp_qat_fw_comp_req_params comp_pars;
+ /**< Compression request Parameters block */
+
+ /**< LWs 20-21 */
+ union {
+ struct icp_qat_fw_xlt_req_params xlt_pars;
+ /**< Translation request Parameters block */
+ uint32_t resrvd1[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /**< Reserved if not used for translation */
+
+ } u1;
+
+ /**< LWs 22-23 */
+ union {
+ uint32_t resrvd2[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /**< Reserved - not used if Batch and Pack is disabled.*/
+
+ uint64_t bnp_res_table_addr;
+ /**< A generic pointer to the unbounded list of
+ * icp_qat_fw_resp_comp_pars members. This pointer is only
+ * used when the Batch and Pack is enabled.
+ */
+ } u3;
+
+ /**< LWs 24-29 */
+ struct icp_qat_fw_comp_cd_hdr comp_cd_ctrl;
+ /**< Compression request content descriptor control block header */
+
+ /**< LWs 30-31 */
+ union {
+ struct icp_qat_fw_xlt_cd_hdr xlt_cd_ctrl;
+ /**< Translation request content descriptor
+ * control block header
+ */
+
+ uint32_t resrvd3[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /**< Reserved if not used for translation */
+ } u2;
+};
+
+struct icp_qat_fw_resp_comp_pars {
+ /**< LW 4 */
+ uint32_t input_byte_counter;
+ /**< Input byte counter */
+
+ /**< LW 5 */
+ uint32_t output_byte_counter;
+ /**< Output byte counter */
+
+ /**< LW 6 & 7*/
+ union {
+ uint64_t curr_chksum;
+ struct {
+ /**< LW 6 */
+ uint32_t curr_crc32;
+ /**< LW 7 */
+ uint32_t curr_adler_32;
+ };
+ };
+};
+
+struct icp_qat_fw_comp_resp {
+ /**< LWs 0-1 */
+ struct icp_qat_fw_comn_resp_hdr comn_resp;
+ /**< Common interface response format see icp_qat_fw.h */
+
+ /**< LWs 2-3 */
+ uint64_t opaque_data;
+ /**< Opaque data passed from the request to the response message */
+
+ /**< LWs 4-7 */
+ struct icp_qat_fw_resp_comp_pars comp_resp_pars;
+ /**< Common response params (checksums and byte counts) */
+};
+
+#endif
diff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h b/drivers/common/qat/qat_adf/icp_qat_hw.h
index 56e3cf7..e7961db 100644
--- a/drivers/common/qat/qat_adf/icp_qat_hw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_hw.h
@@ -72,19 +72,44 @@ struct icp_qat_hw_auth_config {
#define QAT_AUTH_ALGO_MASK 0xF
#define QAT_AUTH_CMP_BITPOS 8
#define QAT_AUTH_CMP_MASK 0x7F
-#define QAT_AUTH_SHA3_PADDING_BITPOS 16
-#define QAT_AUTH_SHA3_PADDING_MASK 0x1
+#define QAT_AUTH_SHA3_PADDING_DISABLE_BITPOS 16
+#define QAT_AUTH_SHA3_PADDING_DISABLE_MASK 0x1
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_BITPOS 17
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_MASK 0x1
#define QAT_AUTH_ALGO_SHA3_BITPOS 22
#define QAT_AUTH_ALGO_SHA3_MASK 0x3
-#define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \
- (((mode & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \
- ((algo & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \
- (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) << \
- QAT_AUTH_ALGO_SHA3_BITPOS) | \
- (((((algo == ICP_QAT_HW_AUTH_ALGO_SHA3_256) || \
- (algo == ICP_QAT_HW_AUTH_ALGO_SHA3_512)) ? 1 : 0) \
- & QAT_AUTH_SHA3_PADDING_MASK) << QAT_AUTH_SHA3_PADDING_BITPOS) | \
- ((cmp_len & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
+#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_BITPOS 16
+#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_MASK 0xF
+#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_BITPOS 24
+#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_MASK 0xFF
+#define QAT_AUTH_SHA3_HW_PADDING_ENABLE 0
+#define QAT_AUTH_SHA3_HW_PADDING_DISABLE 1
+#define QAT_AUTH_SHA3_PADDING_DISABLE_USE_DEFAULT 0
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_USE_DEFAULT 0
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_PROGRAMMABLE 1
+#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_RESERVED 0
+#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_RESERVED 0
+
+#define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \
+ ((((mode) & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \
+ (((algo) & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \
+ (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) \
+ << QAT_AUTH_ALGO_SHA3_BITPOS) | \
+ (((QAT_AUTH_SHA3_PADDING_DISABLE_USE_DEFAULT) & \
+ QAT_AUTH_SHA3_PADDING_DISABLE_MASK) \
+ << QAT_AUTH_SHA3_PADDING_DISABLE_BITPOS) | \
+ (((QAT_AUTH_SHA3_PADDING_OVERRIDE_USE_DEFAULT) & \
+ QAT_AUTH_SHA3_PADDING_OVERRIDE_MASK) \
+ << QAT_AUTH_SHA3_PADDING_OVERRIDE_BITPOS) | \
+ (((cmp_len) & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
+
+#define ICP_QAT_HW_AUTH_CONFIG_BUILD_UPPER \
+ ((((QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_RESERVED) & \
+ QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_MASK) \
+ << QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_BITPOS) | \
+ (((QAT_AUTH_SHA3_PROG_PADDING_PREFIX_RESERVED) & \
+ QAT_AUTH_SHA3_PROG_PADDING_PREFIX_MASK) \
+ << QAT_AUTH_SHA3_PROG_PADDING_PREFIX_BITPOS))
struct icp_qat_hw_auth_counter {
uint32_t counter;
@@ -107,13 +132,13 @@ struct icp_qat_hw_auth_setup {
#define ICP_QAT_HW_MD5_STATE1_SZ 16
#define ICP_QAT_HW_SHA1_STATE1_SZ 20
#define ICP_QAT_HW_SHA224_STATE1_SZ 32
+#define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
#define ICP_QAT_HW_SHA256_STATE1_SZ 32
#define ICP_QAT_HW_SHA3_256_STATE1_SZ 32
#define ICP_QAT_HW_SHA384_STATE1_SZ 64
+#define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
#define ICP_QAT_HW_SHA512_STATE1_SZ 64
#define ICP_QAT_HW_SHA3_512_STATE1_SZ 64
-#define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
-#define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
#define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ 16
#define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ 16
#define ICP_QAT_HW_AES_F9_STATE1_SZ 32
@@ -121,17 +146,18 @@ struct icp_qat_hw_auth_setup {
#define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16
#define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8
#define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8
+
#define ICP_QAT_HW_NULL_STATE2_SZ 32
#define ICP_QAT_HW_MD5_STATE2_SZ 16
#define ICP_QAT_HW_SHA1_STATE2_SZ 20
#define ICP_QAT_HW_SHA224_STATE2_SZ 32
+#define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
#define ICP_QAT_HW_SHA256_STATE2_SZ 32
#define ICP_QAT_HW_SHA3_256_STATE2_SZ 0
#define ICP_QAT_HW_SHA384_STATE2_SZ 64
+#define ICP_QAT_HW_SHA3_384_STATE2_SZ 0
#define ICP_QAT_HW_SHA512_STATE2_SZ 64
#define ICP_QAT_HW_SHA3_512_STATE2_SZ 0
-#define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
-#define ICP_QAT_HW_SHA3_384_STATE2_SZ 0
#define ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ 48
#define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16
#define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16
@@ -154,6 +180,12 @@ struct icp_qat_hw_auth_sha512 {
uint8_t state2[ICP_QAT_HW_SHA512_STATE2_SZ];
};
+struct icp_qat_hw_auth_sha3_512 {
+ struct icp_qat_hw_auth_setup inner_setup;
+ uint8_t state1[ICP_QAT_HW_SHA3_512_STATE1_SZ];
+ struct icp_qat_hw_auth_setup outer_setup;
+};
+
struct icp_qat_hw_auth_algo_blk {
struct icp_qat_hw_auth_sha512 sha;
};
@@ -283,4 +315,72 @@ struct icp_qat_hw_cipher_algo_blk {
uint8_t key[ICP_QAT_HW_CIPHER_MAX_KEY_SZ];
} __rte_cache_aligned;
+/* ========================================================================= */
+/* COMPRESSION SLICE */
+/* ========================================================================= */
+
+enum icp_qat_hw_compression_direction {
+ ICP_QAT_HW_COMPRESSION_DIR_COMPRESS = 0,
+ ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS = 1,
+ ICP_QAT_HW_COMPRESSION_DIR_DELIMITER = 2
+};
+
+enum icp_qat_hw_compression_delayed_match {
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED = 0,
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_ENABLED = 1,
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DELIMITER = 2
+};
+
+enum icp_qat_hw_compression_algo {
+ ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE = 0,
+ ICP_QAT_HW_COMPRESSION_ALGO_LZS = 1,
+ ICP_QAT_HW_COMPRESSION_ALGO_DELIMITER = 2
+};
+
+
+enum icp_qat_hw_compression_depth {
+ ICP_QAT_HW_COMPRESSION_DEPTH_1 = 0,
+ ICP_QAT_HW_COMPRESSION_DEPTH_4 = 1,
+ ICP_QAT_HW_COMPRESSION_DEPTH_8 = 2,
+ ICP_QAT_HW_COMPRESSION_DEPTH_16 = 3,
+ ICP_QAT_HW_COMPRESSION_DEPTH_DELIMITER = 4
+};
+
+enum icp_qat_hw_compression_file_type {
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_0 = 0,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_1 = 1,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_2 = 2,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_3 = 3,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_4 = 4,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_DELIMITER = 5
+};
+
+struct icp_qat_hw_compression_config {
+ uint32_t val;
+ uint32_t reserved;
+};
+
+#define QAT_COMPRESSION_DIR_BITPOS 4
+#define QAT_COMPRESSION_DIR_MASK 0x7
+#define QAT_COMPRESSION_DELAYED_MATCH_BITPOS 16
+#define QAT_COMPRESSION_DELAYED_MATCH_MASK 0x1
+#define QAT_COMPRESSION_ALGO_BITPOS 31
+#define QAT_COMPRESSION_ALGO_MASK 0x1
+#define QAT_COMPRESSION_DEPTH_BITPOS 28
+#define QAT_COMPRESSION_DEPTH_MASK 0x7
+#define QAT_COMPRESSION_FILE_TYPE_BITPOS 24
+#define QAT_COMPRESSION_FILE_TYPE_MASK 0xF
+
+#define ICP_QAT_HW_COMPRESSION_CONFIG_BUILD( \
+ dir, delayed, algo, depth, filetype) \
+ ((((dir) & QAT_COMPRESSION_DIR_MASK) << QAT_COMPRESSION_DIR_BITPOS) | \
+ (((delayed) & QAT_COMPRESSION_DELAYED_MATCH_MASK) \
+ << QAT_COMPRESSION_DELAYED_MATCH_BITPOS) | \
+ (((algo) & QAT_COMPRESSION_ALGO_MASK) \
+ << QAT_COMPRESSION_ALGO_BITPOS) | \
+ (((depth) & QAT_COMPRESSION_DEPTH_MASK) \
+ << QAT_COMPRESSION_DEPTH_BITPOS) | \
+ (((filetype) & QAT_COMPRESSION_FILE_TYPE_MASK) \
+ << QAT_COMPRESSION_FILE_TYPE_BITPOS))
+
#endif
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v5 02/16] compress/qat: add makefiles for PMD
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 " Fiona Trahe
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 " Fiona Trahe
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 01/16] common/qat: updated firmware headers Fiona Trahe
@ 2018-07-11 11:56 ` Fiona Trahe
2018-07-12 12:41 ` De Lara Guarch, Pablo
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 03/16] compress/qat: add meson build Fiona Trahe
` (13 subsequent siblings)
16 siblings, 1 reply; 106+ messages in thread
From: Fiona Trahe @ 2018-07-11 11:56 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add Makefiles, directory and empty source files for compression PMD.
Handle cases for building either symmetric crypto PMD
or compression PMD or both and the common files both depend on.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
MAINTAINERS | 4 +++
config/common_base | 3 +-
drivers/common/qat/Makefile | 60 +++++++++++++++++++++++--------------
drivers/compress/qat/qat_comp.c | 5 ++++
drivers/compress/qat/qat_comp.h | 14 +++++++++
drivers/compress/qat/qat_comp_pmd.c | 5 ++++
drivers/compress/qat/qat_comp_pmd.h | 15 ++++++++++
test/test/test_cryptodev.c | 6 ++--
8 files changed, 86 insertions(+), 26 deletions(-)
create mode 100644 drivers/compress/qat/qat_comp.c
create mode 100644 drivers/compress/qat/qat_comp.h
create mode 100644 drivers/compress/qat/qat_comp_pmd.c
create mode 100644 drivers/compress/qat/qat_comp_pmd.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 8050b5d..50b2dff 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -852,6 +852,10 @@ F: drivers/compress/isal/
F: doc/guides/compressdevs/isal.rst
F: doc/guides/compressdevs/features/isal.ini
+Intel QuickAssist
+M: Fiona Trahe <fiona.trahe@intel.com>
+F: drivers/compress/qat/
+F: drivers/common/qat/
Eventdev Drivers
----------------
diff --git a/config/common_base b/config/common_base
index e4241db..1e340b4 100644
--- a/config/common_base
+++ b/config/common_base
@@ -480,7 +480,8 @@ CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4
#
# Compile PMD for QuickAssist based devices
#
-CONFIG_RTE_LIBRTE_PMD_QAT=n
+CONFIG_RTE_LIBRTE_PMD_QAT=y
+CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
#
# Max. number of QuickAssist devices, which can be detected and attached
#
diff --git a/drivers/common/qat/Makefile b/drivers/common/qat/Makefile
index 02e83f9..2a4c99b 100644
--- a/drivers/common/qat/Makefile
+++ b/drivers/common/qat/Makefile
@@ -3,48 +3,64 @@
include $(RTE_SDK)/mk/rte.vars.mk
-# library name
-LIB = librte_pmd_qat.a
-
-# library version
-LIBABIVER := 1
-
-# build flags
-CFLAGS += $(WERROR_FLAGS)
-CFLAGS += -O3
-
# build directories
QAT_CRYPTO_DIR := $(RTE_SDK)/drivers/crypto/qat
-VPATH=$(QAT_CRYPTO_DIR)
+QAT_COMPRESS_DIR := $(RTE_SDK)/drivers/compress/qat
+VPATH=$(QAT_CRYPTO_DIR):$(QAT_COMPRESS_DIR)
# external library include paths
CFLAGS += -I$(SRCDIR)/qat_adf
CFLAGS += -I$(SRCDIR)
CFLAGS += -I$(QAT_CRYPTO_DIR)
+CFLAGS += -I$(QAT_COMPRESS_DIR)
-# library common source files
-SRCS-y += qat_device.c
-SRCS-y += qat_common.c
-SRCS-y += qat_logs.c
-SRCS-y += qat_qp.c
+
+ifeq ($(CONFIG_RTE_LIBRTE_COMPRESSDEV),y)
+ CFLAGS += -DALLOW_EXPERIMENTAL_API
+ LDLIBS += -lrte_compressdev
+ SRCS-y += qat_comp.c
+ SRCS-y += qat_comp_pmd.c
+ build_qat = yes
+endif
# library symmetric crypto source files
ifeq ($(CONFIG_RTE_LIBRTE_CRYPTODEV),y)
+ifeq ($(CONFIG_RTE_LIBRTE_PMD_QAT_SYM),y)
LDLIBS += -lrte_cryptodev
LDLIBS += -lcrypto
CFLAGS += -DBUILD_QAT_SYM
SRCS-y += qat_sym.c
SRCS-y += qat_sym_session.c
SRCS-y += qat_sym_pmd.c
+ build_qat = yes
+endif
endif
-LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool
-LDLIBS += -lrte_pci -lrte_bus_pci
+ifdef build_qat
-# export include files
-SYMLINK-y-include +=
+ # library name
+ LIB = librte_pmd_qat.a
-# versioning export map
-EXPORT_MAP := ../../crypto/qat/rte_pmd_qat_version.map
+ # library version
+ LIBABIVER := 1
+ # build flags
+ CFLAGS += $(WERROR_FLAGS)
+ CFLAGS += -O3
+
+ # library common source files
+ SRCS-y += qat_device.c
+ SRCS-y += qat_common.c
+ SRCS-y += qat_logs.c
+ SRCS-y += qat_qp.c
+
+ LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool
+ LDLIBS += -lrte_pci -lrte_bus_pci
+
+ # export include files
+ SYMLINK-y-include +=
+
+ # versioning export map
+ EXPORT_MAP := ../../crypto/qat/rte_pmd_qat_version.map
+endif
include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
new file mode 100644
index 0000000..caa1158
--- /dev/null
+++ b/drivers/compress/qat/qat_comp.c
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Intel Corporation
+ */
+
+#include "qat_comp.h"
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
new file mode 100644
index 0000000..89c475e
--- /dev/null
+++ b/drivers/compress/qat/qat_comp.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+
+#ifndef _QAT_COMP_H_
+#define _QAT_COMP_H_
+
+#ifdef RTE_LIBRTE_COMPRESSDEV
+
+#include <rte_compressdev.h>
+#include <rte_compressdev_pmd.h>
+
+#endif
+#endif
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
new file mode 100644
index 0000000..fb035d1
--- /dev/null
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+
+#include "qat_comp_pmd.h"
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
new file mode 100644
index 0000000..9b5b543
--- /dev/null
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+
+#ifndef _QAT_COMP_PMD_H_
+#define _QAT_COMP_PMD_H_
+
+#ifdef RTE_LIBRTE_COMPRESSDEV
+
+#include <rte_compressdev.h>
+#include <rte_compressdev_pmd.h>
+
+
+#endif
+#endif /* _QAT_COMP_PMD_H_ */
diff --git a/test/test/test_cryptodev.c b/test/test/test_cryptodev.c
index b759e08..cbbdb15 100644
--- a/test/test/test_cryptodev.c
+++ b/test/test/test_cryptodev.c
@@ -9938,9 +9938,9 @@ test_cryptodev_qat(void /*argv __rte_unused, int argc __rte_unused*/)
RTE_STR(CRYPTODEV_NAME_QAT_SYM_PMD));
if (gbl_driver_id == -1) {
- RTE_LOG(ERR, USER1, "QAT PMD must be loaded. Check if "
- "CONFIG_RTE_LIBRTE_PMD_QAT is enabled "
- "in config file to run this testsuite.\n");
+ RTE_LOG(ERR, USER1, "QAT PMD must be loaded. Check that both "
+ "CONFIG_RTE_LIBRTE_PMD_QAT and CONFIG_RTE_LIBRTE_PMD_QAT_SYM "
+ "are enabled in config file to run this testsuite.\n");
return TEST_SKIPPED;
}
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v5 03/16] compress/qat: add meson build
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 " Fiona Trahe
` (2 preceding siblings ...)
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 02/16] compress/qat: add makefiles for PMD Fiona Trahe
@ 2018-07-11 11:56 ` Fiona Trahe
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 04/16] compress/qat: add xform processing Fiona Trahe
` (12 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-11 11:56 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add meson build files.
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
drivers/common/qat/Makefile | 2 +-
drivers/compress/meson.build | 2 +-
drivers/compress/qat/meson.build | 18 ++++++++++++++++++
drivers/compress/qat/rte_pmd_qat_version.map | 3 +++
drivers/crypto/qat/meson.build | 10 ++--------
drivers/crypto/qat/rte_pmd_qat_version.map | 3 ---
6 files changed, 25 insertions(+), 13 deletions(-)
create mode 100644 drivers/compress/qat/meson.build
create mode 100644 drivers/compress/qat/rte_pmd_qat_version.map
delete mode 100644 drivers/crypto/qat/rte_pmd_qat_version.map
diff --git a/drivers/common/qat/Makefile b/drivers/common/qat/Makefile
index 2a4c99b..c68a032 100644
--- a/drivers/common/qat/Makefile
+++ b/drivers/common/qat/Makefile
@@ -60,7 +60,7 @@ ifdef build_qat
SYMLINK-y-include +=
# versioning export map
- EXPORT_MAP := ../../crypto/qat/rte_pmd_qat_version.map
+ EXPORT_MAP := ../../compress/qat/rte_pmd_qat_version.map
endif
include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/compress/meson.build b/drivers/compress/meson.build
index fb136e1..2352ad5 100644
--- a/drivers/compress/meson.build
+++ b/drivers/compress/meson.build
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2018 Intel Corporation
-drivers = ['isal']
+drivers = ['isal', 'qat']
std_deps = ['compressdev'] # compressdev pulls in all other needed deps
config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'
diff --git a/drivers/compress/qat/meson.build b/drivers/compress/qat/meson.build
new file mode 100644
index 0000000..9d15076
--- /dev/null
+++ b/drivers/compress/qat/meson.build
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2017-2018 Intel Corporation
+
+
+# Add our sources files to the list
+allow_experimental_apis = true
+qat_sources += files('qat_comp_pmd.c',
+ 'qat_comp.c')
+qat_includes += include_directories('.')
+qat_deps += 'compressdev'
+qat_ext_deps += dep
+
+# build the whole driver
+sources += qat_sources
+cflags += qat_cflags
+deps += qat_deps
+ext_deps += qat_ext_deps
+includes += qat_includes
diff --git a/drivers/compress/qat/rte_pmd_qat_version.map b/drivers/compress/qat/rte_pmd_qat_version.map
new file mode 100644
index 0000000..ad6e191
--- /dev/null
+++ b/drivers/compress/qat/rte_pmd_qat_version.map
@@ -0,0 +1,3 @@
+DPDK_18.08 {
+ local: *;
+};
diff --git a/drivers/crypto/qat/meson.build b/drivers/crypto/qat/meson.build
index 2873637..d7cff68 100644
--- a/drivers/crypto/qat/meson.build
+++ b/drivers/crypto/qat/meson.build
@@ -1,6 +1,8 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017-2018 Intel Corporation
+# this does not build the QAT driver, instead that is done in the compression
+# driver which comes later. Here we just add our sources files to the list
build = false
dep = dependency('libcrypto', required: false)
if dep.found()
@@ -13,12 +15,4 @@ if dep.found()
qat_ext_deps += dep
pkgconfig_extra_libs += '-lcrypto'
qat_cflags += '-DBUILD_QAT_SYM'
-
- # build the whole driver
- sources += qat_sources
- cflags += qat_cflags
- deps += qat_deps
- ext_deps += qat_ext_deps
- includes += qat_includes
- build = true
endif
diff --git a/drivers/crypto/qat/rte_pmd_qat_version.map b/drivers/crypto/qat/rte_pmd_qat_version.map
deleted file mode 100644
index bbaf1c8..0000000
--- a/drivers/crypto/qat/rte_pmd_qat_version.map
+++ /dev/null
@@ -1,3 +0,0 @@
-DPDK_2.2 {
- local: *;
-};
\ No newline at end of file
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v5 04/16] compress/qat: add xform processing
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 " Fiona Trahe
` (3 preceding siblings ...)
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 03/16] compress/qat: add meson build Fiona Trahe
@ 2018-07-11 11:56 ` Fiona Trahe
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 05/16] compress/qat: create fw request and process response Fiona Trahe
` (11 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-11 11:56 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add code to process compressdev rte_comp_xforms, creating
private qat_comp_xforms with prepared firmware message templates.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp.c | 239 ++++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp.h | 30 +++++
drivers/compress/qat/qat_comp_pmd.h | 16 +++
3 files changed, 285 insertions(+)
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index caa1158..cb2005a 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -2,4 +2,243 @@
* Copyright(c) 2018 Intel Corporation
*/
+
+#include <rte_mempool.h>
+#include <rte_mbuf.h>
+#include <rte_hexdump.h>
+#include <rte_comp.h>
+#include <rte_bus_pci.h>
+#include <rte_byteorder.h>
+#include <rte_memcpy.h>
+#include <rte_common.h>
+#include <rte_spinlock.h>
+#include <rte_log.h>
+#include <rte_malloc.h>
+
+#include "qat_logs.h"
#include "qat_comp.h"
+#include "qat_comp_pmd.h"
+
+unsigned int
+qat_comp_xform_size(void)
+{
+ return RTE_ALIGN_CEIL(sizeof(struct qat_comp_xform), 8);
+}
+
+static void qat_comp_create_req_hdr(struct icp_qat_fw_comn_req_hdr *header,
+ enum qat_comp_request_type request)
+{
+ if (request == QAT_COMP_REQUEST_FIXED_COMP_STATELESS)
+ header->service_cmd_id = ICP_QAT_FW_COMP_CMD_STATIC;
+ else if (request == QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS)
+ header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DYNAMIC;
+ else if (request == QAT_COMP_REQUEST_DECOMPRESS)
+ header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DECOMPRESS;
+
+ header->service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_COMP;
+ header->hdr_flags =
+ ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
+
+ header->comn_req_flags = ICP_QAT_FW_COMN_FLAGS_BUILD(
+ QAT_COMN_CD_FLD_TYPE_16BYTE_DATA, QAT_COMN_PTR_TYPE_FLAT);
+}
+
+static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,
+ const struct rte_memzone *interm_buff_mz __rte_unused,
+ const struct rte_comp_xform *xform)
+{
+ struct icp_qat_fw_comp_req *comp_req;
+ int comp_level, algo;
+ uint32_t req_par_flags;
+ int direction = ICP_QAT_HW_COMPRESSION_DIR_COMPRESS;
+
+ if (unlikely(qat_xform == NULL)) {
+ QAT_LOG(ERR, "Session was not created for this device");
+ return -EINVAL;
+ }
+
+ if (qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS) {
+ direction = ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS;
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_1;
+ req_par_flags = ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(
+ ICP_QAT_FW_COMP_SOP, ICP_QAT_FW_COMP_EOP,
+ ICP_QAT_FW_COMP_BFINAL, ICP_QAT_FW_COMP_NO_CNV,
+ ICP_QAT_FW_COMP_NO_CNV_RECOVERY);
+
+ } else {
+ if (xform->compress.level == RTE_COMP_LEVEL_PMD_DEFAULT)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_8;
+ else if (xform->compress.level == 1)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_1;
+ else if (xform->compress.level == 2)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_4;
+ else if (xform->compress.level == 3)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_8;
+ else if (xform->compress.level >= 4 &&
+ xform->compress.level <= 9)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_16;
+ else {
+ QAT_LOG(ERR, "compression level not supported");
+ return -EINVAL;
+ }
+ req_par_flags = ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(
+ ICP_QAT_FW_COMP_SOP, ICP_QAT_FW_COMP_EOP,
+ ICP_QAT_FW_COMP_BFINAL, ICP_QAT_FW_COMP_CNV,
+ ICP_QAT_FW_COMP_CNV_RECOVERY);
+ }
+
+ switch (xform->compress.algo) {
+ case RTE_COMP_ALGO_DEFLATE:
+ algo = ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE;
+ break;
+ case RTE_COMP_ALGO_LZS:
+ default:
+ /* RTE_COMP_NULL */
+ QAT_LOG(ERR, "compression algorithm not supported");
+ return -EINVAL;
+ }
+
+ comp_req = &qat_xform->qat_comp_req_tmpl;
+
+ /* Initialize header */
+ qat_comp_create_req_hdr(&comp_req->comn_hdr,
+ qat_xform->qat_comp_request_type);
+
+ comp_req->comn_hdr.serv_specif_flags = ICP_QAT_FW_COMP_FLAGS_BUILD(
+ ICP_QAT_FW_COMP_STATELESS_SESSION,
+ ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST,
+ ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST,
+ ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST,
+ ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_USED_AS_INTMD_BUF);
+
+ comp_req->cd_pars.sl.comp_slice_cfg_word[0] =
+ ICP_QAT_HW_COMPRESSION_CONFIG_BUILD(
+ direction,
+ /* In CPM 1.6 only valid mode ! */
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_ENABLED, algo,
+ /* Translate level to depth */
+ comp_level, ICP_QAT_HW_COMPRESSION_FILE_TYPE_0);
+
+ comp_req->comp_pars.initial_adler = 1;
+ comp_req->comp_pars.initial_crc32 = 0;
+ comp_req->comp_pars.req_par_flags = req_par_flags;
+
+
+ if (qat_xform->qat_comp_request_type ==
+ QAT_COMP_REQUEST_FIXED_COMP_STATELESS ||
+ qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS) {
+ ICP_QAT_FW_COMN_NEXT_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_DRAM_WR);
+ ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_COMP);
+ } else if (qat_xform->qat_comp_request_type ==
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {
+
+ QAT_LOG(ERR, "Dynamic huffman encoding not supported");
+ return -EINVAL;
+ }
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_HEXDUMP_LOG(DEBUG, "qat compression message template:", comp_req,
+ sizeof(struct icp_qat_fw_comp_req));
+#endif
+ return 0;
+}
+
+/**
+ * Create driver private_xform data.
+ *
+ * @param dev
+ * Compressdev device
+ * @param xform
+ * xform data from application
+ * @param private_xform
+ * ptr where handle of pmd's private_xform data should be stored
+ * @return
+ * - if successful returns 0
+ * and valid private_xform handle
+ * - <0 in error cases
+ * - Returns -EINVAL if input parameters are invalid.
+ * - Returns -ENOTSUP if comp device does not support the comp transform.
+ * - Returns -ENOMEM if the private_xform could not be allocated.
+ */
+int
+qat_comp_private_xform_create(struct rte_compressdev *dev,
+ const struct rte_comp_xform *xform,
+ void **private_xform)
+{
+ struct qat_comp_dev_private *qat = dev->data->dev_private;
+
+ if (unlikely(private_xform == NULL)) {
+ QAT_LOG(ERR, "QAT: private_xform parameter is NULL");
+ return -EINVAL;
+ }
+ if (unlikely(qat->xformpool == NULL)) {
+ QAT_LOG(ERR, "QAT device has no private_xform mempool");
+ return -ENOMEM;
+ }
+ if (rte_mempool_get(qat->xformpool, private_xform)) {
+ QAT_LOG(ERR, "Couldn't get object from qat xform mempool");
+ return -ENOMEM;
+ }
+
+ struct qat_comp_xform *qat_xform =
+ (struct qat_comp_xform *)*private_xform;
+
+ if (xform->type == RTE_COMP_COMPRESS) {
+ if (xform->compress.deflate.huffman ==
+ RTE_COMP_HUFFMAN_DYNAMIC) {
+ QAT_LOG(ERR,
+ "QAT device doesn't support dynamic compression");
+ return -ENOTSUP;
+ }
+
+ if (xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_FIXED ||
+ ((xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_DEFAULT)
+ && qat->interm_buff_mz == NULL))
+
+ qat_xform->qat_comp_request_type =
+ QAT_COMP_REQUEST_FIXED_COMP_STATELESS;
+
+
+ } else {
+ qat_xform->qat_comp_request_type = QAT_COMP_REQUEST_DECOMPRESS;
+ }
+
+ qat_xform->checksum_type = xform->compress.chksum;
+
+ if (qat_comp_create_templates(qat_xform, qat->interm_buff_mz, xform)) {
+ QAT_LOG(ERR, "QAT: Problem with setting compression");
+ return -EINVAL;
+ }
+ return 0;
+}
+
+/**
+ * Free driver private_xform data.
+ *
+ * @param dev
+ * Compressdev device
+ * @param private_xform
+ * handle of pmd's private_xform data
+ * @return
+ * - 0 if successful
+ * - <0 in error cases
+ * - Returns -EINVAL if input parameters are invalid.
+ */
+int
+qat_comp_private_xform_free(struct rte_compressdev *dev __rte_unused,
+ void *private_xform)
+{
+ struct qat_comp_xform *qat_xform =
+ (struct qat_comp_xform *)private_xform;
+
+ if (qat_xform) {
+ memset(qat_xform, 0, qat_comp_xform_size());
+ struct rte_mempool *mp = rte_mempool_from_obj(qat_xform);
+
+ rte_mempool_put(mp, qat_xform);
+ return 0;
+ }
+ return -EINVAL;
+}
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 89c475e..0f58a76 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -10,5 +10,35 @@
#include <rte_compressdev.h>
#include <rte_compressdev_pmd.h>
+#include "icp_qat_hw.h"
+#include "icp_qat_fw_comp.h"
+#include "icp_qat_fw_la.h"
+
+enum qat_comp_request_type {
+ QAT_COMP_REQUEST_FIXED_COMP_STATELESS,
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS,
+ QAT_COMP_REQUEST_DECOMPRESS,
+ REQ_COMP_END
+};
+
+
+struct qat_comp_xform {
+ struct icp_qat_fw_comp_req qat_comp_req_tmpl;
+ enum qat_comp_request_type qat_comp_request_type;
+ enum rte_comp_checksum_type checksum_type;
+};
+
+
+int
+qat_comp_private_xform_create(struct rte_compressdev *dev,
+ const struct rte_comp_xform *xform,
+ void **private_xform);
+
+int
+qat_comp_private_xform_free(struct rte_compressdev *dev, void *private_xform);
+
+unsigned int
+qat_comp_xform_size(void);
+
#endif
#endif
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 9b5b543..fd97cbf 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -11,5 +11,21 @@
#include <rte_compressdev_pmd.h>
+/** private data structure for a QAT compression device.
+ * This QAT device is a device offering only a compression service,
+ * there can be one of these on each qat_pci_device (VF).
+ */
+struct qat_comp_dev_private {
+ struct qat_pci_device *qat_dev;
+ /**< The qat pci device hosting the service */
+ struct rte_compressdev *compressdev;
+ /**< The pointer to this compression device structure */
+ const struct rte_memzone *interm_buff_mz;
+ /**< The device's memory for intermediate buffers */
+ struct rte_mempool *xformpool;
+ /**< The device's pool for qat_comp_xforms */
+
+};
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v5 05/16] compress/qat: create fw request and process response
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 " Fiona Trahe
` (4 preceding siblings ...)
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 04/16] compress/qat: add xform processing Fiona Trahe
@ 2018-07-11 11:56 ` Fiona Trahe
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 06/16] compress/qat: check that correct firmware is in use Fiona Trahe
` (10 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-11 11:56 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add functions to create the request message to send to
firmware and to process the firmware response.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp.c | 101 ++++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp.h | 8 +++
drivers/compress/qat/qat_comp_pmd.h | 1 +
3 files changed, 110 insertions(+)
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index cb2005a..a32d6ef 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -19,6 +19,107 @@
#include "qat_comp.h"
#include "qat_comp_pmd.h"
+
+int
+qat_comp_build_request(void *in_op, uint8_t *out_msg,
+ void *op_cookie __rte_unused,
+ enum qat_device_gen qat_dev_gen __rte_unused)
+{
+ struct rte_comp_op *op = in_op;
+ struct qat_comp_xform *qat_xform = op->private_xform;
+ const uint8_t *tmpl = (uint8_t *)&qat_xform->qat_comp_req_tmpl;
+ struct icp_qat_fw_comp_req *comp_req =
+ (struct icp_qat_fw_comp_req *)out_msg;
+
+ if (unlikely(op->op_type != RTE_COMP_OP_STATELESS)) {
+ QAT_DP_LOG(ERR, "QAT PMD only supports stateless compression "
+ "operation requests, op (%p) is not a "
+ "stateless operation.", op);
+ return -EINVAL;
+ }
+
+ rte_mov128(out_msg, tmpl);
+ comp_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
+
+ /* common for sgl and flat buffers */
+ comp_req->comp_pars.comp_len = op->src.length;
+ comp_req->comp_pars.out_buffer_sz = rte_pktmbuf_pkt_len(op->m_dst);
+
+ /* sgl */
+ if (op->m_src->next != NULL || op->m_dst->next != NULL) {
+ QAT_DP_LOG(ERR, "QAT PMD doesn't support scatter gather");
+ return -EINVAL;
+
+ } else {
+ ICP_QAT_FW_COMN_PTR_TYPE_SET(comp_req->comn_hdr.comn_req_flags,
+ QAT_COMN_PTR_TYPE_FLAT);
+ comp_req->comn_mid.src_length = rte_pktmbuf_data_len(op->m_src);
+ comp_req->comn_mid.dst_length = rte_pktmbuf_data_len(op->m_dst);
+
+ comp_req->comn_mid.src_data_addr =
+ rte_pktmbuf_mtophys_offset(op->m_src, op->src.offset);
+ comp_req->comn_mid.dest_data_addr =
+ rte_pktmbuf_mtophys_offset(op->m_dst, op->dst.offset);
+ }
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_LOG(DEBUG, "Direction: %s",
+ qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS ?
+ "decompression" : "compression");
+ QAT_DP_HEXDUMP_LOG(DEBUG, "qat compression message:", comp_req,
+ sizeof(struct icp_qat_fw_comp_req));
+#endif
+ return 0;
+}
+
+int
+qat_comp_process_response(void **op, uint8_t *resp)
+{
+ struct icp_qat_fw_comp_resp *resp_msg =
+ (struct icp_qat_fw_comp_resp *)resp;
+ struct rte_comp_op *rx_op = (struct rte_comp_op *)(uintptr_t)
+ (resp_msg->opaque_data);
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_LOG(DEBUG, "Direction: %s",
+ qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS ?
+ "decompression" : "compression");
+ QAT_DP_HEXDUMP_LOG(DEBUG, "qat_response:", (uint8_t *)resp_msg,
+ sizeof(struct icp_qat_fw_comp_resp));
+#endif
+
+ if ((ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(resp_msg->comn_resp.comn_status)
+ | ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(
+ resp_msg->comn_resp.comn_status)) !=
+ ICP_QAT_FW_COMN_STATUS_FLAG_OK) {
+
+ rx_op->status = RTE_COMP_OP_STATUS_ERROR;
+ rx_op->debug_status =
+ *((uint16_t *)(&resp_msg->comn_resp.comn_error));
+ } else {
+ struct qat_comp_xform *qat_xform = rx_op->private_xform;
+ struct icp_qat_fw_resp_comp_pars *comp_resp =
+ (struct icp_qat_fw_resp_comp_pars *)&resp_msg->comp_resp_pars;
+
+ rx_op->status = RTE_COMP_OP_STATUS_SUCCESS;
+ rx_op->consumed = comp_resp->input_byte_counter;
+ rx_op->produced = comp_resp->output_byte_counter;
+
+ if (qat_xform->checksum_type != RTE_COMP_CHECKSUM_NONE) {
+ if (qat_xform->checksum_type == RTE_COMP_CHECKSUM_CRC32)
+ rx_op->output_chksum = comp_resp->curr_crc32;
+ else if (qat_xform->checksum_type ==
+ RTE_COMP_CHECKSUM_ADLER32)
+ rx_op->output_chksum = comp_resp->curr_adler_32;
+ else
+ rx_op->output_chksum = comp_resp->curr_chksum;
+ }
+ }
+ *op = (void *)rx_op;
+
+ return 0;
+}
+
unsigned int
qat_comp_xform_size(void)
{
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 0f58a76..46105b4 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -10,6 +10,7 @@
#include <rte_compressdev.h>
#include <rte_compressdev_pmd.h>
+#include "qat_common.h"
#include "icp_qat_hw.h"
#include "icp_qat_fw_comp.h"
#include "icp_qat_fw_la.h"
@@ -28,6 +29,13 @@ struct qat_comp_xform {
enum rte_comp_checksum_type checksum_type;
};
+int
+qat_comp_build_request(void *in_op, uint8_t *out_msg, void *op_cookie,
+ enum qat_device_gen qat_dev_gen __rte_unused);
+
+int
+qat_comp_process_response(void **op, uint8_t *resp);
+
int
qat_comp_private_xform_create(struct rte_compressdev *dev,
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index fd97cbf..cd04f11 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -10,6 +10,7 @@
#include <rte_compressdev.h>
#include <rte_compressdev_pmd.h>
+#include "qat_device.h"
/** private data structure for a QAT compression device.
* This QAT device is a device offering only a compression service,
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v5 06/16] compress/qat: check that correct firmware is in use
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 " Fiona Trahe
` (5 preceding siblings ...)
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 05/16] compress/qat: create fw request and process response Fiona Trahe
@ 2018-07-11 11:56 ` Fiona Trahe
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 07/16] compress/qat: add stats functions Fiona Trahe
` (9 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-11 11:56 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Check bit in response message to verify that correct firmware
is in use for compression. If not return an error.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp.c | 16 +++++++++++++++-
drivers/compress/qat/qat_comp.h | 2 ++
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index a32d6ef..e8019eb 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -2,7 +2,6 @@
* Copyright(c) 2018 Intel Corporation
*/
-
#include <rte_mempool.h>
#include <rte_mbuf.h>
#include <rte_hexdump.h>
@@ -79,6 +78,8 @@ qat_comp_process_response(void **op, uint8_t *resp)
(struct icp_qat_fw_comp_resp *)resp;
struct rte_comp_op *rx_op = (struct rte_comp_op *)(uintptr_t)
(resp_msg->opaque_data);
+ struct qat_comp_xform *qat_xform = (struct qat_comp_xform *)
+ (rx_op->private_xform);
#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
QAT_DP_LOG(DEBUG, "Direction: %s",
@@ -88,6 +89,19 @@ qat_comp_process_response(void **op, uint8_t *resp)
sizeof(struct icp_qat_fw_comp_resp));
#endif
+ if (likely(qat_xform->qat_comp_request_type
+ != QAT_COMP_REQUEST_DECOMPRESS)) {
+ if (unlikely(ICP_QAT_FW_COMN_HDR_CNV_FLAG_GET(
+ resp_msg->comn_resp.hdr_flags)
+ == ICP_QAT_FW_COMP_NO_CNV)) {
+ rx_op->status = RTE_COMP_OP_STATUS_ERROR;
+ rx_op->debug_status = ERR_CODE_QAT_COMP_WRONG_FW;
+ *op = (void *)rx_op;
+ QAT_DP_LOG(ERR, "QAT has wrong firmware");
+ return 0;
+ }
+ }
+
if ((ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(resp_msg->comn_resp.comn_status)
| ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(
resp_msg->comn_resp.comn_status)) !=
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 46105b4..937f3c8 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -15,6 +15,8 @@
#include "icp_qat_fw_comp.h"
#include "icp_qat_fw_la.h"
+#define ERR_CODE_QAT_COMP_WRONG_FW -99
+
enum qat_comp_request_type {
QAT_COMP_REQUEST_FIXED_COMP_STATELESS,
QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS,
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v5 07/16] compress/qat: add stats functions
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 " Fiona Trahe
` (6 preceding siblings ...)
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 06/16] compress/qat: check that correct firmware is in use Fiona Trahe
@ 2018-07-11 11:57 ` Fiona Trahe
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 08/16] compress/qat: setup queue-pairs for compression service Fiona Trahe
` (8 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-11 11:57 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add functions to get and clear compression queue-pair statistics.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 35 +++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 7 +++++++
2 files changed, 42 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index fb035d1..6feffb7 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -3,3 +3,38 @@
*/
#include "qat_comp_pmd.h"
+
+void
+qat_comp_stats_get(struct rte_compressdev *dev,
+ struct rte_compressdev_stats *stats)
+{
+ struct qat_common_stats qat_stats = {0};
+ struct qat_comp_dev_private *qat_priv;
+
+ if (stats == NULL || dev == NULL) {
+ QAT_LOG(ERR, "invalid ptr: stats %p, dev %p", stats, dev);
+ return;
+ }
+ qat_priv = dev->data->dev_private;
+
+ qat_stats_get(qat_priv->qat_dev, &qat_stats, QAT_SERVICE_COMPRESSION);
+ stats->enqueued_count = qat_stats.enqueued_count;
+ stats->dequeued_count = qat_stats.dequeued_count;
+ stats->enqueue_err_count = qat_stats.enqueue_err_count;
+ stats->dequeue_err_count = qat_stats.dequeue_err_count;
+}
+
+void
+qat_comp_stats_reset(struct rte_compressdev *dev)
+{
+ struct qat_comp_dev_private *qat_priv;
+
+ if (dev == NULL) {
+ QAT_LOG(ERR, "invalid compressdev ptr %p", dev);
+ return;
+ }
+ qat_priv = dev->data->dev_private;
+
+ qat_stats_reset(qat_priv->qat_dev, QAT_SERVICE_COMPRESSION);
+
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index cd04f11..27d84c8 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -28,5 +28,12 @@ struct qat_comp_dev_private {
};
+void
+qat_comp_stats_reset(struct rte_compressdev *dev);
+
+void
+qat_comp_stats_get(struct rte_compressdev *dev,
+ struct rte_compressdev_stats *stats);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v5 08/16] compress/qat: setup queue-pairs for compression service
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 " Fiona Trahe
` (7 preceding siblings ...)
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 07/16] compress/qat: add stats functions Fiona Trahe
@ 2018-07-11 11:57 ` Fiona Trahe
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 09/16] compress/qat: add fns to configure and clear device Fiona Trahe
` (7 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-11 11:57 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Setup and clear queue-pairs for handling compression
requests and responses.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp.h | 2 ++
drivers/compress/qat/qat_comp_pmd.c | 61 +++++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 6 ++++
3 files changed, 69 insertions(+)
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 937f3c8..9e6861b 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -24,6 +24,8 @@ enum qat_comp_request_type {
REQ_COMP_END
};
+struct qat_comp_op_cookie {
+};
struct qat_comp_xform {
struct icp_qat_fw_comp_req qat_comp_req_tmpl;
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 6feffb7..5ae6caf 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -2,6 +2,7 @@
* Copyright(c) 2015-2018 Intel Corporation
*/
+#include "qat_comp.h"
#include "qat_comp_pmd.h"
void
@@ -38,3 +39,63 @@ qat_comp_stats_reset(struct rte_compressdev *dev)
qat_stats_reset(qat_priv->qat_dev, QAT_SERVICE_COMPRESSION);
}
+
+int
+qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)
+{
+ struct qat_comp_dev_private *qat_private = dev->data->dev_private;
+
+ QAT_LOG(DEBUG, "Release comp qp %u on device %d",
+ queue_pair_id, dev->data->dev_id);
+
+ qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][queue_pair_id]
+ = NULL;
+
+ return qat_qp_release((struct qat_qp **)
+ &(dev->data->queue_pairs[queue_pair_id]));
+}
+
+int
+qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
+ uint32_t max_inflight_ops, int socket_id)
+{
+ int ret = 0;
+ struct qat_qp_config qat_qp_conf;
+
+ struct qat_qp **qp_addr =
+ (struct qat_qp **)&(dev->data->queue_pairs[qp_id]);
+ struct qat_comp_dev_private *qat_private = dev->data->dev_private;
+ const struct qat_qp_hw_data *comp_hw_qps =
+ qat_gen_config[qat_private->qat_dev->qat_dev_gen]
+ .qp_hw_data[QAT_SERVICE_COMPRESSION];
+ const struct qat_qp_hw_data *qp_hw_data = comp_hw_qps + qp_id;
+
+ /* If qp is already in use free ring memory and qp metadata. */
+ if (*qp_addr != NULL) {
+ ret = qat_comp_qp_release(dev, qp_id);
+ if (ret < 0)
+ return ret;
+ }
+ if (qp_id >= qat_qps_per_service(comp_hw_qps,
+ QAT_SERVICE_COMPRESSION)) {
+ QAT_LOG(ERR, "qp_id %u invalid for this device", qp_id);
+ return -EINVAL;
+ }
+
+ qat_qp_conf.hw = qp_hw_data;
+ qat_qp_conf.build_request = qat_comp_build_request;
+ qat_qp_conf.cookie_size = sizeof(struct qat_comp_op_cookie);
+ qat_qp_conf.nb_descriptors = max_inflight_ops;
+ qat_qp_conf.socket_id = socket_id;
+ qat_qp_conf.service_str = "comp";
+
+ ret = qat_qp_setup(qat_private->qat_dev, qp_addr, qp_id, &qat_qp_conf);
+ if (ret != 0)
+ return ret;
+
+ /* store a link to the qp in the qat_pci_device */
+ qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][qp_id]
+ = *qp_addr;
+
+ return ret;
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 27d84c8..5a4bc31 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -34,6 +34,12 @@ qat_comp_stats_reset(struct rte_compressdev *dev);
void
qat_comp_stats_get(struct rte_compressdev *dev,
struct rte_compressdev_stats *stats);
+int
+qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id);
+
+int
+qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
+ uint32_t max_inflight_ops, int socket_id);
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v5 09/16] compress/qat: add fns to configure and clear device
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 " Fiona Trahe
` (8 preceding siblings ...)
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 08/16] compress/qat: setup queue-pairs for compression service Fiona Trahe
@ 2018-07-11 11:57 ` Fiona Trahe
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 10/16] compress/qat: add fn to return device info Fiona Trahe
` (6 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-11 11:57 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add functions to configure and clear the qat comp device,
including the creation and freeing of the xform pool
and the freeing of queue-pairs.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 95 +++++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 7 +++
2 files changed, 102 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 5ae6caf..beab6e3 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -99,3 +99,98 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
return ret;
}
+
+static struct rte_mempool *
+qat_comp_create_xform_pool(struct qat_comp_dev_private *comp_dev,
+ uint32_t num_elements)
+{
+ char xform_pool_name[RTE_MEMPOOL_NAMESIZE];
+ struct rte_mempool *mp;
+
+ snprintf(xform_pool_name, RTE_MEMPOOL_NAMESIZE,
+ "%s_xforms", comp_dev->qat_dev->name);
+
+ QAT_LOG(DEBUG, "xformpool: %s", xform_pool_name);
+ mp = rte_mempool_lookup(xform_pool_name);
+
+ if (mp != NULL) {
+ QAT_LOG(DEBUG, "xformpool already created");
+ if (mp->size != num_elements) {
+ QAT_LOG(DEBUG, "xformpool wrong size - delete it");
+ rte_mempool_free(mp);
+ mp = NULL;
+ comp_dev->xformpool = NULL;
+ }
+ }
+
+ if (mp == NULL)
+ mp = rte_mempool_create(xform_pool_name,
+ num_elements,
+ qat_comp_xform_size(), 0, 0,
+ NULL, NULL, NULL, NULL, rte_socket_id(),
+ 0);
+ if (mp == NULL) {
+ QAT_LOG(ERR, "Err creating mempool %s w %d elements of size %d",
+ xform_pool_name, num_elements, qat_comp_xform_size());
+ return NULL;
+ }
+
+ return mp;
+}
+
+static void
+_qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)
+{
+ /* Free private_xform pool */
+ if (comp_dev->xformpool) {
+ /* Free internal mempool for private xforms */
+ rte_mempool_free(comp_dev->xformpool);
+ comp_dev->xformpool = NULL;
+ }
+}
+
+int
+qat_comp_dev_config(struct rte_compressdev *dev,
+ struct rte_compressdev_config *config)
+{
+ struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
+ int ret = 0;
+
+ if (config->max_nb_streams != 0) {
+ QAT_LOG(ERR,
+ "QAT device does not support STATEFUL so max_nb_streams must be 0");
+ return -EINVAL;
+ }
+
+ comp_dev->xformpool = qat_comp_create_xform_pool(comp_dev,
+ config->max_nb_priv_xforms);
+ if (comp_dev->xformpool == NULL) {
+
+ ret = -ENOMEM;
+ goto error_out;
+ }
+ return 0;
+
+error_out:
+ _qat_comp_dev_config_clear(comp_dev);
+ return ret;
+}
+
+
+int
+qat_comp_dev_close(struct rte_compressdev *dev)
+{
+ int i;
+ int ret = 0;
+ struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
+
+ for (i = 0; i < dev->data->nb_queue_pairs; i++) {
+ ret = qat_comp_qp_release(dev, i);
+ if (ret < 0)
+ return ret;
+ }
+
+ _qat_comp_dev_config_clear(comp_dev);
+
+ return ret;
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 5a4bc31..b10a66f 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -41,5 +41,12 @@ int
qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
uint32_t max_inflight_ops, int socket_id);
+int
+qat_comp_dev_config(struct rte_compressdev *dev,
+ struct rte_compressdev_config *config);
+
+int
+qat_comp_dev_close(struct rte_compressdev *dev);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v5 10/16] compress/qat: add fn to return device info
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 " Fiona Trahe
` (9 preceding siblings ...)
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 09/16] compress/qat: add fns to configure and clear device Fiona Trahe
@ 2018-07-11 11:57 ` Fiona Trahe
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 11/16] compress/qat: add enqueue/dequeue functions Fiona Trahe
` (5 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-11 11:57 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add capabilities pointer to internal qat comp device
and function to return this and other info.
C
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 19 +++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 6 ++++++
2 files changed, 25 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index beab6e3..482ebd1 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -194,3 +194,22 @@ qat_comp_dev_close(struct rte_compressdev *dev)
return ret;
}
+
+
+void
+qat_comp_dev_info_get(struct rte_compressdev *dev,
+ struct rte_compressdev_info *info)
+{
+ struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
+ const struct qat_qp_hw_data *comp_hw_qps =
+ qat_gen_config[comp_dev->qat_dev->qat_dev_gen]
+ .qp_hw_data[QAT_SERVICE_COMPRESSION];
+
+ if (info != NULL) {
+ info->max_nb_queue_pairs =
+ qat_qps_per_service(comp_hw_qps,
+ QAT_SERVICE_COMPRESSION);
+ info->feature_flags = dev->feature_flags;
+ info->capabilities = comp_dev->qat_dev_capabilities;
+ }
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index b10a66f..22576f4 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -21,6 +21,8 @@ struct qat_comp_dev_private {
/**< The qat pci device hosting the service */
struct rte_compressdev *compressdev;
/**< The pointer to this compression device structure */
+ const struct rte_compressdev_capabilities *qat_dev_capabilities;
+ /* QAT device compression capabilities */
const struct rte_memzone *interm_buff_mz;
/**< The device's memory for intermediate buffers */
struct rte_mempool *xformpool;
@@ -48,5 +50,9 @@ qat_comp_dev_config(struct rte_compressdev *dev,
int
qat_comp_dev_close(struct rte_compressdev *dev);
+void
+qat_comp_dev_info_get(struct rte_compressdev *dev,
+ struct rte_compressdev_info *info);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v5 11/16] compress/qat: add enqueue/dequeue functions
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 " Fiona Trahe
` (10 preceding siblings ...)
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 10/16] compress/qat: add fn to return device info Fiona Trahe
@ 2018-07-11 11:57 ` Fiona Trahe
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 12/16] compress/qat: add device start and stop fns Fiona Trahe
` (4 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-11 11:57 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Wrap generic qat enqueue/dequeue functions with
compressdev enqueue and dequeue fns.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 14 ++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 8 ++++++++
2 files changed, 22 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 482ebd1..086b6cf 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -213,3 +213,17 @@ qat_comp_dev_info_get(struct rte_compressdev *dev,
info->capabilities = comp_dev->qat_dev_capabilities;
}
}
+
+uint16_t
+qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops)
+{
+ return qat_enqueue_op_burst(qp, (void **)ops, nb_ops);
+}
+
+uint16_t
+qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops)
+{
+ return qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 22576f4..f360c29 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -54,5 +54,13 @@ void
qat_comp_dev_info_get(struct rte_compressdev *dev,
struct rte_compressdev_info *info);
+uint16_t
+qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops);
+
+uint16_t
+qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v5 12/16] compress/qat: add device start and stop fns
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 " Fiona Trahe
` (11 preceding siblings ...)
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 11/16] compress/qat: add enqueue/dequeue functions Fiona Trahe
@ 2018-07-11 11:57 ` Fiona Trahe
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 13/16] compress/qat: create and populate the ops structure Fiona Trahe
` (3 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-11 11:57 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
There are no specific actions needed to start/stop a QAT comp device
so these are just trivial fns to satisfy the pmd API.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 11 +++++++++++
drivers/compress/qat/qat_comp_pmd.h | 6 ++++++
2 files changed, 17 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 086b6cf..1ab5cf7 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -176,6 +176,17 @@ qat_comp_dev_config(struct rte_compressdev *dev,
return ret;
}
+int
+qat_comp_dev_start(struct rte_compressdev *dev __rte_unused)
+{
+ return 0;
+}
+
+void
+qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused)
+{
+
+}
int
qat_comp_dev_close(struct rte_compressdev *dev)
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index f360c29..22cbefb 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -62,5 +62,11 @@ uint16_t
qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops);
+int
+qat_comp_dev_start(struct rte_compressdev *dev __rte_unused);
+
+void
+qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v5 13/16] compress/qat: create and populate the ops structure
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 " Fiona Trahe
` (12 preceding siblings ...)
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 12/16] compress/qat: add device start and stop fns Fiona Trahe
@ 2018-07-11 11:57 ` Fiona Trahe
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 14/16] compress/qat: add fns to create and destroy the PMD Fiona Trahe
` (2 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-11 11:57 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Create an ops structure and populate it with the
qat-specific functions.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 38 ++++++++++++++++++++++++++++---------
drivers/compress/qat/qat_comp_pmd.h | 30 -----------------------------
2 files changed, 29 insertions(+), 39 deletions(-)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 1ab5cf7..013ff6e 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -5,7 +5,7 @@
#include "qat_comp.h"
#include "qat_comp_pmd.h"
-void
+static void
qat_comp_stats_get(struct rte_compressdev *dev,
struct rte_compressdev_stats *stats)
{
@@ -25,7 +25,7 @@ qat_comp_stats_get(struct rte_compressdev *dev,
stats->dequeue_err_count = qat_stats.dequeue_err_count;
}
-void
+static void
qat_comp_stats_reset(struct rte_compressdev *dev)
{
struct qat_comp_dev_private *qat_priv;
@@ -40,7 +40,7 @@ qat_comp_stats_reset(struct rte_compressdev *dev)
}
-int
+static int
qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)
{
struct qat_comp_dev_private *qat_private = dev->data->dev_private;
@@ -55,7 +55,7 @@ qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)
&(dev->data->queue_pairs[queue_pair_id]));
}
-int
+static int
qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
uint32_t max_inflight_ops, int socket_id)
{
@@ -149,7 +149,7 @@ _qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)
}
}
-int
+static int
qat_comp_dev_config(struct rte_compressdev *dev,
struct rte_compressdev_config *config)
{
@@ -176,19 +176,19 @@ qat_comp_dev_config(struct rte_compressdev *dev,
return ret;
}
-int
+static int
qat_comp_dev_start(struct rte_compressdev *dev __rte_unused)
{
return 0;
}
-void
+static void
qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused)
{
}
-int
+static int
qat_comp_dev_close(struct rte_compressdev *dev)
{
int i;
@@ -207,7 +207,7 @@ qat_comp_dev_close(struct rte_compressdev *dev)
}
-void
+static void
qat_comp_dev_info_get(struct rte_compressdev *dev,
struct rte_compressdev_info *info)
{
@@ -238,3 +238,23 @@ qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
{
return qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
}
+
+
+struct rte_compressdev_ops compress_qat_ops = {
+
+ /* Device related operations */
+ .dev_configure = qat_comp_dev_config,
+ .dev_start = qat_comp_dev_start,
+ .dev_stop = qat_comp_dev_stop,
+ .dev_close = qat_comp_dev_close,
+ .dev_infos_get = qat_comp_dev_info_get,
+
+ .stats_get = qat_comp_stats_get,
+ .stats_reset = qat_comp_stats_reset,
+ .queue_pair_setup = qat_comp_qp_setup,
+ .queue_pair_release = qat_comp_qp_release,
+
+ /* Compression related operations */
+ .private_xform_create = qat_comp_private_xform_create,
+ .private_xform_free = qat_comp_private_xform_free
+};
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 22cbefb..7ba1b8d 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -30,30 +30,6 @@ struct qat_comp_dev_private {
};
-void
-qat_comp_stats_reset(struct rte_compressdev *dev);
-
-void
-qat_comp_stats_get(struct rte_compressdev *dev,
- struct rte_compressdev_stats *stats);
-int
-qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id);
-
-int
-qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
- uint32_t max_inflight_ops, int socket_id);
-
-int
-qat_comp_dev_config(struct rte_compressdev *dev,
- struct rte_compressdev_config *config);
-
-int
-qat_comp_dev_close(struct rte_compressdev *dev);
-
-void
-qat_comp_dev_info_get(struct rte_compressdev *dev,
- struct rte_compressdev_info *info);
-
uint16_t
qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops);
@@ -62,11 +38,5 @@ uint16_t
qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops);
-int
-qat_comp_dev_start(struct rte_compressdev *dev __rte_unused);
-
-void
-qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused);
-
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v5 14/16] compress/qat: add fns to create and destroy the PMD
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 " Fiona Trahe
` (13 preceding siblings ...)
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 13/16] compress/qat: create and populate the ops structure Fiona Trahe
@ 2018-07-11 11:57 ` Fiona Trahe
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 15/16] compress/qat: prevent device usage if incorrect firmware Fiona Trahe
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 16/16] docs/qat: refactor docs adding compression guide Fiona Trahe
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-11 11:57 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Now that all the device operations are available,
add the functions to create and destroy the pmd.
Called on probe and remove of the qat pci device, these
register the device with the compressdev API
and plug in all the device functionality.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/common/qat/qat_device.h | 4 ++
drivers/common/qat/qat_qp.c | 11 ++++-
drivers/common/qat/qat_qp.h | 5 ++
drivers/compress/qat/qat_comp_pmd.c | 98 +++++++++++++++++++++++++++++++++++--
drivers/compress/qat/qat_comp_pmd.h | 11 ++---
5 files changed, 117 insertions(+), 12 deletions(-)
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index 0cb370c..9599fc5 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -25,6 +25,8 @@
* - runtime data
*/
struct qat_sym_dev_private;
+struct qat_comp_dev_private;
+
struct qat_pci_device {
/* Data used by all services */
@@ -55,6 +57,8 @@ struct qat_pci_device {
*/
/* Data relating to compression service */
+ struct qat_comp_dev_private *comp_dev;
+ /**< link back to compressdev private data */
/* Data relating to asymmetric crypto service */
diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c
index 32c1759..7ca7a45 100644
--- a/drivers/common/qat/qat_qp.c
+++ b/drivers/common/qat/qat_qp.c
@@ -15,6 +15,7 @@
#include "qat_device.h"
#include "qat_qp.h"
#include "qat_sym.h"
+#include "qat_comp.h"
#include "adf_transport_access_macros.h"
@@ -606,8 +607,8 @@ qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
if (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC)
qat_sym_process_response(ops, resp_msg);
- /* add qat_asym_process_response here */
- /* add qat_comp_process_response here */
+ else if (tmp_qp->service_type == QAT_SERVICE_COMPRESSION)
+ qat_comp_process_response(ops, resp_msg);
head = adf_modulo(head + rx_queue->msg_size,
rx_queue->modulo_mask);
@@ -633,3 +634,9 @@ qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
}
return resp_counter;
}
+
+__attribute__((weak)) int
+qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused)
+{
+ return 0;
+}
diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h
index 59db945..69f8a61 100644
--- a/drivers/common/qat/qat_qp.h
+++ b/drivers/common/qat/qat_qp.h
@@ -103,4 +103,9 @@ qat_qp_setup(struct qat_pci_device *qat_dev,
int
qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,
enum qat_service_type service);
+
+/* Needed for weak function*/
+int
+qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused);
+
#endif /* _QAT_QP_H_ */
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 013ff6e..9bb9897 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -5,6 +5,18 @@
#include "qat_comp.h"
#include "qat_comp_pmd.h"
+static const struct rte_compressdev_capabilities qat_comp_gen_capabilities[] = {
+ {/* COMPRESSION - deflate */
+ .algo = RTE_COMP_ALGO_DEFLATE,
+ .comp_feature_flags = RTE_COMP_FF_MULTI_PKT_CHECKSUM |
+ RTE_COMP_FF_CRC32_CHECKSUM |
+ RTE_COMP_FF_ADLER32_CHECKSUM |
+ RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
+ RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
+ RTE_COMP_FF_HUFFMAN_FIXED,
+ .window_size = {.min = 15, .max = 15, .increment = 0} },
+ {RTE_COMP_ALGO_LIST_END, 0, {0, 0, 0} } };
+
static void
qat_comp_stats_get(struct rte_compressdev *dev,
struct rte_compressdev_stats *stats)
@@ -225,14 +237,14 @@ qat_comp_dev_info_get(struct rte_compressdev *dev,
}
}
-uint16_t
+static uint16_t
qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops)
{
return qat_enqueue_op_burst(qp, (void **)ops, nb_ops);
}
-uint16_t
+static uint16_t
qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops)
{
@@ -240,7 +252,7 @@ qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
}
-struct rte_compressdev_ops compress_qat_ops = {
+static struct rte_compressdev_ops compress_qat_ops = {
/* Device related operations */
.dev_configure = qat_comp_dev_config,
@@ -258,3 +270,83 @@ struct rte_compressdev_ops compress_qat_ops = {
.private_xform_create = qat_comp_private_xform_create,
.private_xform_free = qat_comp_private_xform_free
};
+
+int
+qat_comp_dev_create(struct qat_pci_device *qat_pci_dev)
+{
+ if (qat_pci_dev->qat_dev_gen == QAT_GEN1) {
+ QAT_LOG(ERR, "Compression PMD not supported on QAT dh895xcc");
+ return 0;
+ }
+
+ struct rte_compressdev_pmd_init_params init_params = {
+ .name = "",
+ .socket_id = qat_pci_dev->pci_dev->device.numa_node,
+ };
+ char name[RTE_COMPRESSDEV_NAME_MAX_LEN];
+ struct rte_compressdev *compressdev;
+ struct qat_comp_dev_private *comp_dev;
+
+ snprintf(name, RTE_COMPRESSDEV_NAME_MAX_LEN, "%s_%s",
+ qat_pci_dev->name, "comp");
+ QAT_LOG(DEBUG, "Creating QAT COMP device %s", name);
+
+ compressdev = rte_compressdev_pmd_create(name,
+ &qat_pci_dev->pci_dev->device,
+ sizeof(struct qat_comp_dev_private),
+ &init_params);
+
+ if (compressdev == NULL)
+ return -ENODEV;
+
+ compressdev->dev_ops = &compress_qat_ops;
+
+ compressdev->enqueue_burst = qat_comp_pmd_enqueue_op_burst;
+ compressdev->dequeue_burst = qat_comp_pmd_dequeue_op_burst;
+
+ compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
+
+ comp_dev = compressdev->data->dev_private;
+ comp_dev->qat_dev = qat_pci_dev;
+ comp_dev->compressdev = compressdev;
+ qat_pci_dev->comp_dev = comp_dev;
+
+ switch (qat_pci_dev->qat_dev_gen) {
+ case QAT_GEN1:
+ case QAT_GEN2:
+ comp_dev->qat_dev_capabilities = qat_comp_gen_capabilities;
+ break;
+ default:
+ comp_dev->qat_dev_capabilities = qat_comp_gen_capabilities;
+ QAT_LOG(DEBUG,
+ "QAT gen %d capabilities unknown, default to GEN1",
+ qat_pci_dev->qat_dev_gen);
+ break;
+ }
+
+ QAT_LOG(DEBUG,
+ "Created QAT COMP device %s as compressdev instance %d",
+ name, compressdev->data->dev_id);
+ return 0;
+}
+
+int
+qat_comp_dev_destroy(struct qat_pci_device *qat_pci_dev)
+{
+ struct qat_comp_dev_private *comp_dev;
+
+ if (qat_pci_dev == NULL)
+ return -ENODEV;
+
+ comp_dev = qat_pci_dev->comp_dev;
+ if (comp_dev == NULL)
+ return 0;
+
+ /* clean up any resources used by the device */
+ qat_comp_dev_close(comp_dev->compressdev);
+
+ rte_compressdev_pmd_destroy(comp_dev->compressdev);
+ qat_pci_dev->comp_dev = NULL;
+
+ return 0;
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 7ba1b8d..9ad2a28 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -27,16 +27,13 @@ struct qat_comp_dev_private {
/**< The device's memory for intermediate buffers */
struct rte_mempool *xformpool;
/**< The device's pool for qat_comp_xforms */
-
};
-uint16_t
-qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
- uint16_t nb_ops);
+int
+qat_comp_dev_create(struct qat_pci_device *qat_pci_dev);
-uint16_t
-qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
- uint16_t nb_ops);
+int
+qat_comp_dev_destroy(struct qat_pci_device *qat_pci_dev);
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v5 15/16] compress/qat: prevent device usage if incorrect firmware
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 " Fiona Trahe
` (14 preceding siblings ...)
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 14/16] compress/qat: add fns to create and destroy the PMD Fiona Trahe
@ 2018-07-11 11:57 ` Fiona Trahe
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 16/16] docs/qat: refactor docs adding compression guide Fiona Trahe
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-11 11:57 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Previous check only causes op to fail on dequeue.
This extends so once first fail is detected, application can
no longer enqueue ops to the device and will also get an
appropriate error if trying to reconfigure or setup the device.
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 57 ++++++++++++++++++++++++++++++++++++-
1 file changed, 56 insertions(+), 1 deletion(-)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 9bb9897..0a571b3 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -252,6 +252,61 @@ qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
}
+static uint16_t
+qat_comp_pmd_enq_deq_dummy_op_burst(void *qp __rte_unused,
+ struct rte_comp_op **ops __rte_unused,
+ uint16_t nb_ops __rte_unused)
+{
+ QAT_DP_LOG(ERR, "QAT PMD detected wrong FW version !");
+ return 0;
+}
+
+static struct rte_compressdev_ops compress_qat_dummy_ops = {
+
+ /* Device related operations */
+ .dev_configure = NULL,
+ .dev_start = NULL,
+ .dev_stop = qat_comp_dev_stop,
+ .dev_close = qat_comp_dev_close,
+ .dev_infos_get = NULL,
+
+ .stats_get = NULL,
+ .stats_reset = qat_comp_stats_reset,
+ .queue_pair_setup = NULL,
+ .queue_pair_release = qat_comp_qp_release,
+
+ /* Compression related operations */
+ .private_xform_create = NULL,
+ .private_xform_free = qat_comp_private_xform_free
+};
+
+static uint16_t
+qat_comp_pmd_dequeue_frst_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops)
+{
+ uint16_t ret = qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
+ struct qat_qp *tmp_qp = (struct qat_qp *)qp;
+
+ if (ret) {
+ if ((*ops)->debug_status ==
+ (uint64_t)ERR_CODE_QAT_COMP_WRONG_FW) {
+ tmp_qp->qat_dev->comp_dev->compressdev->enqueue_burst =
+ qat_comp_pmd_enq_deq_dummy_op_burst;
+ tmp_qp->qat_dev->comp_dev->compressdev->dequeue_burst =
+ qat_comp_pmd_enq_deq_dummy_op_burst;
+
+ tmp_qp->qat_dev->comp_dev->compressdev->dev_ops =
+ &compress_qat_dummy_ops;
+ QAT_LOG(ERR, "QAT PMD detected wrong FW version !");
+
+ } else {
+ tmp_qp->qat_dev->comp_dev->compressdev->dequeue_burst =
+ qat_comp_pmd_dequeue_op_burst;
+ }
+ }
+ return ret;
+}
+
static struct rte_compressdev_ops compress_qat_ops = {
/* Device related operations */
@@ -302,7 +357,7 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev)
compressdev->dev_ops = &compress_qat_ops;
compressdev->enqueue_burst = qat_comp_pmd_enqueue_op_burst;
- compressdev->dequeue_burst = qat_comp_pmd_dequeue_op_burst;
+ compressdev->dequeue_burst = qat_comp_pmd_dequeue_frst_op_burst;
compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v5 16/16] docs/qat: refactor docs adding compression guide
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 " Fiona Trahe
` (15 preceding siblings ...)
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 15/16] compress/qat: prevent device usage if incorrect firmware Fiona Trahe
@ 2018-07-11 11:57 ` Fiona Trahe
2018-07-12 15:56 ` De Lara Guarch, Pablo
16 siblings, 1 reply; 106+ messages in thread
From: Fiona Trahe @ 2018-07-11 11:57 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Extend QAT guide to cover crypto and compression and common
information, particularly about kernel driver dependency.
Update release note.
Update compression feature list for qat.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
config/common_base | 2 +-
doc/guides/compressdevs/features/qat.ini | 24 ++++
doc/guides/compressdevs/index.rst | 1 +
doc/guides/compressdevs/qat_comp.rst | 49 +++++++++
doc/guides/cryptodevs/qat.rst | 183 +++++++++++++++++++++----------
doc/guides/rel_notes/release_18_08.rst | 5 +
6 files changed, 205 insertions(+), 59 deletions(-)
create mode 100644 doc/guides/compressdevs/features/qat.ini
create mode 100644 doc/guides/compressdevs/qat_comp.rst
diff --git a/config/common_base b/config/common_base
index 1e340b4..1380acf 100644
--- a/config/common_base
+++ b/config/common_base
@@ -478,7 +478,7 @@ CONFIG_RTE_LIBRTE_PMD_DPAA_SEC=n
CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4
#
-# Compile PMD for QuickAssist based devices
+# Compile PMD for QuickAssist based devices - see docs for details
#
CONFIG_RTE_LIBRTE_PMD_QAT=y
CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
diff --git a/doc/guides/compressdevs/features/qat.ini b/doc/guides/compressdevs/features/qat.ini
new file mode 100644
index 0000000..0d0e21d
--- /dev/null
+++ b/doc/guides/compressdevs/features/qat.ini
@@ -0,0 +1,24 @@
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+; Supported features of 'QAT' compression driver.
+;
+[Features]
+HW Accelerated = Y
+CPU SSE =
+CPU AVX =
+CPU AVX2 =
+CPU AVX512 =
+CPU NEON =
+Stateful =
+Pass-through =
+OOP SGL In SGL Out =
+OOP SGL In LB Out =
+OOP LB In SGL Out =
+Deflate = Y
+LZS =
+Adler32 = Y
+Crc32 = Y
+Adler32&Crc32 = Y
+Fixed = Y
+Dynamic =
diff --git a/doc/guides/compressdevs/index.rst b/doc/guides/compressdevs/index.rst
index bc59ce8..4228768 100644
--- a/doc/guides/compressdevs/index.rst
+++ b/doc/guides/compressdevs/index.rst
@@ -11,3 +11,4 @@ Compression Device Drivers
overview
isal
+ qat_comp
diff --git a/doc/guides/compressdevs/qat_comp.rst b/doc/guides/compressdevs/qat_comp.rst
new file mode 100644
index 0000000..167f816
--- /dev/null
+++ b/doc/guides/compressdevs/qat_comp.rst
@@ -0,0 +1,49 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+ Copyright(c) 2018 Intel Corporation.
+
+Intel(R) QuickAssist (QAT) Compression Poll Mode Driver
+=======================================================
+
+The QAT compression PMD provides poll mode compression & decompression driver
+support for the following hardware accelerator devices:
+
+* ``Intel QuickAssist Technology C62x``
+* ``Intel QuickAssist Technology C3xxx``
+
+
+Features
+--------
+
+QAT compression PMD has support for:
+
+Compression/Decompression algorithm:
+
+ * DEFLATE
+
+Huffman code type:
+
+ * FIXED
+
+Window size support:
+
+ * 32K
+
+Checksum generation:
+
+ * CRC32, Adler and combined checksum
+
+Limitations
+-----------
+
+* Chained mbufs are not yet supported, therefore max data size which can be passed to the PMD in a single mbuf is 64K - 1. If data is larger than this it will need to be split up and sent as multiple operations.
+
+* Compressdev level 0, no compression, is not supported.
+
+* Dynamic Huffman encoding is not yet supported.
+
+Installation
+------------
+
+The QAT compression PMD is built by default with a standard DPDK build.
+
+It depends on a QAT kernel driver, see :ref:`qat_kernel_installation`.
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index b899985..bdc58eb 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -68,12 +68,32 @@ Limitations
* Queue pairs are not thread-safe (that is, within a single queue pair, RX and TX from different lcores is not supported).
-Installation
-------------
+Extra notes on KASUMI F9
+------------------------
+
+When using KASUMI F9 authentication algorithm, the input buffer must be
+constructed according to the 3GPP KASUMI specifications (section 4.4, page 13):
+`<http://cryptome.org/3gpp/35201-900.pdf>`_.
+Input buffer has to have COUNT (4 bytes), FRESH (4 bytes), MESSAGE and DIRECTION (1 bit)
+concatenated. After the DIRECTION bit, a single '1' bit is appended, followed by
+between 0 and 7 '0' bits, so that the total length of the buffer is multiple of 8 bits.
+Note that the actual message can be any length, specified in bits.
-To enable QAT in DPDK, follow the instructions for modifying the compile-time
+Once this buffer is passed this way, when creating the crypto operation,
+length of data to authenticate (op.sym.auth.data.length) must be the length
+of all the items described above, including the padding at the end.
+Also, offset of data to authenticate (op.sym.auth.data.offset)
+must be such that points at the start of the COUNT bytes.
+
+
+Building the DPDK QAT cryptodev PMD
+-----------------------------------
+
+
+To enable QAT crypto in DPDK, follow the instructions for modifying the compile-time
configuration file as described `here <http://dpdk.org/doc/guides/linux_gsg/build_dpdk.html>`_.
+
Quick instructions are as follows:
.. code-block:: console
@@ -81,29 +101,95 @@ Quick instructions are as follows:
cd to the top-level DPDK directory
make config T=x86_64-native-linuxapp-gcc
sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT\)=n,\1=y,' build/.config
+ sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT_SYM\)=n,\1=y,' build/.config
make
-To use the DPDK QAT PMD an SRIOV-enabled QAT kernel driver is required. The VF
-devices exposed by this driver will be used by the QAT PMD. The devices and
-available kernel drivers and device ids are :
+
+.. _qat_kernel_installation:
+
+Dependency on the QAT kernel driver
+-----------------------------------
+
+To use the QAT PMD an SRIOV-enabled QAT kernel driver is required. The VF
+devices created and initialised by this driver will be used by the QAT PMD.
+
+Instructions for installation are below, but first an explanation of the
+relationships between the PF/VF devices and the PMDs visible to
+DPDK applications.
+
+
+Acceleration services - cryptography and compression - are provided to DPDK
+applications via PMDs which register to implement the corresponding
+cryptodev and compressdev APIs.
+
+Each QuickAssist VF device can expose one cryptodev PMD and/or one compressdev PMD.
+These QAT PMDs share the same underlying device and pci-mgmt code, but are
+enumerated independently on their respective APIs and appear as independent
+devices to applications.
+
+.. Note::
+
+ Each VF can only be used by one DPDK process. It is not possible to share
+ the same VF across multiple processes, even if these processes are using
+ different acceleration services.
+
+ Conversely one DPDK process can use one or more QAT VFs and can expose both
+ cryptodev and compressdev instances on each of those VFs.
+
+
+
+Device and driver naming
+------------------------
+
+* The qat cryptodev driver name is "crypto_qat".
+ The rte_cryptodev_devices_get() returns the devices exposed by this driver.
+
+* Each qat crypto device has a unique name, in format
+ <pci bdf>_<service>, e.g. "0000:41:01.0_qat_sym".
+ This name can be passed to rte_cryptodev_get_dev_id() to get the device_id.
+
+.. Note::
+
+ The qat crypto driver name is passed to the dpdk-test-crypto-perf tool in the -devtype parameter.
+
+ The qat crypto device name is in the format of the slave parameter passed to the crypto scheduler.
+
+* The qat compressdev driver name is "comp_qat".
+ The rte_compressdev_devices_get() returns the devices exposed by this driver.
+
+* Each qat compression device has a unique name, in format
+ <pci bdf>_<service>, e.g. "0000:41:01.0_qat_comp".
+ This name can be passed to rte_compressdev_get_dev_id() to get the device_id.
+
+
+Available kernel drivers
+------------------------
+
+Kernel drivers for each device are listed in the following table. Scroll right
+to check that the driver and device supports the servic you require.
+
.. _table_qat_pmds_drivers:
.. table:: QAT device generations, devices and drivers
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | Gen | Device | Driver | Kernel Module | Pci Driver | PF Did | #PFs | Vf Did | VFs/PF |
- +=====+==========+========+===============+============+========+======+========+========+
- | 1 | DH895xCC | 01.org | icp_qa_al | n/a | 435 | 1 | 443 | 32 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | 1 | DH895xCC | 4.4+ | qat_dh895xcc | dh895xcc | 435 | 1 | 443 | 32 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | 2 | C62x | 4.5+ | qat_c62x | c6xx | 37c8 | 3 | 37c9 | 16 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | 2 | C3xxx | 4.5+ | qat_c3xxx | c3xxx | 19e2 | 1 | 19e3 | 16 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | 2 | D15xx | p | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | Gen | Device | Driver/ver | Kernel Module | Pci Driver | PF Did | #PFs | VF Did | VFs/PF | cryptodev | compressdev |
+ +=====+==========+===============+===============+============+========+======+========+========+===========+=============+
+ | 1 | DH895xCC | linux/4.4+ | qat_dh895xcc | dh895xcc | 435 | 1 | 443 | 32 | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | 2 | C62x | linux/4.5+ | qat_c62x | c6xx | 37c8 | 3 | 37c9 | 16 | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | Yes | Yes |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | 2 | C3xxx | linux/4.5+ | qat_c3xxx | c3xxx | 19e2 | 1 | 19e3 | 16 | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | Yes | Yes |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | 2 | D15xx | p | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
The ``Driver`` column indicates either the Linux kernel version in which
@@ -196,9 +282,9 @@ Consult the *Getting Started Guide* at the same URL for further information.
The steps below assume you are:
-* Building on a platform with one ``DH895xCC`` device.
-* Using package ``qatmux.l.2.3.0-34.tgz``.
-* On Fedora21 kernel ``3.17.4-301.fc21.x86_64``.
+* Building on a platform with one ``C62x`` device.
+* Using package ``qat1.7.l.4.2.0-000xx.tar.gz``.
+* On Fedora26 kernel ``4.11.11-300.fc26.x86_64``.
In the BIOS ensure that SRIOV is enabled and VT-d is disabled.
@@ -206,21 +292,30 @@ Uninstall any existing QAT driver, for example by running:
* ``./installer.sh uninstall`` in the directory where originally installed.
-* or ``rmmod qat_dh895xcc; rmmod intel_qat``.
Build and install the SRIOV-enabled QAT driver::
mkdir /QAT
cd /QAT
- # Copy qatmux.l.2.3.0-34.tgz to this location
- tar zxof qatmux.l.2.3.0-34.tgz
+ # Copy the package to this location and unpack
+ tar zxof qat1.7.l.4.2.0-000xx.tar.gz
- export ICP_WITHOUT_IOMMU=1
- ./installer.sh install QAT1.6 host
+ ./configure --enable-icp-sriov=host
+ make install
+
+You can use ``cat /sys/kernel/debug/qat<your device type and bdf>/version/fw`` to confirm the driver is correctly installed and is using firmware version 4.2.0.
+You can use ``lspci -d:37c9`` to confirm the presence of the 16 VF devices available per ``C62x`` PF.
+
+Confirm the driver is correctly installed and is using firmware version 4.2.0::
+
+ cat /sys/kernel/debug/qat<your device type and bdf>/version/fw
+
+
+Confirm the presence of 48 VF devices - 16 per PF::
+
+ lspci -d:37c9
-You can use ``cat /proc/icp_dh895xcc_dev0/version`` to confirm the driver is correctly installed.
-You can use ``lspci -d:443`` to confirm the of the 32 VF devices available per ``DH895xCC`` device.
To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_.
@@ -261,6 +356,7 @@ To complete the installation - follow instructions in `Binding the available VFs
sudo yum install zlib-devel
sudo yum install openssl-devel
+ sudo yum install libudev-devel
.. Note::
@@ -343,35 +439,6 @@ Another way to bind the VFs to the DPDK UIO driver is by using the
./usertools/dpdk-devbind.py -b igb_uio 0000:03:01.1
-Extra notes on KASUMI F9
-------------------------
-
-When using KASUMI F9 authentication algorithm, the input buffer must be
-constructed according to the 3GPP KASUMI specifications (section 4.4, page 13):
-`<http://cryptome.org/3gpp/35201-900.pdf>`_.
-Input buffer has to have COUNT (4 bytes), FRESH (4 bytes), MESSAGE and DIRECTION (1 bit)
-concatenated. After the DIRECTION bit, a single '1' bit is appended, followed by
-between 0 and 7 '0' bits, so that the total length of the buffer is multiple of 8 bits.
-Note that the actual message can be any length, specified in bits.
-
-Once this buffer is passed this way, when creating the crypto operation,
-length of data to authenticate (op.sym.auth.data.length) must be the length
-of all the items described above, including the padding at the end.
-Also, offset of data to authenticate (op.sym.auth.data.offset)
-must be such that points at the start of the COUNT bytes.
-
-Device and driver naming
-------------------------
-
-The qat crypto driver name is "crypto_qat".
-This name is passed to the dpdk-test-crypto-perf tool in the -devtype parameter.
-The rte_cryptodev_devices_get() can return the devices exposed by a driver.
-
-Each qat crypto device has a unique name, in format
-<pci bdf>_<service>, e.g. "0000:41:01.0_qat_sym".
-This name can be passed to rte_cryptodev_get_dev_id() to get the device_id.
-This is also the format of the slave parameter passed to the crypto scheduler.
-
Debugging
----------------------------------------
diff --git a/doc/guides/rel_notes/release_18_08.rst b/doc/guides/rel_notes/release_18_08.rst
index d41546c..e554613 100644
--- a/doc/guides/rel_notes/release_18_08.rst
+++ b/doc/guides/rel_notes/release_18_08.rst
@@ -68,6 +68,11 @@ New Features
* Add handlers to add/delete VxLAN port number.
* Add devarg to specify ingress VLAN rewrite mode.
+* **Added a new compression PMD using Intel's QuickAssist (QAT) device family.**
+
+ Added the new ``QAT`` compression driver, for compression and decompression
+ operations in software. See the :doc:`../compressdevs/qat_comp` compression
+ driver guide for details on this new driver.
API Changes
-----------
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [dpdk-dev] [PATCH v5 02/16] compress/qat: add makefiles for PMD
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 02/16] compress/qat: add makefiles for PMD Fiona Trahe
@ 2018-07-12 12:41 ` De Lara Guarch, Pablo
0 siblings, 0 replies; 106+ messages in thread
From: De Lara Guarch, Pablo @ 2018-07-12 12:41 UTC (permalink / raw)
To: Trahe, Fiona, dev; +Cc: Jozwiak, TomaszX
> -----Original Message-----
> From: Trahe, Fiona
> Sent: Wednesday, July 11, 2018 12:57 PM
> To: dev@dpdk.org
> Cc: De Lara Guarch, Pablo <pablo.de.lara.guarch@intel.com>; Trahe, Fiona
> <fiona.trahe@intel.com>; Jozwiak, TomaszX <tomaszx.jozwiak@intel.com>
> Subject: [PATCH v5 02/16] compress/qat: add makefiles for PMD
>
> Add Makefiles, directory and empty source files for compression PMD.
> Handle cases for building either symmetric crypto PMD or compression PMD or
> both and the common files both depend on.
>
> Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
> Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
> ---
> MAINTAINERS | 4 +++
> config/common_base | 3 +-
> drivers/common/qat/Makefile | 60 +++++++++++++++++++++++--------------
> drivers/compress/qat/qat_comp.c | 5 ++++
> drivers/compress/qat/qat_comp.h | 14 +++++++++
> drivers/compress/qat/qat_comp_pmd.c | 5 ++++
> drivers/compress/qat/qat_comp_pmd.h | 15 ++++++++++
> test/test/test_cryptodev.c | 6 ++--
> 8 files changed, 86 insertions(+), 26 deletions(-) create mode 100644
> drivers/compress/qat/qat_comp.c create mode 100644
> drivers/compress/qat/qat_comp.h create mode 100644
> drivers/compress/qat/qat_comp_pmd.c
> create mode 100644 drivers/compress/qat/qat_comp_pmd.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 8050b5d..50b2dff 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -852,6 +852,10 @@ F: drivers/compress/isal/
> F: doc/guides/compressdevs/isal.rst
> F: doc/guides/compressdevs/features/isal.ini
>
> +Intel QuickAssist
> +M: Fiona Trahe <fiona.trahe@intel.com>
> +F: drivers/compress/qat/
> +F: drivers/common/qat/
>
> Eventdev Drivers
> ----------------
> diff --git a/config/common_base b/config/common_base index
> e4241db..1e340b4 100644
> --- a/config/common_base
> +++ b/config/common_base
> @@ -480,7 +480,8 @@ CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4
> #
> # Compile PMD for QuickAssist based devices # -
> CONFIG_RTE_LIBRTE_PMD_QAT=n
> +CONFIG_RTE_LIBRTE_PMD_QAT=y
> +CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
Since now you are enabling QAT driver by default, mk/rte.app.mk needs to be changed.
QAT_SYM requires libcrypto, not QAT itself, so right now, by default libcrypto is needed.
A change like the following would solve the problem, but not sure if it is correct.
+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += -lrte_pmd_qat
ifeq ($(CONFIG_RTE_LIBRTE_CRYPTODEV),y)
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_MB) += -lrte_pmd_aesni_mb
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_MB) += -lIPSec_MB
@@ -190,7 +191,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_GCM) += -lIPSec_MB
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += -lrte_pmd_ccp -lcrypto
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OPENSSL) += -lrte_pmd_openssl -lcrypto
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO) += -lrte_pmd_null_crypto
-_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += -lrte_pmd_qat -lcrypto
+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_QAT_SYM) += -lcrypto
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [dpdk-dev] [PATCH v5 16/16] docs/qat: refactor docs adding compression guide
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 16/16] docs/qat: refactor docs adding compression guide Fiona Trahe
@ 2018-07-12 15:56 ` De Lara Guarch, Pablo
0 siblings, 0 replies; 106+ messages in thread
From: De Lara Guarch, Pablo @ 2018-07-12 15:56 UTC (permalink / raw)
To: Trahe, Fiona, dev; +Cc: Jozwiak, TomaszX
> -----Original Message-----
> From: Trahe, Fiona
> Sent: Wednesday, July 11, 2018 12:57 PM
> To: dev@dpdk.org
> Cc: De Lara Guarch, Pablo <pablo.de.lara.guarch@intel.com>; Trahe, Fiona
> <fiona.trahe@intel.com>; Jozwiak, TomaszX <tomaszx.jozwiak@intel.com>
> Subject: [PATCH v5 16/16] docs/qat: refactor docs adding compression guide
>
> Extend QAT guide to cover crypto and compression and common information,
> particularly about kernel driver dependency.
> Update release note.
> Update compression feature list for qat.
>
>
> Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
> ---
> config/common_base | 2 +-
> doc/guides/compressdevs/features/qat.ini | 24 ++++
> doc/guides/compressdevs/index.rst | 1 +
> doc/guides/compressdevs/qat_comp.rst | 49 +++++++++
> doc/guides/cryptodevs/qat.rst | 183 +++++++++++++++++++++----------
> doc/guides/rel_notes/release_18_08.rst | 5 +
> 6 files changed, 205 insertions(+), 59 deletions(-) create mode 100644
> doc/guides/compressdevs/features/qat.ini
> create mode 100644 doc/guides/compressdevs/qat_comp.rst
>
> diff --git a/config/common_base b/config/common_base index
> 1e340b4..1380acf 100644
> --- a/config/common_base
> +++ b/config/common_base
> @@ -478,7 +478,7 @@ CONFIG_RTE_LIBRTE_PMD_DPAA_SEC=n
> CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4
>
> #
> -# Compile PMD for QuickAssist based devices
> +# Compile PMD for QuickAssist based devices - see docs for details
> #
> CONFIG_RTE_LIBRTE_PMD_QAT=y
> CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
> diff --git a/doc/guides/compressdevs/features/qat.ini
> b/doc/guides/compressdevs/features/qat.ini
> new file mode 100644
> index 0000000..0d0e21d
> --- /dev/null
> +++ b/doc/guides/compressdevs/features/qat.ini
> @@ -0,0 +1,24 @@
> +;
> +; Refer to default.ini for the full list of available PMD features.
> +;
> +; Supported features of 'QAT' compression driver.
> +;
> +[Features]
> +HW Accelerated = Y
> +CPU SSE =
> +CPU AVX =
> +CPU AVX2 =
> +CPU AVX512 =
> +CPU NEON =
> +Stateful =
> +Pass-through =
> +OOP SGL In SGL Out =
> +OOP SGL In LB Out =
> +OOP LB In SGL Out =
> +Deflate = Y
> +LZS =
> +Adler32 = Y
> +Crc32 = Y
> +Adler32&Crc32 = Y
> +Fixed = Y
> +Dynamic =
No need to add the features that are not supported here (the ones that do not have "Y").
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v6 00/16] compress/qat: add compression PMD
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 " Fiona Trahe
@ 2018-07-12 16:04 ` Fiona Trahe
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 " Pablo de Lara
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 01/16] common/qat: updated firmware headers Fiona Trahe
` (15 subsequent siblings)
16 siblings, 1 reply; 106+ messages in thread
From: Fiona Trahe @ 2018-07-12 16:04 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Create compression PMD for Intel QuickAssist devices
Currently only the C62x and c3xxx devices are supported.
The qat comp PMD supports
- stateless compression and
decompression using the Deflate algorithm with Fixed Huffman
encoding. Dynamic huffman encoding is not supported, it
will be added in a later patch.
- checksum generation: Adler32, CRC32 and combined.
The compression service is hosted on a QuickAssist VF PCI
device, which is managed by code in the
drivers/common/qat directory.
v6 changes:
- fixed makefile issue when cross compiling
v5 changes:
- rebased against latest r/n and features/default.ini
- fixed common/qat/Makefile so no build output files
left hanging around in compress/qat src dir.
v4 changes:
- corrected capabilities
v3 changes:
- only commit message changes, i.e. removed ChangeId and fixed typos
v2 changes:
- Added check for correct firmware
- Split patchset
- Added documentation
- removed support for scatter-gather-lists and related config flag
- Removed support for Dynamic huffman encoding and related IM buffer config flag
- Removed support for DH895xcc device
Fiona Trahe (16):
common/qat: updated firmware headers
compress/qat: add makefiles for PMD
compress/qat: add meson build
compress/qat: add xform processing
compress/qat: create fw request and process response
compress/qat: check that correct firmware is in use
compress/qat: add stats functions
compress/qat: setup queue-pairs for compression service
compress/qat: add fns to configure and clear device
compress/qat: add fn to return device info
compress/qat: add enqueue/dequeue functions
compress/qat: add device start and stop fns
compress/qat: create and populate the ops structure
compress/qat: add fns to create and destroy the PMD
compress/qat: prevent device usage if incorrect firmware
docs/qat: refactor docs adding compression guide
MAINTAINERS | 4 +
config/common_base | 5 +-
doc/guides/compressdevs/features/qat.ini | 24 ++
doc/guides/compressdevs/index.rst | 1 +
doc/guides/compressdevs/qat_comp.rst | 49 +++
doc/guides/cryptodevs/qat.rst | 183 ++++++----
doc/guides/rel_notes/release_18_08.rst | 5 +
drivers/common/qat/Makefile | 47 ++-
drivers/common/qat/qat_adf/icp_qat_fw.h | 69 +++-
drivers/common/qat/qat_adf/icp_qat_fw_comp.h | 482 +++++++++++++++++++++++++++
drivers/common/qat/qat_adf/icp_qat_hw.h | 130 +++++++-
drivers/common/qat/qat_device.h | 4 +
drivers/common/qat/qat_qp.c | 11 +-
drivers/common/qat/qat_qp.h | 5 +
drivers/compress/meson.build | 2 +-
drivers/compress/qat/meson.build | 18 +
drivers/compress/qat/qat_comp.c | 359 ++++++++++++++++++++
drivers/compress/qat/qat_comp.h | 56 ++++
drivers/compress/qat/qat_comp_pmd.c | 407 ++++++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 39 +++
drivers/compress/qat/rte_pmd_qat_version.map | 3 +
drivers/crypto/qat/meson.build | 10 +-
drivers/crypto/qat/rte_pmd_qat_version.map | 3 -
mk/rte.app.mk | 5 +-
test/test/test_cryptodev.c | 6 +-
25 files changed, 1805 insertions(+), 122 deletions(-)
create mode 100644 doc/guides/compressdevs/features/qat.ini
create mode 100644 doc/guides/compressdevs/qat_comp.rst
create mode 100644 drivers/common/qat/qat_adf/icp_qat_fw_comp.h
create mode 100644 drivers/compress/qat/meson.build
create mode 100644 drivers/compress/qat/qat_comp.c
create mode 100644 drivers/compress/qat/qat_comp.h
create mode 100644 drivers/compress/qat/qat_comp_pmd.c
create mode 100644 drivers/compress/qat/qat_comp_pmd.h
create mode 100644 drivers/compress/qat/rte_pmd_qat_version.map
delete mode 100644 drivers/crypto/qat/rte_pmd_qat_version.map
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v6 01/16] common/qat: updated firmware headers
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 " Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 " Fiona Trahe
@ 2018-07-12 16:04 ` Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 02/16] compress/qat: add makefiles for PMD Fiona Trahe
` (14 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-12 16:04 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Updated to latest firmware headers files for QuickAssist devices.
Includes updates for symmetric crypto, PKE and Compression services.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
drivers/common/qat/qat_adf/icp_qat_fw.h | 69 +++-
drivers/common/qat/qat_adf/icp_qat_fw_comp.h | 482 +++++++++++++++++++++++++++
drivers/common/qat/qat_adf/icp_qat_hw.h | 130 +++++++-
3 files changed, 654 insertions(+), 27 deletions(-)
create mode 100644 drivers/common/qat/qat_adf/icp_qat_fw_comp.h
diff --git a/drivers/common/qat/qat_adf/icp_qat_fw.h b/drivers/common/qat/qat_adf/icp_qat_fw.h
index ae39b7f..8f7cb37 100644
--- a/drivers/common/qat/qat_adf/icp_qat_fw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_fw.h
@@ -117,6 +117,10 @@ struct icp_qat_fw_comn_resp {
#define ICP_QAT_FW_COMN_VALID_FLAG_BITPOS 7
#define ICP_QAT_FW_COMN_VALID_FLAG_MASK 0x1
#define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK 0x7F
+#define ICP_QAT_FW_COMN_CNV_FLAG_BITPOS 6
+#define ICP_QAT_FW_COMN_CNV_FLAG_MASK 0x1
+#define ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS 5
+#define ICP_QAT_FW_COMN_CNVNR_FLAG_MASK 0x1
#define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \
icp_qat_fw_comn_req_hdr_t.service_type
@@ -133,6 +137,16 @@ struct icp_qat_fw_comn_resp {
#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_GET(hdr_t) \
ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_t.hdr_flags)
+#define ICP_QAT_FW_COMN_HDR_CNVNR_FLAG_GET(hdr_flags) \
+ QAT_FIELD_GET(hdr_flags, \
+ ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS, \
+ ICP_QAT_FW_COMN_CNVNR_FLAG_MASK)
+
+#define ICP_QAT_FW_COMN_HDR_CNV_FLAG_GET(hdr_flags) \
+ QAT_FIELD_GET(hdr_flags, \
+ ICP_QAT_FW_COMN_CNV_FLAG_BITPOS, \
+ ICP_QAT_FW_COMN_CNV_FLAG_MASK)
+
#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_SET(hdr_t, val) \
ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val)
@@ -204,29 +218,44 @@ struct icp_qat_fw_comn_resp {
& ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)); }
+#define ICP_QAT_FW_COMN_NEXT_ID_SET_2(next_curr_id, val) \
+ do { \
+ (next_curr_id) = \
+ (((next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK) | \
+ (((val) << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) & \
+ ICP_QAT_FW_COMN_NEXT_ID_MASK)) \
+ } while (0)
+
+#define ICP_QAT_FW_COMN_CURR_ID_SET_2(next_curr_id, val) \
+ do { \
+ (next_curr_id) = \
+ (((next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
+ ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) \
+ } while (0)
+
#define QAT_COMN_RESP_CRYPTO_STATUS_BITPOS 7
#define QAT_COMN_RESP_CRYPTO_STATUS_MASK 0x1
+#define QAT_COMN_RESP_PKE_STATUS_BITPOS 6
+#define QAT_COMN_RESP_PKE_STATUS_MASK 0x1
#define QAT_COMN_RESP_CMP_STATUS_BITPOS 5
#define QAT_COMN_RESP_CMP_STATUS_MASK 0x1
#define QAT_COMN_RESP_XLAT_STATUS_BITPOS 4
#define QAT_COMN_RESP_XLAT_STATUS_MASK 0x1
#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS 3
#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1
-
-#define ICP_QAT_FW_COMN_RESP_STATUS_BUILD(crypto, comp, xlat, eolb) \
- ((((crypto) & QAT_COMN_RESP_CRYPTO_STATUS_MASK) << \
- QAT_COMN_RESP_CRYPTO_STATUS_BITPOS) | \
- (((comp) & QAT_COMN_RESP_CMP_STATUS_MASK) << \
- QAT_COMN_RESP_CMP_STATUS_BITPOS) | \
- (((xlat) & QAT_COMN_RESP_XLAT_STATUS_MASK) << \
- QAT_COMN_RESP_XLAT_STATUS_BITPOS) | \
- (((eolb) & QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK) << \
- QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS))
+#define QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS 2
+#define QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK 0x1
+#define QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS 0
+#define QAT_COMN_RESP_XLT_WA_APPLIED_MASK 0x1
#define ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(status) \
QAT_FIELD_GET(status, QAT_COMN_RESP_CRYPTO_STATUS_BITPOS, \
QAT_COMN_RESP_CRYPTO_STATUS_MASK)
+#define ICP_QAT_FW_COMN_RESP_PKE_STAT_GET(status) \
+ QAT_FIELD_GET(status, QAT_COMN_RESP_PKE_STATUS_BITPOS, \
+ QAT_COMN_RESP_PKE_STATUS_MASK)
+
#define ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(status) \
QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_STATUS_BITPOS, \
QAT_COMN_RESP_CMP_STATUS_MASK)
@@ -235,10 +264,18 @@ struct icp_qat_fw_comn_resp {
QAT_FIELD_GET(status, QAT_COMN_RESP_XLAT_STATUS_BITPOS, \
QAT_COMN_RESP_XLAT_STATUS_MASK)
+#define ICP_QAT_FW_COMN_RESP_XLT_WA_APPLIED_GET(status) \
+ QAT_FIELD_GET(status, QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS, \
+ QAT_COMN_RESP_XLT_WA_APPLIED_MASK)
+
#define ICP_QAT_FW_COMN_RESP_CMP_END_OF_LAST_BLK_FLAG_GET(status) \
QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS, \
QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK)
+#define ICP_QAT_FW_COMN_RESP_UNSUPPORTED_REQUEST_STAT_GET(status) \
+ QAT_FIELD_GET(status, QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS, \
+ QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK)
+
#define ICP_QAT_FW_COMN_STATUS_FLAG_OK 0
#define ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 1
#define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0
@@ -257,8 +294,16 @@ struct icp_qat_fw_comn_resp {
#define ERR_CODE_OVERFLOW_ERROR -11
#define ERR_CODE_SOFT_ERROR -12
#define ERR_CODE_FATAL_ERROR -13
-#define ERR_CODE_SSM_ERROR -14
-#define ERR_CODE_ENDPOINT_ERROR -15
+#define ERR_CODE_COMP_OUTPUT_CORRUPTION -14
+#define ERR_CODE_HW_INCOMPLETE_FILE -15
+#define ERR_CODE_SSM_ERROR -16
+#define ERR_CODE_ENDPOINT_ERROR -17
+#define ERR_CODE_CNV_ERROR -18
+#define ERR_CODE_EMPTY_DYM_BLOCK -19
+#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_HANDLE -20
+#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_HMAC_FAILED -21
+#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_WRAPPING_ALGO -22
+#define ERR_CODE_KPT_DRNG_SEED_NOT_LOAD -23
enum icp_qat_fw_slice {
ICP_QAT_FW_SLICE_NULL = 0,
diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_comp.h b/drivers/common/qat/qat_adf/icp_qat_fw_comp.h
new file mode 100644
index 0000000..8138177
--- /dev/null
+++ b/drivers/common/qat/qat_adf/icp_qat_fw_comp.h
@@ -0,0 +1,482 @@
+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+#ifndef _ICP_QAT_FW_COMP_H_
+#define _ICP_QAT_FW_COMP_H_
+
+#include "icp_qat_fw.h"
+
+enum icp_qat_fw_comp_cmd_id {
+ ICP_QAT_FW_COMP_CMD_STATIC = 0,
+ /*!< Static Compress Request */
+
+ ICP_QAT_FW_COMP_CMD_DYNAMIC = 1,
+ /*!< Dynamic Compress Request */
+
+ ICP_QAT_FW_COMP_CMD_DECOMPRESS = 2,
+ /*!< Decompress Request */
+
+ ICP_QAT_FW_COMP_CMD_DELIMITER
+ /**< Delimiter type */
+};
+
+/**< Flag usage */
+
+#define ICP_QAT_FW_COMP_STATELESS_SESSION 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that session is stateless
+ */
+
+#define ICP_QAT_FW_COMP_STATEFUL_SESSION 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that session is stateful
+ */
+
+#define ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that autoselectbest is NOT used
+ */
+
+#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that autoselectbest is used
+ */
+
+#define ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is NOT used
+ */
+
+#define ICP_QAT_FW_COMP_ENH_AUTO_SELECT_BEST 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is used
+ */
+
+#define ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is NOT used
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is used
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_USED_AS_INTMD_BUF 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing secure RAM from being used as
+ * an intermediate buffer is DISABLED.
+ */
+
+#define ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing secure RAM from being used as
+ * an intermediate buffer is ENABLED.
+ */
+
+/**< Flag mask & bit position */
+
+#define ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS 2
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the session type
+ */
+
+#define ICP_QAT_FW_COMP_SESSION_TYPE_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask used to determine the session type
+ */
+
+#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS 3
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for auto select best
+ */
+
+#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for auto select best
+ */
+
+#define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS 4
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for enhanced auto select best
+ */
+
+#define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for enhanced auto select best
+ */
+
+#define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS 5
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for disabling type zero header write back
+ * when Enhanced autoselect best is enabled. If set firmware does
+ * not return type0 store block header, only copies src to dest.
+ * (if best output is Type0)
+ */
+
+#define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for auto select best
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS 7
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for flag used to disable secure ram from
+ * being used as an intermediate buffer.
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for disable secure ram for use as an intermediate
+ * buffer.
+ */
+
+#define ICP_QAT_FW_COMP_FLAGS_BUILD(sesstype, autoselect, enhanced_asb, \
+ ret_uncomp, secure_ram) \
+ ((((sesstype)&ICP_QAT_FW_COMP_SESSION_TYPE_MASK) \
+ << ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS) | \
+ (((autoselect)&ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK) \
+ << ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS) | \
+ (((enhanced_asb)&ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK) \
+ << ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS) | \
+ (((ret_uncomp)&ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK) \
+ << ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS) | \
+ (((secure_ram)&ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK) \
+ << ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS))
+
+union icp_qat_fw_comp_req_hdr_cd_pars {
+ /**< LWs 2-5 */
+ struct {
+ uint64_t content_desc_addr;
+ /**< Address of the content descriptor */
+
+ uint16_t content_desc_resrvd1;
+ /**< Content descriptor reserved field */
+
+ uint8_t content_desc_params_sz;
+ /**< Size of the content descriptor parameters in quad words.
+ * These parameters describe the session setup configuration
+ * info for the slices that this request relies upon i.e.
+ * the configuration word and cipher key needed by the cipher
+ * slice if there is a request for cipher processing.
+ */
+
+ uint8_t content_desc_hdr_resrvd2;
+ /**< Content descriptor reserved field */
+
+ uint32_t content_desc_resrvd3;
+ /**< Content descriptor reserved field */
+ } s;
+
+ struct {
+ uint32_t comp_slice_cfg_word[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /* Compression Slice Config Word */
+
+ uint32_t content_desc_resrvd4;
+ /**< Content descriptor reserved field */
+
+ } sl;
+
+};
+
+struct icp_qat_fw_comp_req_params {
+ /**< LW 14 */
+ uint32_t comp_len;
+ /**< Size of input to process in bytes Note: Only EOP requests can be
+ * odd for decompression. IA must set LSB to zero for odd sized
+ * intermediate inputs
+ */
+
+ /**< LW 15 */
+ uint32_t out_buffer_sz;
+ /**< Size of output buffer in bytes */
+
+ /**< LW 16 */
+ uint32_t initial_crc32;
+ /**< CRC of previously processed bytes */
+
+ /**< LW 17 */
+ uint32_t initial_adler;
+ /**< Adler of previously processed bytes */
+
+ /**< LW 18 */
+ uint32_t req_par_flags;
+
+ /**< LW 19 */
+ uint32_t rsrvd;
+};
+
+#define ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(sop, eop, bfinal, cnv, cnvnr) \
+ ((((sop)&ICP_QAT_FW_COMP_SOP_MASK) << ICP_QAT_FW_COMP_SOP_BITPOS) | \
+ (((eop)&ICP_QAT_FW_COMP_EOP_MASK) << ICP_QAT_FW_COMP_EOP_BITPOS) | \
+ (((bfinal)&ICP_QAT_FW_COMP_BFINAL_MASK) \
+ << ICP_QAT_FW_COMP_BFINAL_BITPOS) | \
+ ((cnv & ICP_QAT_FW_COMP_CNV_MASK) << ICP_QAT_FW_COMP_CNV_BITPOS) | \
+ ((cnvnr & ICP_QAT_FW_COMP_CNV_RECOVERY_MASK) \
+ << ICP_QAT_FW_COMP_CNV_RECOVERY_BITPOS))
+
+#define ICP_QAT_FW_COMP_NOT_SOP 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request is NOT Start of Packet
+ */
+
+#define ICP_QAT_FW_COMP_SOP 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request IS Start of Packet
+ */
+
+#define ICP_QAT_FW_COMP_NOT_EOP 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request is NOT Start of Packet
+ */
+
+#define ICP_QAT_FW_COMP_EOP 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request IS End of Packet
+ */
+
+#define ICP_QAT_FW_COMP_NOT_BFINAL 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing to indicate firmware this is not the last block
+ */
+
+#define ICP_QAT_FW_COMP_BFINAL 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing to indicate firmware this is the last block
+ */
+
+#define ICP_QAT_FW_COMP_NO_CNV 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that NO cnv check is to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_CNV 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that a cnv check IS to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_NO_CNV_RECOVERY 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that NO cnv recovery is to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_CNV_RECOVERY 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that a cnv recovery is to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_SOP_BITPOS 0
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for SOP
+ */
+
+#define ICP_QAT_FW_COMP_SOP_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask used to determine SOP
+ */
+
+#define ICP_QAT_FW_COMP_EOP_BITPOS 1
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for EOP
+ */
+
+#define ICP_QAT_FW_COMP_EOP_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask used to determine EOP
+ */
+
+#define ICP_QAT_FW_COMP_BFINAL_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for the bfinal bit
+ */
+
+#define ICP_QAT_FW_COMP_BFINAL_BITPOS 6
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the bfinal bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for the CNV bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_BITPOS 16
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the CNV bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_RECOVERY_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for the CNV Recovery bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_RECOVERY_BITPOS 17
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the CNV Recovery bit
+ */
+
+struct icp_qat_fw_xlt_req_params {
+ /**< LWs 20-21 */
+ uint64_t inter_buff_ptr;
+ /**< This field specifies the physical address of an intermediate
+ * buffer SGL array. The array contains a pair of 64-bit
+ * intermediate buffer pointers to SGL buffer descriptors, one pair
+ * per CPM. Please refer to the CPM1.6 Firmware Interface HLD
+ * specification for more details.
+ */
+};
+
+
+struct icp_qat_fw_comp_cd_hdr {
+ /**< LW 24 */
+ uint16_t ram_bank_flags;
+ /**< Flags to show which ram banks to access */
+
+ uint8_t comp_cfg_offset;
+ /**< Quad word offset from the content descriptor parameters address
+ * to the parameters for the compression processing
+ */
+
+ uint8_t next_curr_id;
+ /**< This field combines the next and current id (each four bits) -
+ * the next id is the most significant nibble.
+ * Next Id: Set to the next slice to pass the compressed data through.
+ * Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through
+ * anymore slices after compression
+ * Current Id: Initialised with the compression slice type
+ */
+
+ /**< LW 25 */
+ uint32_t resrvd;
+ /**< LWs 26-27 */
+
+ uint64_t comp_state_addr;
+ /**< Pointer to compression state */
+
+ /**< LWs 28-29 */
+ uint64_t ram_banks_addr;
+ /**< Pointer to banks */
+
+};
+
+
+struct icp_qat_fw_xlt_cd_hdr {
+ /**< LW 30 */
+ uint16_t resrvd1;
+ /**< Reserved field and assumed set to 0 */
+
+ uint8_t resrvd2;
+ /**< Reserved field and assumed set to 0 */
+
+ uint8_t next_curr_id;
+ /**< This field combines the next and current id (each four bits) -
+ * the next id is the most significant nibble.
+ * Next Id: Set to the next slice to pass the translated data through.
+ * Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through
+ * any more slices after compression
+ * Current Id: Initialised with the translation slice type
+ */
+
+ /**< LW 31 */
+ uint32_t resrvd3;
+ /**< Reserved and should be set to zero, needed for quadword
+ * alignment
+ */
+};
+
+struct icp_qat_fw_comp_req {
+ /**< LWs 0-1 */
+ struct icp_qat_fw_comn_req_hdr comn_hdr;
+ /**< Common request header - for Service Command Id,
+ * use service-specific Compression Command Id.
+ * Service Specific Flags - use Compression Command Flags
+ */
+
+ /**< LWs 2-5 */
+ union icp_qat_fw_comp_req_hdr_cd_pars cd_pars;
+ /**< Compression service-specific content descriptor field which points
+ * either to a content descriptor parameter block or contains the
+ * compression slice config word.
+ */
+
+ /**< LWs 6-13 */
+ struct icp_qat_fw_comn_req_mid comn_mid;
+ /**< Common request middle section */
+
+ /**< LWs 14-19 */
+ struct icp_qat_fw_comp_req_params comp_pars;
+ /**< Compression request Parameters block */
+
+ /**< LWs 20-21 */
+ union {
+ struct icp_qat_fw_xlt_req_params xlt_pars;
+ /**< Translation request Parameters block */
+ uint32_t resrvd1[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /**< Reserved if not used for translation */
+
+ } u1;
+
+ /**< LWs 22-23 */
+ union {
+ uint32_t resrvd2[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /**< Reserved - not used if Batch and Pack is disabled.*/
+
+ uint64_t bnp_res_table_addr;
+ /**< A generic pointer to the unbounded list of
+ * icp_qat_fw_resp_comp_pars members. This pointer is only
+ * used when the Batch and Pack is enabled.
+ */
+ } u3;
+
+ /**< LWs 24-29 */
+ struct icp_qat_fw_comp_cd_hdr comp_cd_ctrl;
+ /**< Compression request content descriptor control block header */
+
+ /**< LWs 30-31 */
+ union {
+ struct icp_qat_fw_xlt_cd_hdr xlt_cd_ctrl;
+ /**< Translation request content descriptor
+ * control block header
+ */
+
+ uint32_t resrvd3[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /**< Reserved if not used for translation */
+ } u2;
+};
+
+struct icp_qat_fw_resp_comp_pars {
+ /**< LW 4 */
+ uint32_t input_byte_counter;
+ /**< Input byte counter */
+
+ /**< LW 5 */
+ uint32_t output_byte_counter;
+ /**< Output byte counter */
+
+ /**< LW 6 & 7*/
+ union {
+ uint64_t curr_chksum;
+ struct {
+ /**< LW 6 */
+ uint32_t curr_crc32;
+ /**< LW 7 */
+ uint32_t curr_adler_32;
+ };
+ };
+};
+
+struct icp_qat_fw_comp_resp {
+ /**< LWs 0-1 */
+ struct icp_qat_fw_comn_resp_hdr comn_resp;
+ /**< Common interface response format see icp_qat_fw.h */
+
+ /**< LWs 2-3 */
+ uint64_t opaque_data;
+ /**< Opaque data passed from the request to the response message */
+
+ /**< LWs 4-7 */
+ struct icp_qat_fw_resp_comp_pars comp_resp_pars;
+ /**< Common response params (checksums and byte counts) */
+};
+
+#endif
diff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h b/drivers/common/qat/qat_adf/icp_qat_hw.h
index 56e3cf7..e7961db 100644
--- a/drivers/common/qat/qat_adf/icp_qat_hw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_hw.h
@@ -72,19 +72,44 @@ struct icp_qat_hw_auth_config {
#define QAT_AUTH_ALGO_MASK 0xF
#define QAT_AUTH_CMP_BITPOS 8
#define QAT_AUTH_CMP_MASK 0x7F
-#define QAT_AUTH_SHA3_PADDING_BITPOS 16
-#define QAT_AUTH_SHA3_PADDING_MASK 0x1
+#define QAT_AUTH_SHA3_PADDING_DISABLE_BITPOS 16
+#define QAT_AUTH_SHA3_PADDING_DISABLE_MASK 0x1
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_BITPOS 17
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_MASK 0x1
#define QAT_AUTH_ALGO_SHA3_BITPOS 22
#define QAT_AUTH_ALGO_SHA3_MASK 0x3
-#define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \
- (((mode & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \
- ((algo & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \
- (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) << \
- QAT_AUTH_ALGO_SHA3_BITPOS) | \
- (((((algo == ICP_QAT_HW_AUTH_ALGO_SHA3_256) || \
- (algo == ICP_QAT_HW_AUTH_ALGO_SHA3_512)) ? 1 : 0) \
- & QAT_AUTH_SHA3_PADDING_MASK) << QAT_AUTH_SHA3_PADDING_BITPOS) | \
- ((cmp_len & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
+#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_BITPOS 16
+#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_MASK 0xF
+#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_BITPOS 24
+#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_MASK 0xFF
+#define QAT_AUTH_SHA3_HW_PADDING_ENABLE 0
+#define QAT_AUTH_SHA3_HW_PADDING_DISABLE 1
+#define QAT_AUTH_SHA3_PADDING_DISABLE_USE_DEFAULT 0
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_USE_DEFAULT 0
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_PROGRAMMABLE 1
+#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_RESERVED 0
+#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_RESERVED 0
+
+#define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \
+ ((((mode) & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \
+ (((algo) & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \
+ (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) \
+ << QAT_AUTH_ALGO_SHA3_BITPOS) | \
+ (((QAT_AUTH_SHA3_PADDING_DISABLE_USE_DEFAULT) & \
+ QAT_AUTH_SHA3_PADDING_DISABLE_MASK) \
+ << QAT_AUTH_SHA3_PADDING_DISABLE_BITPOS) | \
+ (((QAT_AUTH_SHA3_PADDING_OVERRIDE_USE_DEFAULT) & \
+ QAT_AUTH_SHA3_PADDING_OVERRIDE_MASK) \
+ << QAT_AUTH_SHA3_PADDING_OVERRIDE_BITPOS) | \
+ (((cmp_len) & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
+
+#define ICP_QAT_HW_AUTH_CONFIG_BUILD_UPPER \
+ ((((QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_RESERVED) & \
+ QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_MASK) \
+ << QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_BITPOS) | \
+ (((QAT_AUTH_SHA3_PROG_PADDING_PREFIX_RESERVED) & \
+ QAT_AUTH_SHA3_PROG_PADDING_PREFIX_MASK) \
+ << QAT_AUTH_SHA3_PROG_PADDING_PREFIX_BITPOS))
struct icp_qat_hw_auth_counter {
uint32_t counter;
@@ -107,13 +132,13 @@ struct icp_qat_hw_auth_setup {
#define ICP_QAT_HW_MD5_STATE1_SZ 16
#define ICP_QAT_HW_SHA1_STATE1_SZ 20
#define ICP_QAT_HW_SHA224_STATE1_SZ 32
+#define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
#define ICP_QAT_HW_SHA256_STATE1_SZ 32
#define ICP_QAT_HW_SHA3_256_STATE1_SZ 32
#define ICP_QAT_HW_SHA384_STATE1_SZ 64
+#define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
#define ICP_QAT_HW_SHA512_STATE1_SZ 64
#define ICP_QAT_HW_SHA3_512_STATE1_SZ 64
-#define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
-#define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
#define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ 16
#define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ 16
#define ICP_QAT_HW_AES_F9_STATE1_SZ 32
@@ -121,17 +146,18 @@ struct icp_qat_hw_auth_setup {
#define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16
#define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8
#define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8
+
#define ICP_QAT_HW_NULL_STATE2_SZ 32
#define ICP_QAT_HW_MD5_STATE2_SZ 16
#define ICP_QAT_HW_SHA1_STATE2_SZ 20
#define ICP_QAT_HW_SHA224_STATE2_SZ 32
+#define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
#define ICP_QAT_HW_SHA256_STATE2_SZ 32
#define ICP_QAT_HW_SHA3_256_STATE2_SZ 0
#define ICP_QAT_HW_SHA384_STATE2_SZ 64
+#define ICP_QAT_HW_SHA3_384_STATE2_SZ 0
#define ICP_QAT_HW_SHA512_STATE2_SZ 64
#define ICP_QAT_HW_SHA3_512_STATE2_SZ 0
-#define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
-#define ICP_QAT_HW_SHA3_384_STATE2_SZ 0
#define ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ 48
#define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16
#define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16
@@ -154,6 +180,12 @@ struct icp_qat_hw_auth_sha512 {
uint8_t state2[ICP_QAT_HW_SHA512_STATE2_SZ];
};
+struct icp_qat_hw_auth_sha3_512 {
+ struct icp_qat_hw_auth_setup inner_setup;
+ uint8_t state1[ICP_QAT_HW_SHA3_512_STATE1_SZ];
+ struct icp_qat_hw_auth_setup outer_setup;
+};
+
struct icp_qat_hw_auth_algo_blk {
struct icp_qat_hw_auth_sha512 sha;
};
@@ -283,4 +315,72 @@ struct icp_qat_hw_cipher_algo_blk {
uint8_t key[ICP_QAT_HW_CIPHER_MAX_KEY_SZ];
} __rte_cache_aligned;
+/* ========================================================================= */
+/* COMPRESSION SLICE */
+/* ========================================================================= */
+
+enum icp_qat_hw_compression_direction {
+ ICP_QAT_HW_COMPRESSION_DIR_COMPRESS = 0,
+ ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS = 1,
+ ICP_QAT_HW_COMPRESSION_DIR_DELIMITER = 2
+};
+
+enum icp_qat_hw_compression_delayed_match {
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED = 0,
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_ENABLED = 1,
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DELIMITER = 2
+};
+
+enum icp_qat_hw_compression_algo {
+ ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE = 0,
+ ICP_QAT_HW_COMPRESSION_ALGO_LZS = 1,
+ ICP_QAT_HW_COMPRESSION_ALGO_DELIMITER = 2
+};
+
+
+enum icp_qat_hw_compression_depth {
+ ICP_QAT_HW_COMPRESSION_DEPTH_1 = 0,
+ ICP_QAT_HW_COMPRESSION_DEPTH_4 = 1,
+ ICP_QAT_HW_COMPRESSION_DEPTH_8 = 2,
+ ICP_QAT_HW_COMPRESSION_DEPTH_16 = 3,
+ ICP_QAT_HW_COMPRESSION_DEPTH_DELIMITER = 4
+};
+
+enum icp_qat_hw_compression_file_type {
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_0 = 0,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_1 = 1,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_2 = 2,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_3 = 3,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_4 = 4,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_DELIMITER = 5
+};
+
+struct icp_qat_hw_compression_config {
+ uint32_t val;
+ uint32_t reserved;
+};
+
+#define QAT_COMPRESSION_DIR_BITPOS 4
+#define QAT_COMPRESSION_DIR_MASK 0x7
+#define QAT_COMPRESSION_DELAYED_MATCH_BITPOS 16
+#define QAT_COMPRESSION_DELAYED_MATCH_MASK 0x1
+#define QAT_COMPRESSION_ALGO_BITPOS 31
+#define QAT_COMPRESSION_ALGO_MASK 0x1
+#define QAT_COMPRESSION_DEPTH_BITPOS 28
+#define QAT_COMPRESSION_DEPTH_MASK 0x7
+#define QAT_COMPRESSION_FILE_TYPE_BITPOS 24
+#define QAT_COMPRESSION_FILE_TYPE_MASK 0xF
+
+#define ICP_QAT_HW_COMPRESSION_CONFIG_BUILD( \
+ dir, delayed, algo, depth, filetype) \
+ ((((dir) & QAT_COMPRESSION_DIR_MASK) << QAT_COMPRESSION_DIR_BITPOS) | \
+ (((delayed) & QAT_COMPRESSION_DELAYED_MATCH_MASK) \
+ << QAT_COMPRESSION_DELAYED_MATCH_BITPOS) | \
+ (((algo) & QAT_COMPRESSION_ALGO_MASK) \
+ << QAT_COMPRESSION_ALGO_BITPOS) | \
+ (((depth) & QAT_COMPRESSION_DEPTH_MASK) \
+ << QAT_COMPRESSION_DEPTH_BITPOS) | \
+ (((filetype) & QAT_COMPRESSION_FILE_TYPE_MASK) \
+ << QAT_COMPRESSION_FILE_TYPE_BITPOS))
+
#endif
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v6 02/16] compress/qat: add makefiles for PMD
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 " Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 " Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 01/16] common/qat: updated firmware headers Fiona Trahe
@ 2018-07-12 16:04 ` Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 03/16] compress/qat: add meson build Fiona Trahe
` (13 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-12 16:04 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add Makefiles, directory and empty source files for compression PMD.
Handle cases for building either symmetric crypto PMD
or compression PMD or both and the common files both depend on.
Change-Id: Ic162d05db77e3421311c7bc364e0da69be7f797c
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
MAINTAINERS | 4 ++++
config/common_base | 3 ++-
drivers/common/qat/Makefile | 45 ++++++++++++++++++++++++-------------
drivers/compress/qat/qat_comp.c | 5 +++++
drivers/compress/qat/qat_comp.h | 14 ++++++++++++
drivers/compress/qat/qat_comp_pmd.c | 5 +++++
drivers/compress/qat/qat_comp_pmd.h | 15 +++++++++++++
mk/rte.app.mk | 5 ++++-
test/test/test_cryptodev.c | 6 ++---
9 files changed, 81 insertions(+), 21 deletions(-)
create mode 100644 drivers/compress/qat/qat_comp.c
create mode 100644 drivers/compress/qat/qat_comp.h
create mode 100644 drivers/compress/qat/qat_comp_pmd.c
create mode 100644 drivers/compress/qat/qat_comp_pmd.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 4d508de..412fd77 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -853,6 +853,10 @@ F: drivers/compress/isal/
F: doc/guides/compressdevs/isal.rst
F: doc/guides/compressdevs/features/isal.ini
+Intel QuickAssist
+M: Fiona Trahe <fiona.trahe@intel.com>
+F: drivers/compress/qat/
+F: drivers/common/qat/
Eventdev Drivers
----------------
diff --git a/config/common_base b/config/common_base
index c305a77..8b539af 100644
--- a/config/common_base
+++ b/config/common_base
@@ -480,7 +480,8 @@ CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4
#
# Compile PMD for QuickAssist based devices
#
-CONFIG_RTE_LIBRTE_PMD_QAT=n
+CONFIG_RTE_LIBRTE_PMD_QAT=y
+CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
#
# Max. number of QuickAssist devices, which can be detected and attached
#
diff --git a/drivers/common/qat/Makefile b/drivers/common/qat/Makefile
index 02e83f9..6ec0bd3 100644
--- a/drivers/common/qat/Makefile
+++ b/drivers/common/qat/Makefile
@@ -3,33 +3,28 @@
include $(RTE_SDK)/mk/rte.vars.mk
-# library name
-LIB = librte_pmd_qat.a
-
-# library version
-LIBABIVER := 1
-
-# build flags
-CFLAGS += $(WERROR_FLAGS)
-CFLAGS += -O3
-
# build directories
QAT_CRYPTO_DIR := $(RTE_SDK)/drivers/crypto/qat
-VPATH=$(QAT_CRYPTO_DIR)
+QAT_COMPRESS_DIR := $(RTE_SDK)/drivers/compress/qat
+VPATH=$(QAT_CRYPTO_DIR):$(QAT_COMPRESS_DIR)
# external library include paths
CFLAGS += -I$(SRCDIR)/qat_adf
CFLAGS += -I$(SRCDIR)
CFLAGS += -I$(QAT_CRYPTO_DIR)
+CFLAGS += -I$(QAT_COMPRESS_DIR)
-# library common source files
-SRCS-y += qat_device.c
-SRCS-y += qat_common.c
-SRCS-y += qat_logs.c
-SRCS-y += qat_qp.c
+
+ifeq ($(CONFIG_RTE_LIBRTE_COMPRESSDEV),y)
+ CFLAGS += -DALLOW_EXPERIMENTAL_API
+ LDLIBS += -lrte_compressdev
+ SRCS-y += qat_comp.c
+ SRCS-y += qat_comp_pmd.c
+endif
# library symmetric crypto source files
ifeq ($(CONFIG_RTE_LIBRTE_CRYPTODEV),y)
+ifeq ($(CONFIG_RTE_LIBRTE_PMD_QAT_SYM),y)
LDLIBS += -lrte_cryptodev
LDLIBS += -lcrypto
CFLAGS += -DBUILD_QAT_SYM
@@ -37,6 +32,23 @@ ifeq ($(CONFIG_RTE_LIBRTE_CRYPTODEV),y)
SRCS-y += qat_sym_session.c
SRCS-y += qat_sym_pmd.c
endif
+endif
+
+
+# library name
+LIB = librte_pmd_qat.a
+
+# library version
+LIBABIVER := 1
+# build flags
+CFLAGS += $(WERROR_FLAGS)
+CFLAGS += -O3
+
+# library common source files
+SRCS-y += qat_device.c
+SRCS-y += qat_common.c
+SRCS-y += qat_logs.c
+SRCS-y += qat_qp.c
LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool
LDLIBS += -lrte_pci -lrte_bus_pci
@@ -47,4 +59,5 @@ SYMLINK-y-include +=
# versioning export map
EXPORT_MAP := ../../crypto/qat/rte_pmd_qat_version.map
+
include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
new file mode 100644
index 0000000..caa1158
--- /dev/null
+++ b/drivers/compress/qat/qat_comp.c
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Intel Corporation
+ */
+
+#include "qat_comp.h"
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
new file mode 100644
index 0000000..89c475e
--- /dev/null
+++ b/drivers/compress/qat/qat_comp.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+
+#ifndef _QAT_COMP_H_
+#define _QAT_COMP_H_
+
+#ifdef RTE_LIBRTE_COMPRESSDEV
+
+#include <rte_compressdev.h>
+#include <rte_compressdev_pmd.h>
+
+#endif
+#endif
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
new file mode 100644
index 0000000..fb035d1
--- /dev/null
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+
+#include "qat_comp_pmd.h"
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
new file mode 100644
index 0000000..9b5b543
--- /dev/null
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+
+#ifndef _QAT_COMP_PMD_H_
+#define _QAT_COMP_PMD_H_
+
+#ifdef RTE_LIBRTE_COMPRESSDEV
+
+#include <rte_compressdev.h>
+#include <rte_compressdev_pmd.h>
+
+
+#endif
+#endif /* _QAT_COMP_PMD_H_ */
diff --git a/mk/rte.app.mk b/mk/rte.app.mk
index 7bcf630..b449e81 100644
--- a/mk/rte.app.mk
+++ b/mk/rte.app.mk
@@ -182,6 +182,9 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += -L$(FLEXRAN_SDK)/lib_common -
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += -lirc -limf -lstdc++ -lipps
endif # CONFIG_RTE_LIBRTE_BBDEV
+# alway load the base QAT lib
+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += -lrte_pmd_qat
+
ifeq ($(CONFIG_RTE_LIBRTE_CRYPTODEV),y)
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_MB) += -lrte_pmd_aesni_mb
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_MB) += -lIPSec_MB
@@ -190,7 +193,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_GCM) += -lIPSec_MB
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += -lrte_pmd_ccp -lcrypto
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OPENSSL) += -lrte_pmd_openssl -lcrypto
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO) += -lrte_pmd_null_crypto
-_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += -lrte_pmd_qat -lcrypto
+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_QAT_SYM) += -lcrypto
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += -lrte_pmd_snow3g
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += -L$(LIBSSO_SNOW3G_PATH)/build -lsso_snow3g
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_KASUMI) += -lrte_pmd_kasumi
diff --git a/test/test/test_cryptodev.c b/test/test/test_cryptodev.c
index b759e08..cbbdb15 100644
--- a/test/test/test_cryptodev.c
+++ b/test/test/test_cryptodev.c
@@ -9938,9 +9938,9 @@ test_cryptodev_qat(void /*argv __rte_unused, int argc __rte_unused*/)
RTE_STR(CRYPTODEV_NAME_QAT_SYM_PMD));
if (gbl_driver_id == -1) {
- RTE_LOG(ERR, USER1, "QAT PMD must be loaded. Check if "
- "CONFIG_RTE_LIBRTE_PMD_QAT is enabled "
- "in config file to run this testsuite.\n");
+ RTE_LOG(ERR, USER1, "QAT PMD must be loaded. Check that both "
+ "CONFIG_RTE_LIBRTE_PMD_QAT and CONFIG_RTE_LIBRTE_PMD_QAT_SYM "
+ "are enabled in config file to run this testsuite.\n");
return TEST_SKIPPED;
}
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v6 03/16] compress/qat: add meson build
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 " Fiona Trahe
` (2 preceding siblings ...)
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 02/16] compress/qat: add makefiles for PMD Fiona Trahe
@ 2018-07-12 16:04 ` Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 04/16] compress/qat: add xform processing Fiona Trahe
` (12 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-12 16:04 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add meson build files.
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
drivers/common/qat/Makefile | 2 +-
drivers/compress/meson.build | 2 +-
drivers/compress/qat/meson.build | 18 ++++++++++++++++++
drivers/compress/qat/rte_pmd_qat_version.map | 3 +++
drivers/crypto/qat/meson.build | 10 ++--------
drivers/crypto/qat/rte_pmd_qat_version.map | 3 ---
6 files changed, 25 insertions(+), 13 deletions(-)
create mode 100644 drivers/compress/qat/meson.build
create mode 100644 drivers/compress/qat/rte_pmd_qat_version.map
delete mode 100644 drivers/crypto/qat/rte_pmd_qat_version.map
diff --git a/drivers/common/qat/Makefile b/drivers/common/qat/Makefile
index 6ec0bd3..e23f727 100644
--- a/drivers/common/qat/Makefile
+++ b/drivers/common/qat/Makefile
@@ -57,7 +57,7 @@ LDLIBS += -lrte_pci -lrte_bus_pci
SYMLINK-y-include +=
# versioning export map
-EXPORT_MAP := ../../crypto/qat/rte_pmd_qat_version.map
+EXPORT_MAP := ../../compress/qat/rte_pmd_qat_version.map
include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/compress/meson.build b/drivers/compress/meson.build
index fb136e1..2352ad5 100644
--- a/drivers/compress/meson.build
+++ b/drivers/compress/meson.build
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2018 Intel Corporation
-drivers = ['isal']
+drivers = ['isal', 'qat']
std_deps = ['compressdev'] # compressdev pulls in all other needed deps
config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'
diff --git a/drivers/compress/qat/meson.build b/drivers/compress/qat/meson.build
new file mode 100644
index 0000000..9d15076
--- /dev/null
+++ b/drivers/compress/qat/meson.build
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2017-2018 Intel Corporation
+
+
+# Add our sources files to the list
+allow_experimental_apis = true
+qat_sources += files('qat_comp_pmd.c',
+ 'qat_comp.c')
+qat_includes += include_directories('.')
+qat_deps += 'compressdev'
+qat_ext_deps += dep
+
+# build the whole driver
+sources += qat_sources
+cflags += qat_cflags
+deps += qat_deps
+ext_deps += qat_ext_deps
+includes += qat_includes
diff --git a/drivers/compress/qat/rte_pmd_qat_version.map b/drivers/compress/qat/rte_pmd_qat_version.map
new file mode 100644
index 0000000..ad6e191
--- /dev/null
+++ b/drivers/compress/qat/rte_pmd_qat_version.map
@@ -0,0 +1,3 @@
+DPDK_18.08 {
+ local: *;
+};
diff --git a/drivers/crypto/qat/meson.build b/drivers/crypto/qat/meson.build
index 2873637..d7cff68 100644
--- a/drivers/crypto/qat/meson.build
+++ b/drivers/crypto/qat/meson.build
@@ -1,6 +1,8 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017-2018 Intel Corporation
+# this does not build the QAT driver, instead that is done in the compression
+# driver which comes later. Here we just add our sources files to the list
build = false
dep = dependency('libcrypto', required: false)
if dep.found()
@@ -13,12 +15,4 @@ if dep.found()
qat_ext_deps += dep
pkgconfig_extra_libs += '-lcrypto'
qat_cflags += '-DBUILD_QAT_SYM'
-
- # build the whole driver
- sources += qat_sources
- cflags += qat_cflags
- deps += qat_deps
- ext_deps += qat_ext_deps
- includes += qat_includes
- build = true
endif
diff --git a/drivers/crypto/qat/rte_pmd_qat_version.map b/drivers/crypto/qat/rte_pmd_qat_version.map
deleted file mode 100644
index bbaf1c8..0000000
--- a/drivers/crypto/qat/rte_pmd_qat_version.map
+++ /dev/null
@@ -1,3 +0,0 @@
-DPDK_2.2 {
- local: *;
-};
\ No newline at end of file
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v6 04/16] compress/qat: add xform processing
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 " Fiona Trahe
` (3 preceding siblings ...)
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 03/16] compress/qat: add meson build Fiona Trahe
@ 2018-07-12 16:04 ` Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 05/16] compress/qat: create fw request and process response Fiona Trahe
` (11 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-12 16:04 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add code to process compressdev rte_comp_xforms, creating
private qat_comp_xforms with prepared firmware message templates.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp.c | 239 ++++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp.h | 30 +++++
drivers/compress/qat/qat_comp_pmd.h | 16 +++
3 files changed, 285 insertions(+)
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index caa1158..cb2005a 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -2,4 +2,243 @@
* Copyright(c) 2018 Intel Corporation
*/
+
+#include <rte_mempool.h>
+#include <rte_mbuf.h>
+#include <rte_hexdump.h>
+#include <rte_comp.h>
+#include <rte_bus_pci.h>
+#include <rte_byteorder.h>
+#include <rte_memcpy.h>
+#include <rte_common.h>
+#include <rte_spinlock.h>
+#include <rte_log.h>
+#include <rte_malloc.h>
+
+#include "qat_logs.h"
#include "qat_comp.h"
+#include "qat_comp_pmd.h"
+
+unsigned int
+qat_comp_xform_size(void)
+{
+ return RTE_ALIGN_CEIL(sizeof(struct qat_comp_xform), 8);
+}
+
+static void qat_comp_create_req_hdr(struct icp_qat_fw_comn_req_hdr *header,
+ enum qat_comp_request_type request)
+{
+ if (request == QAT_COMP_REQUEST_FIXED_COMP_STATELESS)
+ header->service_cmd_id = ICP_QAT_FW_COMP_CMD_STATIC;
+ else if (request == QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS)
+ header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DYNAMIC;
+ else if (request == QAT_COMP_REQUEST_DECOMPRESS)
+ header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DECOMPRESS;
+
+ header->service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_COMP;
+ header->hdr_flags =
+ ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
+
+ header->comn_req_flags = ICP_QAT_FW_COMN_FLAGS_BUILD(
+ QAT_COMN_CD_FLD_TYPE_16BYTE_DATA, QAT_COMN_PTR_TYPE_FLAT);
+}
+
+static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,
+ const struct rte_memzone *interm_buff_mz __rte_unused,
+ const struct rte_comp_xform *xform)
+{
+ struct icp_qat_fw_comp_req *comp_req;
+ int comp_level, algo;
+ uint32_t req_par_flags;
+ int direction = ICP_QAT_HW_COMPRESSION_DIR_COMPRESS;
+
+ if (unlikely(qat_xform == NULL)) {
+ QAT_LOG(ERR, "Session was not created for this device");
+ return -EINVAL;
+ }
+
+ if (qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS) {
+ direction = ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS;
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_1;
+ req_par_flags = ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(
+ ICP_QAT_FW_COMP_SOP, ICP_QAT_FW_COMP_EOP,
+ ICP_QAT_FW_COMP_BFINAL, ICP_QAT_FW_COMP_NO_CNV,
+ ICP_QAT_FW_COMP_NO_CNV_RECOVERY);
+
+ } else {
+ if (xform->compress.level == RTE_COMP_LEVEL_PMD_DEFAULT)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_8;
+ else if (xform->compress.level == 1)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_1;
+ else if (xform->compress.level == 2)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_4;
+ else if (xform->compress.level == 3)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_8;
+ else if (xform->compress.level >= 4 &&
+ xform->compress.level <= 9)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_16;
+ else {
+ QAT_LOG(ERR, "compression level not supported");
+ return -EINVAL;
+ }
+ req_par_flags = ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(
+ ICP_QAT_FW_COMP_SOP, ICP_QAT_FW_COMP_EOP,
+ ICP_QAT_FW_COMP_BFINAL, ICP_QAT_FW_COMP_CNV,
+ ICP_QAT_FW_COMP_CNV_RECOVERY);
+ }
+
+ switch (xform->compress.algo) {
+ case RTE_COMP_ALGO_DEFLATE:
+ algo = ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE;
+ break;
+ case RTE_COMP_ALGO_LZS:
+ default:
+ /* RTE_COMP_NULL */
+ QAT_LOG(ERR, "compression algorithm not supported");
+ return -EINVAL;
+ }
+
+ comp_req = &qat_xform->qat_comp_req_tmpl;
+
+ /* Initialize header */
+ qat_comp_create_req_hdr(&comp_req->comn_hdr,
+ qat_xform->qat_comp_request_type);
+
+ comp_req->comn_hdr.serv_specif_flags = ICP_QAT_FW_COMP_FLAGS_BUILD(
+ ICP_QAT_FW_COMP_STATELESS_SESSION,
+ ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST,
+ ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST,
+ ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST,
+ ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_USED_AS_INTMD_BUF);
+
+ comp_req->cd_pars.sl.comp_slice_cfg_word[0] =
+ ICP_QAT_HW_COMPRESSION_CONFIG_BUILD(
+ direction,
+ /* In CPM 1.6 only valid mode ! */
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_ENABLED, algo,
+ /* Translate level to depth */
+ comp_level, ICP_QAT_HW_COMPRESSION_FILE_TYPE_0);
+
+ comp_req->comp_pars.initial_adler = 1;
+ comp_req->comp_pars.initial_crc32 = 0;
+ comp_req->comp_pars.req_par_flags = req_par_flags;
+
+
+ if (qat_xform->qat_comp_request_type ==
+ QAT_COMP_REQUEST_FIXED_COMP_STATELESS ||
+ qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS) {
+ ICP_QAT_FW_COMN_NEXT_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_DRAM_WR);
+ ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_COMP);
+ } else if (qat_xform->qat_comp_request_type ==
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {
+
+ QAT_LOG(ERR, "Dynamic huffman encoding not supported");
+ return -EINVAL;
+ }
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_HEXDUMP_LOG(DEBUG, "qat compression message template:", comp_req,
+ sizeof(struct icp_qat_fw_comp_req));
+#endif
+ return 0;
+}
+
+/**
+ * Create driver private_xform data.
+ *
+ * @param dev
+ * Compressdev device
+ * @param xform
+ * xform data from application
+ * @param private_xform
+ * ptr where handle of pmd's private_xform data should be stored
+ * @return
+ * - if successful returns 0
+ * and valid private_xform handle
+ * - <0 in error cases
+ * - Returns -EINVAL if input parameters are invalid.
+ * - Returns -ENOTSUP if comp device does not support the comp transform.
+ * - Returns -ENOMEM if the private_xform could not be allocated.
+ */
+int
+qat_comp_private_xform_create(struct rte_compressdev *dev,
+ const struct rte_comp_xform *xform,
+ void **private_xform)
+{
+ struct qat_comp_dev_private *qat = dev->data->dev_private;
+
+ if (unlikely(private_xform == NULL)) {
+ QAT_LOG(ERR, "QAT: private_xform parameter is NULL");
+ return -EINVAL;
+ }
+ if (unlikely(qat->xformpool == NULL)) {
+ QAT_LOG(ERR, "QAT device has no private_xform mempool");
+ return -ENOMEM;
+ }
+ if (rte_mempool_get(qat->xformpool, private_xform)) {
+ QAT_LOG(ERR, "Couldn't get object from qat xform mempool");
+ return -ENOMEM;
+ }
+
+ struct qat_comp_xform *qat_xform =
+ (struct qat_comp_xform *)*private_xform;
+
+ if (xform->type == RTE_COMP_COMPRESS) {
+ if (xform->compress.deflate.huffman ==
+ RTE_COMP_HUFFMAN_DYNAMIC) {
+ QAT_LOG(ERR,
+ "QAT device doesn't support dynamic compression");
+ return -ENOTSUP;
+ }
+
+ if (xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_FIXED ||
+ ((xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_DEFAULT)
+ && qat->interm_buff_mz == NULL))
+
+ qat_xform->qat_comp_request_type =
+ QAT_COMP_REQUEST_FIXED_COMP_STATELESS;
+
+
+ } else {
+ qat_xform->qat_comp_request_type = QAT_COMP_REQUEST_DECOMPRESS;
+ }
+
+ qat_xform->checksum_type = xform->compress.chksum;
+
+ if (qat_comp_create_templates(qat_xform, qat->interm_buff_mz, xform)) {
+ QAT_LOG(ERR, "QAT: Problem with setting compression");
+ return -EINVAL;
+ }
+ return 0;
+}
+
+/**
+ * Free driver private_xform data.
+ *
+ * @param dev
+ * Compressdev device
+ * @param private_xform
+ * handle of pmd's private_xform data
+ * @return
+ * - 0 if successful
+ * - <0 in error cases
+ * - Returns -EINVAL if input parameters are invalid.
+ */
+int
+qat_comp_private_xform_free(struct rte_compressdev *dev __rte_unused,
+ void *private_xform)
+{
+ struct qat_comp_xform *qat_xform =
+ (struct qat_comp_xform *)private_xform;
+
+ if (qat_xform) {
+ memset(qat_xform, 0, qat_comp_xform_size());
+ struct rte_mempool *mp = rte_mempool_from_obj(qat_xform);
+
+ rte_mempool_put(mp, qat_xform);
+ return 0;
+ }
+ return -EINVAL;
+}
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 89c475e..0f58a76 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -10,5 +10,35 @@
#include <rte_compressdev.h>
#include <rte_compressdev_pmd.h>
+#include "icp_qat_hw.h"
+#include "icp_qat_fw_comp.h"
+#include "icp_qat_fw_la.h"
+
+enum qat_comp_request_type {
+ QAT_COMP_REQUEST_FIXED_COMP_STATELESS,
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS,
+ QAT_COMP_REQUEST_DECOMPRESS,
+ REQ_COMP_END
+};
+
+
+struct qat_comp_xform {
+ struct icp_qat_fw_comp_req qat_comp_req_tmpl;
+ enum qat_comp_request_type qat_comp_request_type;
+ enum rte_comp_checksum_type checksum_type;
+};
+
+
+int
+qat_comp_private_xform_create(struct rte_compressdev *dev,
+ const struct rte_comp_xform *xform,
+ void **private_xform);
+
+int
+qat_comp_private_xform_free(struct rte_compressdev *dev, void *private_xform);
+
+unsigned int
+qat_comp_xform_size(void);
+
#endif
#endif
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 9b5b543..fd97cbf 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -11,5 +11,21 @@
#include <rte_compressdev_pmd.h>
+/** private data structure for a QAT compression device.
+ * This QAT device is a device offering only a compression service,
+ * there can be one of these on each qat_pci_device (VF).
+ */
+struct qat_comp_dev_private {
+ struct qat_pci_device *qat_dev;
+ /**< The qat pci device hosting the service */
+ struct rte_compressdev *compressdev;
+ /**< The pointer to this compression device structure */
+ const struct rte_memzone *interm_buff_mz;
+ /**< The device's memory for intermediate buffers */
+ struct rte_mempool *xformpool;
+ /**< The device's pool for qat_comp_xforms */
+
+};
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v6 05/16] compress/qat: create fw request and process response
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 " Fiona Trahe
` (4 preceding siblings ...)
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 04/16] compress/qat: add xform processing Fiona Trahe
@ 2018-07-12 16:04 ` Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 06/16] compress/qat: check that correct firmware is in use Fiona Trahe
` (10 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-12 16:04 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add functions to create the request message to send to
firmware and to process the firmware response.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp.c | 101 ++++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp.h | 8 +++
drivers/compress/qat/qat_comp_pmd.h | 1 +
3 files changed, 110 insertions(+)
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index cb2005a..a32d6ef 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -19,6 +19,107 @@
#include "qat_comp.h"
#include "qat_comp_pmd.h"
+
+int
+qat_comp_build_request(void *in_op, uint8_t *out_msg,
+ void *op_cookie __rte_unused,
+ enum qat_device_gen qat_dev_gen __rte_unused)
+{
+ struct rte_comp_op *op = in_op;
+ struct qat_comp_xform *qat_xform = op->private_xform;
+ const uint8_t *tmpl = (uint8_t *)&qat_xform->qat_comp_req_tmpl;
+ struct icp_qat_fw_comp_req *comp_req =
+ (struct icp_qat_fw_comp_req *)out_msg;
+
+ if (unlikely(op->op_type != RTE_COMP_OP_STATELESS)) {
+ QAT_DP_LOG(ERR, "QAT PMD only supports stateless compression "
+ "operation requests, op (%p) is not a "
+ "stateless operation.", op);
+ return -EINVAL;
+ }
+
+ rte_mov128(out_msg, tmpl);
+ comp_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
+
+ /* common for sgl and flat buffers */
+ comp_req->comp_pars.comp_len = op->src.length;
+ comp_req->comp_pars.out_buffer_sz = rte_pktmbuf_pkt_len(op->m_dst);
+
+ /* sgl */
+ if (op->m_src->next != NULL || op->m_dst->next != NULL) {
+ QAT_DP_LOG(ERR, "QAT PMD doesn't support scatter gather");
+ return -EINVAL;
+
+ } else {
+ ICP_QAT_FW_COMN_PTR_TYPE_SET(comp_req->comn_hdr.comn_req_flags,
+ QAT_COMN_PTR_TYPE_FLAT);
+ comp_req->comn_mid.src_length = rte_pktmbuf_data_len(op->m_src);
+ comp_req->comn_mid.dst_length = rte_pktmbuf_data_len(op->m_dst);
+
+ comp_req->comn_mid.src_data_addr =
+ rte_pktmbuf_mtophys_offset(op->m_src, op->src.offset);
+ comp_req->comn_mid.dest_data_addr =
+ rte_pktmbuf_mtophys_offset(op->m_dst, op->dst.offset);
+ }
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_LOG(DEBUG, "Direction: %s",
+ qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS ?
+ "decompression" : "compression");
+ QAT_DP_HEXDUMP_LOG(DEBUG, "qat compression message:", comp_req,
+ sizeof(struct icp_qat_fw_comp_req));
+#endif
+ return 0;
+}
+
+int
+qat_comp_process_response(void **op, uint8_t *resp)
+{
+ struct icp_qat_fw_comp_resp *resp_msg =
+ (struct icp_qat_fw_comp_resp *)resp;
+ struct rte_comp_op *rx_op = (struct rte_comp_op *)(uintptr_t)
+ (resp_msg->opaque_data);
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_LOG(DEBUG, "Direction: %s",
+ qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS ?
+ "decompression" : "compression");
+ QAT_DP_HEXDUMP_LOG(DEBUG, "qat_response:", (uint8_t *)resp_msg,
+ sizeof(struct icp_qat_fw_comp_resp));
+#endif
+
+ if ((ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(resp_msg->comn_resp.comn_status)
+ | ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(
+ resp_msg->comn_resp.comn_status)) !=
+ ICP_QAT_FW_COMN_STATUS_FLAG_OK) {
+
+ rx_op->status = RTE_COMP_OP_STATUS_ERROR;
+ rx_op->debug_status =
+ *((uint16_t *)(&resp_msg->comn_resp.comn_error));
+ } else {
+ struct qat_comp_xform *qat_xform = rx_op->private_xform;
+ struct icp_qat_fw_resp_comp_pars *comp_resp =
+ (struct icp_qat_fw_resp_comp_pars *)&resp_msg->comp_resp_pars;
+
+ rx_op->status = RTE_COMP_OP_STATUS_SUCCESS;
+ rx_op->consumed = comp_resp->input_byte_counter;
+ rx_op->produced = comp_resp->output_byte_counter;
+
+ if (qat_xform->checksum_type != RTE_COMP_CHECKSUM_NONE) {
+ if (qat_xform->checksum_type == RTE_COMP_CHECKSUM_CRC32)
+ rx_op->output_chksum = comp_resp->curr_crc32;
+ else if (qat_xform->checksum_type ==
+ RTE_COMP_CHECKSUM_ADLER32)
+ rx_op->output_chksum = comp_resp->curr_adler_32;
+ else
+ rx_op->output_chksum = comp_resp->curr_chksum;
+ }
+ }
+ *op = (void *)rx_op;
+
+ return 0;
+}
+
unsigned int
qat_comp_xform_size(void)
{
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 0f58a76..46105b4 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -10,6 +10,7 @@
#include <rte_compressdev.h>
#include <rte_compressdev_pmd.h>
+#include "qat_common.h"
#include "icp_qat_hw.h"
#include "icp_qat_fw_comp.h"
#include "icp_qat_fw_la.h"
@@ -28,6 +29,13 @@ struct qat_comp_xform {
enum rte_comp_checksum_type checksum_type;
};
+int
+qat_comp_build_request(void *in_op, uint8_t *out_msg, void *op_cookie,
+ enum qat_device_gen qat_dev_gen __rte_unused);
+
+int
+qat_comp_process_response(void **op, uint8_t *resp);
+
int
qat_comp_private_xform_create(struct rte_compressdev *dev,
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index fd97cbf..cd04f11 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -10,6 +10,7 @@
#include <rte_compressdev.h>
#include <rte_compressdev_pmd.h>
+#include "qat_device.h"
/** private data structure for a QAT compression device.
* This QAT device is a device offering only a compression service,
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v6 06/16] compress/qat: check that correct firmware is in use
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 " Fiona Trahe
` (5 preceding siblings ...)
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 05/16] compress/qat: create fw request and process response Fiona Trahe
@ 2018-07-12 16:04 ` Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 07/16] compress/qat: add stats functions Fiona Trahe
` (9 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-12 16:04 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Check bit in response message to verify that correct firmware
is in use for compression. If not return an error.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp.c | 16 +++++++++++++++-
drivers/compress/qat/qat_comp.h | 2 ++
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index a32d6ef..e8019eb 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -2,7 +2,6 @@
* Copyright(c) 2018 Intel Corporation
*/
-
#include <rte_mempool.h>
#include <rte_mbuf.h>
#include <rte_hexdump.h>
@@ -79,6 +78,8 @@ qat_comp_process_response(void **op, uint8_t *resp)
(struct icp_qat_fw_comp_resp *)resp;
struct rte_comp_op *rx_op = (struct rte_comp_op *)(uintptr_t)
(resp_msg->opaque_data);
+ struct qat_comp_xform *qat_xform = (struct qat_comp_xform *)
+ (rx_op->private_xform);
#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
QAT_DP_LOG(DEBUG, "Direction: %s",
@@ -88,6 +89,19 @@ qat_comp_process_response(void **op, uint8_t *resp)
sizeof(struct icp_qat_fw_comp_resp));
#endif
+ if (likely(qat_xform->qat_comp_request_type
+ != QAT_COMP_REQUEST_DECOMPRESS)) {
+ if (unlikely(ICP_QAT_FW_COMN_HDR_CNV_FLAG_GET(
+ resp_msg->comn_resp.hdr_flags)
+ == ICP_QAT_FW_COMP_NO_CNV)) {
+ rx_op->status = RTE_COMP_OP_STATUS_ERROR;
+ rx_op->debug_status = ERR_CODE_QAT_COMP_WRONG_FW;
+ *op = (void *)rx_op;
+ QAT_DP_LOG(ERR, "QAT has wrong firmware");
+ return 0;
+ }
+ }
+
if ((ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(resp_msg->comn_resp.comn_status)
| ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(
resp_msg->comn_resp.comn_status)) !=
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 46105b4..937f3c8 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -15,6 +15,8 @@
#include "icp_qat_fw_comp.h"
#include "icp_qat_fw_la.h"
+#define ERR_CODE_QAT_COMP_WRONG_FW -99
+
enum qat_comp_request_type {
QAT_COMP_REQUEST_FIXED_COMP_STATELESS,
QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS,
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v6 07/16] compress/qat: add stats functions
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 " Fiona Trahe
` (6 preceding siblings ...)
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 06/16] compress/qat: check that correct firmware is in use Fiona Trahe
@ 2018-07-12 16:04 ` Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 08/16] compress/qat: setup queue-pairs for compression service Fiona Trahe
` (8 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-12 16:04 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add functions to get and clear compression queue-pair statistics.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 35 +++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 7 +++++++
2 files changed, 42 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index fb035d1..6feffb7 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -3,3 +3,38 @@
*/
#include "qat_comp_pmd.h"
+
+void
+qat_comp_stats_get(struct rte_compressdev *dev,
+ struct rte_compressdev_stats *stats)
+{
+ struct qat_common_stats qat_stats = {0};
+ struct qat_comp_dev_private *qat_priv;
+
+ if (stats == NULL || dev == NULL) {
+ QAT_LOG(ERR, "invalid ptr: stats %p, dev %p", stats, dev);
+ return;
+ }
+ qat_priv = dev->data->dev_private;
+
+ qat_stats_get(qat_priv->qat_dev, &qat_stats, QAT_SERVICE_COMPRESSION);
+ stats->enqueued_count = qat_stats.enqueued_count;
+ stats->dequeued_count = qat_stats.dequeued_count;
+ stats->enqueue_err_count = qat_stats.enqueue_err_count;
+ stats->dequeue_err_count = qat_stats.dequeue_err_count;
+}
+
+void
+qat_comp_stats_reset(struct rte_compressdev *dev)
+{
+ struct qat_comp_dev_private *qat_priv;
+
+ if (dev == NULL) {
+ QAT_LOG(ERR, "invalid compressdev ptr %p", dev);
+ return;
+ }
+ qat_priv = dev->data->dev_private;
+
+ qat_stats_reset(qat_priv->qat_dev, QAT_SERVICE_COMPRESSION);
+
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index cd04f11..27d84c8 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -28,5 +28,12 @@ struct qat_comp_dev_private {
};
+void
+qat_comp_stats_reset(struct rte_compressdev *dev);
+
+void
+qat_comp_stats_get(struct rte_compressdev *dev,
+ struct rte_compressdev_stats *stats);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v6 08/16] compress/qat: setup queue-pairs for compression service
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 " Fiona Trahe
` (7 preceding siblings ...)
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 07/16] compress/qat: add stats functions Fiona Trahe
@ 2018-07-12 16:04 ` Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 09/16] compress/qat: add fns to configure and clear device Fiona Trahe
` (7 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-12 16:04 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Setup and clear queue-pairs for handling compression
requests and responses.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp.h | 2 ++
drivers/compress/qat/qat_comp_pmd.c | 61 +++++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 6 ++++
3 files changed, 69 insertions(+)
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 937f3c8..9e6861b 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -24,6 +24,8 @@ enum qat_comp_request_type {
REQ_COMP_END
};
+struct qat_comp_op_cookie {
+};
struct qat_comp_xform {
struct icp_qat_fw_comp_req qat_comp_req_tmpl;
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 6feffb7..5ae6caf 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -2,6 +2,7 @@
* Copyright(c) 2015-2018 Intel Corporation
*/
+#include "qat_comp.h"
#include "qat_comp_pmd.h"
void
@@ -38,3 +39,63 @@ qat_comp_stats_reset(struct rte_compressdev *dev)
qat_stats_reset(qat_priv->qat_dev, QAT_SERVICE_COMPRESSION);
}
+
+int
+qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)
+{
+ struct qat_comp_dev_private *qat_private = dev->data->dev_private;
+
+ QAT_LOG(DEBUG, "Release comp qp %u on device %d",
+ queue_pair_id, dev->data->dev_id);
+
+ qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][queue_pair_id]
+ = NULL;
+
+ return qat_qp_release((struct qat_qp **)
+ &(dev->data->queue_pairs[queue_pair_id]));
+}
+
+int
+qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
+ uint32_t max_inflight_ops, int socket_id)
+{
+ int ret = 0;
+ struct qat_qp_config qat_qp_conf;
+
+ struct qat_qp **qp_addr =
+ (struct qat_qp **)&(dev->data->queue_pairs[qp_id]);
+ struct qat_comp_dev_private *qat_private = dev->data->dev_private;
+ const struct qat_qp_hw_data *comp_hw_qps =
+ qat_gen_config[qat_private->qat_dev->qat_dev_gen]
+ .qp_hw_data[QAT_SERVICE_COMPRESSION];
+ const struct qat_qp_hw_data *qp_hw_data = comp_hw_qps + qp_id;
+
+ /* If qp is already in use free ring memory and qp metadata. */
+ if (*qp_addr != NULL) {
+ ret = qat_comp_qp_release(dev, qp_id);
+ if (ret < 0)
+ return ret;
+ }
+ if (qp_id >= qat_qps_per_service(comp_hw_qps,
+ QAT_SERVICE_COMPRESSION)) {
+ QAT_LOG(ERR, "qp_id %u invalid for this device", qp_id);
+ return -EINVAL;
+ }
+
+ qat_qp_conf.hw = qp_hw_data;
+ qat_qp_conf.build_request = qat_comp_build_request;
+ qat_qp_conf.cookie_size = sizeof(struct qat_comp_op_cookie);
+ qat_qp_conf.nb_descriptors = max_inflight_ops;
+ qat_qp_conf.socket_id = socket_id;
+ qat_qp_conf.service_str = "comp";
+
+ ret = qat_qp_setup(qat_private->qat_dev, qp_addr, qp_id, &qat_qp_conf);
+ if (ret != 0)
+ return ret;
+
+ /* store a link to the qp in the qat_pci_device */
+ qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][qp_id]
+ = *qp_addr;
+
+ return ret;
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 27d84c8..5a4bc31 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -34,6 +34,12 @@ qat_comp_stats_reset(struct rte_compressdev *dev);
void
qat_comp_stats_get(struct rte_compressdev *dev,
struct rte_compressdev_stats *stats);
+int
+qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id);
+
+int
+qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
+ uint32_t max_inflight_ops, int socket_id);
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v6 09/16] compress/qat: add fns to configure and clear device
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 " Fiona Trahe
` (8 preceding siblings ...)
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 08/16] compress/qat: setup queue-pairs for compression service Fiona Trahe
@ 2018-07-12 16:04 ` Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 10/16] compress/qat: add fn to return device info Fiona Trahe
` (6 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-12 16:04 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add functions to configure and clear the qat comp device,
including the creation and freeing of the xform pool
and the freeing of queue-pairs.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 95 +++++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 7 +++
2 files changed, 102 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 5ae6caf..beab6e3 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -99,3 +99,98 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
return ret;
}
+
+static struct rte_mempool *
+qat_comp_create_xform_pool(struct qat_comp_dev_private *comp_dev,
+ uint32_t num_elements)
+{
+ char xform_pool_name[RTE_MEMPOOL_NAMESIZE];
+ struct rte_mempool *mp;
+
+ snprintf(xform_pool_name, RTE_MEMPOOL_NAMESIZE,
+ "%s_xforms", comp_dev->qat_dev->name);
+
+ QAT_LOG(DEBUG, "xformpool: %s", xform_pool_name);
+ mp = rte_mempool_lookup(xform_pool_name);
+
+ if (mp != NULL) {
+ QAT_LOG(DEBUG, "xformpool already created");
+ if (mp->size != num_elements) {
+ QAT_LOG(DEBUG, "xformpool wrong size - delete it");
+ rte_mempool_free(mp);
+ mp = NULL;
+ comp_dev->xformpool = NULL;
+ }
+ }
+
+ if (mp == NULL)
+ mp = rte_mempool_create(xform_pool_name,
+ num_elements,
+ qat_comp_xform_size(), 0, 0,
+ NULL, NULL, NULL, NULL, rte_socket_id(),
+ 0);
+ if (mp == NULL) {
+ QAT_LOG(ERR, "Err creating mempool %s w %d elements of size %d",
+ xform_pool_name, num_elements, qat_comp_xform_size());
+ return NULL;
+ }
+
+ return mp;
+}
+
+static void
+_qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)
+{
+ /* Free private_xform pool */
+ if (comp_dev->xformpool) {
+ /* Free internal mempool for private xforms */
+ rte_mempool_free(comp_dev->xformpool);
+ comp_dev->xformpool = NULL;
+ }
+}
+
+int
+qat_comp_dev_config(struct rte_compressdev *dev,
+ struct rte_compressdev_config *config)
+{
+ struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
+ int ret = 0;
+
+ if (config->max_nb_streams != 0) {
+ QAT_LOG(ERR,
+ "QAT device does not support STATEFUL so max_nb_streams must be 0");
+ return -EINVAL;
+ }
+
+ comp_dev->xformpool = qat_comp_create_xform_pool(comp_dev,
+ config->max_nb_priv_xforms);
+ if (comp_dev->xformpool == NULL) {
+
+ ret = -ENOMEM;
+ goto error_out;
+ }
+ return 0;
+
+error_out:
+ _qat_comp_dev_config_clear(comp_dev);
+ return ret;
+}
+
+
+int
+qat_comp_dev_close(struct rte_compressdev *dev)
+{
+ int i;
+ int ret = 0;
+ struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
+
+ for (i = 0; i < dev->data->nb_queue_pairs; i++) {
+ ret = qat_comp_qp_release(dev, i);
+ if (ret < 0)
+ return ret;
+ }
+
+ _qat_comp_dev_config_clear(comp_dev);
+
+ return ret;
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 5a4bc31..b10a66f 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -41,5 +41,12 @@ int
qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
uint32_t max_inflight_ops, int socket_id);
+int
+qat_comp_dev_config(struct rte_compressdev *dev,
+ struct rte_compressdev_config *config);
+
+int
+qat_comp_dev_close(struct rte_compressdev *dev);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v6 10/16] compress/qat: add fn to return device info
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 " Fiona Trahe
` (9 preceding siblings ...)
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 09/16] compress/qat: add fns to configure and clear device Fiona Trahe
@ 2018-07-12 16:04 ` Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 11/16] compress/qat: add enqueue/dequeue functions Fiona Trahe
` (5 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-12 16:04 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Add capabilities pointer to internal qat comp device
and function to return this and other info.
C
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 19 +++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 6 ++++++
2 files changed, 25 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index beab6e3..482ebd1 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -194,3 +194,22 @@ qat_comp_dev_close(struct rte_compressdev *dev)
return ret;
}
+
+
+void
+qat_comp_dev_info_get(struct rte_compressdev *dev,
+ struct rte_compressdev_info *info)
+{
+ struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
+ const struct qat_qp_hw_data *comp_hw_qps =
+ qat_gen_config[comp_dev->qat_dev->qat_dev_gen]
+ .qp_hw_data[QAT_SERVICE_COMPRESSION];
+
+ if (info != NULL) {
+ info->max_nb_queue_pairs =
+ qat_qps_per_service(comp_hw_qps,
+ QAT_SERVICE_COMPRESSION);
+ info->feature_flags = dev->feature_flags;
+ info->capabilities = comp_dev->qat_dev_capabilities;
+ }
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index b10a66f..22576f4 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -21,6 +21,8 @@ struct qat_comp_dev_private {
/**< The qat pci device hosting the service */
struct rte_compressdev *compressdev;
/**< The pointer to this compression device structure */
+ const struct rte_compressdev_capabilities *qat_dev_capabilities;
+ /* QAT device compression capabilities */
const struct rte_memzone *interm_buff_mz;
/**< The device's memory for intermediate buffers */
struct rte_mempool *xformpool;
@@ -48,5 +50,9 @@ qat_comp_dev_config(struct rte_compressdev *dev,
int
qat_comp_dev_close(struct rte_compressdev *dev);
+void
+qat_comp_dev_info_get(struct rte_compressdev *dev,
+ struct rte_compressdev_info *info);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v6 11/16] compress/qat: add enqueue/dequeue functions
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 " Fiona Trahe
` (10 preceding siblings ...)
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 10/16] compress/qat: add fn to return device info Fiona Trahe
@ 2018-07-12 16:04 ` Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 12/16] compress/qat: add device start and stop fns Fiona Trahe
` (4 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-12 16:04 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Wrap generic qat enqueue/dequeue functions with
compressdev enqueue and dequeue fns.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 14 ++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 8 ++++++++
2 files changed, 22 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 482ebd1..086b6cf 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -213,3 +213,17 @@ qat_comp_dev_info_get(struct rte_compressdev *dev,
info->capabilities = comp_dev->qat_dev_capabilities;
}
}
+
+uint16_t
+qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops)
+{
+ return qat_enqueue_op_burst(qp, (void **)ops, nb_ops);
+}
+
+uint16_t
+qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops)
+{
+ return qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 22576f4..f360c29 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -54,5 +54,13 @@ void
qat_comp_dev_info_get(struct rte_compressdev *dev,
struct rte_compressdev_info *info);
+uint16_t
+qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops);
+
+uint16_t
+qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v6 12/16] compress/qat: add device start and stop fns
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 " Fiona Trahe
` (11 preceding siblings ...)
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 11/16] compress/qat: add enqueue/dequeue functions Fiona Trahe
@ 2018-07-12 16:04 ` Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 13/16] compress/qat: create and populate the ops structure Fiona Trahe
` (3 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-12 16:04 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
There are no specific actions needed to start/stop a QAT comp device
so these are just trivial fns to satisfy the pmd API.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 11 +++++++++++
drivers/compress/qat/qat_comp_pmd.h | 6 ++++++
2 files changed, 17 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 086b6cf..1ab5cf7 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -176,6 +176,17 @@ qat_comp_dev_config(struct rte_compressdev *dev,
return ret;
}
+int
+qat_comp_dev_start(struct rte_compressdev *dev __rte_unused)
+{
+ return 0;
+}
+
+void
+qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused)
+{
+
+}
int
qat_comp_dev_close(struct rte_compressdev *dev)
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index f360c29..22cbefb 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -62,5 +62,11 @@ uint16_t
qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops);
+int
+qat_comp_dev_start(struct rte_compressdev *dev __rte_unused);
+
+void
+qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v6 13/16] compress/qat: create and populate the ops structure
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 " Fiona Trahe
` (12 preceding siblings ...)
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 12/16] compress/qat: add device start and stop fns Fiona Trahe
@ 2018-07-12 16:04 ` Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 14/16] compress/qat: add fns to create and destroy the PMD Fiona Trahe
` (2 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-12 16:04 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Create an ops structure and populate it with the
qat-specific functions.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 38 ++++++++++++++++++++++++++++---------
drivers/compress/qat/qat_comp_pmd.h | 30 -----------------------------
2 files changed, 29 insertions(+), 39 deletions(-)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 1ab5cf7..013ff6e 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -5,7 +5,7 @@
#include "qat_comp.h"
#include "qat_comp_pmd.h"
-void
+static void
qat_comp_stats_get(struct rte_compressdev *dev,
struct rte_compressdev_stats *stats)
{
@@ -25,7 +25,7 @@ qat_comp_stats_get(struct rte_compressdev *dev,
stats->dequeue_err_count = qat_stats.dequeue_err_count;
}
-void
+static void
qat_comp_stats_reset(struct rte_compressdev *dev)
{
struct qat_comp_dev_private *qat_priv;
@@ -40,7 +40,7 @@ qat_comp_stats_reset(struct rte_compressdev *dev)
}
-int
+static int
qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)
{
struct qat_comp_dev_private *qat_private = dev->data->dev_private;
@@ -55,7 +55,7 @@ qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)
&(dev->data->queue_pairs[queue_pair_id]));
}
-int
+static int
qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
uint32_t max_inflight_ops, int socket_id)
{
@@ -149,7 +149,7 @@ _qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)
}
}
-int
+static int
qat_comp_dev_config(struct rte_compressdev *dev,
struct rte_compressdev_config *config)
{
@@ -176,19 +176,19 @@ qat_comp_dev_config(struct rte_compressdev *dev,
return ret;
}
-int
+static int
qat_comp_dev_start(struct rte_compressdev *dev __rte_unused)
{
return 0;
}
-void
+static void
qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused)
{
}
-int
+static int
qat_comp_dev_close(struct rte_compressdev *dev)
{
int i;
@@ -207,7 +207,7 @@ qat_comp_dev_close(struct rte_compressdev *dev)
}
-void
+static void
qat_comp_dev_info_get(struct rte_compressdev *dev,
struct rte_compressdev_info *info)
{
@@ -238,3 +238,23 @@ qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
{
return qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
}
+
+
+struct rte_compressdev_ops compress_qat_ops = {
+
+ /* Device related operations */
+ .dev_configure = qat_comp_dev_config,
+ .dev_start = qat_comp_dev_start,
+ .dev_stop = qat_comp_dev_stop,
+ .dev_close = qat_comp_dev_close,
+ .dev_infos_get = qat_comp_dev_info_get,
+
+ .stats_get = qat_comp_stats_get,
+ .stats_reset = qat_comp_stats_reset,
+ .queue_pair_setup = qat_comp_qp_setup,
+ .queue_pair_release = qat_comp_qp_release,
+
+ /* Compression related operations */
+ .private_xform_create = qat_comp_private_xform_create,
+ .private_xform_free = qat_comp_private_xform_free
+};
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 22cbefb..7ba1b8d 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -30,30 +30,6 @@ struct qat_comp_dev_private {
};
-void
-qat_comp_stats_reset(struct rte_compressdev *dev);
-
-void
-qat_comp_stats_get(struct rte_compressdev *dev,
- struct rte_compressdev_stats *stats);
-int
-qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id);
-
-int
-qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
- uint32_t max_inflight_ops, int socket_id);
-
-int
-qat_comp_dev_config(struct rte_compressdev *dev,
- struct rte_compressdev_config *config);
-
-int
-qat_comp_dev_close(struct rte_compressdev *dev);
-
-void
-qat_comp_dev_info_get(struct rte_compressdev *dev,
- struct rte_compressdev_info *info);
-
uint16_t
qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops);
@@ -62,11 +38,5 @@ uint16_t
qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops);
-int
-qat_comp_dev_start(struct rte_compressdev *dev __rte_unused);
-
-void
-qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused);
-
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v6 14/16] compress/qat: add fns to create and destroy the PMD
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 " Fiona Trahe
` (13 preceding siblings ...)
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 13/16] compress/qat: create and populate the ops structure Fiona Trahe
@ 2018-07-12 16:04 ` Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 15/16] compress/qat: prevent device usage if incorrect firmware Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 16/16] docs/qat: refactor docs adding compression guide Fiona Trahe
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-12 16:04 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Now that all the device operations are available,
add the functions to create and destroy the pmd.
Called on probe and remove of the qat pci device, these
register the device with the compressdev API
and plug in all the device functionality.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/common/qat/qat_device.h | 4 ++
drivers/common/qat/qat_qp.c | 11 ++++-
drivers/common/qat/qat_qp.h | 5 ++
drivers/compress/qat/qat_comp_pmd.c | 98 +++++++++++++++++++++++++++++++++++--
drivers/compress/qat/qat_comp_pmd.h | 11 ++---
5 files changed, 117 insertions(+), 12 deletions(-)
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index 0cb370c..9599fc5 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -25,6 +25,8 @@
* - runtime data
*/
struct qat_sym_dev_private;
+struct qat_comp_dev_private;
+
struct qat_pci_device {
/* Data used by all services */
@@ -55,6 +57,8 @@ struct qat_pci_device {
*/
/* Data relating to compression service */
+ struct qat_comp_dev_private *comp_dev;
+ /**< link back to compressdev private data */
/* Data relating to asymmetric crypto service */
diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c
index 32c1759..7ca7a45 100644
--- a/drivers/common/qat/qat_qp.c
+++ b/drivers/common/qat/qat_qp.c
@@ -15,6 +15,7 @@
#include "qat_device.h"
#include "qat_qp.h"
#include "qat_sym.h"
+#include "qat_comp.h"
#include "adf_transport_access_macros.h"
@@ -606,8 +607,8 @@ qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
if (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC)
qat_sym_process_response(ops, resp_msg);
- /* add qat_asym_process_response here */
- /* add qat_comp_process_response here */
+ else if (tmp_qp->service_type == QAT_SERVICE_COMPRESSION)
+ qat_comp_process_response(ops, resp_msg);
head = adf_modulo(head + rx_queue->msg_size,
rx_queue->modulo_mask);
@@ -633,3 +634,9 @@ qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
}
return resp_counter;
}
+
+__attribute__((weak)) int
+qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused)
+{
+ return 0;
+}
diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h
index 59db945..69f8a61 100644
--- a/drivers/common/qat/qat_qp.h
+++ b/drivers/common/qat/qat_qp.h
@@ -103,4 +103,9 @@ qat_qp_setup(struct qat_pci_device *qat_dev,
int
qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,
enum qat_service_type service);
+
+/* Needed for weak function*/
+int
+qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused);
+
#endif /* _QAT_QP_H_ */
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 013ff6e..9bb9897 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -5,6 +5,18 @@
#include "qat_comp.h"
#include "qat_comp_pmd.h"
+static const struct rte_compressdev_capabilities qat_comp_gen_capabilities[] = {
+ {/* COMPRESSION - deflate */
+ .algo = RTE_COMP_ALGO_DEFLATE,
+ .comp_feature_flags = RTE_COMP_FF_MULTI_PKT_CHECKSUM |
+ RTE_COMP_FF_CRC32_CHECKSUM |
+ RTE_COMP_FF_ADLER32_CHECKSUM |
+ RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
+ RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
+ RTE_COMP_FF_HUFFMAN_FIXED,
+ .window_size = {.min = 15, .max = 15, .increment = 0} },
+ {RTE_COMP_ALGO_LIST_END, 0, {0, 0, 0} } };
+
static void
qat_comp_stats_get(struct rte_compressdev *dev,
struct rte_compressdev_stats *stats)
@@ -225,14 +237,14 @@ qat_comp_dev_info_get(struct rte_compressdev *dev,
}
}
-uint16_t
+static uint16_t
qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops)
{
return qat_enqueue_op_burst(qp, (void **)ops, nb_ops);
}
-uint16_t
+static uint16_t
qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops)
{
@@ -240,7 +252,7 @@ qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
}
-struct rte_compressdev_ops compress_qat_ops = {
+static struct rte_compressdev_ops compress_qat_ops = {
/* Device related operations */
.dev_configure = qat_comp_dev_config,
@@ -258,3 +270,83 @@ struct rte_compressdev_ops compress_qat_ops = {
.private_xform_create = qat_comp_private_xform_create,
.private_xform_free = qat_comp_private_xform_free
};
+
+int
+qat_comp_dev_create(struct qat_pci_device *qat_pci_dev)
+{
+ if (qat_pci_dev->qat_dev_gen == QAT_GEN1) {
+ QAT_LOG(ERR, "Compression PMD not supported on QAT dh895xcc");
+ return 0;
+ }
+
+ struct rte_compressdev_pmd_init_params init_params = {
+ .name = "",
+ .socket_id = qat_pci_dev->pci_dev->device.numa_node,
+ };
+ char name[RTE_COMPRESSDEV_NAME_MAX_LEN];
+ struct rte_compressdev *compressdev;
+ struct qat_comp_dev_private *comp_dev;
+
+ snprintf(name, RTE_COMPRESSDEV_NAME_MAX_LEN, "%s_%s",
+ qat_pci_dev->name, "comp");
+ QAT_LOG(DEBUG, "Creating QAT COMP device %s", name);
+
+ compressdev = rte_compressdev_pmd_create(name,
+ &qat_pci_dev->pci_dev->device,
+ sizeof(struct qat_comp_dev_private),
+ &init_params);
+
+ if (compressdev == NULL)
+ return -ENODEV;
+
+ compressdev->dev_ops = &compress_qat_ops;
+
+ compressdev->enqueue_burst = qat_comp_pmd_enqueue_op_burst;
+ compressdev->dequeue_burst = qat_comp_pmd_dequeue_op_burst;
+
+ compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
+
+ comp_dev = compressdev->data->dev_private;
+ comp_dev->qat_dev = qat_pci_dev;
+ comp_dev->compressdev = compressdev;
+ qat_pci_dev->comp_dev = comp_dev;
+
+ switch (qat_pci_dev->qat_dev_gen) {
+ case QAT_GEN1:
+ case QAT_GEN2:
+ comp_dev->qat_dev_capabilities = qat_comp_gen_capabilities;
+ break;
+ default:
+ comp_dev->qat_dev_capabilities = qat_comp_gen_capabilities;
+ QAT_LOG(DEBUG,
+ "QAT gen %d capabilities unknown, default to GEN1",
+ qat_pci_dev->qat_dev_gen);
+ break;
+ }
+
+ QAT_LOG(DEBUG,
+ "Created QAT COMP device %s as compressdev instance %d",
+ name, compressdev->data->dev_id);
+ return 0;
+}
+
+int
+qat_comp_dev_destroy(struct qat_pci_device *qat_pci_dev)
+{
+ struct qat_comp_dev_private *comp_dev;
+
+ if (qat_pci_dev == NULL)
+ return -ENODEV;
+
+ comp_dev = qat_pci_dev->comp_dev;
+ if (comp_dev == NULL)
+ return 0;
+
+ /* clean up any resources used by the device */
+ qat_comp_dev_close(comp_dev->compressdev);
+
+ rte_compressdev_pmd_destroy(comp_dev->compressdev);
+ qat_pci_dev->comp_dev = NULL;
+
+ return 0;
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 7ba1b8d..9ad2a28 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -27,16 +27,13 @@ struct qat_comp_dev_private {
/**< The device's memory for intermediate buffers */
struct rte_mempool *xformpool;
/**< The device's pool for qat_comp_xforms */
-
};
-uint16_t
-qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
- uint16_t nb_ops);
+int
+qat_comp_dev_create(struct qat_pci_device *qat_pci_dev);
-uint16_t
-qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
- uint16_t nb_ops);
+int
+qat_comp_dev_destroy(struct qat_pci_device *qat_pci_dev);
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v6 15/16] compress/qat: prevent device usage if incorrect firmware
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 " Fiona Trahe
` (14 preceding siblings ...)
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 14/16] compress/qat: add fns to create and destroy the PMD Fiona Trahe
@ 2018-07-12 16:04 ` Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 16/16] docs/qat: refactor docs adding compression guide Fiona Trahe
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-12 16:04 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Previous check only causes op to fail on dequeue.
This extends so once first fail is detected, application can
no longer enqueue ops to the device and will also get an
appropriate error if trying to reconfigure or setup the device.
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 57 ++++++++++++++++++++++++++++++++++++-
1 file changed, 56 insertions(+), 1 deletion(-)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 9bb9897..0a571b3 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -252,6 +252,61 @@ qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
}
+static uint16_t
+qat_comp_pmd_enq_deq_dummy_op_burst(void *qp __rte_unused,
+ struct rte_comp_op **ops __rte_unused,
+ uint16_t nb_ops __rte_unused)
+{
+ QAT_DP_LOG(ERR, "QAT PMD detected wrong FW version !");
+ return 0;
+}
+
+static struct rte_compressdev_ops compress_qat_dummy_ops = {
+
+ /* Device related operations */
+ .dev_configure = NULL,
+ .dev_start = NULL,
+ .dev_stop = qat_comp_dev_stop,
+ .dev_close = qat_comp_dev_close,
+ .dev_infos_get = NULL,
+
+ .stats_get = NULL,
+ .stats_reset = qat_comp_stats_reset,
+ .queue_pair_setup = NULL,
+ .queue_pair_release = qat_comp_qp_release,
+
+ /* Compression related operations */
+ .private_xform_create = NULL,
+ .private_xform_free = qat_comp_private_xform_free
+};
+
+static uint16_t
+qat_comp_pmd_dequeue_frst_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops)
+{
+ uint16_t ret = qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
+ struct qat_qp *tmp_qp = (struct qat_qp *)qp;
+
+ if (ret) {
+ if ((*ops)->debug_status ==
+ (uint64_t)ERR_CODE_QAT_COMP_WRONG_FW) {
+ tmp_qp->qat_dev->comp_dev->compressdev->enqueue_burst =
+ qat_comp_pmd_enq_deq_dummy_op_burst;
+ tmp_qp->qat_dev->comp_dev->compressdev->dequeue_burst =
+ qat_comp_pmd_enq_deq_dummy_op_burst;
+
+ tmp_qp->qat_dev->comp_dev->compressdev->dev_ops =
+ &compress_qat_dummy_ops;
+ QAT_LOG(ERR, "QAT PMD detected wrong FW version !");
+
+ } else {
+ tmp_qp->qat_dev->comp_dev->compressdev->dequeue_burst =
+ qat_comp_pmd_dequeue_op_burst;
+ }
+ }
+ return ret;
+}
+
static struct rte_compressdev_ops compress_qat_ops = {
/* Device related operations */
@@ -302,7 +357,7 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev)
compressdev->dev_ops = &compress_qat_ops;
compressdev->enqueue_burst = qat_comp_pmd_enqueue_op_burst;
- compressdev->dequeue_burst = qat_comp_pmd_dequeue_op_burst;
+ compressdev->dequeue_burst = qat_comp_pmd_dequeue_frst_op_burst;
compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v6 16/16] docs/qat: refactor docs adding compression guide
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 " Fiona Trahe
` (15 preceding siblings ...)
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 15/16] compress/qat: prevent device usage if incorrect firmware Fiona Trahe
@ 2018-07-12 16:04 ` Fiona Trahe
16 siblings, 0 replies; 106+ messages in thread
From: Fiona Trahe @ 2018-07-12 16:04 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, tomaszx.jozwiak
Extend QAT guide to cover crypto and compression and common
information, particularly about kernel driver dependency.
Update release note.
Update compression feature list for qat.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
config/common_base | 2 +-
doc/guides/compressdevs/features/qat.ini | 24 ++++
doc/guides/compressdevs/index.rst | 1 +
doc/guides/compressdevs/qat_comp.rst | 49 +++++++++
doc/guides/cryptodevs/qat.rst | 183 +++++++++++++++++++++----------
doc/guides/rel_notes/release_18_08.rst | 5 +
6 files changed, 205 insertions(+), 59 deletions(-)
create mode 100644 doc/guides/compressdevs/features/qat.ini
create mode 100644 doc/guides/compressdevs/qat_comp.rst
diff --git a/config/common_base b/config/common_base
index 8b539af..e569b35 100644
--- a/config/common_base
+++ b/config/common_base
@@ -478,7 +478,7 @@ CONFIG_RTE_LIBRTE_PMD_DPAA_SEC=n
CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4
#
-# Compile PMD for QuickAssist based devices
+# Compile PMD for QuickAssist based devices - see docs for details
#
CONFIG_RTE_LIBRTE_PMD_QAT=y
CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
diff --git a/doc/guides/compressdevs/features/qat.ini b/doc/guides/compressdevs/features/qat.ini
new file mode 100644
index 0000000..0d0e21d
--- /dev/null
+++ b/doc/guides/compressdevs/features/qat.ini
@@ -0,0 +1,24 @@
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+; Supported features of 'QAT' compression driver.
+;
+[Features]
+HW Accelerated = Y
+CPU SSE =
+CPU AVX =
+CPU AVX2 =
+CPU AVX512 =
+CPU NEON =
+Stateful =
+Pass-through =
+OOP SGL In SGL Out =
+OOP SGL In LB Out =
+OOP LB In SGL Out =
+Deflate = Y
+LZS =
+Adler32 = Y
+Crc32 = Y
+Adler32&Crc32 = Y
+Fixed = Y
+Dynamic =
diff --git a/doc/guides/compressdevs/index.rst b/doc/guides/compressdevs/index.rst
index bc59ce8..4228768 100644
--- a/doc/guides/compressdevs/index.rst
+++ b/doc/guides/compressdevs/index.rst
@@ -11,3 +11,4 @@ Compression Device Drivers
overview
isal
+ qat_comp
diff --git a/doc/guides/compressdevs/qat_comp.rst b/doc/guides/compressdevs/qat_comp.rst
new file mode 100644
index 0000000..167f816
--- /dev/null
+++ b/doc/guides/compressdevs/qat_comp.rst
@@ -0,0 +1,49 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+ Copyright(c) 2018 Intel Corporation.
+
+Intel(R) QuickAssist (QAT) Compression Poll Mode Driver
+=======================================================
+
+The QAT compression PMD provides poll mode compression & decompression driver
+support for the following hardware accelerator devices:
+
+* ``Intel QuickAssist Technology C62x``
+* ``Intel QuickAssist Technology C3xxx``
+
+
+Features
+--------
+
+QAT compression PMD has support for:
+
+Compression/Decompression algorithm:
+
+ * DEFLATE
+
+Huffman code type:
+
+ * FIXED
+
+Window size support:
+
+ * 32K
+
+Checksum generation:
+
+ * CRC32, Adler and combined checksum
+
+Limitations
+-----------
+
+* Chained mbufs are not yet supported, therefore max data size which can be passed to the PMD in a single mbuf is 64K - 1. If data is larger than this it will need to be split up and sent as multiple operations.
+
+* Compressdev level 0, no compression, is not supported.
+
+* Dynamic Huffman encoding is not yet supported.
+
+Installation
+------------
+
+The QAT compression PMD is built by default with a standard DPDK build.
+
+It depends on a QAT kernel driver, see :ref:`qat_kernel_installation`.
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index b899985..bdc58eb 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -68,12 +68,32 @@ Limitations
* Queue pairs are not thread-safe (that is, within a single queue pair, RX and TX from different lcores is not supported).
-Installation
-------------
+Extra notes on KASUMI F9
+------------------------
+
+When using KASUMI F9 authentication algorithm, the input buffer must be
+constructed according to the 3GPP KASUMI specifications (section 4.4, page 13):
+`<http://cryptome.org/3gpp/35201-900.pdf>`_.
+Input buffer has to have COUNT (4 bytes), FRESH (4 bytes), MESSAGE and DIRECTION (1 bit)
+concatenated. After the DIRECTION bit, a single '1' bit is appended, followed by
+between 0 and 7 '0' bits, so that the total length of the buffer is multiple of 8 bits.
+Note that the actual message can be any length, specified in bits.
-To enable QAT in DPDK, follow the instructions for modifying the compile-time
+Once this buffer is passed this way, when creating the crypto operation,
+length of data to authenticate (op.sym.auth.data.length) must be the length
+of all the items described above, including the padding at the end.
+Also, offset of data to authenticate (op.sym.auth.data.offset)
+must be such that points at the start of the COUNT bytes.
+
+
+Building the DPDK QAT cryptodev PMD
+-----------------------------------
+
+
+To enable QAT crypto in DPDK, follow the instructions for modifying the compile-time
configuration file as described `here <http://dpdk.org/doc/guides/linux_gsg/build_dpdk.html>`_.
+
Quick instructions are as follows:
.. code-block:: console
@@ -81,29 +101,95 @@ Quick instructions are as follows:
cd to the top-level DPDK directory
make config T=x86_64-native-linuxapp-gcc
sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT\)=n,\1=y,' build/.config
+ sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT_SYM\)=n,\1=y,' build/.config
make
-To use the DPDK QAT PMD an SRIOV-enabled QAT kernel driver is required. The VF
-devices exposed by this driver will be used by the QAT PMD. The devices and
-available kernel drivers and device ids are :
+
+.. _qat_kernel_installation:
+
+Dependency on the QAT kernel driver
+-----------------------------------
+
+To use the QAT PMD an SRIOV-enabled QAT kernel driver is required. The VF
+devices created and initialised by this driver will be used by the QAT PMD.
+
+Instructions for installation are below, but first an explanation of the
+relationships between the PF/VF devices and the PMDs visible to
+DPDK applications.
+
+
+Acceleration services - cryptography and compression - are provided to DPDK
+applications via PMDs which register to implement the corresponding
+cryptodev and compressdev APIs.
+
+Each QuickAssist VF device can expose one cryptodev PMD and/or one compressdev PMD.
+These QAT PMDs share the same underlying device and pci-mgmt code, but are
+enumerated independently on their respective APIs and appear as independent
+devices to applications.
+
+.. Note::
+
+ Each VF can only be used by one DPDK process. It is not possible to share
+ the same VF across multiple processes, even if these processes are using
+ different acceleration services.
+
+ Conversely one DPDK process can use one or more QAT VFs and can expose both
+ cryptodev and compressdev instances on each of those VFs.
+
+
+
+Device and driver naming
+------------------------
+
+* The qat cryptodev driver name is "crypto_qat".
+ The rte_cryptodev_devices_get() returns the devices exposed by this driver.
+
+* Each qat crypto device has a unique name, in format
+ <pci bdf>_<service>, e.g. "0000:41:01.0_qat_sym".
+ This name can be passed to rte_cryptodev_get_dev_id() to get the device_id.
+
+.. Note::
+
+ The qat crypto driver name is passed to the dpdk-test-crypto-perf tool in the -devtype parameter.
+
+ The qat crypto device name is in the format of the slave parameter passed to the crypto scheduler.
+
+* The qat compressdev driver name is "comp_qat".
+ The rte_compressdev_devices_get() returns the devices exposed by this driver.
+
+* Each qat compression device has a unique name, in format
+ <pci bdf>_<service>, e.g. "0000:41:01.0_qat_comp".
+ This name can be passed to rte_compressdev_get_dev_id() to get the device_id.
+
+
+Available kernel drivers
+------------------------
+
+Kernel drivers for each device are listed in the following table. Scroll right
+to check that the driver and device supports the servic you require.
+
.. _table_qat_pmds_drivers:
.. table:: QAT device generations, devices and drivers
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | Gen | Device | Driver | Kernel Module | Pci Driver | PF Did | #PFs | Vf Did | VFs/PF |
- +=====+==========+========+===============+============+========+======+========+========+
- | 1 | DH895xCC | 01.org | icp_qa_al | n/a | 435 | 1 | 443 | 32 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | 1 | DH895xCC | 4.4+ | qat_dh895xcc | dh895xcc | 435 | 1 | 443 | 32 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | 2 | C62x | 4.5+ | qat_c62x | c6xx | 37c8 | 3 | 37c9 | 16 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | 2 | C3xxx | 4.5+ | qat_c3xxx | c3xxx | 19e2 | 1 | 19e3 | 16 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | 2 | D15xx | p | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | Gen | Device | Driver/ver | Kernel Module | Pci Driver | PF Did | #PFs | VF Did | VFs/PF | cryptodev | compressdev |
+ +=====+==========+===============+===============+============+========+======+========+========+===========+=============+
+ | 1 | DH895xCC | linux/4.4+ | qat_dh895xcc | dh895xcc | 435 | 1 | 443 | 32 | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | 2 | C62x | linux/4.5+ | qat_c62x | c6xx | 37c8 | 3 | 37c9 | 16 | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | Yes | Yes |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | 2 | C3xxx | linux/4.5+ | qat_c3xxx | c3xxx | 19e2 | 1 | 19e3 | 16 | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | Yes | Yes |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | 2 | D15xx | p | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
The ``Driver`` column indicates either the Linux kernel version in which
@@ -196,9 +282,9 @@ Consult the *Getting Started Guide* at the same URL for further information.
The steps below assume you are:
-* Building on a platform with one ``DH895xCC`` device.
-* Using package ``qatmux.l.2.3.0-34.tgz``.
-* On Fedora21 kernel ``3.17.4-301.fc21.x86_64``.
+* Building on a platform with one ``C62x`` device.
+* Using package ``qat1.7.l.4.2.0-000xx.tar.gz``.
+* On Fedora26 kernel ``4.11.11-300.fc26.x86_64``.
In the BIOS ensure that SRIOV is enabled and VT-d is disabled.
@@ -206,21 +292,30 @@ Uninstall any existing QAT driver, for example by running:
* ``./installer.sh uninstall`` in the directory where originally installed.
-* or ``rmmod qat_dh895xcc; rmmod intel_qat``.
Build and install the SRIOV-enabled QAT driver::
mkdir /QAT
cd /QAT
- # Copy qatmux.l.2.3.0-34.tgz to this location
- tar zxof qatmux.l.2.3.0-34.tgz
+ # Copy the package to this location and unpack
+ tar zxof qat1.7.l.4.2.0-000xx.tar.gz
- export ICP_WITHOUT_IOMMU=1
- ./installer.sh install QAT1.6 host
+ ./configure --enable-icp-sriov=host
+ make install
+
+You can use ``cat /sys/kernel/debug/qat<your device type and bdf>/version/fw`` to confirm the driver is correctly installed and is using firmware version 4.2.0.
+You can use ``lspci -d:37c9`` to confirm the presence of the 16 VF devices available per ``C62x`` PF.
+
+Confirm the driver is correctly installed and is using firmware version 4.2.0::
+
+ cat /sys/kernel/debug/qat<your device type and bdf>/version/fw
+
+
+Confirm the presence of 48 VF devices - 16 per PF::
+
+ lspci -d:37c9
-You can use ``cat /proc/icp_dh895xcc_dev0/version`` to confirm the driver is correctly installed.
-You can use ``lspci -d:443`` to confirm the of the 32 VF devices available per ``DH895xCC`` device.
To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_.
@@ -261,6 +356,7 @@ To complete the installation - follow instructions in `Binding the available VFs
sudo yum install zlib-devel
sudo yum install openssl-devel
+ sudo yum install libudev-devel
.. Note::
@@ -343,35 +439,6 @@ Another way to bind the VFs to the DPDK UIO driver is by using the
./usertools/dpdk-devbind.py -b igb_uio 0000:03:01.1
-Extra notes on KASUMI F9
-------------------------
-
-When using KASUMI F9 authentication algorithm, the input buffer must be
-constructed according to the 3GPP KASUMI specifications (section 4.4, page 13):
-`<http://cryptome.org/3gpp/35201-900.pdf>`_.
-Input buffer has to have COUNT (4 bytes), FRESH (4 bytes), MESSAGE and DIRECTION (1 bit)
-concatenated. After the DIRECTION bit, a single '1' bit is appended, followed by
-between 0 and 7 '0' bits, so that the total length of the buffer is multiple of 8 bits.
-Note that the actual message can be any length, specified in bits.
-
-Once this buffer is passed this way, when creating the crypto operation,
-length of data to authenticate (op.sym.auth.data.length) must be the length
-of all the items described above, including the padding at the end.
-Also, offset of data to authenticate (op.sym.auth.data.offset)
-must be such that points at the start of the COUNT bytes.
-
-Device and driver naming
-------------------------
-
-The qat crypto driver name is "crypto_qat".
-This name is passed to the dpdk-test-crypto-perf tool in the -devtype parameter.
-The rte_cryptodev_devices_get() can return the devices exposed by a driver.
-
-Each qat crypto device has a unique name, in format
-<pci bdf>_<service>, e.g. "0000:41:01.0_qat_sym".
-This name can be passed to rte_cryptodev_get_dev_id() to get the device_id.
-This is also the format of the slave parameter passed to the crypto scheduler.
-
Debugging
----------------------------------------
diff --git a/doc/guides/rel_notes/release_18_08.rst b/doc/guides/rel_notes/release_18_08.rst
index d41546c..e554613 100644
--- a/doc/guides/rel_notes/release_18_08.rst
+++ b/doc/guides/rel_notes/release_18_08.rst
@@ -68,6 +68,11 @@ New Features
* Add handlers to add/delete VxLAN port number.
* Add devarg to specify ingress VLAN rewrite mode.
+* **Added a new compression PMD using Intel's QuickAssist (QAT) device family.**
+
+ Added the new ``QAT`` compression driver, for compression and decompression
+ operations in software. See the :doc:`../compressdevs/qat_comp` compression
+ driver guide for details on this new driver.
API Changes
-----------
--
2.7.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v7 00/16] compress/qat: add compression PMD
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 " Fiona Trahe
@ 2018-07-13 2:28 ` Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 01/16] common/qat: updated firmware headers Pablo de Lara
` (16 more replies)
0 siblings, 17 replies; 106+ messages in thread
From: Pablo de Lara @ 2018-07-13 2:28 UTC (permalink / raw)
To: fiona.trahe, tomaszx.jozwiak, john.griffin, deepak.k.jain
Cc: dev, Pablo de Lara
Create compression PMD for Intel QuickAssist devices Currently only the C62x and c3xxx devices are supported.
The qat comp PMD supports
- stateless compression and
decompression using the Deflate algorithm with Fixed Huffman
encoding. Dynamic huffman encoding is not supported, it
will be added in a later patch.
- checksum generation: Adler32, CRC32 and combined.
The compression service is hosted on a QuickAssist VF PCI device, which is managed by code in the drivers/common/qat directory.
v7 changes:
- modified makefile to avoid compiling the PMD when no services are
available (like in v5), but solving the build issue when libcrypto is
not present
- fixed meson build when libcrypto is not present
- removed unnecessary unsupported feature list from .ini files
- removed leftover Gerrit-Id tag
- modified commit tile to have uppercase FW
v6 changes:
- fixed makefile issue when cross compiling
v5 changes:
- rebased against latest r/n and features/default.ini
- fixed common/qat/Makefile so no build output files
left hanging around in compress/qat src dir.
v4 changes:
- corrected capabilities
v3 changes:
- only commit message changes, i.e. removed ChangeId and fixed typos
v2 changes:
- Added check for correct firmware
- Split patchset
- Added documentation
- removed support for scatter-gather-lists and related config flag
- Removed support for Dynamic huffman encoding and related IM buffer config flag
- Removed support for DH895xcc device
*** BLURB HERE ***
Fiona Trahe (16):
common/qat: updated firmware headers
compress/qat: add makefiles for PMD
compress/qat: add meson build
compress/qat: add xform processing
compress/qat: create FW request and process response
compress/qat: check that correct firmware is in use
compress/qat: add stats functions
compress/qat: setup queue-pairs for compression service
compress/qat: add fns to configure and clear device
compress/qat: add fn to return device info
compress/qat: add enqueue/dequeue functions
compress/qat: add device start and stop fns
compress/qat: create and populate the ops structure
compress/qat: add fns to create and destroy the PMD
compress/qat: prevent device usage if incorrect firmware
doc/qat: refactor docs adding compression guide
MAINTAINERS | 4 +
config/common_base | 5 +-
doc/guides/compressdevs/features/qat.ini | 12 +
doc/guides/compressdevs/index.rst | 1 +
doc/guides/compressdevs/qat_comp.rst | 49 +++
doc/guides/cryptodevs/qat.rst | 183 ++++++----
doc/guides/rel_notes/release_18_08.rst | 5 +
drivers/common/qat/Makefile | 60 ++--
drivers/common/qat/qat_adf/icp_qat_fw.h | 69 +++-
drivers/common/qat/qat_adf/icp_qat_fw_comp.h | 482 +++++++++++++++++++++++++++
drivers/common/qat/qat_adf/icp_qat_hw.h | 130 +++++++-
drivers/common/qat/qat_device.h | 4 +
drivers/common/qat/qat_qp.c | 11 +-
drivers/common/qat/qat_qp.h | 5 +
drivers/compress/meson.build | 2 +-
drivers/compress/qat/meson.build | 18 +
drivers/compress/qat/qat_comp.c | 359 ++++++++++++++++++++
drivers/compress/qat/qat_comp.h | 56 ++++
drivers/compress/qat/qat_comp_pmd.c | 407 ++++++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 39 +++
drivers/compress/qat/rte_pmd_qat_version.map | 3 +
drivers/crypto/qat/meson.build | 14 +-
drivers/crypto/qat/rte_pmd_qat_version.map | 3 -
mk/rte.app.mk | 8 +-
test/test/test_cryptodev.c | 6 +-
25 files changed, 1806 insertions(+), 129 deletions(-)
create mode 100644 doc/guides/compressdevs/features/qat.ini
create mode 100644 doc/guides/compressdevs/qat_comp.rst
create mode 100644 drivers/common/qat/qat_adf/icp_qat_fw_comp.h
create mode 100644 drivers/compress/qat/meson.build
create mode 100644 drivers/compress/qat/qat_comp.c
create mode 100644 drivers/compress/qat/qat_comp.h
create mode 100644 drivers/compress/qat/qat_comp_pmd.c
create mode 100644 drivers/compress/qat/qat_comp_pmd.h
create mode 100644 drivers/compress/qat/rte_pmd_qat_version.map
delete mode 100644 drivers/crypto/qat/rte_pmd_qat_version.map
--
2.14.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v7 01/16] common/qat: updated firmware headers
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 " Pablo de Lara
@ 2018-07-13 2:28 ` Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 02/16] compress/qat: add makefiles for PMD Pablo de Lara
` (15 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Pablo de Lara @ 2018-07-13 2:28 UTC (permalink / raw)
To: fiona.trahe, tomaszx.jozwiak, john.griffin, deepak.k.jain; +Cc: dev
From: Fiona Trahe <fiona.trahe@intel.com>
Updated to latest firmware headers files for QuickAssist devices.
Includes updates for symmetric crypto, PKE and Compression services.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
drivers/common/qat/qat_adf/icp_qat_fw.h | 69 +++-
drivers/common/qat/qat_adf/icp_qat_fw_comp.h | 482 +++++++++++++++++++++++++++
drivers/common/qat/qat_adf/icp_qat_hw.h | 130 +++++++-
3 files changed, 654 insertions(+), 27 deletions(-)
create mode 100644 drivers/common/qat/qat_adf/icp_qat_fw_comp.h
diff --git a/drivers/common/qat/qat_adf/icp_qat_fw.h b/drivers/common/qat/qat_adf/icp_qat_fw.h
index ae39b7f11..8f7cb37b4 100644
--- a/drivers/common/qat/qat_adf/icp_qat_fw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_fw.h
@@ -117,6 +117,10 @@ struct icp_qat_fw_comn_resp {
#define ICP_QAT_FW_COMN_VALID_FLAG_BITPOS 7
#define ICP_QAT_FW_COMN_VALID_FLAG_MASK 0x1
#define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK 0x7F
+#define ICP_QAT_FW_COMN_CNV_FLAG_BITPOS 6
+#define ICP_QAT_FW_COMN_CNV_FLAG_MASK 0x1
+#define ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS 5
+#define ICP_QAT_FW_COMN_CNVNR_FLAG_MASK 0x1
#define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \
icp_qat_fw_comn_req_hdr_t.service_type
@@ -133,6 +137,16 @@ struct icp_qat_fw_comn_resp {
#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_GET(hdr_t) \
ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_t.hdr_flags)
+#define ICP_QAT_FW_COMN_HDR_CNVNR_FLAG_GET(hdr_flags) \
+ QAT_FIELD_GET(hdr_flags, \
+ ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS, \
+ ICP_QAT_FW_COMN_CNVNR_FLAG_MASK)
+
+#define ICP_QAT_FW_COMN_HDR_CNV_FLAG_GET(hdr_flags) \
+ QAT_FIELD_GET(hdr_flags, \
+ ICP_QAT_FW_COMN_CNV_FLAG_BITPOS, \
+ ICP_QAT_FW_COMN_CNV_FLAG_MASK)
+
#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_SET(hdr_t, val) \
ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val)
@@ -204,29 +218,44 @@ struct icp_qat_fw_comn_resp {
& ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)); }
+#define ICP_QAT_FW_COMN_NEXT_ID_SET_2(next_curr_id, val) \
+ do { \
+ (next_curr_id) = \
+ (((next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK) | \
+ (((val) << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) & \
+ ICP_QAT_FW_COMN_NEXT_ID_MASK)) \
+ } while (0)
+
+#define ICP_QAT_FW_COMN_CURR_ID_SET_2(next_curr_id, val) \
+ do { \
+ (next_curr_id) = \
+ (((next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
+ ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) \
+ } while (0)
+
#define QAT_COMN_RESP_CRYPTO_STATUS_BITPOS 7
#define QAT_COMN_RESP_CRYPTO_STATUS_MASK 0x1
+#define QAT_COMN_RESP_PKE_STATUS_BITPOS 6
+#define QAT_COMN_RESP_PKE_STATUS_MASK 0x1
#define QAT_COMN_RESP_CMP_STATUS_BITPOS 5
#define QAT_COMN_RESP_CMP_STATUS_MASK 0x1
#define QAT_COMN_RESP_XLAT_STATUS_BITPOS 4
#define QAT_COMN_RESP_XLAT_STATUS_MASK 0x1
#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS 3
#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1
-
-#define ICP_QAT_FW_COMN_RESP_STATUS_BUILD(crypto, comp, xlat, eolb) \
- ((((crypto) & QAT_COMN_RESP_CRYPTO_STATUS_MASK) << \
- QAT_COMN_RESP_CRYPTO_STATUS_BITPOS) | \
- (((comp) & QAT_COMN_RESP_CMP_STATUS_MASK) << \
- QAT_COMN_RESP_CMP_STATUS_BITPOS) | \
- (((xlat) & QAT_COMN_RESP_XLAT_STATUS_MASK) << \
- QAT_COMN_RESP_XLAT_STATUS_BITPOS) | \
- (((eolb) & QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK) << \
- QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS))
+#define QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS 2
+#define QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK 0x1
+#define QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS 0
+#define QAT_COMN_RESP_XLT_WA_APPLIED_MASK 0x1
#define ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(status) \
QAT_FIELD_GET(status, QAT_COMN_RESP_CRYPTO_STATUS_BITPOS, \
QAT_COMN_RESP_CRYPTO_STATUS_MASK)
+#define ICP_QAT_FW_COMN_RESP_PKE_STAT_GET(status) \
+ QAT_FIELD_GET(status, QAT_COMN_RESP_PKE_STATUS_BITPOS, \
+ QAT_COMN_RESP_PKE_STATUS_MASK)
+
#define ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(status) \
QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_STATUS_BITPOS, \
QAT_COMN_RESP_CMP_STATUS_MASK)
@@ -235,10 +264,18 @@ struct icp_qat_fw_comn_resp {
QAT_FIELD_GET(status, QAT_COMN_RESP_XLAT_STATUS_BITPOS, \
QAT_COMN_RESP_XLAT_STATUS_MASK)
+#define ICP_QAT_FW_COMN_RESP_XLT_WA_APPLIED_GET(status) \
+ QAT_FIELD_GET(status, QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS, \
+ QAT_COMN_RESP_XLT_WA_APPLIED_MASK)
+
#define ICP_QAT_FW_COMN_RESP_CMP_END_OF_LAST_BLK_FLAG_GET(status) \
QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS, \
QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK)
+#define ICP_QAT_FW_COMN_RESP_UNSUPPORTED_REQUEST_STAT_GET(status) \
+ QAT_FIELD_GET(status, QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS, \
+ QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK)
+
#define ICP_QAT_FW_COMN_STATUS_FLAG_OK 0
#define ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 1
#define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0
@@ -257,8 +294,16 @@ struct icp_qat_fw_comn_resp {
#define ERR_CODE_OVERFLOW_ERROR -11
#define ERR_CODE_SOFT_ERROR -12
#define ERR_CODE_FATAL_ERROR -13
-#define ERR_CODE_SSM_ERROR -14
-#define ERR_CODE_ENDPOINT_ERROR -15
+#define ERR_CODE_COMP_OUTPUT_CORRUPTION -14
+#define ERR_CODE_HW_INCOMPLETE_FILE -15
+#define ERR_CODE_SSM_ERROR -16
+#define ERR_CODE_ENDPOINT_ERROR -17
+#define ERR_CODE_CNV_ERROR -18
+#define ERR_CODE_EMPTY_DYM_BLOCK -19
+#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_HANDLE -20
+#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_HMAC_FAILED -21
+#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_WRAPPING_ALGO -22
+#define ERR_CODE_KPT_DRNG_SEED_NOT_LOAD -23
enum icp_qat_fw_slice {
ICP_QAT_FW_SLICE_NULL = 0,
diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_comp.h b/drivers/common/qat/qat_adf/icp_qat_fw_comp.h
new file mode 100644
index 000000000..813817720
--- /dev/null
+++ b/drivers/common/qat/qat_adf/icp_qat_fw_comp.h
@@ -0,0 +1,482 @@
+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+#ifndef _ICP_QAT_FW_COMP_H_
+#define _ICP_QAT_FW_COMP_H_
+
+#include "icp_qat_fw.h"
+
+enum icp_qat_fw_comp_cmd_id {
+ ICP_QAT_FW_COMP_CMD_STATIC = 0,
+ /*!< Static Compress Request */
+
+ ICP_QAT_FW_COMP_CMD_DYNAMIC = 1,
+ /*!< Dynamic Compress Request */
+
+ ICP_QAT_FW_COMP_CMD_DECOMPRESS = 2,
+ /*!< Decompress Request */
+
+ ICP_QAT_FW_COMP_CMD_DELIMITER
+ /**< Delimiter type */
+};
+
+/**< Flag usage */
+
+#define ICP_QAT_FW_COMP_STATELESS_SESSION 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that session is stateless
+ */
+
+#define ICP_QAT_FW_COMP_STATEFUL_SESSION 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that session is stateful
+ */
+
+#define ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that autoselectbest is NOT used
+ */
+
+#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that autoselectbest is used
+ */
+
+#define ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is NOT used
+ */
+
+#define ICP_QAT_FW_COMP_ENH_AUTO_SELECT_BEST 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is used
+ */
+
+#define ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is NOT used
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is used
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_USED_AS_INTMD_BUF 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing secure RAM from being used as
+ * an intermediate buffer is DISABLED.
+ */
+
+#define ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing secure RAM from being used as
+ * an intermediate buffer is ENABLED.
+ */
+
+/**< Flag mask & bit position */
+
+#define ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS 2
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the session type
+ */
+
+#define ICP_QAT_FW_COMP_SESSION_TYPE_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask used to determine the session type
+ */
+
+#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS 3
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for auto select best
+ */
+
+#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for auto select best
+ */
+
+#define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS 4
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for enhanced auto select best
+ */
+
+#define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for enhanced auto select best
+ */
+
+#define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS 5
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for disabling type zero header write back
+ * when Enhanced autoselect best is enabled. If set firmware does
+ * not return type0 store block header, only copies src to dest.
+ * (if best output is Type0)
+ */
+
+#define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for auto select best
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS 7
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for flag used to disable secure ram from
+ * being used as an intermediate buffer.
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for disable secure ram for use as an intermediate
+ * buffer.
+ */
+
+#define ICP_QAT_FW_COMP_FLAGS_BUILD(sesstype, autoselect, enhanced_asb, \
+ ret_uncomp, secure_ram) \
+ ((((sesstype)&ICP_QAT_FW_COMP_SESSION_TYPE_MASK) \
+ << ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS) | \
+ (((autoselect)&ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK) \
+ << ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS) | \
+ (((enhanced_asb)&ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK) \
+ << ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS) | \
+ (((ret_uncomp)&ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK) \
+ << ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS) | \
+ (((secure_ram)&ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK) \
+ << ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS))
+
+union icp_qat_fw_comp_req_hdr_cd_pars {
+ /**< LWs 2-5 */
+ struct {
+ uint64_t content_desc_addr;
+ /**< Address of the content descriptor */
+
+ uint16_t content_desc_resrvd1;
+ /**< Content descriptor reserved field */
+
+ uint8_t content_desc_params_sz;
+ /**< Size of the content descriptor parameters in quad words.
+ * These parameters describe the session setup configuration
+ * info for the slices that this request relies upon i.e.
+ * the configuration word and cipher key needed by the cipher
+ * slice if there is a request for cipher processing.
+ */
+
+ uint8_t content_desc_hdr_resrvd2;
+ /**< Content descriptor reserved field */
+
+ uint32_t content_desc_resrvd3;
+ /**< Content descriptor reserved field */
+ } s;
+
+ struct {
+ uint32_t comp_slice_cfg_word[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /* Compression Slice Config Word */
+
+ uint32_t content_desc_resrvd4;
+ /**< Content descriptor reserved field */
+
+ } sl;
+
+};
+
+struct icp_qat_fw_comp_req_params {
+ /**< LW 14 */
+ uint32_t comp_len;
+ /**< Size of input to process in bytes Note: Only EOP requests can be
+ * odd for decompression. IA must set LSB to zero for odd sized
+ * intermediate inputs
+ */
+
+ /**< LW 15 */
+ uint32_t out_buffer_sz;
+ /**< Size of output buffer in bytes */
+
+ /**< LW 16 */
+ uint32_t initial_crc32;
+ /**< CRC of previously processed bytes */
+
+ /**< LW 17 */
+ uint32_t initial_adler;
+ /**< Adler of previously processed bytes */
+
+ /**< LW 18 */
+ uint32_t req_par_flags;
+
+ /**< LW 19 */
+ uint32_t rsrvd;
+};
+
+#define ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(sop, eop, bfinal, cnv, cnvnr) \
+ ((((sop)&ICP_QAT_FW_COMP_SOP_MASK) << ICP_QAT_FW_COMP_SOP_BITPOS) | \
+ (((eop)&ICP_QAT_FW_COMP_EOP_MASK) << ICP_QAT_FW_COMP_EOP_BITPOS) | \
+ (((bfinal)&ICP_QAT_FW_COMP_BFINAL_MASK) \
+ << ICP_QAT_FW_COMP_BFINAL_BITPOS) | \
+ ((cnv & ICP_QAT_FW_COMP_CNV_MASK) << ICP_QAT_FW_COMP_CNV_BITPOS) | \
+ ((cnvnr & ICP_QAT_FW_COMP_CNV_RECOVERY_MASK) \
+ << ICP_QAT_FW_COMP_CNV_RECOVERY_BITPOS))
+
+#define ICP_QAT_FW_COMP_NOT_SOP 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request is NOT Start of Packet
+ */
+
+#define ICP_QAT_FW_COMP_SOP 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request IS Start of Packet
+ */
+
+#define ICP_QAT_FW_COMP_NOT_EOP 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request is NOT Start of Packet
+ */
+
+#define ICP_QAT_FW_COMP_EOP 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request IS End of Packet
+ */
+
+#define ICP_QAT_FW_COMP_NOT_BFINAL 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing to indicate firmware this is not the last block
+ */
+
+#define ICP_QAT_FW_COMP_BFINAL 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing to indicate firmware this is the last block
+ */
+
+#define ICP_QAT_FW_COMP_NO_CNV 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that NO cnv check is to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_CNV 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that a cnv check IS to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_NO_CNV_RECOVERY 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that NO cnv recovery is to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_CNV_RECOVERY 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that a cnv recovery is to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_SOP_BITPOS 0
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for SOP
+ */
+
+#define ICP_QAT_FW_COMP_SOP_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask used to determine SOP
+ */
+
+#define ICP_QAT_FW_COMP_EOP_BITPOS 1
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for EOP
+ */
+
+#define ICP_QAT_FW_COMP_EOP_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask used to determine EOP
+ */
+
+#define ICP_QAT_FW_COMP_BFINAL_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for the bfinal bit
+ */
+
+#define ICP_QAT_FW_COMP_BFINAL_BITPOS 6
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the bfinal bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for the CNV bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_BITPOS 16
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the CNV bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_RECOVERY_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for the CNV Recovery bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_RECOVERY_BITPOS 17
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the CNV Recovery bit
+ */
+
+struct icp_qat_fw_xlt_req_params {
+ /**< LWs 20-21 */
+ uint64_t inter_buff_ptr;
+ /**< This field specifies the physical address of an intermediate
+ * buffer SGL array. The array contains a pair of 64-bit
+ * intermediate buffer pointers to SGL buffer descriptors, one pair
+ * per CPM. Please refer to the CPM1.6 Firmware Interface HLD
+ * specification for more details.
+ */
+};
+
+
+struct icp_qat_fw_comp_cd_hdr {
+ /**< LW 24 */
+ uint16_t ram_bank_flags;
+ /**< Flags to show which ram banks to access */
+
+ uint8_t comp_cfg_offset;
+ /**< Quad word offset from the content descriptor parameters address
+ * to the parameters for the compression processing
+ */
+
+ uint8_t next_curr_id;
+ /**< This field combines the next and current id (each four bits) -
+ * the next id is the most significant nibble.
+ * Next Id: Set to the next slice to pass the compressed data through.
+ * Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through
+ * anymore slices after compression
+ * Current Id: Initialised with the compression slice type
+ */
+
+ /**< LW 25 */
+ uint32_t resrvd;
+ /**< LWs 26-27 */
+
+ uint64_t comp_state_addr;
+ /**< Pointer to compression state */
+
+ /**< LWs 28-29 */
+ uint64_t ram_banks_addr;
+ /**< Pointer to banks */
+
+};
+
+
+struct icp_qat_fw_xlt_cd_hdr {
+ /**< LW 30 */
+ uint16_t resrvd1;
+ /**< Reserved field and assumed set to 0 */
+
+ uint8_t resrvd2;
+ /**< Reserved field and assumed set to 0 */
+
+ uint8_t next_curr_id;
+ /**< This field combines the next and current id (each four bits) -
+ * the next id is the most significant nibble.
+ * Next Id: Set to the next slice to pass the translated data through.
+ * Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through
+ * any more slices after compression
+ * Current Id: Initialised with the translation slice type
+ */
+
+ /**< LW 31 */
+ uint32_t resrvd3;
+ /**< Reserved and should be set to zero, needed for quadword
+ * alignment
+ */
+};
+
+struct icp_qat_fw_comp_req {
+ /**< LWs 0-1 */
+ struct icp_qat_fw_comn_req_hdr comn_hdr;
+ /**< Common request header - for Service Command Id,
+ * use service-specific Compression Command Id.
+ * Service Specific Flags - use Compression Command Flags
+ */
+
+ /**< LWs 2-5 */
+ union icp_qat_fw_comp_req_hdr_cd_pars cd_pars;
+ /**< Compression service-specific content descriptor field which points
+ * either to a content descriptor parameter block or contains the
+ * compression slice config word.
+ */
+
+ /**< LWs 6-13 */
+ struct icp_qat_fw_comn_req_mid comn_mid;
+ /**< Common request middle section */
+
+ /**< LWs 14-19 */
+ struct icp_qat_fw_comp_req_params comp_pars;
+ /**< Compression request Parameters block */
+
+ /**< LWs 20-21 */
+ union {
+ struct icp_qat_fw_xlt_req_params xlt_pars;
+ /**< Translation request Parameters block */
+ uint32_t resrvd1[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /**< Reserved if not used for translation */
+
+ } u1;
+
+ /**< LWs 22-23 */
+ union {
+ uint32_t resrvd2[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /**< Reserved - not used if Batch and Pack is disabled.*/
+
+ uint64_t bnp_res_table_addr;
+ /**< A generic pointer to the unbounded list of
+ * icp_qat_fw_resp_comp_pars members. This pointer is only
+ * used when the Batch and Pack is enabled.
+ */
+ } u3;
+
+ /**< LWs 24-29 */
+ struct icp_qat_fw_comp_cd_hdr comp_cd_ctrl;
+ /**< Compression request content descriptor control block header */
+
+ /**< LWs 30-31 */
+ union {
+ struct icp_qat_fw_xlt_cd_hdr xlt_cd_ctrl;
+ /**< Translation request content descriptor
+ * control block header
+ */
+
+ uint32_t resrvd3[ICP_QAT_FW_NUM_LONGWORDS_2];
+ /**< Reserved if not used for translation */
+ } u2;
+};
+
+struct icp_qat_fw_resp_comp_pars {
+ /**< LW 4 */
+ uint32_t input_byte_counter;
+ /**< Input byte counter */
+
+ /**< LW 5 */
+ uint32_t output_byte_counter;
+ /**< Output byte counter */
+
+ /**< LW 6 & 7*/
+ union {
+ uint64_t curr_chksum;
+ struct {
+ /**< LW 6 */
+ uint32_t curr_crc32;
+ /**< LW 7 */
+ uint32_t curr_adler_32;
+ };
+ };
+};
+
+struct icp_qat_fw_comp_resp {
+ /**< LWs 0-1 */
+ struct icp_qat_fw_comn_resp_hdr comn_resp;
+ /**< Common interface response format see icp_qat_fw.h */
+
+ /**< LWs 2-3 */
+ uint64_t opaque_data;
+ /**< Opaque data passed from the request to the response message */
+
+ /**< LWs 4-7 */
+ struct icp_qat_fw_resp_comp_pars comp_resp_pars;
+ /**< Common response params (checksums and byte counts) */
+};
+
+#endif
diff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h b/drivers/common/qat/qat_adf/icp_qat_hw.h
index 56e3cf798..e7961dba2 100644
--- a/drivers/common/qat/qat_adf/icp_qat_hw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_hw.h
@@ -72,19 +72,44 @@ struct icp_qat_hw_auth_config {
#define QAT_AUTH_ALGO_MASK 0xF
#define QAT_AUTH_CMP_BITPOS 8
#define QAT_AUTH_CMP_MASK 0x7F
-#define QAT_AUTH_SHA3_PADDING_BITPOS 16
-#define QAT_AUTH_SHA3_PADDING_MASK 0x1
+#define QAT_AUTH_SHA3_PADDING_DISABLE_BITPOS 16
+#define QAT_AUTH_SHA3_PADDING_DISABLE_MASK 0x1
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_BITPOS 17
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_MASK 0x1
#define QAT_AUTH_ALGO_SHA3_BITPOS 22
#define QAT_AUTH_ALGO_SHA3_MASK 0x3
-#define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \
- (((mode & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \
- ((algo & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \
- (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) << \
- QAT_AUTH_ALGO_SHA3_BITPOS) | \
- (((((algo == ICP_QAT_HW_AUTH_ALGO_SHA3_256) || \
- (algo == ICP_QAT_HW_AUTH_ALGO_SHA3_512)) ? 1 : 0) \
- & QAT_AUTH_SHA3_PADDING_MASK) << QAT_AUTH_SHA3_PADDING_BITPOS) | \
- ((cmp_len & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
+#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_BITPOS 16
+#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_MASK 0xF
+#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_BITPOS 24
+#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_MASK 0xFF
+#define QAT_AUTH_SHA3_HW_PADDING_ENABLE 0
+#define QAT_AUTH_SHA3_HW_PADDING_DISABLE 1
+#define QAT_AUTH_SHA3_PADDING_DISABLE_USE_DEFAULT 0
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_USE_DEFAULT 0
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_PROGRAMMABLE 1
+#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_RESERVED 0
+#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_RESERVED 0
+
+#define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \
+ ((((mode) & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \
+ (((algo) & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \
+ (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) \
+ << QAT_AUTH_ALGO_SHA3_BITPOS) | \
+ (((QAT_AUTH_SHA3_PADDING_DISABLE_USE_DEFAULT) & \
+ QAT_AUTH_SHA3_PADDING_DISABLE_MASK) \
+ << QAT_AUTH_SHA3_PADDING_DISABLE_BITPOS) | \
+ (((QAT_AUTH_SHA3_PADDING_OVERRIDE_USE_DEFAULT) & \
+ QAT_AUTH_SHA3_PADDING_OVERRIDE_MASK) \
+ << QAT_AUTH_SHA3_PADDING_OVERRIDE_BITPOS) | \
+ (((cmp_len) & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
+
+#define ICP_QAT_HW_AUTH_CONFIG_BUILD_UPPER \
+ ((((QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_RESERVED) & \
+ QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_MASK) \
+ << QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_BITPOS) | \
+ (((QAT_AUTH_SHA3_PROG_PADDING_PREFIX_RESERVED) & \
+ QAT_AUTH_SHA3_PROG_PADDING_PREFIX_MASK) \
+ << QAT_AUTH_SHA3_PROG_PADDING_PREFIX_BITPOS))
struct icp_qat_hw_auth_counter {
uint32_t counter;
@@ -107,13 +132,13 @@ struct icp_qat_hw_auth_setup {
#define ICP_QAT_HW_MD5_STATE1_SZ 16
#define ICP_QAT_HW_SHA1_STATE1_SZ 20
#define ICP_QAT_HW_SHA224_STATE1_SZ 32
+#define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
#define ICP_QAT_HW_SHA256_STATE1_SZ 32
#define ICP_QAT_HW_SHA3_256_STATE1_SZ 32
#define ICP_QAT_HW_SHA384_STATE1_SZ 64
+#define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
#define ICP_QAT_HW_SHA512_STATE1_SZ 64
#define ICP_QAT_HW_SHA3_512_STATE1_SZ 64
-#define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
-#define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
#define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ 16
#define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ 16
#define ICP_QAT_HW_AES_F9_STATE1_SZ 32
@@ -121,17 +146,18 @@ struct icp_qat_hw_auth_setup {
#define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16
#define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8
#define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8
+
#define ICP_QAT_HW_NULL_STATE2_SZ 32
#define ICP_QAT_HW_MD5_STATE2_SZ 16
#define ICP_QAT_HW_SHA1_STATE2_SZ 20
#define ICP_QAT_HW_SHA224_STATE2_SZ 32
+#define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
#define ICP_QAT_HW_SHA256_STATE2_SZ 32
#define ICP_QAT_HW_SHA3_256_STATE2_SZ 0
#define ICP_QAT_HW_SHA384_STATE2_SZ 64
+#define ICP_QAT_HW_SHA3_384_STATE2_SZ 0
#define ICP_QAT_HW_SHA512_STATE2_SZ 64
#define ICP_QAT_HW_SHA3_512_STATE2_SZ 0
-#define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
-#define ICP_QAT_HW_SHA3_384_STATE2_SZ 0
#define ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ 48
#define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16
#define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16
@@ -154,6 +180,12 @@ struct icp_qat_hw_auth_sha512 {
uint8_t state2[ICP_QAT_HW_SHA512_STATE2_SZ];
};
+struct icp_qat_hw_auth_sha3_512 {
+ struct icp_qat_hw_auth_setup inner_setup;
+ uint8_t state1[ICP_QAT_HW_SHA3_512_STATE1_SZ];
+ struct icp_qat_hw_auth_setup outer_setup;
+};
+
struct icp_qat_hw_auth_algo_blk {
struct icp_qat_hw_auth_sha512 sha;
};
@@ -283,4 +315,72 @@ struct icp_qat_hw_cipher_algo_blk {
uint8_t key[ICP_QAT_HW_CIPHER_MAX_KEY_SZ];
} __rte_cache_aligned;
+/* ========================================================================= */
+/* COMPRESSION SLICE */
+/* ========================================================================= */
+
+enum icp_qat_hw_compression_direction {
+ ICP_QAT_HW_COMPRESSION_DIR_COMPRESS = 0,
+ ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS = 1,
+ ICP_QAT_HW_COMPRESSION_DIR_DELIMITER = 2
+};
+
+enum icp_qat_hw_compression_delayed_match {
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED = 0,
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_ENABLED = 1,
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DELIMITER = 2
+};
+
+enum icp_qat_hw_compression_algo {
+ ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE = 0,
+ ICP_QAT_HW_COMPRESSION_ALGO_LZS = 1,
+ ICP_QAT_HW_COMPRESSION_ALGO_DELIMITER = 2
+};
+
+
+enum icp_qat_hw_compression_depth {
+ ICP_QAT_HW_COMPRESSION_DEPTH_1 = 0,
+ ICP_QAT_HW_COMPRESSION_DEPTH_4 = 1,
+ ICP_QAT_HW_COMPRESSION_DEPTH_8 = 2,
+ ICP_QAT_HW_COMPRESSION_DEPTH_16 = 3,
+ ICP_QAT_HW_COMPRESSION_DEPTH_DELIMITER = 4
+};
+
+enum icp_qat_hw_compression_file_type {
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_0 = 0,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_1 = 1,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_2 = 2,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_3 = 3,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_4 = 4,
+ ICP_QAT_HW_COMPRESSION_FILE_TYPE_DELIMITER = 5
+};
+
+struct icp_qat_hw_compression_config {
+ uint32_t val;
+ uint32_t reserved;
+};
+
+#define QAT_COMPRESSION_DIR_BITPOS 4
+#define QAT_COMPRESSION_DIR_MASK 0x7
+#define QAT_COMPRESSION_DELAYED_MATCH_BITPOS 16
+#define QAT_COMPRESSION_DELAYED_MATCH_MASK 0x1
+#define QAT_COMPRESSION_ALGO_BITPOS 31
+#define QAT_COMPRESSION_ALGO_MASK 0x1
+#define QAT_COMPRESSION_DEPTH_BITPOS 28
+#define QAT_COMPRESSION_DEPTH_MASK 0x7
+#define QAT_COMPRESSION_FILE_TYPE_BITPOS 24
+#define QAT_COMPRESSION_FILE_TYPE_MASK 0xF
+
+#define ICP_QAT_HW_COMPRESSION_CONFIG_BUILD( \
+ dir, delayed, algo, depth, filetype) \
+ ((((dir) & QAT_COMPRESSION_DIR_MASK) << QAT_COMPRESSION_DIR_BITPOS) | \
+ (((delayed) & QAT_COMPRESSION_DELAYED_MATCH_MASK) \
+ << QAT_COMPRESSION_DELAYED_MATCH_BITPOS) | \
+ (((algo) & QAT_COMPRESSION_ALGO_MASK) \
+ << QAT_COMPRESSION_ALGO_BITPOS) | \
+ (((depth) & QAT_COMPRESSION_DEPTH_MASK) \
+ << QAT_COMPRESSION_DEPTH_BITPOS) | \
+ (((filetype) & QAT_COMPRESSION_FILE_TYPE_MASK) \
+ << QAT_COMPRESSION_FILE_TYPE_BITPOS))
+
#endif
--
2.14.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v7 02/16] compress/qat: add makefiles for PMD
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 " Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 01/16] common/qat: updated firmware headers Pablo de Lara
@ 2018-07-13 2:28 ` Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 03/16] compress/qat: add meson build Pablo de Lara
` (14 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Pablo de Lara @ 2018-07-13 2:28 UTC (permalink / raw)
To: fiona.trahe, tomaszx.jozwiak, john.griffin, deepak.k.jain; +Cc: dev
From: Fiona Trahe <fiona.trahe@intel.com>
Add Makefiles, directory and empty source files for compression PMD.
Handle cases for building either symmetric crypto PMD
or compression PMD or both and the common files both depend on.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
MAINTAINERS | 4 +++
config/common_base | 3 +-
drivers/common/qat/Makefile | 60 +++++++++++++++++++++++--------------
drivers/compress/qat/qat_comp.c | 5 ++++
drivers/compress/qat/qat_comp.h | 14 +++++++++
drivers/compress/qat/qat_comp_pmd.c | 5 ++++
drivers/compress/qat/qat_comp_pmd.h | 15 ++++++++++
mk/rte.app.mk | 8 ++++-
test/test/test_cryptodev.c | 6 ++--
9 files changed, 93 insertions(+), 27 deletions(-)
create mode 100644 drivers/compress/qat/qat_comp.c
create mode 100644 drivers/compress/qat/qat_comp.h
create mode 100644 drivers/compress/qat/qat_comp_pmd.c
create mode 100644 drivers/compress/qat/qat_comp_pmd.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 4d508dead..412fd778f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -853,6 +853,10 @@ F: drivers/compress/isal/
F: doc/guides/compressdevs/isal.rst
F: doc/guides/compressdevs/features/isal.ini
+Intel QuickAssist
+M: Fiona Trahe <fiona.trahe@intel.com>
+F: drivers/compress/qat/
+F: drivers/common/qat/
Eventdev Drivers
----------------
diff --git a/config/common_base b/config/common_base
index c305a7725..8b539af65 100644
--- a/config/common_base
+++ b/config/common_base
@@ -480,7 +480,8 @@ CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4
#
# Compile PMD for QuickAssist based devices
#
-CONFIG_RTE_LIBRTE_PMD_QAT=n
+CONFIG_RTE_LIBRTE_PMD_QAT=y
+CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
#
# Max. number of QuickAssist devices, which can be detected and attached
#
diff --git a/drivers/common/qat/Makefile b/drivers/common/qat/Makefile
index 02e83f9f0..2a4c99bc1 100644
--- a/drivers/common/qat/Makefile
+++ b/drivers/common/qat/Makefile
@@ -3,48 +3,64 @@
include $(RTE_SDK)/mk/rte.vars.mk
-# library name
-LIB = librte_pmd_qat.a
-
-# library version
-LIBABIVER := 1
-
-# build flags
-CFLAGS += $(WERROR_FLAGS)
-CFLAGS += -O3
-
# build directories
QAT_CRYPTO_DIR := $(RTE_SDK)/drivers/crypto/qat
-VPATH=$(QAT_CRYPTO_DIR)
+QAT_COMPRESS_DIR := $(RTE_SDK)/drivers/compress/qat
+VPATH=$(QAT_CRYPTO_DIR):$(QAT_COMPRESS_DIR)
# external library include paths
CFLAGS += -I$(SRCDIR)/qat_adf
CFLAGS += -I$(SRCDIR)
CFLAGS += -I$(QAT_CRYPTO_DIR)
+CFLAGS += -I$(QAT_COMPRESS_DIR)
-# library common source files
-SRCS-y += qat_device.c
-SRCS-y += qat_common.c
-SRCS-y += qat_logs.c
-SRCS-y += qat_qp.c
+
+ifeq ($(CONFIG_RTE_LIBRTE_COMPRESSDEV),y)
+ CFLAGS += -DALLOW_EXPERIMENTAL_API
+ LDLIBS += -lrte_compressdev
+ SRCS-y += qat_comp.c
+ SRCS-y += qat_comp_pmd.c
+ build_qat = yes
+endif
# library symmetric crypto source files
ifeq ($(CONFIG_RTE_LIBRTE_CRYPTODEV),y)
+ifeq ($(CONFIG_RTE_LIBRTE_PMD_QAT_SYM),y)
LDLIBS += -lrte_cryptodev
LDLIBS += -lcrypto
CFLAGS += -DBUILD_QAT_SYM
SRCS-y += qat_sym.c
SRCS-y += qat_sym_session.c
SRCS-y += qat_sym_pmd.c
+ build_qat = yes
+endif
endif
-LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool
-LDLIBS += -lrte_pci -lrte_bus_pci
+ifdef build_qat
-# export include files
-SYMLINK-y-include +=
+ # library name
+ LIB = librte_pmd_qat.a
-# versioning export map
-EXPORT_MAP := ../../crypto/qat/rte_pmd_qat_version.map
+ # library version
+ LIBABIVER := 1
+ # build flags
+ CFLAGS += $(WERROR_FLAGS)
+ CFLAGS += -O3
+
+ # library common source files
+ SRCS-y += qat_device.c
+ SRCS-y += qat_common.c
+ SRCS-y += qat_logs.c
+ SRCS-y += qat_qp.c
+
+ LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool
+ LDLIBS += -lrte_pci -lrte_bus_pci
+
+ # export include files
+ SYMLINK-y-include +=
+
+ # versioning export map
+ EXPORT_MAP := ../../crypto/qat/rte_pmd_qat_version.map
+endif
include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
new file mode 100644
index 000000000..caa115806
--- /dev/null
+++ b/drivers/compress/qat/qat_comp.c
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2018 Intel Corporation
+ */
+
+#include "qat_comp.h"
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
new file mode 100644
index 000000000..89c475ee6
--- /dev/null
+++ b/drivers/compress/qat/qat_comp.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+
+#ifndef _QAT_COMP_H_
+#define _QAT_COMP_H_
+
+#ifdef RTE_LIBRTE_COMPRESSDEV
+
+#include <rte_compressdev.h>
+#include <rte_compressdev_pmd.h>
+
+#endif
+#endif
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
new file mode 100644
index 000000000..fb035d1ee
--- /dev/null
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+
+#include "qat_comp_pmd.h"
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
new file mode 100644
index 000000000..9b5b54394
--- /dev/null
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+
+#ifndef _QAT_COMP_PMD_H_
+#define _QAT_COMP_PMD_H_
+
+#ifdef RTE_LIBRTE_COMPRESSDEV
+
+#include <rte_compressdev.h>
+#include <rte_compressdev_pmd.h>
+
+
+#endif
+#endif /* _QAT_COMP_PMD_H_ */
diff --git a/mk/rte.app.mk b/mk/rte.app.mk
index 7bcf6308d..9be45b68d 100644
--- a/mk/rte.app.mk
+++ b/mk/rte.app.mk
@@ -190,7 +190,9 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_GCM) += -lIPSec_MB
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += -lrte_pmd_ccp -lcrypto
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OPENSSL) += -lrte_pmd_openssl -lcrypto
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO) += -lrte_pmd_null_crypto
-_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += -lrte_pmd_qat -lcrypto
+ifeq ($(CONFIG_RTE_LIBRTE_PMD_QAT),y)
+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_QAT_SYM) += -lrte_pmd_qat -lcrypto
+endif # CONFIG_RTE_LIBRTE_PMD_QAT
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += -lrte_pmd_snow3g
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += -L$(LIBSSO_SNOW3G_PATH)/build -lsso_snow3g
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_KASUMI) += -lrte_pmd_kasumi
@@ -213,6 +215,10 @@ endif # CONFIG_RTE_LIBRTE_CRYPTODEV
ifeq ($(CONFIG_RTE_LIBRTE_COMPRESSDEV),y)
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ISAL) += -lrte_pmd_isal_comp
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ISAL) += -lisal
+# Link QAT driver if it has not been linked yet
+ifeq ($(CONFIG_RTE_LIBRTE_PMD_QAT_SYM),n)
+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += -lrte_pmd_qat
+endif # CONFIG_RTE_LIBRTE_PMD_QAT_SYM
endif # CONFIG_RTE_LIBRTE_COMPRESSDEV
ifeq ($(CONFIG_RTE_LIBRTE_EVENTDEV),y)
diff --git a/test/test/test_cryptodev.c b/test/test/test_cryptodev.c
index b759e0811..cbbdb1518 100644
--- a/test/test/test_cryptodev.c
+++ b/test/test/test_cryptodev.c
@@ -9938,9 +9938,9 @@ test_cryptodev_qat(void /*argv __rte_unused, int argc __rte_unused*/)
RTE_STR(CRYPTODEV_NAME_QAT_SYM_PMD));
if (gbl_driver_id == -1) {
- RTE_LOG(ERR, USER1, "QAT PMD must be loaded. Check if "
- "CONFIG_RTE_LIBRTE_PMD_QAT is enabled "
- "in config file to run this testsuite.\n");
+ RTE_LOG(ERR, USER1, "QAT PMD must be loaded. Check that both "
+ "CONFIG_RTE_LIBRTE_PMD_QAT and CONFIG_RTE_LIBRTE_PMD_QAT_SYM "
+ "are enabled in config file to run this testsuite.\n");
return TEST_SKIPPED;
}
--
2.14.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v7 03/16] compress/qat: add meson build
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 " Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 01/16] common/qat: updated firmware headers Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 02/16] compress/qat: add makefiles for PMD Pablo de Lara
@ 2018-07-13 2:28 ` Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 04/16] compress/qat: add xform processing Pablo de Lara
` (13 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Pablo de Lara @ 2018-07-13 2:28 UTC (permalink / raw)
To: fiona.trahe, tomaszx.jozwiak, john.griffin, deepak.k.jain; +Cc: dev
From: Fiona Trahe <fiona.trahe@intel.com>
Add meson build files.
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
drivers/common/qat/Makefile | 2 +-
drivers/compress/meson.build | 2 +-
drivers/compress/qat/meson.build | 18 ++++++++++++++++++
drivers/compress/qat/rte_pmd_qat_version.map | 3 +++
drivers/crypto/qat/meson.build | 14 ++++----------
drivers/crypto/qat/rte_pmd_qat_version.map | 3 ---
6 files changed, 27 insertions(+), 15 deletions(-)
create mode 100644 drivers/compress/qat/meson.build
create mode 100644 drivers/compress/qat/rte_pmd_qat_version.map
delete mode 100644 drivers/crypto/qat/rte_pmd_qat_version.map
diff --git a/drivers/common/qat/Makefile b/drivers/common/qat/Makefile
index 2a4c99bc1..c68a032a5 100644
--- a/drivers/common/qat/Makefile
+++ b/drivers/common/qat/Makefile
@@ -60,7 +60,7 @@ ifdef build_qat
SYMLINK-y-include +=
# versioning export map
- EXPORT_MAP := ../../crypto/qat/rte_pmd_qat_version.map
+ EXPORT_MAP := ../../compress/qat/rte_pmd_qat_version.map
endif
include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/compress/meson.build b/drivers/compress/meson.build
index fb136e1b2..2352ad5bc 100644
--- a/drivers/compress/meson.build
+++ b/drivers/compress/meson.build
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2018 Intel Corporation
-drivers = ['isal']
+drivers = ['isal', 'qat']
std_deps = ['compressdev'] # compressdev pulls in all other needed deps
config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'
diff --git a/drivers/compress/qat/meson.build b/drivers/compress/qat/meson.build
new file mode 100644
index 000000000..9d15076dc
--- /dev/null
+++ b/drivers/compress/qat/meson.build
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2017-2018 Intel Corporation
+
+
+# Add our sources files to the list
+allow_experimental_apis = true
+qat_sources += files('qat_comp_pmd.c',
+ 'qat_comp.c')
+qat_includes += include_directories('.')
+qat_deps += 'compressdev'
+qat_ext_deps += dep
+
+# build the whole driver
+sources += qat_sources
+cflags += qat_cflags
+deps += qat_deps
+ext_deps += qat_ext_deps
+includes += qat_includes
diff --git a/drivers/compress/qat/rte_pmd_qat_version.map b/drivers/compress/qat/rte_pmd_qat_version.map
new file mode 100644
index 000000000..ad6e191e4
--- /dev/null
+++ b/drivers/compress/qat/rte_pmd_qat_version.map
@@ -0,0 +1,3 @@
+DPDK_18.08 {
+ local: *;
+};
diff --git a/drivers/crypto/qat/meson.build b/drivers/crypto/qat/meson.build
index 2873637de..9cc98d2c2 100644
--- a/drivers/crypto/qat/meson.build
+++ b/drivers/crypto/qat/meson.build
@@ -1,24 +1,18 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017-2018 Intel Corporation
+# this does not build the QAT driver, instead that is done in the compression
+# driver which comes later. Here we just add our sources files to the list
build = false
dep = dependency('libcrypto', required: false)
+qat_includes += include_directories('.')
+qat_deps += 'cryptodev'
if dep.found()
# Add our sources files to the list
qat_sources += files('qat_sym_pmd.c',
'qat_sym.c',
'qat_sym_session.c')
- qat_includes += include_directories('.')
- qat_deps += 'cryptodev'
qat_ext_deps += dep
pkgconfig_extra_libs += '-lcrypto'
qat_cflags += '-DBUILD_QAT_SYM'
-
- # build the whole driver
- sources += qat_sources
- cflags += qat_cflags
- deps += qat_deps
- ext_deps += qat_ext_deps
- includes += qat_includes
- build = true
endif
diff --git a/drivers/crypto/qat/rte_pmd_qat_version.map b/drivers/crypto/qat/rte_pmd_qat_version.map
deleted file mode 100644
index bbaf1c850..000000000
--- a/drivers/crypto/qat/rte_pmd_qat_version.map
+++ /dev/null
@@ -1,3 +0,0 @@
-DPDK_2.2 {
- local: *;
-};
\ No newline at end of file
--
2.14.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v7 04/16] compress/qat: add xform processing
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 " Pablo de Lara
` (2 preceding siblings ...)
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 03/16] compress/qat: add meson build Pablo de Lara
@ 2018-07-13 2:28 ` Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 05/16] compress/qat: create FW request and process response Pablo de Lara
` (12 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Pablo de Lara @ 2018-07-13 2:28 UTC (permalink / raw)
To: fiona.trahe, tomaszx.jozwiak, john.griffin, deepak.k.jain; +Cc: dev
From: Fiona Trahe <fiona.trahe@intel.com>
Add code to process compressdev rte_comp_xforms, creating
private qat_comp_xforms with prepared firmware message templates.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp.c | 239 ++++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp.h | 30 +++++
drivers/compress/qat/qat_comp_pmd.h | 16 +++
3 files changed, 285 insertions(+)
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index caa115806..cb2005a4b 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -2,4 +2,243 @@
* Copyright(c) 2018 Intel Corporation
*/
+
+#include <rte_mempool.h>
+#include <rte_mbuf.h>
+#include <rte_hexdump.h>
+#include <rte_comp.h>
+#include <rte_bus_pci.h>
+#include <rte_byteorder.h>
+#include <rte_memcpy.h>
+#include <rte_common.h>
+#include <rte_spinlock.h>
+#include <rte_log.h>
+#include <rte_malloc.h>
+
+#include "qat_logs.h"
#include "qat_comp.h"
+#include "qat_comp_pmd.h"
+
+unsigned int
+qat_comp_xform_size(void)
+{
+ return RTE_ALIGN_CEIL(sizeof(struct qat_comp_xform), 8);
+}
+
+static void qat_comp_create_req_hdr(struct icp_qat_fw_comn_req_hdr *header,
+ enum qat_comp_request_type request)
+{
+ if (request == QAT_COMP_REQUEST_FIXED_COMP_STATELESS)
+ header->service_cmd_id = ICP_QAT_FW_COMP_CMD_STATIC;
+ else if (request == QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS)
+ header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DYNAMIC;
+ else if (request == QAT_COMP_REQUEST_DECOMPRESS)
+ header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DECOMPRESS;
+
+ header->service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_COMP;
+ header->hdr_flags =
+ ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
+
+ header->comn_req_flags = ICP_QAT_FW_COMN_FLAGS_BUILD(
+ QAT_COMN_CD_FLD_TYPE_16BYTE_DATA, QAT_COMN_PTR_TYPE_FLAT);
+}
+
+static int qat_comp_create_templates(struct qat_comp_xform *qat_xform,
+ const struct rte_memzone *interm_buff_mz __rte_unused,
+ const struct rte_comp_xform *xform)
+{
+ struct icp_qat_fw_comp_req *comp_req;
+ int comp_level, algo;
+ uint32_t req_par_flags;
+ int direction = ICP_QAT_HW_COMPRESSION_DIR_COMPRESS;
+
+ if (unlikely(qat_xform == NULL)) {
+ QAT_LOG(ERR, "Session was not created for this device");
+ return -EINVAL;
+ }
+
+ if (qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS) {
+ direction = ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS;
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_1;
+ req_par_flags = ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(
+ ICP_QAT_FW_COMP_SOP, ICP_QAT_FW_COMP_EOP,
+ ICP_QAT_FW_COMP_BFINAL, ICP_QAT_FW_COMP_NO_CNV,
+ ICP_QAT_FW_COMP_NO_CNV_RECOVERY);
+
+ } else {
+ if (xform->compress.level == RTE_COMP_LEVEL_PMD_DEFAULT)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_8;
+ else if (xform->compress.level == 1)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_1;
+ else if (xform->compress.level == 2)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_4;
+ else if (xform->compress.level == 3)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_8;
+ else if (xform->compress.level >= 4 &&
+ xform->compress.level <= 9)
+ comp_level = ICP_QAT_HW_COMPRESSION_DEPTH_16;
+ else {
+ QAT_LOG(ERR, "compression level not supported");
+ return -EINVAL;
+ }
+ req_par_flags = ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(
+ ICP_QAT_FW_COMP_SOP, ICP_QAT_FW_COMP_EOP,
+ ICP_QAT_FW_COMP_BFINAL, ICP_QAT_FW_COMP_CNV,
+ ICP_QAT_FW_COMP_CNV_RECOVERY);
+ }
+
+ switch (xform->compress.algo) {
+ case RTE_COMP_ALGO_DEFLATE:
+ algo = ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE;
+ break;
+ case RTE_COMP_ALGO_LZS:
+ default:
+ /* RTE_COMP_NULL */
+ QAT_LOG(ERR, "compression algorithm not supported");
+ return -EINVAL;
+ }
+
+ comp_req = &qat_xform->qat_comp_req_tmpl;
+
+ /* Initialize header */
+ qat_comp_create_req_hdr(&comp_req->comn_hdr,
+ qat_xform->qat_comp_request_type);
+
+ comp_req->comn_hdr.serv_specif_flags = ICP_QAT_FW_COMP_FLAGS_BUILD(
+ ICP_QAT_FW_COMP_STATELESS_SESSION,
+ ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST,
+ ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST,
+ ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST,
+ ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_USED_AS_INTMD_BUF);
+
+ comp_req->cd_pars.sl.comp_slice_cfg_word[0] =
+ ICP_QAT_HW_COMPRESSION_CONFIG_BUILD(
+ direction,
+ /* In CPM 1.6 only valid mode ! */
+ ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_ENABLED, algo,
+ /* Translate level to depth */
+ comp_level, ICP_QAT_HW_COMPRESSION_FILE_TYPE_0);
+
+ comp_req->comp_pars.initial_adler = 1;
+ comp_req->comp_pars.initial_crc32 = 0;
+ comp_req->comp_pars.req_par_flags = req_par_flags;
+
+
+ if (qat_xform->qat_comp_request_type ==
+ QAT_COMP_REQUEST_FIXED_COMP_STATELESS ||
+ qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS) {
+ ICP_QAT_FW_COMN_NEXT_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_DRAM_WR);
+ ICP_QAT_FW_COMN_CURR_ID_SET(&comp_req->comp_cd_ctrl,
+ ICP_QAT_FW_SLICE_COMP);
+ } else if (qat_xform->qat_comp_request_type ==
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {
+
+ QAT_LOG(ERR, "Dynamic huffman encoding not supported");
+ return -EINVAL;
+ }
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_HEXDUMP_LOG(DEBUG, "qat compression message template:", comp_req,
+ sizeof(struct icp_qat_fw_comp_req));
+#endif
+ return 0;
+}
+
+/**
+ * Create driver private_xform data.
+ *
+ * @param dev
+ * Compressdev device
+ * @param xform
+ * xform data from application
+ * @param private_xform
+ * ptr where handle of pmd's private_xform data should be stored
+ * @return
+ * - if successful returns 0
+ * and valid private_xform handle
+ * - <0 in error cases
+ * - Returns -EINVAL if input parameters are invalid.
+ * - Returns -ENOTSUP if comp device does not support the comp transform.
+ * - Returns -ENOMEM if the private_xform could not be allocated.
+ */
+int
+qat_comp_private_xform_create(struct rte_compressdev *dev,
+ const struct rte_comp_xform *xform,
+ void **private_xform)
+{
+ struct qat_comp_dev_private *qat = dev->data->dev_private;
+
+ if (unlikely(private_xform == NULL)) {
+ QAT_LOG(ERR, "QAT: private_xform parameter is NULL");
+ return -EINVAL;
+ }
+ if (unlikely(qat->xformpool == NULL)) {
+ QAT_LOG(ERR, "QAT device has no private_xform mempool");
+ return -ENOMEM;
+ }
+ if (rte_mempool_get(qat->xformpool, private_xform)) {
+ QAT_LOG(ERR, "Couldn't get object from qat xform mempool");
+ return -ENOMEM;
+ }
+
+ struct qat_comp_xform *qat_xform =
+ (struct qat_comp_xform *)*private_xform;
+
+ if (xform->type == RTE_COMP_COMPRESS) {
+ if (xform->compress.deflate.huffman ==
+ RTE_COMP_HUFFMAN_DYNAMIC) {
+ QAT_LOG(ERR,
+ "QAT device doesn't support dynamic compression");
+ return -ENOTSUP;
+ }
+
+ if (xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_FIXED ||
+ ((xform->compress.deflate.huffman == RTE_COMP_HUFFMAN_DEFAULT)
+ && qat->interm_buff_mz == NULL))
+
+ qat_xform->qat_comp_request_type =
+ QAT_COMP_REQUEST_FIXED_COMP_STATELESS;
+
+
+ } else {
+ qat_xform->qat_comp_request_type = QAT_COMP_REQUEST_DECOMPRESS;
+ }
+
+ qat_xform->checksum_type = xform->compress.chksum;
+
+ if (qat_comp_create_templates(qat_xform, qat->interm_buff_mz, xform)) {
+ QAT_LOG(ERR, "QAT: Problem with setting compression");
+ return -EINVAL;
+ }
+ return 0;
+}
+
+/**
+ * Free driver private_xform data.
+ *
+ * @param dev
+ * Compressdev device
+ * @param private_xform
+ * handle of pmd's private_xform data
+ * @return
+ * - 0 if successful
+ * - <0 in error cases
+ * - Returns -EINVAL if input parameters are invalid.
+ */
+int
+qat_comp_private_xform_free(struct rte_compressdev *dev __rte_unused,
+ void *private_xform)
+{
+ struct qat_comp_xform *qat_xform =
+ (struct qat_comp_xform *)private_xform;
+
+ if (qat_xform) {
+ memset(qat_xform, 0, qat_comp_xform_size());
+ struct rte_mempool *mp = rte_mempool_from_obj(qat_xform);
+
+ rte_mempool_put(mp, qat_xform);
+ return 0;
+ }
+ return -EINVAL;
+}
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 89c475ee6..0f58a76c4 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -10,5 +10,35 @@
#include <rte_compressdev.h>
#include <rte_compressdev_pmd.h>
+#include "icp_qat_hw.h"
+#include "icp_qat_fw_comp.h"
+#include "icp_qat_fw_la.h"
+
+enum qat_comp_request_type {
+ QAT_COMP_REQUEST_FIXED_COMP_STATELESS,
+ QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS,
+ QAT_COMP_REQUEST_DECOMPRESS,
+ REQ_COMP_END
+};
+
+
+struct qat_comp_xform {
+ struct icp_qat_fw_comp_req qat_comp_req_tmpl;
+ enum qat_comp_request_type qat_comp_request_type;
+ enum rte_comp_checksum_type checksum_type;
+};
+
+
+int
+qat_comp_private_xform_create(struct rte_compressdev *dev,
+ const struct rte_comp_xform *xform,
+ void **private_xform);
+
+int
+qat_comp_private_xform_free(struct rte_compressdev *dev, void *private_xform);
+
+unsigned int
+qat_comp_xform_size(void);
+
#endif
#endif
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 9b5b54394..fd97cbfd2 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -11,5 +11,21 @@
#include <rte_compressdev_pmd.h>
+/** private data structure for a QAT compression device.
+ * This QAT device is a device offering only a compression service,
+ * there can be one of these on each qat_pci_device (VF).
+ */
+struct qat_comp_dev_private {
+ struct qat_pci_device *qat_dev;
+ /**< The qat pci device hosting the service */
+ struct rte_compressdev *compressdev;
+ /**< The pointer to this compression device structure */
+ const struct rte_memzone *interm_buff_mz;
+ /**< The device's memory for intermediate buffers */
+ struct rte_mempool *xformpool;
+ /**< The device's pool for qat_comp_xforms */
+
+};
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.14.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v7 05/16] compress/qat: create FW request and process response
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 " Pablo de Lara
` (3 preceding siblings ...)
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 04/16] compress/qat: add xform processing Pablo de Lara
@ 2018-07-13 2:28 ` Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 06/16] compress/qat: check that correct firmware is in use Pablo de Lara
` (11 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Pablo de Lara @ 2018-07-13 2:28 UTC (permalink / raw)
To: fiona.trahe, tomaszx.jozwiak, john.griffin, deepak.k.jain; +Cc: dev
From: Fiona Trahe <fiona.trahe@intel.com>
Add functions to create the request message to send to
firmware and to process the firmware response.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp.c | 101 ++++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp.h | 8 +++
drivers/compress/qat/qat_comp_pmd.h | 1 +
3 files changed, 110 insertions(+)
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index cb2005a4b..a32d6ef1d 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -19,6 +19,107 @@
#include "qat_comp.h"
#include "qat_comp_pmd.h"
+
+int
+qat_comp_build_request(void *in_op, uint8_t *out_msg,
+ void *op_cookie __rte_unused,
+ enum qat_device_gen qat_dev_gen __rte_unused)
+{
+ struct rte_comp_op *op = in_op;
+ struct qat_comp_xform *qat_xform = op->private_xform;
+ const uint8_t *tmpl = (uint8_t *)&qat_xform->qat_comp_req_tmpl;
+ struct icp_qat_fw_comp_req *comp_req =
+ (struct icp_qat_fw_comp_req *)out_msg;
+
+ if (unlikely(op->op_type != RTE_COMP_OP_STATELESS)) {
+ QAT_DP_LOG(ERR, "QAT PMD only supports stateless compression "
+ "operation requests, op (%p) is not a "
+ "stateless operation.", op);
+ return -EINVAL;
+ }
+
+ rte_mov128(out_msg, tmpl);
+ comp_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
+
+ /* common for sgl and flat buffers */
+ comp_req->comp_pars.comp_len = op->src.length;
+ comp_req->comp_pars.out_buffer_sz = rte_pktmbuf_pkt_len(op->m_dst);
+
+ /* sgl */
+ if (op->m_src->next != NULL || op->m_dst->next != NULL) {
+ QAT_DP_LOG(ERR, "QAT PMD doesn't support scatter gather");
+ return -EINVAL;
+
+ } else {
+ ICP_QAT_FW_COMN_PTR_TYPE_SET(comp_req->comn_hdr.comn_req_flags,
+ QAT_COMN_PTR_TYPE_FLAT);
+ comp_req->comn_mid.src_length = rte_pktmbuf_data_len(op->m_src);
+ comp_req->comn_mid.dst_length = rte_pktmbuf_data_len(op->m_dst);
+
+ comp_req->comn_mid.src_data_addr =
+ rte_pktmbuf_mtophys_offset(op->m_src, op->src.offset);
+ comp_req->comn_mid.dest_data_addr =
+ rte_pktmbuf_mtophys_offset(op->m_dst, op->dst.offset);
+ }
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_LOG(DEBUG, "Direction: %s",
+ qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS ?
+ "decompression" : "compression");
+ QAT_DP_HEXDUMP_LOG(DEBUG, "qat compression message:", comp_req,
+ sizeof(struct icp_qat_fw_comp_req));
+#endif
+ return 0;
+}
+
+int
+qat_comp_process_response(void **op, uint8_t *resp)
+{
+ struct icp_qat_fw_comp_resp *resp_msg =
+ (struct icp_qat_fw_comp_resp *)resp;
+ struct rte_comp_op *rx_op = (struct rte_comp_op *)(uintptr_t)
+ (resp_msg->opaque_data);
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+ QAT_DP_LOG(DEBUG, "Direction: %s",
+ qat_xform->qat_comp_request_type == QAT_COMP_REQUEST_DECOMPRESS ?
+ "decompression" : "compression");
+ QAT_DP_HEXDUMP_LOG(DEBUG, "qat_response:", (uint8_t *)resp_msg,
+ sizeof(struct icp_qat_fw_comp_resp));
+#endif
+
+ if ((ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(resp_msg->comn_resp.comn_status)
+ | ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(
+ resp_msg->comn_resp.comn_status)) !=
+ ICP_QAT_FW_COMN_STATUS_FLAG_OK) {
+
+ rx_op->status = RTE_COMP_OP_STATUS_ERROR;
+ rx_op->debug_status =
+ *((uint16_t *)(&resp_msg->comn_resp.comn_error));
+ } else {
+ struct qat_comp_xform *qat_xform = rx_op->private_xform;
+ struct icp_qat_fw_resp_comp_pars *comp_resp =
+ (struct icp_qat_fw_resp_comp_pars *)&resp_msg->comp_resp_pars;
+
+ rx_op->status = RTE_COMP_OP_STATUS_SUCCESS;
+ rx_op->consumed = comp_resp->input_byte_counter;
+ rx_op->produced = comp_resp->output_byte_counter;
+
+ if (qat_xform->checksum_type != RTE_COMP_CHECKSUM_NONE) {
+ if (qat_xform->checksum_type == RTE_COMP_CHECKSUM_CRC32)
+ rx_op->output_chksum = comp_resp->curr_crc32;
+ else if (qat_xform->checksum_type ==
+ RTE_COMP_CHECKSUM_ADLER32)
+ rx_op->output_chksum = comp_resp->curr_adler_32;
+ else
+ rx_op->output_chksum = comp_resp->curr_chksum;
+ }
+ }
+ *op = (void *)rx_op;
+
+ return 0;
+}
+
unsigned int
qat_comp_xform_size(void)
{
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 0f58a76c4..46105b40d 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -10,6 +10,7 @@
#include <rte_compressdev.h>
#include <rte_compressdev_pmd.h>
+#include "qat_common.h"
#include "icp_qat_hw.h"
#include "icp_qat_fw_comp.h"
#include "icp_qat_fw_la.h"
@@ -28,6 +29,13 @@ struct qat_comp_xform {
enum rte_comp_checksum_type checksum_type;
};
+int
+qat_comp_build_request(void *in_op, uint8_t *out_msg, void *op_cookie,
+ enum qat_device_gen qat_dev_gen __rte_unused);
+
+int
+qat_comp_process_response(void **op, uint8_t *resp);
+
int
qat_comp_private_xform_create(struct rte_compressdev *dev,
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index fd97cbfd2..cd04f1188 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -10,6 +10,7 @@
#include <rte_compressdev.h>
#include <rte_compressdev_pmd.h>
+#include "qat_device.h"
/** private data structure for a QAT compression device.
* This QAT device is a device offering only a compression service,
--
2.14.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v7 06/16] compress/qat: check that correct firmware is in use
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 " Pablo de Lara
` (4 preceding siblings ...)
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 05/16] compress/qat: create FW request and process response Pablo de Lara
@ 2018-07-13 2:28 ` Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 07/16] compress/qat: add stats functions Pablo de Lara
` (10 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Pablo de Lara @ 2018-07-13 2:28 UTC (permalink / raw)
To: fiona.trahe, tomaszx.jozwiak, john.griffin, deepak.k.jain; +Cc: dev
From: Fiona Trahe <fiona.trahe@intel.com>
Check bit in response message to verify that correct firmware
is in use for compression. If not return an error.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp.c | 16 +++++++++++++++-
drivers/compress/qat/qat_comp.h | 2 ++
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c
index a32d6ef1d..e8019ebc8 100644
--- a/drivers/compress/qat/qat_comp.c
+++ b/drivers/compress/qat/qat_comp.c
@@ -2,7 +2,6 @@
* Copyright(c) 2018 Intel Corporation
*/
-
#include <rte_mempool.h>
#include <rte_mbuf.h>
#include <rte_hexdump.h>
@@ -79,6 +78,8 @@ qat_comp_process_response(void **op, uint8_t *resp)
(struct icp_qat_fw_comp_resp *)resp;
struct rte_comp_op *rx_op = (struct rte_comp_op *)(uintptr_t)
(resp_msg->opaque_data);
+ struct qat_comp_xform *qat_xform = (struct qat_comp_xform *)
+ (rx_op->private_xform);
#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
QAT_DP_LOG(DEBUG, "Direction: %s",
@@ -88,6 +89,19 @@ qat_comp_process_response(void **op, uint8_t *resp)
sizeof(struct icp_qat_fw_comp_resp));
#endif
+ if (likely(qat_xform->qat_comp_request_type
+ != QAT_COMP_REQUEST_DECOMPRESS)) {
+ if (unlikely(ICP_QAT_FW_COMN_HDR_CNV_FLAG_GET(
+ resp_msg->comn_resp.hdr_flags)
+ == ICP_QAT_FW_COMP_NO_CNV)) {
+ rx_op->status = RTE_COMP_OP_STATUS_ERROR;
+ rx_op->debug_status = ERR_CODE_QAT_COMP_WRONG_FW;
+ *op = (void *)rx_op;
+ QAT_DP_LOG(ERR, "QAT has wrong firmware");
+ return 0;
+ }
+ }
+
if ((ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(resp_msg->comn_resp.comn_status)
| ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(
resp_msg->comn_resp.comn_status)) !=
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 46105b40d..937f3c83e 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -15,6 +15,8 @@
#include "icp_qat_fw_comp.h"
#include "icp_qat_fw_la.h"
+#define ERR_CODE_QAT_COMP_WRONG_FW -99
+
enum qat_comp_request_type {
QAT_COMP_REQUEST_FIXED_COMP_STATELESS,
QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS,
--
2.14.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v7 07/16] compress/qat: add stats functions
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 " Pablo de Lara
` (5 preceding siblings ...)
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 06/16] compress/qat: check that correct firmware is in use Pablo de Lara
@ 2018-07-13 2:28 ` Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 08/16] compress/qat: setup queue-pairs for compression service Pablo de Lara
` (9 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Pablo de Lara @ 2018-07-13 2:28 UTC (permalink / raw)
To: fiona.trahe, tomaszx.jozwiak, john.griffin, deepak.k.jain; +Cc: dev
From: Fiona Trahe <fiona.trahe@intel.com>
Add functions to get and clear compression queue-pair statistics.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 35 +++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 7 +++++++
2 files changed, 42 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index fb035d1ee..6feffb784 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -3,3 +3,38 @@
*/
#include "qat_comp_pmd.h"
+
+void
+qat_comp_stats_get(struct rte_compressdev *dev,
+ struct rte_compressdev_stats *stats)
+{
+ struct qat_common_stats qat_stats = {0};
+ struct qat_comp_dev_private *qat_priv;
+
+ if (stats == NULL || dev == NULL) {
+ QAT_LOG(ERR, "invalid ptr: stats %p, dev %p", stats, dev);
+ return;
+ }
+ qat_priv = dev->data->dev_private;
+
+ qat_stats_get(qat_priv->qat_dev, &qat_stats, QAT_SERVICE_COMPRESSION);
+ stats->enqueued_count = qat_stats.enqueued_count;
+ stats->dequeued_count = qat_stats.dequeued_count;
+ stats->enqueue_err_count = qat_stats.enqueue_err_count;
+ stats->dequeue_err_count = qat_stats.dequeue_err_count;
+}
+
+void
+qat_comp_stats_reset(struct rte_compressdev *dev)
+{
+ struct qat_comp_dev_private *qat_priv;
+
+ if (dev == NULL) {
+ QAT_LOG(ERR, "invalid compressdev ptr %p", dev);
+ return;
+ }
+ qat_priv = dev->data->dev_private;
+
+ qat_stats_reset(qat_priv->qat_dev, QAT_SERVICE_COMPRESSION);
+
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index cd04f1188..27d84c8fd 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -28,5 +28,12 @@ struct qat_comp_dev_private {
};
+void
+qat_comp_stats_reset(struct rte_compressdev *dev);
+
+void
+qat_comp_stats_get(struct rte_compressdev *dev,
+ struct rte_compressdev_stats *stats);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.14.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v7 08/16] compress/qat: setup queue-pairs for compression service
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 " Pablo de Lara
` (6 preceding siblings ...)
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 07/16] compress/qat: add stats functions Pablo de Lara
@ 2018-07-13 2:28 ` Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 09/16] compress/qat: add fns to configure and clear device Pablo de Lara
` (8 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Pablo de Lara @ 2018-07-13 2:28 UTC (permalink / raw)
To: fiona.trahe, tomaszx.jozwiak, john.griffin, deepak.k.jain; +Cc: dev
From: Fiona Trahe <fiona.trahe@intel.com>
Setup and clear queue-pairs for handling compression
requests and responses.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp.h | 2 ++
drivers/compress/qat/qat_comp_pmd.c | 61 +++++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 6 ++++
3 files changed, 69 insertions(+)
diff --git a/drivers/compress/qat/qat_comp.h b/drivers/compress/qat/qat_comp.h
index 937f3c83e..9e6861b8a 100644
--- a/drivers/compress/qat/qat_comp.h
+++ b/drivers/compress/qat/qat_comp.h
@@ -24,6 +24,8 @@ enum qat_comp_request_type {
REQ_COMP_END
};
+struct qat_comp_op_cookie {
+};
struct qat_comp_xform {
struct icp_qat_fw_comp_req qat_comp_req_tmpl;
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 6feffb784..5ae6caf83 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -2,6 +2,7 @@
* Copyright(c) 2015-2018 Intel Corporation
*/
+#include "qat_comp.h"
#include "qat_comp_pmd.h"
void
@@ -38,3 +39,63 @@ qat_comp_stats_reset(struct rte_compressdev *dev)
qat_stats_reset(qat_priv->qat_dev, QAT_SERVICE_COMPRESSION);
}
+
+int
+qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)
+{
+ struct qat_comp_dev_private *qat_private = dev->data->dev_private;
+
+ QAT_LOG(DEBUG, "Release comp qp %u on device %d",
+ queue_pair_id, dev->data->dev_id);
+
+ qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][queue_pair_id]
+ = NULL;
+
+ return qat_qp_release((struct qat_qp **)
+ &(dev->data->queue_pairs[queue_pair_id]));
+}
+
+int
+qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
+ uint32_t max_inflight_ops, int socket_id)
+{
+ int ret = 0;
+ struct qat_qp_config qat_qp_conf;
+
+ struct qat_qp **qp_addr =
+ (struct qat_qp **)&(dev->data->queue_pairs[qp_id]);
+ struct qat_comp_dev_private *qat_private = dev->data->dev_private;
+ const struct qat_qp_hw_data *comp_hw_qps =
+ qat_gen_config[qat_private->qat_dev->qat_dev_gen]
+ .qp_hw_data[QAT_SERVICE_COMPRESSION];
+ const struct qat_qp_hw_data *qp_hw_data = comp_hw_qps + qp_id;
+
+ /* If qp is already in use free ring memory and qp metadata. */
+ if (*qp_addr != NULL) {
+ ret = qat_comp_qp_release(dev, qp_id);
+ if (ret < 0)
+ return ret;
+ }
+ if (qp_id >= qat_qps_per_service(comp_hw_qps,
+ QAT_SERVICE_COMPRESSION)) {
+ QAT_LOG(ERR, "qp_id %u invalid for this device", qp_id);
+ return -EINVAL;
+ }
+
+ qat_qp_conf.hw = qp_hw_data;
+ qat_qp_conf.build_request = qat_comp_build_request;
+ qat_qp_conf.cookie_size = sizeof(struct qat_comp_op_cookie);
+ qat_qp_conf.nb_descriptors = max_inflight_ops;
+ qat_qp_conf.socket_id = socket_id;
+ qat_qp_conf.service_str = "comp";
+
+ ret = qat_qp_setup(qat_private->qat_dev, qp_addr, qp_id, &qat_qp_conf);
+ if (ret != 0)
+ return ret;
+
+ /* store a link to the qp in the qat_pci_device */
+ qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][qp_id]
+ = *qp_addr;
+
+ return ret;
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 27d84c8fd..5a4bc3154 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -34,6 +34,12 @@ qat_comp_stats_reset(struct rte_compressdev *dev);
void
qat_comp_stats_get(struct rte_compressdev *dev,
struct rte_compressdev_stats *stats);
+int
+qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id);
+
+int
+qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
+ uint32_t max_inflight_ops, int socket_id);
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.14.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v7 09/16] compress/qat: add fns to configure and clear device
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 " Pablo de Lara
` (7 preceding siblings ...)
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 08/16] compress/qat: setup queue-pairs for compression service Pablo de Lara
@ 2018-07-13 2:28 ` Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 10/16] compress/qat: add fn to return device info Pablo de Lara
` (7 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Pablo de Lara @ 2018-07-13 2:28 UTC (permalink / raw)
To: fiona.trahe, tomaszx.jozwiak, john.griffin, deepak.k.jain; +Cc: dev
From: Fiona Trahe <fiona.trahe@intel.com>
Add functions to configure and clear the qat comp device,
including the creation and freeing of the xform pool
and the freeing of queue-pairs.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 95 +++++++++++++++++++++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 7 +++
2 files changed, 102 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 5ae6caf83..beab6e32f 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -99,3 +99,98 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
return ret;
}
+
+static struct rte_mempool *
+qat_comp_create_xform_pool(struct qat_comp_dev_private *comp_dev,
+ uint32_t num_elements)
+{
+ char xform_pool_name[RTE_MEMPOOL_NAMESIZE];
+ struct rte_mempool *mp;
+
+ snprintf(xform_pool_name, RTE_MEMPOOL_NAMESIZE,
+ "%s_xforms", comp_dev->qat_dev->name);
+
+ QAT_LOG(DEBUG, "xformpool: %s", xform_pool_name);
+ mp = rte_mempool_lookup(xform_pool_name);
+
+ if (mp != NULL) {
+ QAT_LOG(DEBUG, "xformpool already created");
+ if (mp->size != num_elements) {
+ QAT_LOG(DEBUG, "xformpool wrong size - delete it");
+ rte_mempool_free(mp);
+ mp = NULL;
+ comp_dev->xformpool = NULL;
+ }
+ }
+
+ if (mp == NULL)
+ mp = rte_mempool_create(xform_pool_name,
+ num_elements,
+ qat_comp_xform_size(), 0, 0,
+ NULL, NULL, NULL, NULL, rte_socket_id(),
+ 0);
+ if (mp == NULL) {
+ QAT_LOG(ERR, "Err creating mempool %s w %d elements of size %d",
+ xform_pool_name, num_elements, qat_comp_xform_size());
+ return NULL;
+ }
+
+ return mp;
+}
+
+static void
+_qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)
+{
+ /* Free private_xform pool */
+ if (comp_dev->xformpool) {
+ /* Free internal mempool for private xforms */
+ rte_mempool_free(comp_dev->xformpool);
+ comp_dev->xformpool = NULL;
+ }
+}
+
+int
+qat_comp_dev_config(struct rte_compressdev *dev,
+ struct rte_compressdev_config *config)
+{
+ struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
+ int ret = 0;
+
+ if (config->max_nb_streams != 0) {
+ QAT_LOG(ERR,
+ "QAT device does not support STATEFUL so max_nb_streams must be 0");
+ return -EINVAL;
+ }
+
+ comp_dev->xformpool = qat_comp_create_xform_pool(comp_dev,
+ config->max_nb_priv_xforms);
+ if (comp_dev->xformpool == NULL) {
+
+ ret = -ENOMEM;
+ goto error_out;
+ }
+ return 0;
+
+error_out:
+ _qat_comp_dev_config_clear(comp_dev);
+ return ret;
+}
+
+
+int
+qat_comp_dev_close(struct rte_compressdev *dev)
+{
+ int i;
+ int ret = 0;
+ struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
+
+ for (i = 0; i < dev->data->nb_queue_pairs; i++) {
+ ret = qat_comp_qp_release(dev, i);
+ if (ret < 0)
+ return ret;
+ }
+
+ _qat_comp_dev_config_clear(comp_dev);
+
+ return ret;
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 5a4bc3154..b10a66f65 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -41,5 +41,12 @@ int
qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
uint32_t max_inflight_ops, int socket_id);
+int
+qat_comp_dev_config(struct rte_compressdev *dev,
+ struct rte_compressdev_config *config);
+
+int
+qat_comp_dev_close(struct rte_compressdev *dev);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.14.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v7 10/16] compress/qat: add fn to return device info
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 " Pablo de Lara
` (8 preceding siblings ...)
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 09/16] compress/qat: add fns to configure and clear device Pablo de Lara
@ 2018-07-13 2:28 ` Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 11/16] compress/qat: add enqueue/dequeue functions Pablo de Lara
` (6 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Pablo de Lara @ 2018-07-13 2:28 UTC (permalink / raw)
To: fiona.trahe, tomaszx.jozwiak, john.griffin, deepak.k.jain; +Cc: dev
From: Fiona Trahe <fiona.trahe@intel.com>
Add capabilities pointer to internal qat comp device
and function to return this and other info.
C
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 19 +++++++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 6 ++++++
2 files changed, 25 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index beab6e32f..482ebd1a9 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -194,3 +194,22 @@ qat_comp_dev_close(struct rte_compressdev *dev)
return ret;
}
+
+
+void
+qat_comp_dev_info_get(struct rte_compressdev *dev,
+ struct rte_compressdev_info *info)
+{
+ struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
+ const struct qat_qp_hw_data *comp_hw_qps =
+ qat_gen_config[comp_dev->qat_dev->qat_dev_gen]
+ .qp_hw_data[QAT_SERVICE_COMPRESSION];
+
+ if (info != NULL) {
+ info->max_nb_queue_pairs =
+ qat_qps_per_service(comp_hw_qps,
+ QAT_SERVICE_COMPRESSION);
+ info->feature_flags = dev->feature_flags;
+ info->capabilities = comp_dev->qat_dev_capabilities;
+ }
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index b10a66f65..22576f44b 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -21,6 +21,8 @@ struct qat_comp_dev_private {
/**< The qat pci device hosting the service */
struct rte_compressdev *compressdev;
/**< The pointer to this compression device structure */
+ const struct rte_compressdev_capabilities *qat_dev_capabilities;
+ /* QAT device compression capabilities */
const struct rte_memzone *interm_buff_mz;
/**< The device's memory for intermediate buffers */
struct rte_mempool *xformpool;
@@ -48,5 +50,9 @@ qat_comp_dev_config(struct rte_compressdev *dev,
int
qat_comp_dev_close(struct rte_compressdev *dev);
+void
+qat_comp_dev_info_get(struct rte_compressdev *dev,
+ struct rte_compressdev_info *info);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.14.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v7 11/16] compress/qat: add enqueue/dequeue functions
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 " Pablo de Lara
` (9 preceding siblings ...)
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 10/16] compress/qat: add fn to return device info Pablo de Lara
@ 2018-07-13 2:28 ` Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 12/16] compress/qat: add device start and stop fns Pablo de Lara
` (5 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Pablo de Lara @ 2018-07-13 2:28 UTC (permalink / raw)
To: fiona.trahe, tomaszx.jozwiak, john.griffin, deepak.k.jain; +Cc: dev
From: Fiona Trahe <fiona.trahe@intel.com>
Wrap generic qat enqueue/dequeue functions with
compressdev enqueue and dequeue fns.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 14 ++++++++++++++
drivers/compress/qat/qat_comp_pmd.h | 8 ++++++++
2 files changed, 22 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 482ebd1a9..086b6cfd2 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -213,3 +213,17 @@ qat_comp_dev_info_get(struct rte_compressdev *dev,
info->capabilities = comp_dev->qat_dev_capabilities;
}
}
+
+uint16_t
+qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops)
+{
+ return qat_enqueue_op_burst(qp, (void **)ops, nb_ops);
+}
+
+uint16_t
+qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops)
+{
+ return qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 22576f44b..f360c2982 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -54,5 +54,13 @@ void
qat_comp_dev_info_get(struct rte_compressdev *dev,
struct rte_compressdev_info *info);
+uint16_t
+qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops);
+
+uint16_t
+qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.14.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v7 12/16] compress/qat: add device start and stop fns
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 " Pablo de Lara
` (10 preceding siblings ...)
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 11/16] compress/qat: add enqueue/dequeue functions Pablo de Lara
@ 2018-07-13 2:28 ` Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 13/16] compress/qat: create and populate the ops structure Pablo de Lara
` (4 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Pablo de Lara @ 2018-07-13 2:28 UTC (permalink / raw)
To: fiona.trahe, tomaszx.jozwiak, john.griffin, deepak.k.jain; +Cc: dev
From: Fiona Trahe <fiona.trahe@intel.com>
There are no specific actions needed to start/stop a QAT comp device
so these are just trivial fns to satisfy the pmd API.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 11 +++++++++++
drivers/compress/qat/qat_comp_pmd.h | 6 ++++++
2 files changed, 17 insertions(+)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 086b6cfd2..1ab5cf74e 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -176,6 +176,17 @@ qat_comp_dev_config(struct rte_compressdev *dev,
return ret;
}
+int
+qat_comp_dev_start(struct rte_compressdev *dev __rte_unused)
+{
+ return 0;
+}
+
+void
+qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused)
+{
+
+}
int
qat_comp_dev_close(struct rte_compressdev *dev)
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index f360c2982..22cbefbc8 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -62,5 +62,11 @@ uint16_t
qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops);
+int
+qat_comp_dev_start(struct rte_compressdev *dev __rte_unused);
+
+void
+qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused);
+
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.14.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v7 13/16] compress/qat: create and populate the ops structure
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 " Pablo de Lara
` (11 preceding siblings ...)
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 12/16] compress/qat: add device start and stop fns Pablo de Lara
@ 2018-07-13 2:28 ` Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 14/16] compress/qat: add fns to create and destroy the PMD Pablo de Lara
` (3 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Pablo de Lara @ 2018-07-13 2:28 UTC (permalink / raw)
To: fiona.trahe, tomaszx.jozwiak, john.griffin, deepak.k.jain; +Cc: dev
From: Fiona Trahe <fiona.trahe@intel.com>
Create an ops structure and populate it with the
qat-specific functions.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 38 ++++++++++++++++++++++++++++---------
drivers/compress/qat/qat_comp_pmd.h | 30 -----------------------------
2 files changed, 29 insertions(+), 39 deletions(-)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 1ab5cf74e..013ff6e8d 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -5,7 +5,7 @@
#include "qat_comp.h"
#include "qat_comp_pmd.h"
-void
+static void
qat_comp_stats_get(struct rte_compressdev *dev,
struct rte_compressdev_stats *stats)
{
@@ -25,7 +25,7 @@ qat_comp_stats_get(struct rte_compressdev *dev,
stats->dequeue_err_count = qat_stats.dequeue_err_count;
}
-void
+static void
qat_comp_stats_reset(struct rte_compressdev *dev)
{
struct qat_comp_dev_private *qat_priv;
@@ -40,7 +40,7 @@ qat_comp_stats_reset(struct rte_compressdev *dev)
}
-int
+static int
qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)
{
struct qat_comp_dev_private *qat_private = dev->data->dev_private;
@@ -55,7 +55,7 @@ qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id)
&(dev->data->queue_pairs[queue_pair_id]));
}
-int
+static int
qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
uint32_t max_inflight_ops, int socket_id)
{
@@ -149,7 +149,7 @@ _qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev)
}
}
-int
+static int
qat_comp_dev_config(struct rte_compressdev *dev,
struct rte_compressdev_config *config)
{
@@ -176,19 +176,19 @@ qat_comp_dev_config(struct rte_compressdev *dev,
return ret;
}
-int
+static int
qat_comp_dev_start(struct rte_compressdev *dev __rte_unused)
{
return 0;
}
-void
+static void
qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused)
{
}
-int
+static int
qat_comp_dev_close(struct rte_compressdev *dev)
{
int i;
@@ -207,7 +207,7 @@ qat_comp_dev_close(struct rte_compressdev *dev)
}
-void
+static void
qat_comp_dev_info_get(struct rte_compressdev *dev,
struct rte_compressdev_info *info)
{
@@ -238,3 +238,23 @@ qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
{
return qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
}
+
+
+struct rte_compressdev_ops compress_qat_ops = {
+
+ /* Device related operations */
+ .dev_configure = qat_comp_dev_config,
+ .dev_start = qat_comp_dev_start,
+ .dev_stop = qat_comp_dev_stop,
+ .dev_close = qat_comp_dev_close,
+ .dev_infos_get = qat_comp_dev_info_get,
+
+ .stats_get = qat_comp_stats_get,
+ .stats_reset = qat_comp_stats_reset,
+ .queue_pair_setup = qat_comp_qp_setup,
+ .queue_pair_release = qat_comp_qp_release,
+
+ /* Compression related operations */
+ .private_xform_create = qat_comp_private_xform_create,
+ .private_xform_free = qat_comp_private_xform_free
+};
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 22cbefbc8..7ba1b8dc6 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -30,30 +30,6 @@ struct qat_comp_dev_private {
};
-void
-qat_comp_stats_reset(struct rte_compressdev *dev);
-
-void
-qat_comp_stats_get(struct rte_compressdev *dev,
- struct rte_compressdev_stats *stats);
-int
-qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id);
-
-int
-qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
- uint32_t max_inflight_ops, int socket_id);
-
-int
-qat_comp_dev_config(struct rte_compressdev *dev,
- struct rte_compressdev_config *config);
-
-int
-qat_comp_dev_close(struct rte_compressdev *dev);
-
-void
-qat_comp_dev_info_get(struct rte_compressdev *dev,
- struct rte_compressdev_info *info);
-
uint16_t
qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops);
@@ -62,11 +38,5 @@ uint16_t
qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops);
-int
-qat_comp_dev_start(struct rte_compressdev *dev __rte_unused);
-
-void
-qat_comp_dev_stop(struct rte_compressdev *dev __rte_unused);
-
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.14.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v7 14/16] compress/qat: add fns to create and destroy the PMD
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 " Pablo de Lara
` (12 preceding siblings ...)
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 13/16] compress/qat: create and populate the ops structure Pablo de Lara
@ 2018-07-13 2:28 ` Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 15/16] compress/qat: prevent device usage if incorrect firmware Pablo de Lara
` (2 subsequent siblings)
16 siblings, 0 replies; 106+ messages in thread
From: Pablo de Lara @ 2018-07-13 2:28 UTC (permalink / raw)
To: fiona.trahe, tomaszx.jozwiak, john.griffin, deepak.k.jain; +Cc: dev
From: Fiona Trahe <fiona.trahe@intel.com>
Now that all the device operations are available,
add the functions to create and destroy the pmd.
Called on probe and remove of the qat pci device, these
register the device with the compressdev API
and plug in all the device functionality.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
---
drivers/common/qat/qat_device.h | 4 ++
drivers/common/qat/qat_qp.c | 11 ++++-
drivers/common/qat/qat_qp.h | 5 ++
drivers/compress/qat/qat_comp_pmd.c | 98 +++++++++++++++++++++++++++++++++++--
drivers/compress/qat/qat_comp_pmd.h | 11 ++---
5 files changed, 117 insertions(+), 12 deletions(-)
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index 0cb370c72..9599fc596 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -25,6 +25,8 @@
* - runtime data
*/
struct qat_sym_dev_private;
+struct qat_comp_dev_private;
+
struct qat_pci_device {
/* Data used by all services */
@@ -55,6 +57,8 @@ struct qat_pci_device {
*/
/* Data relating to compression service */
+ struct qat_comp_dev_private *comp_dev;
+ /**< link back to compressdev private data */
/* Data relating to asymmetric crypto service */
diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c
index 32c17596b..7ca7a45eb 100644
--- a/drivers/common/qat/qat_qp.c
+++ b/drivers/common/qat/qat_qp.c
@@ -15,6 +15,7 @@
#include "qat_device.h"
#include "qat_qp.h"
#include "qat_sym.h"
+#include "qat_comp.h"
#include "adf_transport_access_macros.h"
@@ -606,8 +607,8 @@ qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
if (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC)
qat_sym_process_response(ops, resp_msg);
- /* add qat_asym_process_response here */
- /* add qat_comp_process_response here */
+ else if (tmp_qp->service_type == QAT_SERVICE_COMPRESSION)
+ qat_comp_process_response(ops, resp_msg);
head = adf_modulo(head + rx_queue->msg_size,
rx_queue->modulo_mask);
@@ -633,3 +634,9 @@ qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
}
return resp_counter;
}
+
+__attribute__((weak)) int
+qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused)
+{
+ return 0;
+}
diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h
index 59db945e7..69f8a6131 100644
--- a/drivers/common/qat/qat_qp.h
+++ b/drivers/common/qat/qat_qp.h
@@ -103,4 +103,9 @@ qat_qp_setup(struct qat_pci_device *qat_dev,
int
qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,
enum qat_service_type service);
+
+/* Needed for weak function*/
+int
+qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused);
+
#endif /* _QAT_QP_H_ */
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 013ff6e8d..9bb98974c 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -5,6 +5,18 @@
#include "qat_comp.h"
#include "qat_comp_pmd.h"
+static const struct rte_compressdev_capabilities qat_comp_gen_capabilities[] = {
+ {/* COMPRESSION - deflate */
+ .algo = RTE_COMP_ALGO_DEFLATE,
+ .comp_feature_flags = RTE_COMP_FF_MULTI_PKT_CHECKSUM |
+ RTE_COMP_FF_CRC32_CHECKSUM |
+ RTE_COMP_FF_ADLER32_CHECKSUM |
+ RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
+ RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
+ RTE_COMP_FF_HUFFMAN_FIXED,
+ .window_size = {.min = 15, .max = 15, .increment = 0} },
+ {RTE_COMP_ALGO_LIST_END, 0, {0, 0, 0} } };
+
static void
qat_comp_stats_get(struct rte_compressdev *dev,
struct rte_compressdev_stats *stats)
@@ -225,14 +237,14 @@ qat_comp_dev_info_get(struct rte_compressdev *dev,
}
}
-uint16_t
+static uint16_t
qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops)
{
return qat_enqueue_op_burst(qp, (void **)ops, nb_ops);
}
-uint16_t
+static uint16_t
qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
uint16_t nb_ops)
{
@@ -240,7 +252,7 @@ qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
}
-struct rte_compressdev_ops compress_qat_ops = {
+static struct rte_compressdev_ops compress_qat_ops = {
/* Device related operations */
.dev_configure = qat_comp_dev_config,
@@ -258,3 +270,83 @@ struct rte_compressdev_ops compress_qat_ops = {
.private_xform_create = qat_comp_private_xform_create,
.private_xform_free = qat_comp_private_xform_free
};
+
+int
+qat_comp_dev_create(struct qat_pci_device *qat_pci_dev)
+{
+ if (qat_pci_dev->qat_dev_gen == QAT_GEN1) {
+ QAT_LOG(ERR, "Compression PMD not supported on QAT dh895xcc");
+ return 0;
+ }
+
+ struct rte_compressdev_pmd_init_params init_params = {
+ .name = "",
+ .socket_id = qat_pci_dev->pci_dev->device.numa_node,
+ };
+ char name[RTE_COMPRESSDEV_NAME_MAX_LEN];
+ struct rte_compressdev *compressdev;
+ struct qat_comp_dev_private *comp_dev;
+
+ snprintf(name, RTE_COMPRESSDEV_NAME_MAX_LEN, "%s_%s",
+ qat_pci_dev->name, "comp");
+ QAT_LOG(DEBUG, "Creating QAT COMP device %s", name);
+
+ compressdev = rte_compressdev_pmd_create(name,
+ &qat_pci_dev->pci_dev->device,
+ sizeof(struct qat_comp_dev_private),
+ &init_params);
+
+ if (compressdev == NULL)
+ return -ENODEV;
+
+ compressdev->dev_ops = &compress_qat_ops;
+
+ compressdev->enqueue_burst = qat_comp_pmd_enqueue_op_burst;
+ compressdev->dequeue_burst = qat_comp_pmd_dequeue_op_burst;
+
+ compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
+
+ comp_dev = compressdev->data->dev_private;
+ comp_dev->qat_dev = qat_pci_dev;
+ comp_dev->compressdev = compressdev;
+ qat_pci_dev->comp_dev = comp_dev;
+
+ switch (qat_pci_dev->qat_dev_gen) {
+ case QAT_GEN1:
+ case QAT_GEN2:
+ comp_dev->qat_dev_capabilities = qat_comp_gen_capabilities;
+ break;
+ default:
+ comp_dev->qat_dev_capabilities = qat_comp_gen_capabilities;
+ QAT_LOG(DEBUG,
+ "QAT gen %d capabilities unknown, default to GEN1",
+ qat_pci_dev->qat_dev_gen);
+ break;
+ }
+
+ QAT_LOG(DEBUG,
+ "Created QAT COMP device %s as compressdev instance %d",
+ name, compressdev->data->dev_id);
+ return 0;
+}
+
+int
+qat_comp_dev_destroy(struct qat_pci_device *qat_pci_dev)
+{
+ struct qat_comp_dev_private *comp_dev;
+
+ if (qat_pci_dev == NULL)
+ return -ENODEV;
+
+ comp_dev = qat_pci_dev->comp_dev;
+ if (comp_dev == NULL)
+ return 0;
+
+ /* clean up any resources used by the device */
+ qat_comp_dev_close(comp_dev->compressdev);
+
+ rte_compressdev_pmd_destroy(comp_dev->compressdev);
+ qat_pci_dev->comp_dev = NULL;
+
+ return 0;
+}
diff --git a/drivers/compress/qat/qat_comp_pmd.h b/drivers/compress/qat/qat_comp_pmd.h
index 7ba1b8dc6..9ad2a2836 100644
--- a/drivers/compress/qat/qat_comp_pmd.h
+++ b/drivers/compress/qat/qat_comp_pmd.h
@@ -27,16 +27,13 @@ struct qat_comp_dev_private {
/**< The device's memory for intermediate buffers */
struct rte_mempool *xformpool;
/**< The device's pool for qat_comp_xforms */
-
};
-uint16_t
-qat_comp_pmd_enqueue_op_burst(void *qp, struct rte_comp_op **ops,
- uint16_t nb_ops);
+int
+qat_comp_dev_create(struct qat_pci_device *qat_pci_dev);
-uint16_t
-qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
- uint16_t nb_ops);
+int
+qat_comp_dev_destroy(struct qat_pci_device *qat_pci_dev);
#endif
#endif /* _QAT_COMP_PMD_H_ */
--
2.14.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v7 15/16] compress/qat: prevent device usage if incorrect firmware
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 " Pablo de Lara
` (13 preceding siblings ...)
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 14/16] compress/qat: add fns to create and destroy the PMD Pablo de Lara
@ 2018-07-13 2:28 ` Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 16/16] doc/qat: refactor docs adding compression guide Pablo de Lara
2018-07-13 14:22 ` [dpdk-dev] [PATCH v7 00/16] compress/qat: add compression PMD De Lara Guarch, Pablo
16 siblings, 0 replies; 106+ messages in thread
From: Pablo de Lara @ 2018-07-13 2:28 UTC (permalink / raw)
To: fiona.trahe, tomaszx.jozwiak, john.griffin, deepak.k.jain; +Cc: dev
From: Fiona Trahe <fiona.trahe@intel.com>
Previous check only causes op to fail on dequeue.
This extends so once first fail is detected, application can
no longer enqueue ops to the device and will also get an
appropriate error if trying to reconfigure or setup the device.
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
drivers/compress/qat/qat_comp_pmd.c | 57 ++++++++++++++++++++++++++++++++++++-
1 file changed, 56 insertions(+), 1 deletion(-)
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 9bb98974c..0a571b3d6 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -252,6 +252,61 @@ qat_comp_pmd_dequeue_op_burst(void *qp, struct rte_comp_op **ops,
}
+static uint16_t
+qat_comp_pmd_enq_deq_dummy_op_burst(void *qp __rte_unused,
+ struct rte_comp_op **ops __rte_unused,
+ uint16_t nb_ops __rte_unused)
+{
+ QAT_DP_LOG(ERR, "QAT PMD detected wrong FW version !");
+ return 0;
+}
+
+static struct rte_compressdev_ops compress_qat_dummy_ops = {
+
+ /* Device related operations */
+ .dev_configure = NULL,
+ .dev_start = NULL,
+ .dev_stop = qat_comp_dev_stop,
+ .dev_close = qat_comp_dev_close,
+ .dev_infos_get = NULL,
+
+ .stats_get = NULL,
+ .stats_reset = qat_comp_stats_reset,
+ .queue_pair_setup = NULL,
+ .queue_pair_release = qat_comp_qp_release,
+
+ /* Compression related operations */
+ .private_xform_create = NULL,
+ .private_xform_free = qat_comp_private_xform_free
+};
+
+static uint16_t
+qat_comp_pmd_dequeue_frst_op_burst(void *qp, struct rte_comp_op **ops,
+ uint16_t nb_ops)
+{
+ uint16_t ret = qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
+ struct qat_qp *tmp_qp = (struct qat_qp *)qp;
+
+ if (ret) {
+ if ((*ops)->debug_status ==
+ (uint64_t)ERR_CODE_QAT_COMP_WRONG_FW) {
+ tmp_qp->qat_dev->comp_dev->compressdev->enqueue_burst =
+ qat_comp_pmd_enq_deq_dummy_op_burst;
+ tmp_qp->qat_dev->comp_dev->compressdev->dequeue_burst =
+ qat_comp_pmd_enq_deq_dummy_op_burst;
+
+ tmp_qp->qat_dev->comp_dev->compressdev->dev_ops =
+ &compress_qat_dummy_ops;
+ QAT_LOG(ERR, "QAT PMD detected wrong FW version !");
+
+ } else {
+ tmp_qp->qat_dev->comp_dev->compressdev->dequeue_burst =
+ qat_comp_pmd_dequeue_op_burst;
+ }
+ }
+ return ret;
+}
+
static struct rte_compressdev_ops compress_qat_ops = {
/* Device related operations */
@@ -302,7 +357,7 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev)
compressdev->dev_ops = &compress_qat_ops;
compressdev->enqueue_burst = qat_comp_pmd_enqueue_op_burst;
- compressdev->dequeue_burst = qat_comp_pmd_dequeue_op_burst;
+ compressdev->dequeue_burst = qat_comp_pmd_dequeue_frst_op_burst;
compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
--
2.14.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* [dpdk-dev] [PATCH v7 16/16] doc/qat: refactor docs adding compression guide
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 " Pablo de Lara
` (14 preceding siblings ...)
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 15/16] compress/qat: prevent device usage if incorrect firmware Pablo de Lara
@ 2018-07-13 2:28 ` Pablo de Lara
2018-07-13 14:22 ` [dpdk-dev] [PATCH v7 00/16] compress/qat: add compression PMD De Lara Guarch, Pablo
16 siblings, 0 replies; 106+ messages in thread
From: Pablo de Lara @ 2018-07-13 2:28 UTC (permalink / raw)
To: fiona.trahe, tomaszx.jozwiak, john.griffin, deepak.k.jain; +Cc: dev
From: Fiona Trahe <fiona.trahe@intel.com>
Extend QAT guide to cover crypto and compression and common
information, particularly about kernel driver dependency.
Update release note.
Update compression feature list for qat.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
config/common_base | 2 +-
doc/guides/compressdevs/features/qat.ini | 12 ++
doc/guides/compressdevs/index.rst | 1 +
doc/guides/compressdevs/qat_comp.rst | 49 +++++++++
doc/guides/cryptodevs/qat.rst | 183 +++++++++++++++++++++----------
doc/guides/rel_notes/release_18_08.rst | 5 +
6 files changed, 193 insertions(+), 59 deletions(-)
create mode 100644 doc/guides/compressdevs/features/qat.ini
create mode 100644 doc/guides/compressdevs/qat_comp.rst
diff --git a/config/common_base b/config/common_base
index 8b539af65..e569b35ee 100644
--- a/config/common_base
+++ b/config/common_base
@@ -478,7 +478,7 @@ CONFIG_RTE_LIBRTE_PMD_DPAA_SEC=n
CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4
#
-# Compile PMD for QuickAssist based devices
+# Compile PMD for QuickAssist based devices - see docs for details
#
CONFIG_RTE_LIBRTE_PMD_QAT=y
CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
diff --git a/doc/guides/compressdevs/features/qat.ini b/doc/guides/compressdevs/features/qat.ini
new file mode 100644
index 000000000..12bfb21d3
--- /dev/null
+++ b/doc/guides/compressdevs/features/qat.ini
@@ -0,0 +1,12 @@
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+; Supported features of 'QAT' compression driver.
+;
+[Features]
+HW Accelerated = Y
+Deflate = Y
+Adler32 = Y
+Crc32 = Y
+Adler32&Crc32 = Y
+Fixed = Y
diff --git a/doc/guides/compressdevs/index.rst b/doc/guides/compressdevs/index.rst
index bc59ce810..422876873 100644
--- a/doc/guides/compressdevs/index.rst
+++ b/doc/guides/compressdevs/index.rst
@@ -11,3 +11,4 @@ Compression Device Drivers
overview
isal
+ qat_comp
diff --git a/doc/guides/compressdevs/qat_comp.rst b/doc/guides/compressdevs/qat_comp.rst
new file mode 100644
index 000000000..167f816b7
--- /dev/null
+++ b/doc/guides/compressdevs/qat_comp.rst
@@ -0,0 +1,49 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+ Copyright(c) 2018 Intel Corporation.
+
+Intel(R) QuickAssist (QAT) Compression Poll Mode Driver
+=======================================================
+
+The QAT compression PMD provides poll mode compression & decompression driver
+support for the following hardware accelerator devices:
+
+* ``Intel QuickAssist Technology C62x``
+* ``Intel QuickAssist Technology C3xxx``
+
+
+Features
+--------
+
+QAT compression PMD has support for:
+
+Compression/Decompression algorithm:
+
+ * DEFLATE
+
+Huffman code type:
+
+ * FIXED
+
+Window size support:
+
+ * 32K
+
+Checksum generation:
+
+ * CRC32, Adler and combined checksum
+
+Limitations
+-----------
+
+* Chained mbufs are not yet supported, therefore max data size which can be passed to the PMD in a single mbuf is 64K - 1. If data is larger than this it will need to be split up and sent as multiple operations.
+
+* Compressdev level 0, no compression, is not supported.
+
+* Dynamic Huffman encoding is not yet supported.
+
+Installation
+------------
+
+The QAT compression PMD is built by default with a standard DPDK build.
+
+It depends on a QAT kernel driver, see :ref:`qat_kernel_installation`.
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index b899985ad..bdc58eb2c 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -68,12 +68,32 @@ Limitations
* Queue pairs are not thread-safe (that is, within a single queue pair, RX and TX from different lcores is not supported).
-Installation
-------------
+Extra notes on KASUMI F9
+------------------------
+
+When using KASUMI F9 authentication algorithm, the input buffer must be
+constructed according to the 3GPP KASUMI specifications (section 4.4, page 13):
+`<http://cryptome.org/3gpp/35201-900.pdf>`_.
+Input buffer has to have COUNT (4 bytes), FRESH (4 bytes), MESSAGE and DIRECTION (1 bit)
+concatenated. After the DIRECTION bit, a single '1' bit is appended, followed by
+between 0 and 7 '0' bits, so that the total length of the buffer is multiple of 8 bits.
+Note that the actual message can be any length, specified in bits.
-To enable QAT in DPDK, follow the instructions for modifying the compile-time
+Once this buffer is passed this way, when creating the crypto operation,
+length of data to authenticate (op.sym.auth.data.length) must be the length
+of all the items described above, including the padding at the end.
+Also, offset of data to authenticate (op.sym.auth.data.offset)
+must be such that points at the start of the COUNT bytes.
+
+
+Building the DPDK QAT cryptodev PMD
+-----------------------------------
+
+
+To enable QAT crypto in DPDK, follow the instructions for modifying the compile-time
configuration file as described `here <http://dpdk.org/doc/guides/linux_gsg/build_dpdk.html>`_.
+
Quick instructions are as follows:
.. code-block:: console
@@ -81,29 +101,95 @@ Quick instructions are as follows:
cd to the top-level DPDK directory
make config T=x86_64-native-linuxapp-gcc
sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT\)=n,\1=y,' build/.config
+ sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT_SYM\)=n,\1=y,' build/.config
make
-To use the DPDK QAT PMD an SRIOV-enabled QAT kernel driver is required. The VF
-devices exposed by this driver will be used by the QAT PMD. The devices and
-available kernel drivers and device ids are :
+
+.. _qat_kernel_installation:
+
+Dependency on the QAT kernel driver
+-----------------------------------
+
+To use the QAT PMD an SRIOV-enabled QAT kernel driver is required. The VF
+devices created and initialised by this driver will be used by the QAT PMD.
+
+Instructions for installation are below, but first an explanation of the
+relationships between the PF/VF devices and the PMDs visible to
+DPDK applications.
+
+
+Acceleration services - cryptography and compression - are provided to DPDK
+applications via PMDs which register to implement the corresponding
+cryptodev and compressdev APIs.
+
+Each QuickAssist VF device can expose one cryptodev PMD and/or one compressdev PMD.
+These QAT PMDs share the same underlying device and pci-mgmt code, but are
+enumerated independently on their respective APIs and appear as independent
+devices to applications.
+
+.. Note::
+
+ Each VF can only be used by one DPDK process. It is not possible to share
+ the same VF across multiple processes, even if these processes are using
+ different acceleration services.
+
+ Conversely one DPDK process can use one or more QAT VFs and can expose both
+ cryptodev and compressdev instances on each of those VFs.
+
+
+
+Device and driver naming
+------------------------
+
+* The qat cryptodev driver name is "crypto_qat".
+ The rte_cryptodev_devices_get() returns the devices exposed by this driver.
+
+* Each qat crypto device has a unique name, in format
+ <pci bdf>_<service>, e.g. "0000:41:01.0_qat_sym".
+ This name can be passed to rte_cryptodev_get_dev_id() to get the device_id.
+
+.. Note::
+
+ The qat crypto driver name is passed to the dpdk-test-crypto-perf tool in the -devtype parameter.
+
+ The qat crypto device name is in the format of the slave parameter passed to the crypto scheduler.
+
+* The qat compressdev driver name is "comp_qat".
+ The rte_compressdev_devices_get() returns the devices exposed by this driver.
+
+* Each qat compression device has a unique name, in format
+ <pci bdf>_<service>, e.g. "0000:41:01.0_qat_comp".
+ This name can be passed to rte_compressdev_get_dev_id() to get the device_id.
+
+
+Available kernel drivers
+------------------------
+
+Kernel drivers for each device are listed in the following table. Scroll right
+to check that the driver and device supports the servic you require.
+
.. _table_qat_pmds_drivers:
.. table:: QAT device generations, devices and drivers
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | Gen | Device | Driver | Kernel Module | Pci Driver | PF Did | #PFs | Vf Did | VFs/PF |
- +=====+==========+========+===============+============+========+======+========+========+
- | 1 | DH895xCC | 01.org | icp_qa_al | n/a | 435 | 1 | 443 | 32 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | 1 | DH895xCC | 4.4+ | qat_dh895xcc | dh895xcc | 435 | 1 | 443 | 32 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | 2 | C62x | 4.5+ | qat_c62x | c6xx | 37c8 | 3 | 37c9 | 16 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | 2 | C3xxx | 4.5+ | qat_c3xxx | c3xxx | 19e2 | 1 | 19e3 | 16 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
- | 2 | D15xx | p | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 |
- +-----+----------+--------+---------------+------------+--------+------+--------+--------+
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | Gen | Device | Driver/ver | Kernel Module | Pci Driver | PF Did | #PFs | VF Did | VFs/PF | cryptodev | compressdev |
+ +=====+==========+===============+===============+============+========+======+========+========+===========+=============+
+ | 1 | DH895xCC | linux/4.4+ | qat_dh895xcc | dh895xcc | 435 | 1 | 443 | 32 | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | 2 | C62x | linux/4.5+ | qat_c62x | c6xx | 37c8 | 3 | 37c9 | 16 | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | Yes | Yes |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | 2 | C3xxx | linux/4.5+ | qat_c3xxx | c3xxx | 19e2 | 1 | 19e3 | 16 | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | Yes | Yes |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+ | 2 | D15xx | p | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 | Yes | No |
+ +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
The ``Driver`` column indicates either the Linux kernel version in which
@@ -196,9 +282,9 @@ Consult the *Getting Started Guide* at the same URL for further information.
The steps below assume you are:
-* Building on a platform with one ``DH895xCC`` device.
-* Using package ``qatmux.l.2.3.0-34.tgz``.
-* On Fedora21 kernel ``3.17.4-301.fc21.x86_64``.
+* Building on a platform with one ``C62x`` device.
+* Using package ``qat1.7.l.4.2.0-000xx.tar.gz``.
+* On Fedora26 kernel ``4.11.11-300.fc26.x86_64``.
In the BIOS ensure that SRIOV is enabled and VT-d is disabled.
@@ -206,21 +292,30 @@ Uninstall any existing QAT driver, for example by running:
* ``./installer.sh uninstall`` in the directory where originally installed.
-* or ``rmmod qat_dh895xcc; rmmod intel_qat``.
Build and install the SRIOV-enabled QAT driver::
mkdir /QAT
cd /QAT
- # Copy qatmux.l.2.3.0-34.tgz to this location
- tar zxof qatmux.l.2.3.0-34.tgz
+ # Copy the package to this location and unpack
+ tar zxof qat1.7.l.4.2.0-000xx.tar.gz
- export ICP_WITHOUT_IOMMU=1
- ./installer.sh install QAT1.6 host
+ ./configure --enable-icp-sriov=host
+ make install
+
+You can use ``cat /sys/kernel/debug/qat<your device type and bdf>/version/fw`` to confirm the driver is correctly installed and is using firmware version 4.2.0.
+You can use ``lspci -d:37c9`` to confirm the presence of the 16 VF devices available per ``C62x`` PF.
+
+Confirm the driver is correctly installed and is using firmware version 4.2.0::
+
+ cat /sys/kernel/debug/qat<your device type and bdf>/version/fw
+
+
+Confirm the presence of 48 VF devices - 16 per PF::
+
+ lspci -d:37c9
-You can use ``cat /proc/icp_dh895xcc_dev0/version`` to confirm the driver is correctly installed.
-You can use ``lspci -d:443`` to confirm the of the 32 VF devices available per ``DH895xCC`` device.
To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_.
@@ -261,6 +356,7 @@ To complete the installation - follow instructions in `Binding the available VFs
sudo yum install zlib-devel
sudo yum install openssl-devel
+ sudo yum install libudev-devel
.. Note::
@@ -343,35 +439,6 @@ Another way to bind the VFs to the DPDK UIO driver is by using the
./usertools/dpdk-devbind.py -b igb_uio 0000:03:01.1
-Extra notes on KASUMI F9
-------------------------
-
-When using KASUMI F9 authentication algorithm, the input buffer must be
-constructed according to the 3GPP KASUMI specifications (section 4.4, page 13):
-`<http://cryptome.org/3gpp/35201-900.pdf>`_.
-Input buffer has to have COUNT (4 bytes), FRESH (4 bytes), MESSAGE and DIRECTION (1 bit)
-concatenated. After the DIRECTION bit, a single '1' bit is appended, followed by
-between 0 and 7 '0' bits, so that the total length of the buffer is multiple of 8 bits.
-Note that the actual message can be any length, specified in bits.
-
-Once this buffer is passed this way, when creating the crypto operation,
-length of data to authenticate (op.sym.auth.data.length) must be the length
-of all the items described above, including the padding at the end.
-Also, offset of data to authenticate (op.sym.auth.data.offset)
-must be such that points at the start of the COUNT bytes.
-
-Device and driver naming
-------------------------
-
-The qat crypto driver name is "crypto_qat".
-This name is passed to the dpdk-test-crypto-perf tool in the -devtype parameter.
-The rte_cryptodev_devices_get() can return the devices exposed by a driver.
-
-Each qat crypto device has a unique name, in format
-<pci bdf>_<service>, e.g. "0000:41:01.0_qat_sym".
-This name can be passed to rte_cryptodev_get_dev_id() to get the device_id.
-This is also the format of the slave parameter passed to the crypto scheduler.
-
Debugging
----------------------------------------
diff --git a/doc/guides/rel_notes/release_18_08.rst b/doc/guides/rel_notes/release_18_08.rst
index d41546c27..e5546133e 100644
--- a/doc/guides/rel_notes/release_18_08.rst
+++ b/doc/guides/rel_notes/release_18_08.rst
@@ -68,6 +68,11 @@ New Features
* Add handlers to add/delete VxLAN port number.
* Add devarg to specify ingress VLAN rewrite mode.
+* **Added a new compression PMD using Intel's QuickAssist (QAT) device family.**
+
+ Added the new ``QAT`` compression driver, for compression and decompression
+ operations in software. See the :doc:`../compressdevs/qat_comp` compression
+ driver guide for details on this new driver.
API Changes
-----------
--
2.14.4
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [dpdk-dev] [PATCH v7 00/16] compress/qat: add compression PMD
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 " Pablo de Lara
` (15 preceding siblings ...)
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 16/16] doc/qat: refactor docs adding compression guide Pablo de Lara
@ 2018-07-13 14:22 ` De Lara Guarch, Pablo
16 siblings, 0 replies; 106+ messages in thread
From: De Lara Guarch, Pablo @ 2018-07-13 14:22 UTC (permalink / raw)
To: Trahe, Fiona, Jozwiak, TomaszX, Griffin, John, Jain, Deepak K; +Cc: dev
> -----Original Message-----
> From: De Lara Guarch, Pablo
> Sent: Friday, July 13, 2018 3:28 AM
> To: Trahe, Fiona <fiona.trahe@intel.com>; Jozwiak, TomaszX
> <tomaszx.jozwiak@intel.com>; Griffin, John <john.griffin@intel.com>; Jain,
> Deepak K <deepak.k.jain@intel.com>
> Cc: dev@dpdk.org; De Lara Guarch, Pablo <pablo.de.lara.guarch@intel.com>
> Subject: [PATCH v7 00/16] compress/qat: add compression PMD
>
> Create compression PMD for Intel QuickAssist devices Currently only the C62x
> and c3xxx devices are supported.
>
> The qat comp PMD supports
> - stateless compression and
> decompression using the Deflate algorithm with Fixed Huffman
> encoding. Dynamic huffman encoding is not supported, it
> will be added in a later patch.
> - checksum generation: Adler32, CRC32 and combined.
>
> The compression service is hosted on a QuickAssist VF PCI device, which is
> managed by code in the drivers/common/qat directory.
>
Series applied to dpdk-next-crypto.
Thanks for the work!
Pablo
^ permalink raw reply [flat|nested] 106+ messages in thread
end of thread, other threads:[~2018-07-13 14:22 UTC | newest]
Thread overview: 106+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-05-23 18:40 [dpdk-dev] [PATCH] compress/qat: add compression PMD Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 00/16] " Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 " Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 " Fiona Trahe
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 " Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 " Fiona Trahe
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 " Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 01/16] common/qat: updated firmware headers Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 02/16] compress/qat: add makefiles for PMD Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 03/16] compress/qat: add meson build Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 04/16] compress/qat: add xform processing Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 05/16] compress/qat: create FW request and process response Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 06/16] compress/qat: check that correct firmware is in use Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 07/16] compress/qat: add stats functions Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 08/16] compress/qat: setup queue-pairs for compression service Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 09/16] compress/qat: add fns to configure and clear device Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 10/16] compress/qat: add fn to return device info Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 11/16] compress/qat: add enqueue/dequeue functions Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 12/16] compress/qat: add device start and stop fns Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 13/16] compress/qat: create and populate the ops structure Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 14/16] compress/qat: add fns to create and destroy the PMD Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 15/16] compress/qat: prevent device usage if incorrect firmware Pablo de Lara
2018-07-13 2:28 ` [dpdk-dev] [PATCH v7 16/16] doc/qat: refactor docs adding compression guide Pablo de Lara
2018-07-13 14:22 ` [dpdk-dev] [PATCH v7 00/16] compress/qat: add compression PMD De Lara Guarch, Pablo
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 01/16] common/qat: updated firmware headers Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 02/16] compress/qat: add makefiles for PMD Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 03/16] compress/qat: add meson build Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 04/16] compress/qat: add xform processing Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 05/16] compress/qat: create fw request and process response Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 06/16] compress/qat: check that correct firmware is in use Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 07/16] compress/qat: add stats functions Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 08/16] compress/qat: setup queue-pairs for compression service Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 09/16] compress/qat: add fns to configure and clear device Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 10/16] compress/qat: add fn to return device info Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 11/16] compress/qat: add enqueue/dequeue functions Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 12/16] compress/qat: add device start and stop fns Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 13/16] compress/qat: create and populate the ops structure Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 14/16] compress/qat: add fns to create and destroy the PMD Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 15/16] compress/qat: prevent device usage if incorrect firmware Fiona Trahe
2018-07-12 16:04 ` [dpdk-dev] [PATCH v6 16/16] docs/qat: refactor docs adding compression guide Fiona Trahe
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 01/16] common/qat: updated firmware headers Fiona Trahe
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 02/16] compress/qat: add makefiles for PMD Fiona Trahe
2018-07-12 12:41 ` De Lara Guarch, Pablo
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 03/16] compress/qat: add meson build Fiona Trahe
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 04/16] compress/qat: add xform processing Fiona Trahe
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 05/16] compress/qat: create fw request and process response Fiona Trahe
2018-07-11 11:56 ` [dpdk-dev] [PATCH v5 06/16] compress/qat: check that correct firmware is in use Fiona Trahe
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 07/16] compress/qat: add stats functions Fiona Trahe
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 08/16] compress/qat: setup queue-pairs for compression service Fiona Trahe
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 09/16] compress/qat: add fns to configure and clear device Fiona Trahe
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 10/16] compress/qat: add fn to return device info Fiona Trahe
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 11/16] compress/qat: add enqueue/dequeue functions Fiona Trahe
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 12/16] compress/qat: add device start and stop fns Fiona Trahe
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 13/16] compress/qat: create and populate the ops structure Fiona Trahe
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 14/16] compress/qat: add fns to create and destroy the PMD Fiona Trahe
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 15/16] compress/qat: prevent device usage if incorrect firmware Fiona Trahe
2018-07-11 11:57 ` [dpdk-dev] [PATCH v5 16/16] docs/qat: refactor docs adding compression guide Fiona Trahe
2018-07-12 15:56 ` De Lara Guarch, Pablo
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 01/16] common/qat: updated firmware headers Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 02/16] compress/qat: add makefiles for PMD Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 03/16] compress/qat: add meson build Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 04/16] compress/qat: add xform processing Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 05/16] compress/qat: create fw request and process response Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 06/16] compress/qat: check that correct firmware is in use Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 07/16] compress/qat: add stats functions Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 08/16] compress/qat: setup queue-pairs for compression service Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 09/16] compress/qat: add fns to configure and clear device Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 10/16] compress/qat: add fn to return device info Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 11/16] compress/qat: add enqueue/dequeue functions Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 12/16] compress/qat: add device start and stop fns Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 13/16] compress/qat: create and populate the ops structure Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 14/16] compress/qat: add fns to create and destroy the PMD Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 15/16] compress/qat: prevent device usage if incorrect firmware Fiona Trahe
2018-07-10 0:41 ` [dpdk-dev] [PATCH v4 16/16] docs/qat: refactor docs adding compression guide Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 01/16] common/qat: updated firmware headers Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 02/16] compress/qat: add makefiles for PMD Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 03/16] compress/qat: add meson build Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 04/16] compress/qat: add xform processing Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 05/16] compress/qat: create fw request and process response Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 06/16] compress/qat: check that correct firmware is in use Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 07/16] compress/qat: add stats functions Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 08/16] compress/qat: setup queue-pairs for compression service Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 09/16] compress/qat: add fns to configure and clear device Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 10/16] compress/qat: add fn to return device info Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 11/16] compress/qat: add enqueue/dequeue functions Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 12/16] compress/qat: add device start and stop fns Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 13/16] compress/qat: create and populate the ops structure Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 14/16] compress/qat: add fns to create and destroy the PMD Fiona Trahe
2018-07-05 17:32 ` [dpdk-dev] [PATCH v3 15/16] compress/qat: prevent device usage if incorrect firmware Fiona Trahe
2018-07-05 17:33 ` [dpdk-dev] [PATCH v3 16/16] docs/qat: refactor docs adding compression guide Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 01/16] common/qat: updated firmware headers Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 02/16] compress/qat: add makefiles for PMD Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 03/16] compress/qat: add meson build Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 04/16] compress/qat: add xform processing Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 05/16] compress/qat: create fw request and process response Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 06/16] compress/qat: check that correct firmware is in use Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 07/16] compress/qat: add stats functions Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 08/16] compress/qat: setup queue-pairs for compression service Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 09/16] compress/qat: add fns to configure and clear device Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 10/16] compress/qat: add fn to return device info Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 11/16] compress/qat: add enqueue/dequeue functions Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 12/16] compress/qat: add device start and stop fns Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 13/16] compress/qat: create and populate the ops structure Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 14/16] compress/qat: add fns to create and destroy the PMD Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 15/16] compress/qat: prevent device usage if incorrect firmware Fiona Trahe
2018-07-05 16:05 ` [dpdk-dev] [PATCH v2 16/16] docs/qat: refactor docs adding compression guide Fiona Trahe
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