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From: Luca Boccassi <bluca@debian.org>
To: dev@dpdk.org
Cc: maxime.coquelin@redhat.com, zhihong.wang@intel.com, tiwei.bie@intel.com,
bruce.richardson@intel.com, brian.russell@intl.att.com
Date: Fri, 24 Aug 2018 18:14:20 +0100
Message-Id: <20180824171420.31246-2-bluca@debian.org>
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References: <20180820164421.28763-1-bluca@debian.org>
<20180824171420.31246-1-bluca@debian.org>
Subject: [dpdk-dev] [PATCH v4 2/2] virtio: fix PCI config err handling
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From: Brian Russell <brussell@brocade.com>
In virtio_read_caps and vtpci_msix_detect, rte_pci_read_config returns
the number of bytes read from PCI config or < 0 on error.
If less than the expected number of bytes are read then log the
failure and return rather than carrying on with garbage.
Fixes: 6ba1f63b5ab0 ("virtio: support specification 1.0")
Signed-off-by: Brian Russell <brussell@brocade.com>
Signed-off-by: Luca Boccassi <bluca@debian.org>
---
v2: handle additional rte_pci_read_config incomplete reads
v3: do not handle rte_pci_read_config of virtio cap, added in v2,
as it's less clear what the right thing to do there is
v4: do a more robust check - first check what the vendor is, and
skip the cap entirely if it's not what we are looking for.
drivers/net/virtio/virtio_pci.c | 57 ++++++++++++++++++++++++---------
1 file changed, 42 insertions(+), 15 deletions(-)
diff --git a/drivers/net/virtio/virtio_pci.c b/drivers/net/virtio/virtio_pci.c
index 6bd22e54a6..cfefa9789b 100644
--- a/drivers/net/virtio/virtio_pci.c
+++ b/drivers/net/virtio/virtio_pci.c
@@ -567,16 +567,30 @@ virtio_read_caps(struct rte_pci_device *dev, struct virtio_hw *hw)
}
ret = rte_pci_read_config(dev, &pos, 1, PCI_CAPABILITY_LIST);
- if (ret < 0) {
- PMD_INIT_LOG(DEBUG, "failed to read pci capability list");
+ if (ret != 1) {
+ PMD_INIT_LOG(DEBUG,
+ "failed to read pci capability list, ret %d", ret);
return -1;
}
while (pos) {
+ ret = rte_pci_read_config(dev, &cap, 2, pos);
+ if (ret != 2) {
+ PMD_INIT_LOG(DEBUG,
+ "failed to read pci cap at pos: %x ret %d",
+ pos, ret);
+ break;
+ }
+ if (cap.cap_vndr != PCI_CAP_ID_MSIX &&
+ cap.cap_vndr != PCI_CAP_ID_VNDR) {
+ goto next;
+ }
+
ret = rte_pci_read_config(dev, &cap, sizeof(cap), pos);
- if (ret < 0) {
- PMD_INIT_LOG(ERR,
- "failed to read pci cap at pos: %x", pos);
+ if (ret != sizeof(cap)) {
+ PMD_INIT_LOG(DEBUG,
+ "failed to read pci cap at pos: %x ret %d",
+ pos, ret);
break;
}
@@ -689,25 +703,38 @@ enum virtio_msix_status
vtpci_msix_detect(struct rte_pci_device *dev)
{
uint8_t pos;
- struct virtio_pci_cap cap;
int ret;
ret = rte_pci_read_config(dev, &pos, 1, PCI_CAPABILITY_LIST);
- if (ret < 0) {
- PMD_INIT_LOG(DEBUG, "failed to read pci capability list");
+ if (ret != 1) {
+ PMD_INIT_LOG(DEBUG,
+ "failed to read pci capability list, ret %d", ret);
return VIRTIO_MSIX_NONE;
}
while (pos) {
- ret = rte_pci_read_config(dev, &cap, sizeof(cap), pos);
- if (ret < 0) {
- PMD_INIT_LOG(ERR,
- "failed to read pci cap at pos: %x", pos);
+ uint8_t cap[2];
+
+ ret = rte_pci_read_config(dev, cap, sizeof(cap), pos);
+ if (ret != sizeof(cap)) {
+ PMD_INIT_LOG(DEBUG,
+ "failed to read pci cap at pos: %x ret %d",
+ pos, ret);
break;
}
- if (cap.cap_vndr == PCI_CAP_ID_MSIX) {
- uint16_t flags = ((uint16_t *)&cap)[1];
+ if (cap[0] == PCI_CAP_ID_MSIX) {
+ uint16_t flags;
+
+ ret = rte_pci_read_config(dev, &flags, sizeof(flags),
+ pos + sizeof(cap));
+ if (ret != sizeof(flags)) {
+ PMD_INIT_LOG(DEBUG,
+ "failed to read pci cap at pos:"
+ " %x ret %d", pos + sizeof(cap),
+ ret);
+ break;
+ }
if (flags & PCI_MSIX_ENABLE)
return VIRTIO_MSIX_ENABLED;
@@ -715,7 +742,7 @@ vtpci_msix_detect(struct rte_pci_device *dev)
return VIRTIO_MSIX_DISABLED;
}
- pos = cap.cap_next;
+ pos = cap[1];
}
return VIRTIO_MSIX_NONE;
--
2.18.0