From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id 479564C90 for ; Mon, 10 Sep 2018 18:46:34 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Sep 2018 09:46:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,356,1531810800"; d="scan'208";a="82348944" Received: from dpdk-xiaoyun3.sh.intel.com ([10.67.119.41]) by orsmga003.jf.intel.com with ESMTP; 10 Sep 2018 09:46:17 -0700 From: Xiaoyun Li To: wenzhuo.lu@intel.com, dev@dpdk.org Cc: Xiaoyun Li Date: Tue, 11 Sep 2018 00:37:51 +0800 Message-Id: <20180910163753.85966-7-xiaoyun.li@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180910163753.85966-1-xiaoyun.li@intel.com> References: <20180910163753.85966-1-xiaoyun.li@intel.com> Subject: [dpdk-dev] [PATCH 6/8] net/ixgbe/base: add support for DCB registers dump X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 10 Sep 2018 16:46:34 -0000 Add support for DCB registers dump. Signed-off-by: Xiaoyun Li --- drivers/net/ixgbe/base/ixgbe_type.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h index ea34bb979..cee6ba2e0 100644 --- a/drivers/net/ixgbe/base/ixgbe_type.h +++ b/drivers/net/ixgbe/base/ixgbe_type.h @@ -850,6 +850,10 @@ struct ixgbe_dmac_config { #define IXGBE_RTTDQSEL 0x04904 #define IXGBE_RTTDT1C 0x04908 #define IXGBE_RTTDT1S 0x0490C +#define IXGBE_RTTQCNCR 0x08B00 +#define IXGBE_RTTQCNTG 0x04A90 +#define IXGBE_RTTBCNRD 0x0498C +#define IXGBE_RTTQCNRR 0x0498C #define IXGBE_RTTDTECC 0x04990 #define IXGBE_RTTDTECC_NO_BCN 0x00000100 @@ -860,6 +864,7 @@ struct ixgbe_dmac_config { #define IXGBE_RTTBCNRC_RF_INT_MASK \ (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT) #define IXGBE_RTTBCNRM 0x04980 +#define IXGBE_RTTQCNRM 0x04980 /* BCN (for DCB) Registers */ #define IXGBE_RTTBCNRS 0x04988 -- 2.17.1