From: Qi Zhang <qi.z.zhang@intel.com>
To: beilei.xing@intel.com
Cc: dev@dpdk.org, ferruh.yigit@intel.com, helin.zhang@intel.com,
Qi Zhang <qi.z.zhang@intel.com>
Subject: [dpdk-dev] [PATCH 12/20] net/i40e/base: change AQ command for PHY access
Date: Tue, 25 Sep 2018 10:34:34 +0800 [thread overview]
Message-ID: <20180925023442.134705-13-qi.z.zhang@intel.com> (raw)
In-Reply-To: <20180925023442.134705-1-qi.z.zhang@intel.com>
Add new field - command flags with only one flag for now. Added flag
tells FW that it shouldn't change page while accessing QSFP module,
as it was set manually.
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/i40e/base/i40e_adminq_cmd.h | 4 +++-
drivers/net/i40e/base/i40e_common.c | 18 +++++++++++++-----
drivers/net/i40e/base/i40e_prototype.h | 4 ++--
drivers/net/i40e/i40e_ethdev.c | 8 ++++----
4 files changed, 22 insertions(+), 12 deletions(-)
diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h b/drivers/net/i40e/base/i40e_adminq_cmd.h
index 343b48f25..1e6932120 100644
--- a/drivers/net/i40e/base/i40e_adminq_cmd.h
+++ b/drivers/net/i40e/base/i40e_adminq_cmd.h
@@ -2276,7 +2276,9 @@ struct i40e_aqc_phy_register_access {
#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1
#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2
u8 dev_addres;
- u8 reserved1[2];
+ u8 cmd_flags;
+#define I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE 1
+ u8 reserved1;
__le32 reg_address;
__le32 reg_value;
u8 reserved2[4];
diff --git a/drivers/net/i40e/base/i40e_common.c b/drivers/net/i40e/base/i40e_common.c
index 0eb369ff6..e0b7f4086 100644
--- a/drivers/net/i40e/base/i40e_common.c
+++ b/drivers/net/i40e/base/i40e_common.c
@@ -6796,7 +6796,7 @@ static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
status = i40e_aq_get_phy_register(hw,
I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
- I40E_PHY_COM_REG_PAGE,
+ I40E_PHY_COM_REG_PAGE, true,
I40E_PHY_LED_PROV_REG_1,
reg_val, NULL);
} else {
@@ -6824,7 +6824,7 @@ static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
status = i40e_aq_set_phy_register(hw,
I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
- I40E_PHY_COM_REG_PAGE,
+ I40E_PHY_COM_REG_PAGE, true,
I40E_PHY_LED_PROV_REG_1,
reg_val, NULL);
} else {
@@ -6858,7 +6858,7 @@ enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
status = i40e_aq_get_phy_register(hw,
I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
- I40E_PHY_COM_REG_PAGE,
+ I40E_PHY_COM_REG_PAGE, true,
I40E_PHY_LED_PROV_REG_1,
®_val_aq, NULL);
if (status == I40E_SUCCESS)
@@ -7064,6 +7064,7 @@ void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
* @hw: pointer to the hw struct
* @phy_select: select which phy should be accessed
* @dev_addr: PHY device address
+ * @page_change: enable auto page change
* @reg_addr: PHY register address
* @reg_val: new register value
* @cmd_details: pointer to command details structure or NULL
@@ -7071,7 +7072,7 @@ void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
* Write the external PHY register.
**/
enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
- u8 phy_select, u8 dev_addr,
+ u8 phy_select, u8 dev_addr, bool page_change,
u32 reg_addr, u32 reg_val,
struct i40e_asq_cmd_details *cmd_details)
{
@@ -7088,6 +7089,9 @@ enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
cmd->reg_address = CPU_TO_LE32(reg_addr);
cmd->reg_value = CPU_TO_LE32(reg_val);
+ if (!page_change)
+ cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
+
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
return status;
@@ -7098,6 +7102,7 @@ enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
* @hw: pointer to the hw struct
* @phy_select: select which phy should be accessed
* @dev_addr: PHY device address
+ * @page_change: enable auto page change
* @reg_addr: PHY register address
* @reg_val: read register value
* @cmd_details: pointer to command details structure or NULL
@@ -7105,7 +7110,7 @@ enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
* Read the external PHY register.
**/
enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
- u8 phy_select, u8 dev_addr,
+ u8 phy_select, u8 dev_addr, bool page_change,
u32 reg_addr, u32 *reg_val,
struct i40e_asq_cmd_details *cmd_details)
{
@@ -7121,6 +7126,9 @@ enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
cmd->dev_addres = dev_addr;
cmd->reg_address = CPU_TO_LE32(reg_addr);
+ if (!page_change)
+ cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
+
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
if (!status)
*reg_val = LE32_TO_CPU(cmd->reg_value);
diff --git a/drivers/net/i40e/base/i40e_prototype.h b/drivers/net/i40e/base/i40e_prototype.h
index 9dd07de2b..f325924ee 100644
--- a/drivers/net/i40e/base/i40e_prototype.h
+++ b/drivers/net/i40e/base/i40e_prototype.h
@@ -545,11 +545,11 @@ enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
struct i40e_asq_cmd_details *cmd_details);
void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);
enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
- u8 phy_select, u8 dev_addr,
+ u8 phy_select, u8 dev_addr, bool page_change,
u32 reg_addr, u32 reg_val,
struct i40e_asq_cmd_details *cmd_details);
enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
- u8 phy_select, u8 dev_addr,
+ u8 phy_select, u8 dev_addr, bool page_change,
u32 reg_addr, u32 *reg_val,
struct i40e_asq_cmd_details *cmd_details);
diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 8a78a6a4b..8c0fd0091 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -11717,7 +11717,7 @@ static int i40e_get_module_info(struct rte_eth_dev *dev,
case I40E_MODULE_TYPE_SFP:
status = i40e_aq_get_phy_register(hw,
I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
- I40E_I2C_EEPROM_DEV_ADDR,
+ I40E_I2C_EEPROM_DEV_ADDR, 1,
I40E_MODULE_SFF_8472_COMP,
&sff8472_comp, NULL);
if (status)
@@ -11725,7 +11725,7 @@ static int i40e_get_module_info(struct rte_eth_dev *dev,
status = i40e_aq_get_phy_register(hw,
I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
- I40E_I2C_EEPROM_DEV_ADDR,
+ I40E_I2C_EEPROM_DEV_ADDR, 1,
I40E_MODULE_SFF_8472_SWAP,
&sff8472_swap, NULL);
if (status)
@@ -11753,7 +11753,7 @@ static int i40e_get_module_info(struct rte_eth_dev *dev,
/* Read from memory page 0. */
status = i40e_aq_get_phy_register(hw,
I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
- 0,
+ 0, 1,
I40E_MODULE_REVISION_ADDR,
&sff8636_rev, NULL);
if (status)
@@ -11814,7 +11814,7 @@ static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
}
status = i40e_aq_get_phy_register(hw,
I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
- addr, offset, &value, NULL);
+ addr, offset, 1, &value, NULL);
if (status)
return -EIO;
data[i] = (uint8_t)value;
--
2.13.6
next prev parent reply other threads:[~2018-09-25 2:34 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-25 2:34 [dpdk-dev] [PATCH 00/20] base code update Qi Zhang
2018-09-25 2:34 ` [dpdk-dev] [PATCH 01/20] net/i40e/base: replace license text with SPDX tag Qi Zhang
2018-09-25 2:34 ` [dpdk-dev] [PATCH 02/20] net/i40e/base: fix partition id calculation for X722 Qi Zhang
2018-09-25 2:34 ` [dpdk-dev] [PATCH 03/20] net/i40e/base: introduce PHY type bitmask Qi Zhang
2018-09-25 2:34 ` [dpdk-dev] [PATCH 04/20] net/i40e/base: enable cloud filter mode for switch config Qi Zhang
2018-09-25 2:34 ` [dpdk-dev] [PATCH 05/20] net/i40e/base: add admin queue definitions for cloud filters Qi Zhang
2018-09-25 2:34 ` [dpdk-dev] [PATCH 06/20] net/i40e/base: enable cloud filters via tc flower Qi Zhang
2018-09-25 2:34 ` [dpdk-dev] [PATCH 07/20] net/i40e/base: improve the polling mechanism Qi Zhang
2018-09-25 2:34 ` [dpdk-dev] [PATCH 08/20] net/i40e/base: read LLDP config area with correct endianness Qi Zhang
2018-09-25 2:34 ` [dpdk-dev] [PATCH 09/20] net/i40e/base: properly clean resources Qi Zhang
2018-09-25 2:34 ` [dpdk-dev] [PATCH 10/20] net/i40e/base: gracefully clean the resources Qi Zhang
2018-09-25 2:34 ` [dpdk-dev] [PATCH 11/20] net/i40e/base: correct global reset timeout calculation Qi Zhang
2018-09-25 2:34 ` Qi Zhang [this message]
2018-09-25 2:34 ` [dpdk-dev] [PATCH 13/20] net/i40e/base: add additional return code Qi Zhang
2018-09-25 2:34 ` [dpdk-dev] [PATCH 14/20] net/i40e/base: add AQ command for rearrange NVM structure Qi Zhang
2018-09-25 2:34 ` [dpdk-dev] [PATCH 15/20] net/i40e/base: add FC threshold parameter for set MAC Qi Zhang
2018-09-25 2:34 ` [dpdk-dev] [PATCH 16/20] net/i40e/base: add support for carlsville device Qi Zhang
2018-09-25 2:34 ` [dpdk-dev] [PATCH 17/20] net/i40e/base: wrap admin queue set/get PHY register funcs Qi Zhang
2018-09-25 2:34 ` [dpdk-dev] [PATCH 18/20] net/i40e/base: add capability flag for stopping FW LLDP Qi Zhang
2018-09-25 2:34 ` [dpdk-dev] [PATCH 19/20] net/i40e/base: add new TR bits used for cloud filters Qi Zhang
2018-09-25 2:34 ` [dpdk-dev] [PATCH 20/20] net/i40e/base: update readme Qi Zhang
2018-09-27 7:39 ` [dpdk-dev] [PATCH 00/20] base code update Xing, Beilei
2018-09-29 2:13 ` Zhang, Qi Z
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