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From: Gagandeep Singh <G.Singh@nxp.com>
To: "dev@dpdk.org" <dev@dpdk.org>, Akhil Goyal <akhil.goyal@nxp.com>
CC: Gagandeep Singh <G.Singh@nxp.com>, Hemant Agrawal <hemant.agrawal@nxp.com>
Thread-Topic: [PATCH v5 09/15] crypto/caam_jr: add device cababilities
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Date: Mon, 22 Oct 2018 14:57:41 +0000
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Subject: [dpdk-dev] [PATCH v5 09/15] crypto/caam_jr: add device cababilities
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add device capabilities for supported algorithms,
key length etc.
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
---
drivers/crypto/caam_jr/Makefile | 1 +
drivers/crypto/caam_jr/caam_jr.c | 2 +
drivers/crypto/caam_jr/caam_jr_capabilities.c | 232 ++++++++++++++++++
drivers/crypto/caam_jr/caam_jr_capabilities.h | 13 +
drivers/crypto/caam_jr/meson.build | 5 +-
5 files changed, 252 insertions(+), 1 deletion(-)
create mode 100644 drivers/crypto/caam_jr/caam_jr_capabilities.c
create mode 100644 drivers/crypto/caam_jr/caam_jr_capabilities.h
diff --git a/drivers/crypto/caam_jr/Makefile b/drivers/crypto/caam_jr/Makef=
ile
index cfd093a5f..88cdf7410 100644
--- a/drivers/crypto/caam_jr/Makefile
+++ b/drivers/crypto/caam_jr/Makefile
@@ -31,6 +31,7 @@ LIBABIVER :=3D 1
=20
# library source files
SRCS-$(CONFIG_RTE_LIBRTE_PMD_CAAM_JR) +=3D caam_jr.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_CAAM_JR) +=3D caam_jr_capabilities.c
SRCS-$(CONFIG_RTE_LIBRTE_PMD_CAAM_JR) +=3D caam_jr_hw.c
SRCS-$(CONFIG_RTE_LIBRTE_PMD_CAAM_JR) +=3D caam_jr_uio.c
# library dependencies
diff --git a/drivers/crypto/caam_jr/caam_jr.c b/drivers/crypto/caam_jr/caam=
_jr.c
index aec033649..96b18be12 100644
--- a/drivers/crypto/caam_jr/caam_jr.c
+++ b/drivers/crypto/caam_jr/caam_jr.c
@@ -16,6 +16,7 @@
#include <rte_malloc.h>
#include <rte_hexdump.h>
=20
+#include <caam_jr_capabilities.h>
#include <caam_jr_config.h>
#include <caam_jr_hw_specific.h>
#include <caam_jr_pvt.h>
@@ -438,6 +439,7 @@ caam_jr_dev_infos_get(struct rte_cryptodev *dev,
if (info !=3D NULL) {
info->max_nb_queue_pairs =3D internals->max_nb_queue_pairs;
info->feature_flags =3D dev->feature_flags;
+ info->capabilities =3D caam_jr_get_cryptodev_capabilities();
info->sym.max_nb_sessions =3D internals->max_nb_sessions;
info->driver_id =3D cryptodev_driver_id;
}
diff --git a/drivers/crypto/caam_jr/caam_jr_capabilities.c b/drivers/crypto=
/caam_jr/caam_jr_capabilities.c
new file mode 100644
index 000000000..92aa429cc
--- /dev/null
+++ b/drivers/crypto/caam_jr/caam_jr_capabilities.c
@@ -0,0 +1,232 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2017-2018 NXP
+ */
+
+#include <caam_jr_capabilities.h>
+
+static const struct rte_cryptodev_capabilities caam_jr_capabilities[] =3D =
{
+ { /* MD5 HMAC */
+ .op =3D RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym =3D {
+ .xform_type =3D RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth =3D {
+ .algo =3D RTE_CRYPTO_AUTH_MD5_HMAC,
+ .block_size =3D 64,
+ .key_size =3D {
+ .min =3D 1,
+ .max =3D 64,
+ .increment =3D 1
+ },
+ .digest_size =3D {
+ .min =3D 1,
+ .max =3D 16,
+ .increment =3D 1
+ },
+ .iv_size =3D { 0 }
+ }, }
+ }, }
+ },
+ { /* SHA1 HMAC */
+ .op =3D RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym =3D {
+ .xform_type =3D RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth =3D {
+ .algo =3D RTE_CRYPTO_AUTH_SHA1_HMAC,
+ .block_size =3D 64,
+ .key_size =3D {
+ .min =3D 1,
+ .max =3D 64,
+ .increment =3D 1
+ },
+ .digest_size =3D {
+ .min =3D 1,
+ .max =3D 20,
+ .increment =3D 1
+ },
+ .iv_size =3D { 0 }
+ }, }
+ }, }
+ },
+ { /* SHA224 HMAC */
+ .op =3D RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym =3D {
+ .xform_type =3D RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth =3D {
+ .algo =3D RTE_CRYPTO_AUTH_SHA224_HMAC,
+ .block_size =3D 64,
+ .key_size =3D {
+ .min =3D 1,
+ .max =3D 64,
+ .increment =3D 1
+ },
+ .digest_size =3D {
+ .min =3D 1,
+ .max =3D 28,
+ .increment =3D 1
+ },
+ .iv_size =3D { 0 }
+ }, }
+ }, }
+ },
+ { /* SHA256 HMAC */
+ .op =3D RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym =3D {
+ .xform_type =3D RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth =3D {
+ .algo =3D RTE_CRYPTO_AUTH_SHA256_HMAC,
+ .block_size =3D 64,
+ .key_size =3D {
+ .min =3D 1,
+ .max =3D 64,
+ .increment =3D 1
+ },
+ .digest_size =3D {
+ .min =3D 1,
+ .max =3D 32,
+ .increment =3D 1
+ },
+ .iv_size =3D { 0 }
+ }, }
+ }, }
+ },
+ { /* SHA384 HMAC */
+ .op =3D RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym =3D {
+ .xform_type =3D RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth =3D {
+ .algo =3D RTE_CRYPTO_AUTH_SHA384_HMAC,
+ .block_size =3D 128,
+ .key_size =3D {
+ .min =3D 1,
+ .max =3D 128,
+ .increment =3D 1
+ },
+ .digest_size =3D {
+ .min =3D 1,
+ .max =3D 48,
+ .increment =3D 1
+ },
+ .iv_size =3D { 0 }
+ }, }
+ }, }
+ },
+ { /* SHA512 HMAC */
+ .op =3D RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym =3D {
+ .xform_type =3D RTE_CRYPTO_SYM_XFORM_AUTH,
+ {.auth =3D {
+ .algo =3D RTE_CRYPTO_AUTH_SHA512_HMAC,
+ .block_size =3D 128,
+ .key_size =3D {
+ .min =3D 1,
+ .max =3D 128,
+ .increment =3D 1
+ },
+ .digest_size =3D {
+ .min =3D 1,
+ .max =3D 64,
+ .increment =3D 1
+ },
+ .iv_size =3D { 0 }
+ }, }
+ }, }
+ },
+ { /* AES GCM */
+ .op =3D RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym =3D {
+ .xform_type =3D RTE_CRYPTO_SYM_XFORM_AEAD,
+ {.aead =3D {
+ .algo =3D RTE_CRYPTO_AEAD_AES_GCM,
+ .block_size =3D 16,
+ .key_size =3D {
+ .min =3D 16,
+ .max =3D 32,
+ .increment =3D 8
+ },
+ .digest_size =3D {
+ .min =3D 8,
+ .max =3D 16,
+ .increment =3D 4
+ },
+ .aad_size =3D {
+ .min =3D 0,
+ .max =3D 240,
+ .increment =3D 1
+ },
+ .iv_size =3D {
+ .min =3D 12,
+ .max =3D 12,
+ .increment =3D 0
+ },
+ }, }
+ }, }
+ },
+ { /* AES CBC */
+ .op =3D RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym =3D {
+ .xform_type =3D RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher =3D {
+ .algo =3D RTE_CRYPTO_CIPHER_AES_CBC,
+ .block_size =3D 16,
+ .key_size =3D {
+ .min =3D 16,
+ .max =3D 32,
+ .increment =3D 8
+ },
+ .iv_size =3D {
+ .min =3D 16,
+ .max =3D 16,
+ .increment =3D 0
+ }
+ }, }
+ }, }
+ },
+ { /* AES CTR */
+ .op =3D RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym =3D {
+ .xform_type =3D RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher =3D {
+ .algo =3D RTE_CRYPTO_CIPHER_AES_CTR,
+ .block_size =3D 16,
+ .key_size =3D {
+ .min =3D 16,
+ .max =3D 32,
+ .increment =3D 8
+ },
+ .iv_size =3D {
+ .min =3D 16,
+ .max =3D 16,
+ .increment =3D 0
+ }
+ }, }
+ }, }
+ },
+ { /* 3DES CBC */
+ .op =3D RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym =3D {
+ .xform_type =3D RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher =3D {
+ .algo =3D RTE_CRYPTO_CIPHER_3DES_CBC,
+ .block_size =3D 8,
+ .key_size =3D {
+ .min =3D 16,
+ .max =3D 24,
+ .increment =3D 8
+ },
+ .iv_size =3D {
+ .min =3D 8,
+ .max =3D 8,
+ .increment =3D 0
+ }
+ }, }
+ }, }
+ },
+
+ RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
+};
+
+const struct rte_cryptodev_capabilities *
+caam_jr_get_cryptodev_capabilities(void)
+{
+ return caam_jr_capabilities;
+}
diff --git a/drivers/crypto/caam_jr/caam_jr_capabilities.h b/drivers/crypto=
/caam_jr/caam_jr_capabilities.h
new file mode 100644
index 000000000..7a94013e5
--- /dev/null
+++ b/drivers/crypto/caam_jr/caam_jr_capabilities.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2017-2018 NXP
+ */
+
+#ifndef CAAM_JR_CAPABILITIES_H
+#define CAAM_JR_CAPABILITIES_H
+
+#include <rte_cryptodev.h>
+
+/* Get cryptodev capabilities */
+const struct rte_cryptodev_capabilities *
+caam_jr_get_cryptodev_capabilities(void);
+#endif
diff --git a/drivers/crypto/caam_jr/meson.build b/drivers/crypto/caam_jr/me=
son.build
index 7b024e886..99b71aef1 100644
--- a/drivers/crypto/caam_jr/meson.build
+++ b/drivers/crypto/caam_jr/meson.build
@@ -6,7 +6,10 @@ if host_machine.system() !=3D 'linux'
endif
=20
deps +=3D ['bus_vdev', 'bus_dpaa', 'security']
-sources =3D files('caam_jr_hw.c', 'caam_jr_uio.c', 'caam_jr.c')
+sources =3D files('caam_jr_capabilities.c',
+ 'caam_jr_hw.c',
+ 'caam_jr_uio.c',
+ 'caam_jr.c')
=20
allow_experimental_apis =3D true
=20
--=20
2.17.1