From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id 7DEA42B8C; Sun, 28 Oct 2018 03:51:51 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Oct 2018 19:51:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,434,1534834800"; d="scan'208";a="81458960" Received: from silpixa00399752.ir.intel.com (HELO silpixa00399752.ger.corp.intel.com) ([10.237.222.212]) by fmsmga007.fm.intel.com with ESMTP; 27 Oct 2018 19:51:48 -0700 From: Ferruh Yigit To: Jingjing Wu , Wenzhuo Lu Cc: dev@dpdk.org, Ferruh Yigit , stable@dpdk.org Date: Sun, 28 Oct 2018 03:51:33 +0000 Message-Id: <20181028035133.67106-1-ferruh.yigit@intel.com> X-Mailer: git-send-email 2.17.2 Subject: [dpdk-dev] [PATCH] net/avf/base: fix shifting 32 bits signed variable 31 times X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 28 Oct 2018 02:51:52 -0000 Fixes: e5b2a9e957e7 ("net/avf/base: add base code for avf PMD") Cc: stable@dpdk.org Signed-off-by: Ferruh Yigit --- drivers/net/avf/base/avf_register.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/avf/base/avf_register.h b/drivers/net/avf/base/avf_register.h index ba5a9f3fa..adb989583 100644 --- a/drivers/net/avf/base/avf_register.h +++ b/drivers/net/avf/base/avf_register.h @@ -76,7 +76,7 @@ POSSIBILITY OF SUCH DAMAGE. #define AVF_ARQLEN1_ARQCRIT_SHIFT 30 #define AVF_ARQLEN1_ARQCRIT_MASK AVF_MASK(0x1, AVF_ARQLEN1_ARQCRIT_SHIFT) #define AVF_ARQLEN1_ARQENABLE_SHIFT 31 -#define AVF_ARQLEN1_ARQENABLE_MASK AVF_MASK(0x1, AVF_ARQLEN1_ARQENABLE_SHIFT) +#define AVF_ARQLEN1_ARQENABLE_MASK AVF_MASK(0x1U, AVF_ARQLEN1_ARQENABLE_SHIFT) #define AVF_ARQT1 0x00007000 /* Reset: EMPR */ #define AVF_ARQT1_ARQT_SHIFT 0 #define AVF_ARQT1_ARQT_MASK AVF_MASK(0x3FF, AVF_ARQT1_ARQT_SHIFT) @@ -99,7 +99,7 @@ POSSIBILITY OF SUCH DAMAGE. #define AVF_ATQLEN1_ATQCRIT_SHIFT 30 #define AVF_ATQLEN1_ATQCRIT_MASK AVF_MASK(0x1, AVF_ATQLEN1_ATQCRIT_SHIFT) #define AVF_ATQLEN1_ATQENABLE_SHIFT 31 -#define AVF_ATQLEN1_ATQENABLE_MASK AVF_MASK(0x1, AVF_ATQLEN1_ATQENABLE_SHIFT) +#define AVF_ATQLEN1_ATQENABLE_MASK AVF_MASK(0x1U, AVF_ATQLEN1_ATQENABLE_SHIFT) #define AVF_ATQT1 0x00008400 /* Reset: EMPR */ #define AVF_ATQT1_ATQT_SHIFT 0 #define AVF_ATQT1_ATQT_MASK AVF_MASK(0x3FF, AVF_ATQT1_ATQT_SHIFT) -- 2.17.2