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Date: Fri, 2 Nov 2018 11:43:44 +0000
From: Bruce Richardson <bruce.richardson@intel.com>
To: Gavin Hu <gavin.hu@arm.com>
Cc: dev@dpdk.org, thomas@monjalon.net, stephen@networkplumber.org,
olivier.matz@6wind.com, chaozhu@linux.vnet.ibm.com,
konstantin.ananyev@intel.com, jerin.jacob@caviumnetworks.com,
Honnappa.Nagarahalli@arm.com, stable@dpdk.org
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Organization: Intel Research and Development Ireland Ltd.
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Subject: Re: [dpdk-dev] [PATCH v5 2/2] ring: move the atomic load of head
above the loop
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On Fri, Nov 02, 2018 at 07:21:28PM +0800, Gavin Hu wrote:
> In __rte_ring_move_prod_head, move the __atomic_load_n up and out of
> the do {} while loop as upon failure the old_head will be updated,
> another load is costly and not necessary.
>
> This helps a little on the latency,about 1~5%.
>
> Test result with the patch(two cores):
> SP/SC bulk enq/dequeue (size: 8): 5.64
> MP/MC bulk enq/dequeue (size: 8): 9.58
> SP/SC bulk enq/dequeue (size: 32): 1.98
> MP/MC bulk enq/dequeue (size: 32): 2.30
>
> Fixes: 39368ebfc606 ("ring: introduce C11 memory model barrier option")
> Cc: stable@dpdk.org
>
> Signed-off-by: Gavin Hu <gavin.hu@arm.com>
> Reviewed-by: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
> Reviewed-by: Steve Capper <steve.capper@arm.com>
> Reviewed-by: Ola Liljedahl <Ola.Liljedahl@arm.com>
> Reviewed-by: Jia He <justin.he@arm.com>
> Acked-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
> Tested-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
> ---
> doc/guides/rel_notes/release_18_11.rst | 7 +++++++
> lib/librte_ring/rte_ring_c11_mem.h | 10 ++++------
> 2 files changed, 11 insertions(+), 6 deletions(-)
>
> diff --git a/doc/guides/rel_notes/release_18_11.rst b/doc/guides/rel_notes/release_18_11.rst
> index 376128f..b68afab 100644
> --- a/doc/guides/rel_notes/release_18_11.rst
> +++ b/doc/guides/rel_notes/release_18_11.rst
> @@ -69,6 +69,13 @@ New Features
> checked out against that dma mask and rejected if out of range. If more than
> one device has addressing limitations, the dma mask is the more restricted one.
>
> +* **Updated the ring library with C11 memory model.**
> +
> + Updated the ring library with C11 memory model, in our tests the changes
> + decreased latency by 27~29% and 3~15% for MPMC and SPSC cases respectively.
> + The real improvements may vary with the number of contending lcores and the
> + size of ring.
> +
Is this a little misleading, and will users expect massive performance
improvements generally? The C11 model seems to be used only on some, but
not all, arm platforms, and then only with "make" builds.
config/arm/meson.build: ['RTE_USE_C11_MEM_MODEL', false]]
config/common_armv8a_linuxapp:CONFIG_RTE_USE_C11_MEM_MODEL=y
config/common_base:CONFIG_RTE_USE_C11_MEM_MODEL=n
config/defconfig_arm64-thunderx-linuxapp-gcc:CONFIG_RTE_USE_C11_MEM_MODEL=n
/Bruce