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Wed, 7 Nov 2018 18:30:40 +0000 From: "Player, Timmons" To: Wenzhuo Lu CC: "dev@dpdk.org" , "Player, Timmons" Thread-Topic: [PATCH] net/igb: fix LSC interrupt when using MSI-X Thread-Index: AQHUdsf7tZNGRyuh0k2uNoLXtooBHg== Date: Wed, 7 Nov 2018 18:30:39 +0000 Message-ID: <20181107183004.21778-1-timmons.player@spirent.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [2605:a601:a204:3390:e9d:92ff:fe82:3675] x-clientproxiedby: BN6PR1401CA0004.namprd14.prod.outlook.com (2603:10b6:405:4b::14) To BN7PR10MB2739.namprd10.prod.outlook.com (2603:10b6:406:c6::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Timmons.Player@spirent.com; x-ms-exchange-messagesentrepresentingtype: 1 x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BN7PR10MB2417; 6:gy2kvyBEWPdqmhok82xqdY0s4PQWmE1mmwA5G45fyD4rKA2j9lu1YkGKWDBU9Ki3Lp+CFqw1esqgAMlpWaLNfEYGlo1CET9jilx8vtLfaH4kxb0nm+jlZZDlsOBFwhP0NgoWKUnAQ57+MhmWu/PxYFNgM1RgozVZDdKb3NKTcPEJ7hiFLuHwVm0T5RfNlTwL3fv8XgpwFEfSXmCwqJtXSQJ49wd95ITJv2+8dGLvDAPOkB3PCamGMjo/BBniA1kQhE6Mb54Czkx1kzt/9HrV2+25X+4RBczHcSIEPYKI0vtsPs1ekM12KpL7Dcxdz+0+cu8FExC1UPxEm+PE6FeeMmYoSjTm4oWHzq2UFSHFlTy6c3S7PLiFyV7GKgXeJWTDYCuGNqgRVM7gUMMb6FuHMc14kNqB8juFOECzP5lzioE0OTP6ng0HlnbU44wfP742f7gC0+w0Ib5+csqIxwXXpA==; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: spirent.com X-MS-Exchange-CrossTenant-Network-Message-Id: 295f57d7-e854-4b10-31a6-08d644df1e23 X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Nov 2018 18:30:40.0907 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: eb68cad0-6bd5-483f-a802-0f72f974373f X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR10MB2417 Subject: [dpdk-dev] [PATCH] net/igb: fix LSC interrupt when using MSI-X X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 07 Nov 2018 18:30:43 -0000 Take the 'other interrupt' into account when setting up MSI-X interrupts and use the proper mask when enabling it. Also rearm the MSI-X vector after the LSC interrupt fires. This change allows both LSC and RXQ interrupts to work at the same time. Signed-off-by: Timmons C. Player --- drivers/net/e1000/igb_ethdev.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.= c index d9d29d22f..62c63a623 100644 --- a/drivers/net/e1000/igb_ethdev.c +++ b/drivers/net/e1000/igb_ethdev.c @@ -68,6 +68,9 @@ #define E1000_VET_VET_EXT 0xFFFF0000 #define E1000_VET_VET_EXT_SHIFT 16 =20 +/* MSI-X other interrupt vector */ +#define IGB_MSIX_OTHER_INTR_VEC 0 + static int eth_igb_configure(struct rte_eth_dev *dev); static int eth_igb_start(struct rte_eth_dev *dev); static void eth_igb_stop(struct rte_eth_dev *dev); @@ -540,6 +543,7 @@ igb_intr_enable(struct rte_eth_dev *dev) E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); =20 E1000_WRITE_REG(hw, E1000_IMS, intr->mask); + E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC); E1000_WRITE_FLUSH(hw); } =20 @@ -2768,12 +2772,15 @@ static int eth_igb_rxq_interrupt_setup(struct rte_e= th_dev *dev) uint32_t mask, regval; struct e1000_hw *hw =3D E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct rte_pci_device *pci_dev =3D RTE_ETH_DEV_TO_PCI(dev); + struct rte_intr_handle *intr_handle =3D &pci_dev->intr_handle; + int misc_shift =3D rte_intr_allow_others(intr_handle) ? 1 : 0; struct rte_eth_dev_info dev_info; =20 memset(&dev_info, 0, sizeof(dev_info)); eth_igb_infos_get(dev, &dev_info); =20 - mask =3D 0xFFFFFFFF >> (32 - dev_info.max_rx_queues); + mask =3D (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift; regval =3D E1000_READ_REG(hw, E1000_EIMS); E1000_WRITE_REG(hw, E1000_EIMS, regval | mask); =20 @@ -5583,13 +5590,17 @@ eth_igb_configure_msix_intr(struct rte_eth_dev *dev= ) E1000_GPIE_NSICR); intr_mask =3D RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) << misc_shift; + + if (dev->data->dev_conf.intr_conf.lsc !=3D 0) + intr_mask |=3D (1 << IGB_MSIX_OTHER_INTR_VEC); + regval =3D E1000_READ_REG(hw, E1000_EIAC); E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask); =20 /* enable msix_other interrupt */ regval =3D E1000_READ_REG(hw, E1000_EIMS); E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask); - tmpval =3D (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8; + tmpval =3D (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8; E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval); } =20 @@ -5598,6 +5609,10 @@ eth_igb_configure_msix_intr(struct rte_eth_dev *dev) */ intr_mask =3D RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) << misc_shift; + + if (dev->data->dev_conf.intr_conf.lsc !=3D 0) + intr_mask |=3D (1 << IGB_MSIX_OTHER_INTR_VEC); + regval =3D E1000_READ_REG(hw, E1000_EIAM); E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask); =20 --=20 2.17.1