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DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR18MB2679; H:BYAPR18MB2424.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: JV0CTOPwlkEJXV7L0db7mSqAWcftzkNoD8PNbHDg/xyJPBfB6K8+jpievNPTtncjGT/h3poUjP73EiqUfjlb+ck3kexwQsqw+JF8jjnjtbntx0RmfWamXYesccznj/Utm6U3o+3ax22rpd8kjgcwai/l5/dEfzMG+u8rXNBFS3xx0cl4ng4vlCMAZ3WSt9TGIFV230l2c1vvpDYu+YbFhODTC90I3n0CTZYooaog+3Xx+l/1s9m+Qg3qPh+JZSnPdkaOSJI/k3UtlUF6+ByJBeBWbk1TPY8cGS3eM3lQ9Ngt2QMPwyMt5DoqqJB5WknbYSRTFRujKSq51DW1SU0YQWLTH1SroBa/KAVzQ6ex3a6BlMuui29WAAJv1FfhogD6e2oRPJ95gUBs/b9WRKgyeKWfuRMvWo63DhF7B1jZe+4= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: c58e55e7-32b0-436f-8e07-08d69a837f77 X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Feb 2019 18:11:24.2044 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR18MB2679 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-02-24_10:, , signatures=0 X-Proofpoint-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1902240143 Subject: [dpdk-dev] [PATCH v5 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 24 Feb 2019 18:11:36 -0000 From: Pavan Nikhilesh Currently, RTE_* flags are set based on the implementer ID but there might be some micro arch specific differences from the same vendor eg. CACHE_LINESIZE. Add support to set micro arch specific flags. Signed-off-by: Pavan Nikhilesh Signed-off-by: Jerin Jacob --- config/arm/meson.build | 54 +++++++++++++++++++++++++----------------- 1 file changed, 32 insertions(+), 22 deletions(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index dae55d6b2..7eb6f5c99 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -7,23 +7,6 @@ march_opt =3D '-march=3D@0@'.format(machine) =20 arm_force_native_march =3D false =20 -machine_args_generic =3D [ - ['default', ['-march=3Darmv8-a+crc+crypto']], - ['native', ['-march=3Dnative']], - ['0xd03', ['-mcpu=3Dcortex-a53']], - ['0xd04', ['-mcpu=3Dcortex-a35']], - ['0xd07', ['-mcpu=3Dcortex-a57']], - ['0xd08', ['-mcpu=3Dcortex-a72']], - ['0xd09', ['-mcpu=3Dcortex-a73']], - ['0xd0a', ['-mcpu=3Dcortex-a75']], -] -machine_args_cavium =3D [ - ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], - ['native', ['-march=3Dnative']], - ['0xa1', ['-mcpu=3Dthunderxt88']], - ['0xa2', ['-mcpu=3Dthunderxt81']], - ['0xa3', ['-mcpu=3Dthunderxt83']]] - flags_common_default =3D [ # Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest) # to determine the best threshold in code. Refer to notes in source file @@ -50,12 +33,10 @@ flags_generic =3D [ ['RTE_USE_C11_MEM_MODEL', true], ['RTE_CACHE_LINE_SIZE', 128]] flags_cavium =3D [ - ['RTE_MACHINE', '"thunderx"'], ['RTE_CACHE_LINE_SIZE', 128], ['RTE_MAX_NUMA_NODES', 2], ['RTE_MAX_LCORE', 96], - ['RTE_MAX_VFIO_GROUPS', 128], - ['RTE_USE_C11_MEM_MODEL', false]] + ['RTE_MAX_VFIO_GROUPS', 128]] flags_dpaa =3D [ ['RTE_MACHINE', '"dpaa"'], ['RTE_USE_C11_MEM_MODEL', true], @@ -69,6 +50,27 @@ flags_dpaa2 =3D [ ['RTE_MAX_NUMA_NODES', 1], ['RTE_MAX_LCORE', 16], ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] +flags_default_extra =3D [] +flags_thunderx_extra =3D [ + ['RTE_MACHINE', '"thunderx"'], + ['RTE_USE_C11_MEM_MODEL', false]] + +machine_args_generic =3D [ + ['default', ['-march=3Darmv8-a+crc+crypto']], + ['native', ['-march=3Dnative']], + ['0xd03', ['-mcpu=3Dcortex-a53']], + ['0xd04', ['-mcpu=3Dcortex-a35']], + ['0xd07', ['-mcpu=3Dcortex-a57']], + ['0xd08', ['-mcpu=3Dcortex-a72']], + ['0xd09', ['-mcpu=3Dcortex-a73']], + ['0xd0a', ['-mcpu=3Dcortex-a75']]] + +machine_args_cavium =3D [ + ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], + ['native', ['-march=3Dnative']], + ['0xa1', ['-mcpu=3Dthunderxt88'], flags_thunderx_extra], + ['0xa2', ['-mcpu=3Dthunderxt81'], flags_thunderx_extra], + ['0xa3', ['-mcpu=3Dthunderxt83'], flags_thunderx_extra]] =20 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) impl_generic =3D ['Generic armv8', flags_generic, machine_args_generic] @@ -156,8 +158,16 @@ else endif foreach marg: machine[2] if marg[0] =3D=3D impl_pn - foreach f: marg[1] - machine_args +=3D f + foreach flag: marg[1] + if cc.has_argument(flag) + machine_args +=3D flag + endif + endforeach + # Apply any extra machine specific flags. + foreach flag: marg.get(2, flags_default_extra) + if flag.length() > 0 + dpdk_conf.set(flag[0], flag[1]) + endif endforeach endif endforeach --=20 2.20.1