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LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: C3AAdEIwOX5ZZQiqTzrw/bj8vriK9FGcmW7YoNysgocgMDGE1w+XbE/JL/VoN5FSRHTLxEoKV8KhG4Yf/RZBdZ2yEIRObXD6mX78/9Yqg9auzjG5Ke+V86Fn9AeWk7ORItfAMp7ZvC+f0ROjuqpJ9inLkmiO/Peqz12jUMG8hJOmpvszbc0GLgz6KZE/8rdfYa/6/uHsA1rHu7gr8rGReQ6Izw2jf3L3IgJEc8d3Y35laD0Vt8iEaHZFFtLlAWsKEb7nhDpF6L8IzXpbY4VGkUfg4vlVjfiujdfod/2jloM358HiAjRwYFdz08M1ubXRtpKJQKDPrf5LiD8c1UnJUqAL/q/tVVzC6sEH6oHps4VLLTio5Q1R4qYydYCH00kkmv314X6edfsOZE4TvbLWZfF6I5RPHHGsGMBOTgStFsw= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: f956aff6-1673-4cf3-1ee6-08d6ae072e4e X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Mar 2019 14:11:58.2528 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR05MB3364 Subject: Re: [dpdk-dev] [PATCH 14/14] net/mlx5: add source vport match to the ingress rules X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190321141158.SX6W5onNNqroLaItfEPhqPyKSHLfmW9uY2WwFNgXHbw@z> > -----Original Message----- > From: Shahaf Shuler > Sent: Thursday, March 21, 2019 14:15 > To: Slava Ovsiienko ; dev@dpdk.org > Subject: RE: [PATCH 14/14] net/mlx5: add source vport match to the ingres= s > rules >=20 > Thursday, March 21, 2019 10:11 AM, Viacheslav Ovsiienko: > > Subject: [PATCH 14/14] net/mlx5: add source vport match to the ingress > > rules > > > > For E-Switch configurations over multiport Infiniband devices we > > should add source vport match to correctly distribute traffic between > representors. > > > > Signed-off-by: Viacheslav Ovsiienko > > --- > > drivers/net/mlx5/mlx5_flow_dv.c | 38 > > ++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 38 insertions(+) > > > > diff --git a/drivers/net/mlx5/mlx5_flow_dv.c > > b/drivers/net/mlx5/mlx5_flow_dv.c index b8943da..489b3bd 100644 > > --- a/drivers/net/mlx5/mlx5_flow_dv.c > > +++ b/drivers/net/mlx5/mlx5_flow_dv.c > > @@ -3095,6 +3095,29 @@ struct field_modify_info modify_tcp[] =3D { } > > > > /** > > + * Add source vport match to the specified matcher. > > + * > > + * @param[in, out] matcher > > + * Flow matcher. > > + * @param[in, out] key > > + * Flow matcher value. > > + * @param[in] port > > + * Source vport value to match > > + * @param[in] mask > > + * Mask > > + */ > > +static void > > +flow_dv_translate_source_vport(void *matcher, void *key, > > + int16_t port, uint16_t mask) { > > + void *misc_m =3D MLX5_ADDR_OF(fte_match_param, matcher, > > misc_parameters); > > + void *misc_v =3D MLX5_ADDR_OF(fte_match_param, key, > > misc_parameters); > > + > > + MLX5_SET(fte_match_set_misc, misc_m, source_port, mask); > > + MLX5_SET(fte_match_set_misc, misc_v, source_port, port); } > > + > > +/** > > * Fill the flow with DV spec. > > * > > * @param[in] dev > > @@ -3389,6 +3412,21 @@ struct field_modify_info modify_tcp[] =3D { > > } > > dev_flow->dv.actions_n =3D actions_n; > > flow->actions =3D action_flags; > > + if (attr->ingress && !attr->transfer && > > + (priv->representor || priv->master)) { > > + /* It was validated - we support unidirections flows only. */ > > + assert(!attr->egress); > > + /* > > + * Add matching on source vport index only > > + * for ingress rules in E-Switch configurations. > > + */ > > + flow_dv_translate_source_vport(matcher.mask.buf, > > + dev_flow->dv.value.buf, > > + priv->representor_id < 0 ? > > + priv->representor_id : > > + priv->representor_id + 1, >=20 > The vport of representor_id 0 will be 1? > Who owns vport 0? PF. There is the foillowing vport mapping (for single E-Switch per PF): -1 - wire 0 - PF (uplink + VF reps) 1 - VF0 2 - VF1 ... n+1 - VFn This code is subject to change - (SF, multi E-Switch per function, etc), this patch currently supports single E-Switch per PF. >=20 > > + 0xffff); > > + } > > for (; items->type !=3D RTE_FLOW_ITEM_TYPE_END; items++) { > > int tunnel =3D !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); > > void *match_mask =3D matcher.mask.buf; > > -- > > 1.8.3.1