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PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: K4OOUFPSfygsCAOKBYXuthk6S4KarME9pXWTydAIJA9hEmqEtriuTkjdiRyedNFqyhWXrYarlTwQUJEaN5GmnXbydlbcwAWhtS24pZ7us2MBaTHRlrtv1lHgRLgrK9uivMgN9le5ItoUdhjbCaqMiQtN0QCOfV8HYdtV2TTx9ILFiYl4Bg+zPsOLqLV/1HnPGOpX+iWxEE96nO48i0ODVT8ajHXMCDV48EBMkuJMbdujcrda3RkF+6RLvcc0lcHzrqj+oWTGJdwu6HA1un3Cikm9rSeyTAX5KkTwflpYGNHGpOwJ6jm/4kA5TXPd6IrvzLbDoyqP0lBbr8dvXGyCPgVKSg/fS+zC6C2q8mMj44DRrcLoX3F7Xwuq1VlkCstzkDcEo+S2tBuXIl158qQo7mQ8levxKwUyN0oF5025W1k= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: c2280bd4-189c-474c-776b-08d6b0f5aafa X-MS-Exchange-CrossTenant-originalarrivaltime: 25 Mar 2019 07:44:10.0050 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR05MB3123 Subject: Re: [dpdk-dev] [PATCH 14/14] net/mlx5: add source vport match to the ingress rules X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190325074409.39aFbFmfhOC1HbUUhD6eBjeh68UqeyCqXBD3PCUIvII@z> > -----Original Message----- > From: Shahaf Shuler > Sent: Sunday, March 24, 2019 11:14 > To: Slava Ovsiienko ; dev@dpdk.org > Subject: RE: [PATCH 14/14] net/mlx5: add source vport match to the ingres= s > rules >=20 > Thursday, March 21, 2019 4:12 PM, Slava Ovsiienko: > > Subject: RE: [PATCH 14/14] net/mlx5: add source vport match to the > > ingress rules > > > > > > > > Signed-off-by: Viacheslav Ovsiienko >=20 > [...] >=20 > > > > + flow_dv_translate_source_vport(matcher.mask.buf, > > > > + dev_flow->dv.value.buf, > > > > + priv->representor_id < 0 ? > > > > + priv->representor_id : > > > > + priv->representor_id + 1, > > > > > > The vport of representor_id 0 will be 1? > > > Who owns vport 0? > > > > PF. > > There is the foillowing vport mapping (for single E-Switch per PF): > > > > -1 - wire >=20 > Wire, i.e. the uplink representor. indeed it's index is defined by PRM to= -1. >=20 > > 0 - PF (uplink + VF reps) >=20 > I don't understand this part. When you have uplink representor you don't > have PF. We do. There is PF anyway. In meaning we always have PCI function, which Is some kind of "container" for representors and also serves as E-Switch ma= nager. It may contain only "uplink rep" if there is no VF enabled, or may contain = the bunch=20 of uplink and VF reps. This PF has vport zero assigned. > Moreover, I would expect the first representor created to have vport_num= =3D0 > (w/ name pf0vf0). > Isn't it the case? No. Representors do not have dedicated vports, they share the vport zero (P= F) instead. And VFs have dedicated vports. >=20 > > 1 - VF0 > > 2 - VF1 > > ... > > n+1 - VFn > > > > This code is subject to change - (SF, multi E-Switch per function, > > etc), this patch currently supports single E-Switch per PF. > > > > > > > > > + 0xffff); > > > > + } > > > > for (; items->type !=3D RTE_FLOW_ITEM_TYPE_END; items++) { > > > > int tunnel =3D !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); > > > > void *match_mask =3D matcher.mask.buf; > > > > -- > > > > 1.8.3.1