From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 1AF8DA0679 for ; Thu, 4 Apr 2019 13:05:09 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8391B1B203; Thu, 4 Apr 2019 13:04:35 +0200 (CEST) Received: from EUR01-DB5-obe.outbound.protection.outlook.com (mail-eopbgr150055.outbound.protection.outlook.com [40.107.15.55]) by dpdk.org (Postfix) with ESMTP id 2FE791B1A0 for ; Thu, 4 Apr 2019 13:04:27 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=vn1U+zzG049sHExzz/S/ee/M7JES0DW224cmLdzdoLI=; b=V6mpX20SsJvGj/QAo8LI6ei5R+FvBbD+sFuywC6EdlQ60hIMv35OVtjzVyhfigaUFsnlVwlpUIarTnxlnyMFrHT09Q1VddcBOQa05lpINKHGEvVolno07wWEv7O1x8BhnJdX6RNSaJ6ciJI928lD30O/XX7zNEKlubSmabcYKl0= Received: from VI1PR0401MB2541.eurprd04.prod.outlook.com (10.168.65.19) by VI1PR0401MB2543.eurprd04.prod.outlook.com (10.168.65.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1750.19; Thu, 4 Apr 2019 11:04:25 +0000 Received: from VI1PR0401MB2541.eurprd04.prod.outlook.com ([fe80::18e3:39b6:c61d:3f18]) by VI1PR0401MB2541.eurprd04.prod.outlook.com ([fe80::18e3:39b6:c61d:3f18%12]) with mapi id 15.20.1750.017; Thu, 4 Apr 2019 11:04:25 +0000 From: Hemant Agrawal To: "dev@dpdk.org" CC: "thomas@monjalon.net" , Shreyansh Jain , "M.h. Lian" , Sachin Saxena Thread-Topic: [PATCH v2 5/7] raw/dpaa2_qdma: add rbp mode support Thread-Index: AQHU6tYqL3Nc9aAEeku9SWvztCm+jg== Date: Thu, 4 Apr 2019 11:04:25 +0000 Message-ID: <20190404110215.14410-5-hemant.agrawal@nxp.com> References: <20190326121610.28024-1-hemant.agrawal@nxp.com> <20190404110215.14410-1-hemant.agrawal@nxp.com> In-Reply-To: <20190404110215.14410-1-hemant.agrawal@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [92.120.1.72] x-mailer: git-send-email 2.17.1 x-clientproxiedby: BMXPR01CA0041.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:c::27) To VI1PR0401MB2541.eurprd04.prod.outlook.com (2603:10a6:800:56::19) authentication-results: spf=none (sender IP is ) smtp.mailfrom=hemant.agrawal@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 03969632-3fa4-43c0-484f-08d6b8ed4c7a x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(5600139)(711020)(4605104)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020); SRVR:VI1PR0401MB2543; x-ms-traffictypediagnostic: VI1PR0401MB2543: x-microsoft-antispam-prvs: x-forefront-prvs: 0997523C40 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(136003)(376002)(346002)(396003)(366004)(39860400002)(199004)(189003)(6916009)(6486002)(53936002)(50226002)(2906002)(8936002)(2616005)(86362001)(54906003)(7736002)(11346002)(44832011)(53946003)(486006)(316002)(8676002)(6512007)(446003)(1076003)(66066001)(5640700003)(99286004)(3846002)(6116002)(478600001)(386003)(5660300002)(26005)(81166006)(25786009)(1730700003)(76176011)(68736007)(102836004)(476003)(14454004)(4326008)(71200400001)(105586002)(81156014)(97736004)(256004)(14444005)(2501003)(186003)(2351001)(106356001)(30864003)(6436002)(305945005)(71190400001)(52116002)(6506007)(36756003)(579004); DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR0401MB2543; H:VI1PR0401MB2541.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: pMK337ClpTIN7cbMp1/EBse3Q2eNA795RcshqVm2UJVAmWUoGZcCMo52grjPMGrLW67SEfTcrDmpbP2XtHCyTiwo/AOXqU+4eyTFlocHKvp6Lea+bIc3EKIswiG5RoPPwrtJcJm+6dM11pB7tqjoRnSKVon6QCB94q9M2FXerfazidBPDmsn+BR0kVYRT/udi7mlAPulbm4fs3LJO5BA9KsJRjPSb5vzGIl8gQXI/4+3KsuAfOJQ4QsSxxly0v9+jG5p78ZpE+oAPCNBWyVfH4zAlg/ZU41hDT5AZaOObJpuILlwpQEKHxJ3DTqLAFNO1ayCbIviMsWbI4s1ZvtSdZn1nz2otwf+xUscoJUChLss21YK6w+ovebT46zDBjAqfgqLYGbA6DgWIuzpmvC26N0aokQDxwx+9pOBEQd5ABM= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 03969632-3fa4-43c0-484f-08d6b8ed4c7a X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Apr 2019 11:04:25.3449 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0401MB2543 Subject: [dpdk-dev] [PATCH v2 5/7] raw/dpaa2_qdma: add rbp mode support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190404110425.up-PAI0-DbWac0gysFnFBX7FDIAGE1nbzxAKyYPIFp0@z> Add support for route by port mode. The route by port feature in HW helps in translating the PCI address of connected device. Signed-off-by: Minghuan Lian Signed-off-by: Sachin Saxena Signed-off-by: Hemant Agrawal --- drivers/raw/dpaa2_qdma/Makefile | 2 +- drivers/raw/dpaa2_qdma/dpaa2_qdma.c | 403 +++++++++++++------- drivers/raw/dpaa2_qdma/dpaa2_qdma.h | 65 +++- drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h | 60 ++- 4 files changed, 383 insertions(+), 147 deletions(-) diff --git a/drivers/raw/dpaa2_qdma/Makefile b/drivers/raw/dpaa2_qdma/Makef= ile index 5c75f5fa0..ee95662f1 100644 --- a/drivers/raw/dpaa2_qdma/Makefile +++ b/drivers/raw/dpaa2_qdma/Makefile @@ -26,7 +26,7 @@ LDLIBS +=3D -lrte_common_dpaax =20 EXPORT_MAP :=3D rte_pmd_dpaa2_qdma_version.map =20 -LIBABIVER :=3D 2 +LIBABIVER :=3D 3 =20 # # all source are stored in SRCS-y diff --git a/drivers/raw/dpaa2_qdma/dpaa2_qdma.c b/drivers/raw/dpaa2_qdma/d= paa2_qdma.c index a1351e648..cf1a1aaa6 100644 --- a/drivers/raw/dpaa2_qdma/dpaa2_qdma.c +++ b/drivers/raw/dpaa2_qdma/dpaa2_qdma.c @@ -19,13 +19,16 @@ #include #include =20 +#include "rte_pmd_dpaa2_qdma.h" #include "dpaa2_qdma.h" #include "dpaa2_qdma_logs.h" -#include "rte_pmd_dpaa2_qdma.h" =20 /* Dynamic log type identifier */ int dpaa2_qdma_logtype; =20 +uint32_t dpaa2_coherent_no_alloc_cache; +uint32_t dpaa2_coherent_alloc_cache; + /* QDMA device */ static struct qdma_device qdma_dev; =20 @@ -345,14 +348,29 @@ rte_qdma_vq_create(uint32_t lcore_id, uint32_t flags) =20 qdma_vqs[i].in_use =3D 1; qdma_vqs[i].lcore_id =3D lcore_id; - + memset(&qdma_vqs[i].rbp, 0, sizeof(struct rte_qdma_rbp)); rte_spinlock_unlock(&qdma_dev.lock); =20 return i; } =20 +/*create vq for route-by-port*/ +int +rte_qdma_vq_create_rbp(uint32_t lcore_id, uint32_t flags, + struct rte_qdma_rbp *rbp) +{ + int i; + + i =3D rte_qdma_vq_create(lcore_id, flags); + + memcpy(&qdma_vqs[i].rbp, rbp, sizeof(struct rte_qdma_rbp)); + + return i; +} + static void dpaa2_qdma_populate_fle(struct qbman_fle *fle, + struct rte_qdma_rbp *rbp, uint64_t src, uint64_t dest, size_t len, uint32_t flags) { @@ -368,10 +386,36 @@ dpaa2_qdma_populate_fle(struct qbman_fle *fle, DPAA2_SET_FLE_LEN(fle, (2 * (sizeof(struct qdma_sdd)))); =20 /* source and destination descriptor */ - DPAA2_SET_SDD_RD_COHERENT(sdd); /* source descriptor CMD */ - sdd++; - DPAA2_SET_SDD_WR_COHERENT(sdd); /* dest descriptor CMD */ + if (rbp && rbp->enable) { + /* source */ + sdd->read_cmd.portid =3D rbp->sportid; + sdd->rbpcmd_simple.pfid =3D rbp->spfid; + sdd->rbpcmd_simple.vfid =3D rbp->svfid; + + if (rbp->srbp) { + sdd->read_cmd.rbp =3D rbp->srbp; + sdd->read_cmd.rdtype =3D DPAA2_RBP_MEM_RW; + } else { + sdd->read_cmd.rdtype =3D dpaa2_coherent_no_alloc_cache; + } + sdd++; + /* destination */ + sdd->write_cmd.portid =3D rbp->dportid; + sdd->rbpcmd_simple.pfid =3D rbp->dpfid; + sdd->rbpcmd_simple.vfid =3D rbp->dvfid; + + if (rbp->drbp) { + sdd->write_cmd.rbp =3D rbp->drbp; + sdd->write_cmd.wrttype =3D DPAA2_RBP_MEM_RW; + } else { + sdd->write_cmd.wrttype =3D dpaa2_coherent_alloc_cache; + } =20 + } else { + sdd->read_cmd.rdtype =3D dpaa2_coherent_no_alloc_cache; + sdd++; + sdd->write_cmd.wrttype =3D dpaa2_coherent_alloc_cache; + } fle++; /* source frame list to source buffer */ if (flags & RTE_QDMA_JOB_SRC_PHY) { @@ -396,31 +440,57 @@ dpaa2_qdma_populate_fle(struct qbman_fle *fle, DPAA2_SET_FLE_FIN(fle); } =20 -int -rte_qdma_vq_enqueue_multi(uint16_t vq_id, - struct rte_qdma_job **job, - uint16_t nb_jobs) +static inline uint16_t dpdmai_dev_set_fd(struct qbman_fd *fd, + struct rte_qdma_job *job, + struct rte_qdma_rbp *rbp, + uint16_t vq_id) { - struct qdma_virt_queue *qdma_vq =3D &qdma_vqs[vq_id]; - struct qdma_hw_queue *qdma_pq =3D qdma_vq->hw_queue; - struct dpaa2_dpdmai_dev *dpdmai_dev =3D qdma_pq->dpdmai_dev; struct qdma_io_meta *io_meta; - struct qbman_fd fd_arr[MAX_TX_RING_SLOTS]; - struct dpaa2_queue *txq; struct qbman_fle *fle; + int ret =3D 0; + /* + * Get an FLE/SDD from FLE pool. + * Note: IO metadata is before the FLE and SDD memory. + */ + ret =3D rte_mempool_get(qdma_dev.fle_pool, (void **)(&io_meta)); + if (ret) { + DPAA2_QDMA_DP_DEBUG("Memory alloc failed for FLE"); + return ret; + } + + /* Set the metadata */ + io_meta->cnxt =3D (size_t)job; + io_meta->id =3D vq_id; + + fle =3D (struct qbman_fle *)(io_meta + 1); + + DPAA2_SET_FD_ADDR(fd, DPAA2_VADDR_TO_IOVA(fle)); + DPAA2_SET_FD_COMPOUND_FMT(fd); + DPAA2_SET_FD_FRC(fd, QDMA_SER_CTX); + + /* Populate FLE */ + memset(fle, 0, QDMA_FLE_POOL_SIZE); + dpaa2_qdma_populate_fle(fle, rbp, job->src, job->dest, + job->len, job->flags); + + return 0; +} + +static int +dpdmai_dev_enqueue_multi(struct dpaa2_dpdmai_dev *dpdmai_dev, + uint16_t txq_id, + uint16_t vq_id, + struct rte_qdma_rbp *rbp, + struct rte_qdma_job **job, + uint16_t nb_jobs) +{ + struct qbman_fd fd[RTE_QDMA_BURST_NB_MAX]; + struct dpaa2_queue *txq; struct qbman_eq_desc eqdesc; struct qbman_swp *swp; int ret; uint32_t num_to_send =3D 0; uint16_t num_tx =3D 0; - uint16_t num_txed =3D 0; - - /* Return error in case of wrong lcore_id */ - if (rte_lcore_id() !=3D qdma_vq->lcore_id) { - DPAA2_QDMA_ERR("QDMA enqueue for vqid %d on wrong core", - vq_id); - return -1; - } =20 if (unlikely(!DPAA2_PER_LCORE_DPIO)) { ret =3D dpaa2_affine_qbman_swp(); @@ -431,7 +501,7 @@ rte_qdma_vq_enqueue_multi(uint16_t vq_id, } swp =3D DPAA2_PER_LCORE_PORTAL; =20 - txq =3D &(dpdmai_dev->tx_queue[qdma_pq->queue_id]); + txq =3D &(dpdmai_dev->tx_queue[txq_id]); =20 /* Prepare enqueue descriptor */ qbman_eq_desc_clear(&eqdesc); @@ -439,6 +509,8 @@ rte_qdma_vq_enqueue_multi(uint16_t vq_id, qbman_eq_desc_set_no_orp(&eqdesc, 0); qbman_eq_desc_set_response(&eqdesc, 0, 0); =20 + memset(fd, 0, RTE_QDMA_BURST_NB_MAX * sizeof(struct qbman_fd)); + while (nb_jobs > 0) { uint32_t loop; =20 @@ -446,73 +518,100 @@ rte_qdma_vq_enqueue_multi(uint16_t vq_id, dpaa2_eqcr_size : nb_jobs; =20 for (loop =3D 0; loop < num_to_send; loop++) { - /* - * Get an FLE/SDD from FLE pool. - * Note: IO metadata is before the FLE and SDD memory. - */ - ret =3D rte_mempool_get(qdma_dev.fle_pool, - (void **)(&io_meta)); - if (ret) { - DPAA2_QDMA_DP_WARN("Me alloc failed for FLE"); - return ret; + ret =3D dpdmai_dev_set_fd(&fd[loop], + job[num_tx], rbp, vq_id); + if (ret < 0) { + /* Set nb_jobs to loop, so outer while loop + * breaks out. + */ + nb_jobs =3D loop; + break; } =20 - /* Set the metadata */ - io_meta->cnxt =3D (size_t)job[num_tx]; - io_meta->id =3D vq_id; - - fle =3D (struct qbman_fle *)(io_meta + 1); - - /* populate Frame descriptor */ - memset(&fd_arr[loop], 0, sizeof(struct qbman_fd)); - DPAA2_SET_FD_ADDR(&fd_arr[loop], - DPAA2_VADDR_TO_IOVA(fle)); - DPAA2_SET_FD_COMPOUND_FMT(&fd_arr[loop]); - DPAA2_SET_FD_FRC(&fd_arr[loop], QDMA_SER_CTX); - - /* Populate FLE */ - memset(fle, 0, QDMA_FLE_POOL_SIZE); - dpaa2_qdma_populate_fle(fle, job[num_tx]->src, - job[num_tx]->dest, - job[num_tx]->len, - job[num_tx]->flags); - num_tx++; } =20 /* Enqueue the packet to the QBMAN */ uint32_t enqueue_loop =3D 0; - while (enqueue_loop < num_to_send) { + while (enqueue_loop < loop) { enqueue_loop +=3D qbman_swp_enqueue_multiple(swp, &eqdesc, - &fd_arr[enqueue_loop], + &fd[enqueue_loop], NULL, - num_to_send - enqueue_loop); + loop - enqueue_loop); } - - num_txed +=3D num_to_send; - nb_jobs -=3D num_to_send; + nb_jobs -=3D loop; } - qdma_vq->num_enqueues +=3D num_txed; - return num_txed; + return num_tx; } =20 int -rte_qdma_vq_enqueue(uint16_t vq_id, - struct rte_qdma_job *job) +rte_qdma_vq_enqueue_multi(uint16_t vq_id, + struct rte_qdma_job **job, + uint16_t nb_jobs) { + struct qdma_virt_queue *qdma_vq =3D &qdma_vqs[vq_id]; + struct qdma_hw_queue *qdma_pq =3D qdma_vq->hw_queue; + struct dpaa2_dpdmai_dev *dpdmai_dev =3D qdma_pq->dpdmai_dev; int ret; =20 - ret =3D rte_qdma_vq_enqueue_multi(vq_id, &job, 1); + DPAA2_QDMA_FUNC_TRACE(); + + /* Return error in case of wrong lcore_id */ + if (rte_lcore_id() !=3D qdma_vq->lcore_id) { + DPAA2_QDMA_ERR("QDMA enqueue for vqid %d on wrong core", + vq_id); + return -EINVAL; + } + + ret =3D dpdmai_dev_enqueue_multi(dpdmai_dev, + qdma_pq->queue_id, + vq_id, + &qdma_vq->rbp, + job, + nb_jobs); if (ret < 0) { DPAA2_QDMA_ERR("DPDMAI device enqueue failed: %d", ret); return ret; } =20 - return 1; + qdma_vq->num_enqueues +=3D ret; + + return ret; +} + +int +rte_qdma_vq_enqueue(uint16_t vq_id, + struct rte_qdma_job *job) +{ + return rte_qdma_vq_enqueue_multi(vq_id, &job, 1); +} + +static inline uint16_t dpdmai_dev_get_job(const struct qbman_fd *fd, + struct rte_qdma_job **job) +{ + struct qbman_fle *fle; + struct qdma_io_meta *io_meta; + uint16_t vqid; + /* + * Fetch metadata from FLE. job and vq_id were set + * in metadata in the enqueue operation. + */ + fle =3D (struct qbman_fle *)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)); + io_meta =3D (struct qdma_io_meta *)(fle) - 1; + + *job =3D (struct rte_qdma_job *)(size_t)io_meta->cnxt; + (*job)->status =3D (DPAA2_GET_FD_ERR(fd) << 8) | + (DPAA2_GET_FD_FRC(fd) & 0xFF); + + vqid =3D io_meta->id; + + /* Free FLE to the pool */ + rte_mempool_put(qdma_dev.fle_pool, io_meta); + + return vqid; } =20 -/* Function to receive a QDMA job for a given device and queue*/ static int dpdmai_dev_dequeue_multijob(struct dpaa2_dpdmai_dev *dpdmai_dev, uint16_t rxq_id, @@ -520,16 +619,18 @@ dpdmai_dev_dequeue_multijob(struct dpaa2_dpdmai_dev *= dpdmai_dev, struct rte_qdma_job **job, uint16_t nb_jobs) { - struct qdma_io_meta *io_meta; struct dpaa2_queue *rxq; struct qbman_result *dq_storage; struct qbman_pull_desc pulldesc; - const struct qbman_fd *fd; struct qbman_swp *swp; - struct qbman_fle *fle; uint32_t fqid; - uint8_t status; - int ret; + uint8_t status, pending; + uint8_t num_rx =3D 0; + const struct qbman_fd *fd; + uint16_t vqid; + int ret, next_pull =3D nb_jobs, num_pulled =3D 0; + + DPAA2_QDMA_FUNC_TRACE(); =20 if (unlikely(!DPAA2_PER_LCORE_DPIO)) { ret =3D dpaa2_affine_qbman_swp(); @@ -539,77 +640,75 @@ dpdmai_dev_dequeue_multijob(struct dpaa2_dpdmai_dev *= dpdmai_dev, } } swp =3D DPAA2_PER_LCORE_PORTAL; + rxq =3D &(dpdmai_dev->rx_queue[rxq_id]); - dq_storage =3D rxq->q_storage->dq_storage[0]; fqid =3D rxq->fqid; =20 - /* Prepare dequeue descriptor */ - qbman_pull_desc_clear(&pulldesc); - qbman_pull_desc_set_fq(&pulldesc, fqid); - qbman_pull_desc_set_storage(&pulldesc, dq_storage, - (uint64_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1); - if (nb_jobs > dpaa2_dqrr_size) - qbman_pull_desc_set_numframes(&pulldesc, dpaa2_dqrr_size); - else - qbman_pull_desc_set_numframes(&pulldesc, nb_jobs); - - while (1) { - if (qbman_swp_pull(swp, &pulldesc)) { - DPAA2_QDMA_DP_WARN("VDQ command not issued. QBMAN busy"); - continue; + do { + dq_storage =3D rxq->q_storage->dq_storage[0]; + /* Prepare dequeue descriptor */ + qbman_pull_desc_clear(&pulldesc); + qbman_pull_desc_set_fq(&pulldesc, fqid); + qbman_pull_desc_set_storage(&pulldesc, dq_storage, + (uint64_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1); + + if (next_pull > dpaa2_dqrr_size) { + qbman_pull_desc_set_numframes(&pulldesc, + dpaa2_dqrr_size); + next_pull -=3D dpaa2_dqrr_size; + } else { + qbman_pull_desc_set_numframes(&pulldesc, next_pull); + next_pull =3D 0; } - break; - } =20 - rte_prefetch0((void *)((size_t)(dq_storage + 1))); - /* Check if the previous issued command is completed. */ - while (!qbman_check_command_complete(dq_storage)) - ; + while (1) { + if (qbman_swp_pull(swp, &pulldesc)) { + DPAA2_QDMA_DP_WARN("VDQ command not issued. QBMAN busy"); + /* Portal was busy, try again */ + continue; + } + break; + } =20 - int num_pulled =3D 0; - int pending =3D 1; - do { - /* Loop until the dq_storage is updated with - * new token by QBMAN - */ - while (!qbman_check_new_result(dq_storage)) + rte_prefetch0((void *)((size_t)(dq_storage + 1))); + /* Check if the previous issued command is completed. */ + while (!qbman_check_command_complete(dq_storage)) ; =20 - rte_prefetch0((void *)((size_t)(dq_storage + 2))); - /* Check whether Last Pull command is Expired and - * setting Condition for Loop termination - */ - if (qbman_result_DQ_is_pull_complete(dq_storage)) { - pending =3D 0; - /* Check for valid frame. */ - status =3D qbman_result_DQ_flags(dq_storage); - if (unlikely((status & - QBMAN_DQ_STAT_VALIDFRAME) =3D=3D 0)) - continue; - } - fd =3D qbman_result_DQ_fd(dq_storage); + num_pulled =3D 0; + pending =3D 1; =20 - /* - * Fetch metadata from FLE. job and vq_id were set - * in metadata in the enqueue operation. - */ - fle =3D (struct qbman_fle *) - DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)); - io_meta =3D (struct qdma_io_meta *)(fle) - 1; - if (vq_id) - vq_id[num_pulled] =3D io_meta->id; + do { + /* Loop until dq_storage is updated + * with new token by QBMAN + */ + while (!qbman_check_new_result(dq_storage)) + ; + rte_prefetch0((void *)((size_t)(dq_storage + 2))); + + if (qbman_result_DQ_is_pull_complete(dq_storage)) { + pending =3D 0; + /* Check for valid frame. */ + status =3D qbman_result_DQ_flags(dq_storage); + if (unlikely((status & + QBMAN_DQ_STAT_VALIDFRAME) =3D=3D 0)) + continue; + } + fd =3D qbman_result_DQ_fd(dq_storage); =20 - job[num_pulled] =3D (struct rte_qdma_job *)(size_t)io_meta->cnxt; - job[num_pulled]->status =3D DPAA2_GET_FD_ERR(fd); + vqid =3D dpdmai_dev_get_job(fd, &job[num_rx]); + if (vq_id) + vq_id[num_rx] =3D vqid; =20 - /* Free FLE to the pool */ - rte_mempool_put(qdma_dev.fle_pool, io_meta); + dq_storage++; + num_rx++; + num_pulled++; =20 - dq_storage++; - num_pulled++; - } while (pending && (num_pulled <=3D dpaa2_dqrr_size)); + } while (pending); + /* Last VDQ provided all packets and more packets are requested */ + } while (next_pull && num_pulled =3D=3D dpaa2_dqrr_size); =20 - return num_pulled; + return num_rx; } =20 int @@ -664,9 +763,9 @@ rte_qdma_vq_dequeue_multi(uint16_t vq_id, temp_qdma_vq =3D &qdma_vqs[temp_vq_id[i]]; rte_ring_enqueue(temp_qdma_vq->status_ring, (void *)(job[i])); - ring_count =3D rte_ring_count( - qdma_vq->status_ring); } + ring_count =3D rte_ring_count( + qdma_vq->status_ring); } =20 if (ring_count) { @@ -743,6 +842,35 @@ rte_qdma_vq_destroy(uint16_t vq_id) return 0; } =20 +int +rte_qdma_vq_destroy_rbp(uint16_t vq_id) +{ + struct qdma_virt_queue *qdma_vq =3D &qdma_vqs[vq_id]; + + DPAA2_QDMA_FUNC_TRACE(); + + /* In case there are pending jobs on any VQ, return -EBUSY */ + if (qdma_vq->num_enqueues !=3D qdma_vq->num_dequeues) + return -EBUSY; + + rte_spinlock_lock(&qdma_dev.lock); + + if (qdma_vq->exclusive_hw_queue) { + free_hw_queue(qdma_vq->hw_queue); + } else { + if (qdma_vqs->status_ring) + rte_ring_free(qdma_vqs->status_ring); + + put_hw_queue(qdma_vq->hw_queue); + } + + memset(qdma_vq, 0, sizeof(struct qdma_virt_queue)); + + rte_spinlock_lock(&qdma_dev.lock); + + return 0; +} + void rte_qdma_stop(void) { @@ -939,6 +1067,21 @@ dpaa2_dpdmai_dev_init(struct rte_rawdev *rawdev, int = dpdmai_id) DPAA2_QDMA_ERR("Adding H/W queue to list failed"); goto init_err; } + + if (!dpaa2_coherent_no_alloc_cache) { + if (dpaa2_svr_family =3D=3D SVR_LX2160A) { + dpaa2_coherent_no_alloc_cache =3D + DPAA2_LX2_COHERENT_NO_ALLOCATE_CACHE; + dpaa2_coherent_alloc_cache =3D + DPAA2_LX2_COHERENT_ALLOCATE_CACHE; + } else { + dpaa2_coherent_no_alloc_cache =3D + DPAA2_COHERENT_NO_ALLOCATE_CACHE; + dpaa2_coherent_alloc_cache =3D + DPAA2_COHERENT_ALLOCATE_CACHE; + } + } + DPAA2_QDMA_DEBUG("Initialized dpdmai object successfully"); =20 return 0; diff --git a/drivers/raw/dpaa2_qdma/dpaa2_qdma.h b/drivers/raw/dpaa2_qdma/d= paa2_qdma.h index 0cbe90255..f15dda694 100644 --- a/drivers/raw/dpaa2_qdma/dpaa2_qdma.h +++ b/drivers/raw/dpaa2_qdma/dpaa2_qdma.h @@ -22,28 +22,24 @@ struct qdma_io_meta; =20 /** Notification by FQD_CTX[fqid] */ #define QDMA_SER_CTX (1 << 8) - +#define DPAA2_RBP_MEM_RW 0x0 /** * Source descriptor command read transaction type for RBP=3D0: * coherent copy of cacheable memory */ -#define DPAA2_SET_SDD_RD_COHERENT(sdd) ((sdd)->cmd =3D (0xb << 28)) +#define DPAA2_COHERENT_NO_ALLOCATE_CACHE 0xb +#define DPAA2_LX2_COHERENT_NO_ALLOCATE_CACHE 0x7 /** * Destination descriptor command write transaction type for RBP=3D0: * coherent copy of cacheable memory */ -#define DPAA2_SET_SDD_WR_COHERENT(sdd) ((sdd)->cmd =3D (0x6 << 28)) +#define DPAA2_COHERENT_ALLOCATE_CACHE 0x6 +#define DPAA2_LX2_COHERENT_ALLOCATE_CACHE 0xb =20 /** Maximum possible H/W Queues on each core */ #define MAX_HW_QUEUE_PER_CORE 64 =20 -/** - * In case of Virtual Queue mode, this specifies the number of - * dequeue the 'qdma_vq_dequeue/multi' API does from the H/W Queue - * in case there is no job present on the Virtual Queue ring. - */ -#define QDMA_DEQUEUE_BUDGET 64 - +#define QDMA_RBP_UPPER_ADDRESS_MASK (0xfff0000000000) /** * Represents a QDMA device. * A single QDMA device exists which is combination of multiple DPDMAI raw= dev's. @@ -90,6 +86,8 @@ struct qdma_virt_queue { struct rte_ring *status_ring; /** Associated hw queue */ struct qdma_hw_queue *hw_queue; + /** Route by port */ + struct rte_qdma_rbp rbp; /** Associated lcore id */ uint32_t lcore_id; /** States if this vq is in use or not */ @@ -118,7 +116,7 @@ struct qdma_io_meta { */ uint64_t cnxt; /** VQ ID is stored as a part of metadata of the enqueue command */ - uint64_t id; + uint64_t id; }; =20 /** Source/Destination Descriptor */ @@ -127,9 +125,48 @@ struct qdma_sdd { /** Stride configuration */ uint32_t stride; /** Route-by-port command */ - uint32_t rbpcmd; - uint32_t cmd; -} __attribute__((__packed__)); + union { + uint32_t rbpcmd; + struct rbpcmd_st { + uint32_t vfid:6; + uint32_t rsv4:2; + uint32_t pfid:1; + uint32_t rsv3:7; + uint32_t attr:3; + uint32_t rsv2:1; + uint32_t at:2; + uint32_t vfa:1; + uint32_t ca:1; + uint32_t tc:3; + uint32_t rsv1:5; + } rbpcmd_simple; + }; + union { + uint32_t cmd; + struct rcmd_simple { + uint32_t portid:4; + uint32_t rsv1:14; + uint32_t rbp:1; + uint32_t ssen:1; + uint32_t rthrotl:4; + uint32_t sqos:3; + uint32_t ns:1; + uint32_t rdtype:4; + } read_cmd; + struct wcmd_simple { + uint32_t portid:4; + uint32_t rsv3:10; + uint32_t rsv2:2; + uint32_t lwc:2; + uint32_t rbp:1; + uint32_t dsen:1; + uint32_t rsv1:4; + uint32_t dqos:3; + uint32_t ns:1; + uint32_t wrttype:4; + } write_cmd; + }; +} __attribute__ ((__packed__)); =20 /** Represents a DPDMAI raw device */ struct dpaa2_dpdmai_dev { diff --git a/drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h b/drivers/raw/dpaa= 2_qdma/rte_pmd_dpaa2_qdma.h index e1ccc19e8..bbc66a286 100644 --- a/drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h +++ b/drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h @@ -13,7 +13,7 @@ */ =20 /** Maximum qdma burst size */ -#define RTE_QDMA_BURST_NB_MAX 32 +#define RTE_QDMA_BURST_NB_MAX 256 =20 /** Determines the mode of operation */ enum { @@ -73,6 +73,40 @@ struct rte_qdma_config { int fle_pool_count; }; =20 +struct rte_qdma_rbp { + uint32_t use_ultrashort:1; + uint32_t enable:1; + /** + * dportid: + * 0000 PCI-Express 1 + * 0001 PCI-Express 2 + * 0010 PCI-Express 3 + * 0011 PCI-Express 4 + * 0100 PCI-Express 5 + * 0101 PCI-Express 6 + */ + uint32_t dportid:4; + uint32_t dpfid:2; + uint32_t dvfid:6; + /*using route by port for destination */ + uint32_t drbp:1; + /** + * sportid: + * 0000 PCI-Express 1 + * 0001 PCI-Express 2 + * 0010 PCI-Express 3 + * 0011 PCI-Express 4 + * 0100 PCI-Express 5 + * 0101 PCI-Express 6 + */ + uint32_t sportid:4; + uint32_t spfid:2; + uint32_t svfid:6; + /* using route by port for source */ + uint32_t srbp:1; + uint32_t rsv:4; +}; + /** Provides QDMA device statistics */ struct rte_qdma_vq_stats { /** States if this vq has exclusively associated hw queue */ @@ -105,8 +139,10 @@ struct rte_qdma_job { /** * Status of the transaction. * This is filled in the dequeue operation by the driver. + * upper 8bits acc_err for route by port. + * lower 8bits fd error */ - uint8_t status; + uint16_t status; }; =20 /** @@ -177,6 +213,11 @@ rte_qdma_start(void); int rte_qdma_vq_create(uint32_t lcore_id, uint32_t flags); =20 +/*create vq for route-by-port*/ +int +rte_qdma_vq_create_rbp(uint32_t lcore_id, uint32_t flags, + struct rte_qdma_rbp *rbp); + /** * Enqueue multiple jobs to a Virtual Queue. * If the enqueue is successful, the H/W will perform DMA operations @@ -275,6 +316,21 @@ rte_qdma_vq_stats(uint16_t vq_id, int rte_qdma_vq_destroy(uint16_t vq_id); =20 +/** + * Destroy the RBP specific Virtual Queue specified by vq_id. + * This API can be called from any thread/core. User can create/destroy + * VQ's at runtime. + * + * @param vq_id + * RBP based Virtual Queue ID which needs to be deinialized. + * + * @returns + * - 0: Success. + * - <0: Error code. + */ + +int __rte_experimental +rte_qdma_vq_destroy_rbp(uint16_t vq_id); /** * Stop QDMA device. */ --=20 2.17.1