[dpdk-dev] [PATCH 1/3] mk: introduce helper to check valid compiler argument

[dpdk-dev] [PATCH 1/3] mk: introduce helper to check valid compiler argument

[Jerin Jacob Kollanukkaran]

Introduce rte_cc_has_argument() Makefile helper to
check a given argument is support by the compiler.

Example Usage:

include $(RTE_SDK)/mk/rte.helper.mk
MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)

This would allow adding -mcpu=octeontx2 in MACHINE_CFLAGS
if it is only supported by the compiler. The use case for such
scheme is to enable the mcpu optimization if the compiler
supports else it needs to compile the source code without
any errors.

This patch also moves inclusion of toolchain's rte.vars.mk
to before the machine's rte.vars.mk inclusion to make
correct CC available for the cross compile case.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
---
 mk/rte.helper.mk              | 12 ++++++++++++
 mk/target/generic/rte.vars.mk | 22 +++++++++++-----------
 2 files changed, 23 insertions(+), 11 deletions(-)
 create mode 100644 mk/rte.helper.mk

diff --git a/mk/rte.helper.mk b/mk/rte.helper.mk
new file mode 100644
index 000000000..2c5d5275e
--- /dev/null
+++ b/mk/rte.helper.mk
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+
+# rte_cc_has_argument
+# Usage: MACHINE_CFLAGS += $(call rte_cc_has_argument, -mno-avx512f)
+# Return the argument if the argument is supported by the compiler.
+#
+define rte_cc_has_argument
+	$(shell $(CC) -Werror $(1) -c -x c /dev/null -o tmp$$ 2> /dev/null && rm -f tmp$$ && echo $(1) | xargs echo -n)
+endef
+
+
diff --git a/mk/target/generic/rte.vars.mk b/mk/target/generic/rte.vars.mk
index dd149acc9..25a578ad7 100644
--- a/mk/target/generic/rte.vars.mk
+++ b/mk/target/generic/rte.vars.mk
@@ -7,6 +7,17 @@
 # executive environment.
 #
 
+#
+# toolchain:
+#
+#   - define CC, LD, AR, AS, ...
+#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
+#   - may override any previously defined variable
+#
+include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
+
 #
 # machine:
 #
@@ -45,17 +56,6 @@ endif
 #
 include $(RTE_SDK)/mk/arch/$(RTE_ARCH)/rte.vars.mk
 
-#
-# toolchain:
-#
-#   - define CC, LD, AR, AS, ...
-#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
-#   - may override any previously defined variable
-#
-include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
-
 #
 # exec-env:
 #
-- 
2.20.1

[dpdk-dev] [PATCH 2/3] config: add thunderx2 machine config

[Jerin Jacob Kollanukkaran]

Optimized configuration for Marvell thunderx2 SoC.

Product details are here:

https://www.marvell.com/server-processors/thunderx2-arm-processors/

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
---
 config/defconfig_arm64-thunderx2-linuxapp-gcc | 11 ++++++
 mk/machine/thunderx2/rte.vars.mk              | 34 +++++++++++++++++++
 2 files changed, 45 insertions(+)
 create mode 100644 config/defconfig_arm64-thunderx2-linuxapp-gcc
 create mode 100644 mk/machine/thunderx2/rte.vars.mk

diff --git a/config/defconfig_arm64-thunderx2-linuxapp-gcc b/config/defconfig_arm64-thunderx2-linuxapp-gcc
new file mode 100644
index 000000000..27db58e50
--- /dev/null
+++ b/config/defconfig_arm64-thunderx2-linuxapp-gcc
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linuxapp-gcc"
+
+CONFIG_RTE_MACHINE="thunderx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=64
+CONFIG_RTE_MAX_NUMA_NODES=2
+CONFIG_RTE_MAX_LCORE=256
diff --git a/mk/machine/thunderx2/rte.vars.mk b/mk/machine/thunderx2/rte.vars.mk
new file mode 100644
index 000000000..b80dc8680
--- /dev/null
+++ b/mk/machine/thunderx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.1-a+crc+crypto)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=thunderx2t99)
-- 
2.20.1

[dpdk-dev] [PATCH 3/3] config: add octeontx2 machine config

[Jerin Jacob Kollanukkaran]

Optimized configuration for Marvell octeontx2 SoC.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
---
 config/defconfig_arm64-octeontx2-linuxapp-gcc | 18 ++++++++++
 mk/machine/octeontx2/rte.vars.mk              | 34 +++++++++++++++++++
 2 files changed, 52 insertions(+)
 create mode 100644 config/defconfig_arm64-octeontx2-linuxapp-gcc
 create mode 100644 mk/machine/octeontx2/rte.vars.mk

diff --git a/config/defconfig_arm64-octeontx2-linuxapp-gcc b/config/defconfig_arm64-octeontx2-linuxapp-gcc
new file mode 100644
index 000000000..9a99eada1
--- /dev/null
+++ b/config/defconfig_arm64-octeontx2-linuxapp-gcc
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linuxapp-gcc"
+
+CONFIG_RTE_MACHINE="octeontx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=128
+CONFIG_RTE_MAX_NUMA_NODES=1
+CONFIG_RTE_MAX_LCORE=24
+
+# Doesn't support NUMA
+CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
+CONFIG_RTE_LIBRTE_VHOST_NUMA=n
+
+# Recommend to use VFIO as co-processors needs SMMU/IOMMU
+CONFIG_RTE_EAL_IGB_UIO=n
diff --git a/mk/machine/octeontx2/rte.vars.mk b/mk/machine/octeontx2/rte.vars.mk
new file mode 100644
index 000000000..e209cf492
--- /dev/null
+++ b/mk/machine/octeontx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.2-a+crc+crypto+lse)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)
-- 
2.20.1

Re: [dpdk-dev] [PATCH 2/3] config: add thunderx2 machine config

[Thomas Monjalon]

Hi Jerin,

06/01/2019 14:20, Jerin Jacob Kollanukkaran:
> Optimized configuration for Marvell thunderx2 SoC.
> 
> Product details are here:
> 
> https://www.marvell.com/server-processors/thunderx2-arm-processors/
> 
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> ---
>  config/defconfig_arm64-thunderx2-linuxapp-gcc | 11 ++++++
>  mk/machine/thunderx2/rte.vars.mk              | 34 +++++++++++++++++++

You should enable meson build at the same time.

Re: [dpdk-dev] [PATCH 2/3] config: add thunderx2 machine config

[Gavin Hu (Arm Technology China)]

> -----Original Message-----
> From: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
> Sent: Sunday, January 6, 2019 9:20 PM
> To: thomas@monjalon.net
> Cc: dev@dpdk.org; Gavin Hu (Arm Technology China) <Gavin.Hu@arm.com>;
> jerinj@marvell.com
> Subject: [dpdk-dev] [PATCH 2/3] config: add thunderx2 machine config
> 
> Optimized configuration for Marvell thunderx2 SoC.
> 
> Product details are here:
> 
> https://www.marvell.com/server-processors/thunderx2-arm-processors/
> 
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> ---
>  config/defconfig_arm64-thunderx2-linuxapp-gcc | 11 ++++++
>  mk/machine/thunderx2/rte.vars.mk              | 34 +++++++++++++++++++
>  2 files changed, 45 insertions(+)
>  create mode 100644 config/defconfig_arm64-thunderx2-linuxapp-gcc
>  create mode 100644 mk/machine/thunderx2/rte.vars.mk
> 
> diff --git a/config/defconfig_arm64-thunderx2-linuxapp-gcc
> b/config/defconfig_arm64-thunderx2-linuxapp-gcc
> new file mode 100644
> index 000000000..27db58e50
> --- /dev/null
> +++ b/config/defconfig_arm64-thunderx2-linuxapp-gcc
> @@ -0,0 +1,11 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(c) 2018 Marvell International Ltd
> +#
> +
> +#include "defconfig_arm64-armv8a-linuxapp-gcc"
> +
> +CONFIG_RTE_MACHINE="thunderx2"
> +
> +CONFIG_RTE_CACHE_LINE_SIZE=64

ThunderX is 128, ThunderX2 downsized the cache line? 

> +CONFIG_RTE_MAX_NUMA_NODES=2
> +CONFIG_RTE_MAX_LCORE=256
> diff --git a/mk/machine/thunderx2/rte.vars.mk
> b/mk/machine/thunderx2/rte.vars.mk
> new file mode 100644
> index 000000000..b80dc8680
> --- /dev/null
> +++ b/mk/machine/thunderx2/rte.vars.mk
> @@ -0,0 +1,34 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(c) 2018 Marvell International Ltd
> +#
> +
> +#
> +# machine:
> +#
> +#   - can define ARCH variable (overridden by cmdline value)
> +#   - can define CROSS variable (overridden by cmdline value)
> +#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
> +#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
> +#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
> +#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
> +#     overrides the one defined in arch.
> +#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
> +#     overrides the one defined in arch.
> +#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
> +#     overrides the one defined in arch.
> +#   - may override any previously defined variable
> +#
> +
> +# ARCH =
> +# CROSS =
> +# MACHINE_CFLAGS =
> +# MACHINE_LDFLAGS =
> +# MACHINE_ASFLAGS =
> +# CPU_CFLAGS =
> +# CPU_LDFLAGS =
> +# CPU_ASFLAGS =
> +
> +include $(RTE_SDK)/mk/rte.helper.mk
> +
> +MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.1-
> a+crc+crypto)
> +MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=thunderx2t99)
> --
> 2.20.1

Re: [dpdk-dev] [EXT] Re: [PATCH 2/3] config: add thunderx2 machine config

[Jerin Jacob Kollanukkaran]

On Sun, 2019-01-06 at 21:56 +0100, Thomas Monjalon wrote:
> Hi Jerin,

Hi Thomas,

> 06/01/2019 14:20, Jerin Jacob Kollanukkaran:
> > Optimized configuration for Marvell thunderx2 SoC.
> > 
> > Product details are here:
> > 
> > https://www.marvell.com/server-processors/thunderx2-arm-processors/
> > 
> > Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> > ---
> >  config/defconfig_arm64-thunderx2-linuxapp-gcc | 11 ++++++
> >  mk/machine/thunderx2/rte.vars.mk              | 34
> > +++++++++++++++++++
> 
> You should enable meson build at the same time.

OK. Will send the v2.


> 
> 
> 

Re: [dpdk-dev] [EXT] RE: [PATCH 2/3] config: add thunderx2 machine config

[Jerin Jacob Kollanukkaran]

On Mon, 2019-01-07 at 00:21 +0000, Gavin Hu (Arm Technology China)
wrote:
> > -----Original Message-----
> > From: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
> > Sent: Sunday, January 6, 2019 9:20 PM
> > To: thomas@monjalon.net
> > Cc: dev@dpdk.org; Gavin Hu (Arm Technology China) <Gavin.Hu@arm.com
> > >;
> > jerinj@marvell.com
> > Subject: [dpdk-dev] [PATCH 2/3] config: add thunderx2 machine
> > config
> > 
> > Optimized configuration for Marvell thunderx2 SoC.
> > 
> > Product details are here:
> > 
> > https://www.marvell.com/server-processors/thunderx2-arm-processors/
> > 
> > Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> > ---
> >  config/defconfig_arm64-thunderx2-linuxapp-gcc | 11 ++++++
> >  mk/machine/thunderx2/rte.vars.mk              | 34
> > +++++++++++++++++++
> >  2 files changed, 45 insertions(+)
> >  create mode 100644 config/defconfig_arm64-thunderx2-linuxapp-gcc
> >  create mode 100644 mk/machine/thunderx2/rte.vars.mk
> > 
> > diff --git a/config/defconfig_arm64-thunderx2-linuxapp-gcc
> > b/config/defconfig_arm64-thunderx2-linuxapp-gcc
> > new file mode 100644
> > index 000000000..27db58e50
> > --- /dev/null
> > +++ b/config/defconfig_arm64-thunderx2-linuxapp-gcc
> > @@ -0,0 +1,11 @@
> > +# SPDX-License-Identifier: BSD-3-Clause
> > +# Copyright(c) 2018 Marvell International Ltd
> > +#
> > +
> > +#include "defconfig_arm64-armv8a-linuxapp-gcc"
> > +
> > +CONFIG_RTE_MACHINE="thunderx2"
> > +
> > +CONFIG_RTE_CACHE_LINE_SIZE=64
> 
> ThunderX is 128, ThunderX2 downsized the cache line? 

Yes. Tunned for server work load.

[dpdk-dev] [PATCH v2 1/6] mk: introduce helper to check valid compiler argument

[Pavan Nikhilesh Bhagavatula]

From: Jerin Jacob Kollanukkaran <jerinj@marvell.com>

Introduce rte_cc_has_argument() Makefile helper to
check a given argument is support by the compiler.

Example Usage:

include $(RTE_SDK)/mk/rte.helper.mk
MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)

This would allow adding -mcpu=octeontx2 in MACHINE_CFLAGS
if it is only supported by the compiler. The use case for such
scheme is to enable the mcpu optimization if the compiler
supports else it needs to compile the source code without
any errors.

This patch also moves inclusion of toolchain's rte.vars.mk
to before the machine's rte.vars.mk inclusion to make
correct CC available for the cross compile case.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
---
 mk/rte.helper.mk              | 12 ++++++++++++
 mk/target/generic/rte.vars.mk | 22 +++++++++++-----------
 2 files changed, 23 insertions(+), 11 deletions(-)
 create mode 100644 mk/rte.helper.mk

diff --git a/mk/rte.helper.mk b/mk/rte.helper.mk
new file mode 100644
index 000000000..2c5d5275e
--- /dev/null
+++ b/mk/rte.helper.mk
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+
+# rte_cc_has_argument
+# Usage: MACHINE_CFLAGS += $(call rte_cc_has_argument, -mno-avx512f)
+# Return the argument if the argument is supported by the compiler.
+#
+define rte_cc_has_argument
+	$(shell $(CC) -Werror $(1) -c -x c /dev/null -o tmp$$ 2> /dev/null && rm -f tmp$$ && echo $(1) | xargs echo -n)
+endef
+
+
diff --git a/mk/target/generic/rte.vars.mk b/mk/target/generic/rte.vars.mk
index dd149acc9..25a578ad7 100644
--- a/mk/target/generic/rte.vars.mk
+++ b/mk/target/generic/rte.vars.mk
@@ -7,6 +7,17 @@
 # executive environment.
 #
 
+#
+# toolchain:
+#
+#   - define CC, LD, AR, AS, ...
+#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
+#   - may override any previously defined variable
+#
+include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
+
 #
 # machine:
 #
@@ -45,17 +56,6 @@ endif
 #
 include $(RTE_SDK)/mk/arch/$(RTE_ARCH)/rte.vars.mk
 
-#
-# toolchain:
-#
-#   - define CC, LD, AR, AS, ...
-#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
-#   - may override any previously defined variable
-#
-include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
-
 #
 # exec-env:
 #
-- 
2.20.1

[dpdk-dev] [PATCH v2 2/6] config: add thunderx2 machine config

[Pavan Nikhilesh Bhagavatula]

From: Jerin Jacob Kollanukkaran <jerinj@marvell.com>

Optimized configuration for Marvell thunderx2 SoC.

Product details are here:

https://www.marvell.com/server-processors/thunderx2-arm-processors/

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
---
 config/defconfig_arm64-thunderx2-linuxapp-gcc | 11 ++++++
 mk/machine/thunderx2/rte.vars.mk              | 34 +++++++++++++++++++
 2 files changed, 45 insertions(+)
 create mode 100644 config/defconfig_arm64-thunderx2-linuxapp-gcc
 create mode 100644 mk/machine/thunderx2/rte.vars.mk

diff --git a/config/defconfig_arm64-thunderx2-linuxapp-gcc b/config/defconfig_arm64-thunderx2-linuxapp-gcc
new file mode 100644
index 000000000..27db58e50
--- /dev/null
+++ b/config/defconfig_arm64-thunderx2-linuxapp-gcc
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linuxapp-gcc"
+
+CONFIG_RTE_MACHINE="thunderx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=64
+CONFIG_RTE_MAX_NUMA_NODES=2
+CONFIG_RTE_MAX_LCORE=256
diff --git a/mk/machine/thunderx2/rte.vars.mk b/mk/machine/thunderx2/rte.vars.mk
new file mode 100644
index 000000000..b80dc8680
--- /dev/null
+++ b/mk/machine/thunderx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.1-a+crc+crypto)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=thunderx2t99)
-- 
2.20.1

[dpdk-dev] [PATCH v2 3/6] config: add octeontx2 machine config

[Pavan Nikhilesh Bhagavatula]

From: Jerin Jacob Kollanukkaran <jerinj@marvell.com>

Optimized configuration for Marvell octeontx2 SoC.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
---
 config/defconfig_arm64-octeontx2-linuxapp-gcc | 18 ++++++++++
 mk/machine/octeontx2/rte.vars.mk              | 34 +++++++++++++++++++
 2 files changed, 52 insertions(+)
 create mode 100644 config/defconfig_arm64-octeontx2-linuxapp-gcc
 create mode 100644 mk/machine/octeontx2/rte.vars.mk

diff --git a/config/defconfig_arm64-octeontx2-linuxapp-gcc b/config/defconfig_arm64-octeontx2-linuxapp-gcc
new file mode 100644
index 000000000..9a99eada1
--- /dev/null
+++ b/config/defconfig_arm64-octeontx2-linuxapp-gcc
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linuxapp-gcc"
+
+CONFIG_RTE_MACHINE="octeontx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=128
+CONFIG_RTE_MAX_NUMA_NODES=1
+CONFIG_RTE_MAX_LCORE=24
+
+# Doesn't support NUMA
+CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
+CONFIG_RTE_LIBRTE_VHOST_NUMA=n
+
+# Recommend to use VFIO as co-processors needs SMMU/IOMMU
+CONFIG_RTE_EAL_IGB_UIO=n
diff --git a/mk/machine/octeontx2/rte.vars.mk b/mk/machine/octeontx2/rte.vars.mk
new file mode 100644
index 000000000..e209cf492
--- /dev/null
+++ b/mk/machine/octeontx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.2-a+crc+crypto+lse)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)
-- 
2.20.1

[dpdk-dev] [PATCH v2 4/6] meson: add infra to support machine specific flags

[Pavan Nikhilesh Bhagavatula]

From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Currently, RTE_* flags are set based on the implementer ID but there might
be some micro arch specific differences from the same vendor
eg. CACHE_LINESIZE.
Add support to set micro arch specific flags.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
 config/arm/meson.build | 53 +++++++++++++++++++++++++-----------------
 1 file changed, 32 insertions(+), 21 deletions(-)

diff --git a/config/arm/meson.build b/config/arm/meson.build
index dae55d6b2..576363fc0 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -7,23 +7,6 @@ march_opt = '-march=@0@'.format(machine)
 
 arm_force_native_march = false
 
-machine_args_generic = [
-	['default', ['-march=armv8-a+crc+crypto']],
-	['native', ['-march=native']],
-	['0xd03', ['-mcpu=cortex-a53']],
-	['0xd04', ['-mcpu=cortex-a35']],
-	['0xd07', ['-mcpu=cortex-a57']],
-	['0xd08', ['-mcpu=cortex-a72']],
-	['0xd09', ['-mcpu=cortex-a73']],
-	['0xd0a', ['-mcpu=cortex-a75']],
-]
-machine_args_cavium = [
-	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
-	['native', ['-march=native']],
-	['0xa1', ['-mcpu=thunderxt88']],
-	['0xa2', ['-mcpu=thunderxt81']],
-	['0xa3', ['-mcpu=thunderxt83']]]
-
 flags_common_default = [
 	# Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
 	# to determine the best threshold in code. Refer to notes in source file
@@ -50,12 +33,10 @@ flags_generic = [
 	['RTE_USE_C11_MEM_MODEL', true],
 	['RTE_CACHE_LINE_SIZE', 128]]
 flags_cavium = [
-	['RTE_MACHINE', '"thunderx"'],
 	['RTE_CACHE_LINE_SIZE', 128],
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 96],
-	['RTE_MAX_VFIO_GROUPS', 128],
-	['RTE_USE_C11_MEM_MODEL', false]]
+	['RTE_MAX_VFIO_GROUPS', 128]]
 flags_dpaa = [
 	['RTE_MACHINE', '"dpaa"'],
 	['RTE_USE_C11_MEM_MODEL', true],
@@ -69,6 +50,27 @@ flags_dpaa2 = [
 	['RTE_MAX_NUMA_NODES', 1],
 	['RTE_MAX_LCORE', 16],
 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
+flags_default_extra = []
+flags_thunderx_extra = [
+	['RTE_MACHINE', '"thunderx"'],
+	['RTE_USE_C11_MEM_MODEL', false]]
+
+machine_args_generic = [
+	['default', ['-march=armv8-a+crc+crypto']],
+	['native', ['-march=native']],
+	['0xd03', ['-mcpu=cortex-a53']],
+	['0xd04', ['-mcpu=cortex-a35']],
+	['0xd07', ['-mcpu=cortex-a57']],
+	['0xd08', ['-mcpu=cortex-a72']],
+	['0xd09', ['-mcpu=cortex-a73']],
+	['0xd0a', ['-mcpu=cortex-a75']]]
+
+machine_args_cavium = [
+	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
+	['native', ['-march=native']],
+	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
+	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
@@ -157,10 +159,19 @@ else
 	foreach marg: machine[2]
 		if marg[0] == impl_pn
 			foreach f: marg[1]
-				machine_args += f
+				if cc.has_argument(f)
+					machine_args += f
+				endif
 			endforeach
 		endif
 	endforeach
+
+	# Apply any extra machine specific flags.
+	foreach flag: marg.get(2, flags_default_extra)
+		if flag.length() > 0
+			dpdk_conf.set(flag[0], flag[1])
+		endif
+	endforeach
 endif
 message(machine_args)
 
-- 
2.20.1

[dpdk-dev] [PATCH v2 5/6] meson: add thunderx2 machine config

[Pavan Nikhilesh Bhagavatula]

From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Meson configuration for Marvell thunderx2 SoC.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
 config/arm/meson.build | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 576363fc0..aca285b6a 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -54,6 +54,12 @@ flags_default_extra = []
 flags_thunderx_extra = [
 	['RTE_MACHINE', '"thunderx"'],
 	['RTE_USE_C11_MEM_MODEL', false]]
+flags_thunderx2_extra = [
+	['RTE_MACHINE', '"thunderx2"'],
+	['RTE_CACHE_LINE_SIZE', 64],
+	['RTE_MAX_NUMA_NODES', 2],
+	['RTE_MAX_LCORE', 256],
+	['RTE_USE_C11_MEM_MODEL', true]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -70,7 +76,8 @@ machine_args_cavium = [
 	['native', ['-march=native']],
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
-	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
-- 
2.20.1

[dpdk-dev] [PATCH v2 6/6] meson: add octeontx2 machine config

[Pavan Nikhilesh Bhagavatula]

From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Meson configuration for Marvell octeontx2 SoC.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
 config/arm/meson.build | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/config/arm/meson.build b/config/arm/meson.build
index aca285b6a..8086357a1 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -60,6 +60,13 @@ flags_thunderx2_extra = [
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 256],
 	['RTE_USE_C11_MEM_MODEL', true]]
+flags_octeontx2_extra = [
+	['RTE_MACHINE', '"octeontx2"'],
+	['RTE_MAX_NUMA_NODES', 1],
+	['RTE_MAX_LCORE', 24],
+	['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
+	['RTE_LIBRTE_VHOST_NUMA', false],
+	['RTE_EAL_IGB_UIO', false]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -77,7 +84,8 @@ machine_args_cavium = [
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
 	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
-	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra],
+	['0xb2', ['-mcpu=octeontx2'], flags_octeontx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
-- 
2.20.1

Re: [dpdk-dev] [PATCH v2 5/6] meson: add thunderx2 machine config

[Thomas Monjalon]

07/01/2019 16:42, Pavan Nikhilesh Bhagavatula:
> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> 
> Meson configuration for Marvell thunderx2 SoC.
> 
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> ---
>  config/arm/meson.build | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)

I think it can be merged with the patch doing the same for make.

[dpdk-dev] [PATCH v3 1/4] mk: introduce helper to check valid compiler argument

[Pavan Nikhilesh Bhagavatula]

From: Jerin Jacob <jerinj@marvell.com>

Introduce rte_cc_has_argument() Makefile helper to
check a given argument is support by the compiler.

Example Usage:

include $(RTE_SDK)/mk/rte.helper.mk
MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)

This would allow adding -mcpu=octeontx2 in MACHINE_CFLAGS
if it is only supported by the compiler. The use case for such
scheme is to enable the mcpu optimization if the compiler
supports else it needs to compile the source code without
any errors.

This patch also moves inclusion of toolchain's rte.vars.mk
to before the machine's rte.vars.mk inclusion to make
correct CC available for the cross compile case.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marrvell.com>
---
 mk/rte.helper.mk              | 12 ++++++++++++
 mk/target/generic/rte.vars.mk | 22 +++++++++++-----------
 2 files changed, 23 insertions(+), 11 deletions(-)
 create mode 100644 mk/rte.helper.mk

diff --git a/mk/rte.helper.mk b/mk/rte.helper.mk
new file mode 100644
index 000000000..2c5d5275e
--- /dev/null
+++ b/mk/rte.helper.mk
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+
+# rte_cc_has_argument
+# Usage: MACHINE_CFLAGS += $(call rte_cc_has_argument, -mno-avx512f)
+# Return the argument if the argument is supported by the compiler.
+#
+define rte_cc_has_argument
+	$(shell $(CC) -Werror $(1) -c -x c /dev/null -o tmp$$ 2> /dev/null && rm -f tmp$$ && echo $(1) | xargs echo -n)
+endef
+
+
diff --git a/mk/target/generic/rte.vars.mk b/mk/target/generic/rte.vars.mk
index dd149acc9..25a578ad7 100644
--- a/mk/target/generic/rte.vars.mk
+++ b/mk/target/generic/rte.vars.mk
@@ -7,6 +7,17 @@
 # executive environment.
 #
 
+#
+# toolchain:
+#
+#   - define CC, LD, AR, AS, ...
+#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
+#   - may override any previously defined variable
+#
+include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
+
 #
 # machine:
 #
@@ -45,17 +56,6 @@ endif
 #
 include $(RTE_SDK)/mk/arch/$(RTE_ARCH)/rte.vars.mk
 
-#
-# toolchain:
-#
-#   - define CC, LD, AR, AS, ...
-#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
-#   - may override any previously defined variable
-#
-include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
-
 #
 # exec-env:
 #
-- 
2.20.1

[dpdk-dev] [PATCH v3 2/4] meson: add infra to support machine specific flags

[Pavan Nikhilesh Bhagavatula]

From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Currently, RTE_* flags are set based on the implementer ID but there might
be some micro arch specific differences from the same vendor
eg. CACHE_LINESIZE.
Add support to set micro arch specific flags.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
 v2 Changes:
 - Add meson build support.

 config/arm/meson.build | 53 +++++++++++++++++++++++++-----------------
 1 file changed, 32 insertions(+), 21 deletions(-)

diff --git a/config/arm/meson.build b/config/arm/meson.build
index dae55d6b2..576363fc0 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -7,23 +7,6 @@ march_opt = '-march=@0@'.format(machine)

 arm_force_native_march = false

-machine_args_generic = [
-	['default', ['-march=armv8-a+crc+crypto']],
-	['native', ['-march=native']],
-	['0xd03', ['-mcpu=cortex-a53']],
-	['0xd04', ['-mcpu=cortex-a35']],
-	['0xd07', ['-mcpu=cortex-a57']],
-	['0xd08', ['-mcpu=cortex-a72']],
-	['0xd09', ['-mcpu=cortex-a73']],
-	['0xd0a', ['-mcpu=cortex-a75']],
-]
-machine_args_cavium = [
-	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
-	['native', ['-march=native']],
-	['0xa1', ['-mcpu=thunderxt88']],
-	['0xa2', ['-mcpu=thunderxt81']],
-	['0xa3', ['-mcpu=thunderxt83']]]
-
 flags_common_default = [
 	# Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
 	# to determine the best threshold in code. Refer to notes in source file
@@ -50,12 +33,10 @@ flags_generic = [
 	['RTE_USE_C11_MEM_MODEL', true],
 	['RTE_CACHE_LINE_SIZE', 128]]
 flags_cavium = [
-	['RTE_MACHINE', '"thunderx"'],
 	['RTE_CACHE_LINE_SIZE', 128],
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 96],
-	['RTE_MAX_VFIO_GROUPS', 128],
-	['RTE_USE_C11_MEM_MODEL', false]]
+	['RTE_MAX_VFIO_GROUPS', 128]]
 flags_dpaa = [
 	['RTE_MACHINE', '"dpaa"'],
 	['RTE_USE_C11_MEM_MODEL', true],
@@ -69,6 +50,27 @@ flags_dpaa2 = [
 	['RTE_MAX_NUMA_NODES', 1],
 	['RTE_MAX_LCORE', 16],
 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
+flags_default_extra = []
+flags_thunderx_extra = [
+	['RTE_MACHINE', '"thunderx"'],
+	['RTE_USE_C11_MEM_MODEL', false]]
+
+machine_args_generic = [
+	['default', ['-march=armv8-a+crc+crypto']],
+	['native', ['-march=native']],
+	['0xd03', ['-mcpu=cortex-a53']],
+	['0xd04', ['-mcpu=cortex-a35']],
+	['0xd07', ['-mcpu=cortex-a57']],
+	['0xd08', ['-mcpu=cortex-a72']],
+	['0xd09', ['-mcpu=cortex-a73']],
+	['0xd0a', ['-mcpu=cortex-a75']]]
+
+machine_args_cavium = [
+	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
+	['native', ['-march=native']],
+	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
+	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]

 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
@@ -157,10 +159,19 @@ else
 	foreach marg: machine[2]
 		if marg[0] == impl_pn
 			foreach f: marg[1]
-				machine_args += f
+				if cc.has_argument(f)
+					machine_args += f
+				endif
 			endforeach
 		endif
 	endforeach
+
+	# Apply any extra machine specific flags.
+	foreach flag: marg.get(2, flags_default_extra)
+		if flag.length() > 0
+			dpdk_conf.set(flag[0], flag[1])
+		endif
+	endforeach
 endif
 message(machine_args)

--
2.20.1

[dpdk-dev] [PATCH v3 3/4] config: add thunderx2 machine config

[Pavan Nikhilesh Bhagavatula]

From: Jerin Jacob <jerinj@marvell.com>

Optimized configuration for Marvell thunderx2 SoC. Update meson build to
support Marvell thunderx2 SoC.

Product details are here:

https://www.marvell.com/server-processors/thunderx2-arm-processors/

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marrvell.com>
---
 v3 Changes:
 - Squash meson build support into config support for thunderx2/octeontx2.

 config/arm/meson.build                        |  9 ++++-
 config/defconfig_arm64-thunderx2-linuxapp-gcc | 11 ++++++
 mk/machine/thunderx2/rte.vars.mk              | 34 +++++++++++++++++++
 3 files changed, 53 insertions(+), 1 deletion(-)
 create mode 100644 config/defconfig_arm64-thunderx2-linuxapp-gcc
 create mode 100644 mk/machine/thunderx2/rte.vars.mk

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 576363fc0..aca285b6a 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -54,6 +54,12 @@ flags_default_extra = []
 flags_thunderx_extra = [
 	['RTE_MACHINE', '"thunderx"'],
 	['RTE_USE_C11_MEM_MODEL', false]]
+flags_thunderx2_extra = [
+	['RTE_MACHINE', '"thunderx2"'],
+	['RTE_CACHE_LINE_SIZE', 64],
+	['RTE_MAX_NUMA_NODES', 2],
+	['RTE_MAX_LCORE', 256],
+	['RTE_USE_C11_MEM_MODEL', true]]

 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -70,7 +76,8 @@ machine_args_cavium = [
 	['native', ['-march=native']],
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
-	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]

 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-thunderx2-linuxapp-gcc b/config/defconfig_arm64-thunderx2-linuxapp-gcc
new file mode 100644
index 000000000..27db58e50
--- /dev/null
+++ b/config/defconfig_arm64-thunderx2-linuxapp-gcc
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linuxapp-gcc"
+
+CONFIG_RTE_MACHINE="thunderx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=64
+CONFIG_RTE_MAX_NUMA_NODES=2
+CONFIG_RTE_MAX_LCORE=256
diff --git a/mk/machine/thunderx2/rte.vars.mk b/mk/machine/thunderx2/rte.vars.mk
new file mode 100644
index 000000000..b80dc8680
--- /dev/null
+++ b/mk/machine/thunderx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.1-a+crc+crypto)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=thunderx2t99)
--
2.20.1

[dpdk-dev] [PATCH v3 4/4] config: add octeontx2 machine config

[Pavan Nikhilesh Bhagavatula]

From: Jerin Jacob <jerinj@marvell.com>

Optimized configuration for Marvell octeontx2 SoC. Update meson build to
support Marvell octeontx2 SoC.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marrvell.com>
---
 config/arm/meson.build                        | 10 +++++-
 config/defconfig_arm64-octeontx2-linuxapp-gcc | 18 ++++++++++
 mk/machine/octeontx2/rte.vars.mk              | 34 +++++++++++++++++++
 3 files changed, 61 insertions(+), 1 deletion(-)
 create mode 100644 config/defconfig_arm64-octeontx2-linuxapp-gcc
 create mode 100644 mk/machine/octeontx2/rte.vars.mk

diff --git a/config/arm/meson.build b/config/arm/meson.build
index aca285b6a..8086357a1 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -60,6 +60,13 @@ flags_thunderx2_extra = [
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 256],
 	['RTE_USE_C11_MEM_MODEL', true]]
+flags_octeontx2_extra = [
+	['RTE_MACHINE', '"octeontx2"'],
+	['RTE_MAX_NUMA_NODES', 1],
+	['RTE_MAX_LCORE', 24],
+	['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
+	['RTE_LIBRTE_VHOST_NUMA', false],
+	['RTE_EAL_IGB_UIO', false]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -77,7 +84,8 @@ machine_args_cavium = [
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
 	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
-	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra],
+	['0xb2', ['-mcpu=octeontx2'], flags_octeontx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-octeontx2-linuxapp-gcc b/config/defconfig_arm64-octeontx2-linuxapp-gcc
new file mode 100644
index 000000000..9a99eada1
--- /dev/null
+++ b/config/defconfig_arm64-octeontx2-linuxapp-gcc
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linuxapp-gcc"
+
+CONFIG_RTE_MACHINE="octeontx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=128
+CONFIG_RTE_MAX_NUMA_NODES=1
+CONFIG_RTE_MAX_LCORE=24
+
+# Doesn't support NUMA
+CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
+CONFIG_RTE_LIBRTE_VHOST_NUMA=n
+
+# Recommend to use VFIO as co-processors needs SMMU/IOMMU
+CONFIG_RTE_EAL_IGB_UIO=n
diff --git a/mk/machine/octeontx2/rte.vars.mk b/mk/machine/octeontx2/rte.vars.mk
new file mode 100644
index 000000000..e209cf492
--- /dev/null
+++ b/mk/machine/octeontx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.2-a+crc+crypto+lse)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)
-- 
2.20.1

[dpdk-dev] [PATCH v3 5/5] meson: add cross build targets for thunderx2 and octeontx2

[Pavan Nikhilesh Bhagavatula]

From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Add Thunderx2 and Octeontx2 SoC cross build targets.
meson build --cross-file config/arm/arm64_<cpu>_<platform>_<compiler>

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
 config/arm/arm64_octeontx2_linuxapp_gcc | 14 ++++++++++++++
 config/arm/arm64_thunderx2_linuxapp_gcc | 14 ++++++++++++++
 2 files changed, 28 insertions(+)
 create mode 100644 config/arm/arm64_octeontx2_linuxapp_gcc
 create mode 100644 config/arm/arm64_thunderx2_linuxapp_gcc

diff --git a/config/arm/arm64_octeontx2_linuxapp_gcc b/config/arm/arm64_octeontx2_linuxapp_gcc
new file mode 100644
index 000000000..83e28e817
--- /dev/null
+++ b/config/arm/arm64_octeontx2_linuxapp_gcc
@@ -0,0 +1,14 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0xb2'
diff --git a/config/arm/arm64_thunderx2_linuxapp_gcc b/config/arm/arm64_thunderx2_linuxapp_gcc
new file mode 100644
index 000000000..de1146639
--- /dev/null
+++ b/config/arm/arm64_thunderx2_linuxapp_gcc
@@ -0,0 +1,14 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0xaf'
--
2.20.1

[dpdk-dev] [PATCH v4 1/5] mk: introduce helper to check valid compiler argument

[Pavan Nikhilesh Bhagavatula]

From: Jerin Jacob <jerinj@marvell.com>

Introduce rte_cc_has_argument() Makefile helper to
check a given argument is support by the compiler.

Example Usage:

include $(RTE_SDK)/mk/rte.helper.mk
MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)

This would allow adding -mcpu=octeontx2 in MACHINE_CFLAGS
if it is only supported by the compiler. The use case for such
scheme is to enable the mcpu optimization if the compiler
supports else it needs to compile the source code without
any errors.

This patch also moves inclusion of toolchain's rte.vars.mk
to before the machine's rte.vars.mk inclusion to make
correct CC available for the cross compile case.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---

 v2 Changes:
 - Add meson build support.

 v3 Changes:
 - Squash meson build support into config support for thunderx2/octeontx2.

 v4 Changes:
 - Fix incorrect signoff marrvell -> marvell.

 mk/rte.helper.mk              | 12 ++++++++++++
 mk/target/generic/rte.vars.mk | 22 +++++++++++-----------
 2 files changed, 23 insertions(+), 11 deletions(-)
 create mode 100644 mk/rte.helper.mk

diff --git a/mk/rte.helper.mk b/mk/rte.helper.mk
new file mode 100644
index 000000000..2c5d5275e
--- /dev/null
+++ b/mk/rte.helper.mk
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+
+# rte_cc_has_argument
+# Usage: MACHINE_CFLAGS += $(call rte_cc_has_argument, -mno-avx512f)
+# Return the argument if the argument is supported by the compiler.
+#
+define rte_cc_has_argument
+	$(shell $(CC) -Werror $(1) -c -x c /dev/null -o tmp$$ 2> /dev/null && rm -f tmp$$ && echo $(1) | xargs echo -n)
+endef
+
+
diff --git a/mk/target/generic/rte.vars.mk b/mk/target/generic/rte.vars.mk
index dd149acc9..25a578ad7 100644
--- a/mk/target/generic/rte.vars.mk
+++ b/mk/target/generic/rte.vars.mk
@@ -7,6 +7,17 @@
 # executive environment.
 #

+#
+# toolchain:
+#
+#   - define CC, LD, AR, AS, ...
+#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
+#   - may override any previously defined variable
+#
+include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
+
 #
 # machine:
 #
@@ -45,17 +56,6 @@ endif
 #
 include $(RTE_SDK)/mk/arch/$(RTE_ARCH)/rte.vars.mk

-#
-# toolchain:
-#
-#   - define CC, LD, AR, AS, ...
-#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
-#   - may override any previously defined variable
-#
-include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
-
 #
 # exec-env:
 #
--
2.20.1

[dpdk-dev] [PATCH v4 2/5] meson: add infra to support machine specific flags

[Pavan Nikhilesh Bhagavatula]

From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Currently, RTE_* flags are set based on the implementer ID but there might
be some micro arch specific differences from the same vendor
eg. CACHE_LINESIZE.
Add support to set micro arch specific flags.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
 config/arm/meson.build | 53 +++++++++++++++++++++++++-----------------
 1 file changed, 32 insertions(+), 21 deletions(-)

diff --git a/config/arm/meson.build b/config/arm/meson.build
index dae55d6b2..576363fc0 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -7,23 +7,6 @@ march_opt = '-march=@0@'.format(machine)
 
 arm_force_native_march = false
 
-machine_args_generic = [
-	['default', ['-march=armv8-a+crc+crypto']],
-	['native', ['-march=native']],
-	['0xd03', ['-mcpu=cortex-a53']],
-	['0xd04', ['-mcpu=cortex-a35']],
-	['0xd07', ['-mcpu=cortex-a57']],
-	['0xd08', ['-mcpu=cortex-a72']],
-	['0xd09', ['-mcpu=cortex-a73']],
-	['0xd0a', ['-mcpu=cortex-a75']],
-]
-machine_args_cavium = [
-	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
-	['native', ['-march=native']],
-	['0xa1', ['-mcpu=thunderxt88']],
-	['0xa2', ['-mcpu=thunderxt81']],
-	['0xa3', ['-mcpu=thunderxt83']]]
-
 flags_common_default = [
 	# Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
 	# to determine the best threshold in code. Refer to notes in source file
@@ -50,12 +33,10 @@ flags_generic = [
 	['RTE_USE_C11_MEM_MODEL', true],
 	['RTE_CACHE_LINE_SIZE', 128]]
 flags_cavium = [
-	['RTE_MACHINE', '"thunderx"'],
 	['RTE_CACHE_LINE_SIZE', 128],
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 96],
-	['RTE_MAX_VFIO_GROUPS', 128],
-	['RTE_USE_C11_MEM_MODEL', false]]
+	['RTE_MAX_VFIO_GROUPS', 128]]
 flags_dpaa = [
 	['RTE_MACHINE', '"dpaa"'],
 	['RTE_USE_C11_MEM_MODEL', true],
@@ -69,6 +50,27 @@ flags_dpaa2 = [
 	['RTE_MAX_NUMA_NODES', 1],
 	['RTE_MAX_LCORE', 16],
 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
+flags_default_extra = []
+flags_thunderx_extra = [
+	['RTE_MACHINE', '"thunderx"'],
+	['RTE_USE_C11_MEM_MODEL', false]]
+
+machine_args_generic = [
+	['default', ['-march=armv8-a+crc+crypto']],
+	['native', ['-march=native']],
+	['0xd03', ['-mcpu=cortex-a53']],
+	['0xd04', ['-mcpu=cortex-a35']],
+	['0xd07', ['-mcpu=cortex-a57']],
+	['0xd08', ['-mcpu=cortex-a72']],
+	['0xd09', ['-mcpu=cortex-a73']],
+	['0xd0a', ['-mcpu=cortex-a75']]]
+
+machine_args_cavium = [
+	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
+	['native', ['-march=native']],
+	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
+	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
@@ -157,10 +159,19 @@ else
 	foreach marg: machine[2]
 		if marg[0] == impl_pn
 			foreach f: marg[1]
-				machine_args += f
+				if cc.has_argument(f)
+					machine_args += f
+				endif
 			endforeach
 		endif
 	endforeach
+
+	# Apply any extra machine specific flags.
+	foreach flag: marg.get(2, flags_default_extra)
+		if flag.length() > 0
+			dpdk_conf.set(flag[0], flag[1])
+		endif
+	endforeach
 endif
 message(machine_args)
 
-- 
2.20.1

[dpdk-dev] [PATCH v4 3/5] config: add thunderx2 machine config

[Pavan Nikhilesh Bhagavatula]

From: Jerin Jacob <jerinj@marvell.com>

Optimized configuration for Marvell thunderx2 SoC. Update meson build to
support Marvell thunderx2 SoC.

Product details are here:

https://www.marvell.com/server-processors/thunderx2-arm-processors/

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
 config/arm/meson.build                        |  9 ++++-
 config/defconfig_arm64-thunderx2-linuxapp-gcc | 11 ++++++
 mk/machine/thunderx2/rte.vars.mk              | 34 +++++++++++++++++++
 3 files changed, 53 insertions(+), 1 deletion(-)
 create mode 100644 config/defconfig_arm64-thunderx2-linuxapp-gcc
 create mode 100644 mk/machine/thunderx2/rte.vars.mk

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 576363fc0..aca285b6a 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -54,6 +54,12 @@ flags_default_extra = []
 flags_thunderx_extra = [
 	['RTE_MACHINE', '"thunderx"'],
 	['RTE_USE_C11_MEM_MODEL', false]]
+flags_thunderx2_extra = [
+	['RTE_MACHINE', '"thunderx2"'],
+	['RTE_CACHE_LINE_SIZE', 64],
+	['RTE_MAX_NUMA_NODES', 2],
+	['RTE_MAX_LCORE', 256],
+	['RTE_USE_C11_MEM_MODEL', true]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -70,7 +76,8 @@ machine_args_cavium = [
 	['native', ['-march=native']],
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
-	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-thunderx2-linuxapp-gcc b/config/defconfig_arm64-thunderx2-linuxapp-gcc
new file mode 100644
index 000000000..27db58e50
--- /dev/null
+++ b/config/defconfig_arm64-thunderx2-linuxapp-gcc
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linuxapp-gcc"
+
+CONFIG_RTE_MACHINE="thunderx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=64
+CONFIG_RTE_MAX_NUMA_NODES=2
+CONFIG_RTE_MAX_LCORE=256
diff --git a/mk/machine/thunderx2/rte.vars.mk b/mk/machine/thunderx2/rte.vars.mk
new file mode 100644
index 000000000..b80dc8680
--- /dev/null
+++ b/mk/machine/thunderx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.1-a+crc+crypto)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=thunderx2t99)
-- 
2.20.1

[dpdk-dev] [PATCH v4 4/5] config: add octeontx2 machine config

[Pavan Nikhilesh Bhagavatula]

From: Jerin Jacob <jerinj@marvell.com>

Optimized configuration for Marvell octeontx2 SoC. Update meson build to
support Marvell octeontx2 SoC.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
 config/arm/meson.build                        | 10 +++++-
 config/defconfig_arm64-octeontx2-linuxapp-gcc | 18 ++++++++++
 mk/machine/octeontx2/rte.vars.mk              | 34 +++++++++++++++++++
 3 files changed, 61 insertions(+), 1 deletion(-)
 create mode 100644 config/defconfig_arm64-octeontx2-linuxapp-gcc
 create mode 100644 mk/machine/octeontx2/rte.vars.mk

diff --git a/config/arm/meson.build b/config/arm/meson.build
index aca285b6a..8086357a1 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -60,6 +60,13 @@ flags_thunderx2_extra = [
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 256],
 	['RTE_USE_C11_MEM_MODEL', true]]
+flags_octeontx2_extra = [
+	['RTE_MACHINE', '"octeontx2"'],
+	['RTE_MAX_NUMA_NODES', 1],
+	['RTE_MAX_LCORE', 24],
+	['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
+	['RTE_LIBRTE_VHOST_NUMA', false],
+	['RTE_EAL_IGB_UIO', false]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -77,7 +84,8 @@ machine_args_cavium = [
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
 	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
-	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra],
+	['0xb2', ['-mcpu=octeontx2'], flags_octeontx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-octeontx2-linuxapp-gcc b/config/defconfig_arm64-octeontx2-linuxapp-gcc
new file mode 100644
index 000000000..9a99eada1
--- /dev/null
+++ b/config/defconfig_arm64-octeontx2-linuxapp-gcc
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linuxapp-gcc"
+
+CONFIG_RTE_MACHINE="octeontx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=128
+CONFIG_RTE_MAX_NUMA_NODES=1
+CONFIG_RTE_MAX_LCORE=24
+
+# Doesn't support NUMA
+CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
+CONFIG_RTE_LIBRTE_VHOST_NUMA=n
+
+# Recommend to use VFIO as co-processors needs SMMU/IOMMU
+CONFIG_RTE_EAL_IGB_UIO=n
diff --git a/mk/machine/octeontx2/rte.vars.mk b/mk/machine/octeontx2/rte.vars.mk
new file mode 100644
index 000000000..e209cf492
--- /dev/null
+++ b/mk/machine/octeontx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.2-a+crc+crypto+lse)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)
-- 
2.20.1

[dpdk-dev] [PATCH v4 5/5] meson: add cross build targets for thunderx2 and octeontx2

[Pavan Nikhilesh Bhagavatula]

From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Add Thunderx2 and Octeontx2 SoC cross build targets.
meson build --cross-file config/arm/arm64_<cpu>_<platform>_<compiler>

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
 config/arm/arm64_octeontx2_linuxapp_gcc | 14 ++++++++++++++
 config/arm/arm64_thunderx2_linuxapp_gcc | 14 ++++++++++++++
 2 files changed, 28 insertions(+)
 create mode 100644 config/arm/arm64_octeontx2_linuxapp_gcc
 create mode 100644 config/arm/arm64_thunderx2_linuxapp_gcc

diff --git a/config/arm/arm64_octeontx2_linuxapp_gcc b/config/arm/arm64_octeontx2_linuxapp_gcc
new file mode 100644
index 000000000..83e28e817
--- /dev/null
+++ b/config/arm/arm64_octeontx2_linuxapp_gcc
@@ -0,0 +1,14 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0xb2'
diff --git a/config/arm/arm64_thunderx2_linuxapp_gcc b/config/arm/arm64_thunderx2_linuxapp_gcc
new file mode 100644
index 000000000..de1146639
--- /dev/null
+++ b/config/arm/arm64_thunderx2_linuxapp_gcc
@@ -0,0 +1,14 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0xaf'
-- 
2.20.1

Re: [dpdk-dev] [PATCH v4 5/5] meson: add cross build targets for thunderx2 and octeontx2

[Thomas Monjalon]

09/01/2019 11:39, Pavan Nikhilesh Bhagavatula:
> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> 
> Add Thunderx2 and Octeontx2 SoC cross build targets.
> meson build --cross-file config/arm/arm64_<cpu>_<platform>_<compiler>
> 
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> ---
>  config/arm/arm64_octeontx2_linuxapp_gcc | 14 ++++++++++++++
>  config/arm/arm64_thunderx2_linuxapp_gcc | 14 ++++++++++++++
>  2 files changed, 28 insertions(+)

Don't you think it could be merged in patches 3 & 4
for more clarity?

Re: [dpdk-dev] [PATCH v4 2/5] meson: add infra to support machine specific flags

[Thomas Monjalon]

09/01/2019 11:39, Pavan Nikhilesh Bhagavatula:
> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> 
> Currently, RTE_* flags are set based on the implementer ID but there might
> be some micro arch specific differences from the same vendor
> eg. CACHE_LINESIZE.
> Add support to set micro arch specific flags.
> 
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> ---
>  flags_cavium = [
> -	['RTE_MACHINE', '"thunderx"'],
>  	['RTE_CACHE_LINE_SIZE', 128],
>  	['RTE_MAX_NUMA_NODES', 2],
>  	['RTE_MAX_LCORE', 96],
> -	['RTE_MAX_VFIO_GROUPS', 128],
> -	['RTE_USE_C11_MEM_MODEL', false]]
> +	['RTE_MAX_VFIO_GROUPS', 128]]
[...]
> +flags_thunderx_extra = [
> +	['RTE_MACHINE', '"thunderx"'],
> +	['RTE_USE_C11_MEM_MODEL', false]]
[..]
> +machine_args_cavium = [
> +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> +	['native', ['-march=native']],
> +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
> +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
> +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]

This patch is not only adding infra, it also change some Cavium config.
What about splitting, and explaining the change of RTE_USE_C11_MEM_MODEL?

Re: [dpdk-dev] [PATCH v4 1/5] mk: introduce helper to check valid compiler argument

[Thomas Monjalon]

09/01/2019 11:39, Pavan Nikhilesh Bhagavatula:
> From: Jerin Jacob <jerinj@marvell.com>
> 
> Introduce rte_cc_has_argument() Makefile helper to
> check a given argument is support by the compiler.
> 
> Example Usage:
> 
> include $(RTE_SDK)/mk/rte.helper.mk
> MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)
> 
> This would allow adding -mcpu=octeontx2 in MACHINE_CFLAGS
> if it is only supported by the compiler. The use case for such
> scheme is to enable the mcpu optimization if the compiler
> supports else it needs to compile the source code without
> any errors.
> 
> This patch also moves inclusion of toolchain's rte.vars.mk
> to before the machine's rte.vars.mk inclusion to make
> correct CC available for the cross compile case.
> 
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> ---
> --- /dev/null
> +++ b/mk/rte.helper.mk
> @@ -0,0 +1,12 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(c) 2018 Marvell International Ltd
> +
> +# rte_cc_has_argument
> +# Usage: MACHINE_CFLAGS += $(call rte_cc_has_argument, -mno-avx512f)
> +# Return the argument if the argument is supported by the compiler.
> +#
> +define rte_cc_has_argument
> +	$(shell $(CC) -Werror $(1) -c -x c /dev/null -o tmp$$ 2> /dev/null && rm -f tmp$$ && echo $(1) | xargs echo -n)
> +endef

What is tmp$$ ?

If the command is interrupted in the middle, temp file is not cleaned.
We could fix it with "trap".
Is it possible to just avoid creating a temporary file?

Re: [dpdk-dev] [EXT] Re: [PATCH v4 1/5] mk: introduce helper to check valid compiler argument

[Jerin Jacob Kollanukkaran]

On Mon, 2019-01-14 at 12:35 +0100, Thomas Monjalon wrote:
> -------------------------------------------------------------------
> ---
> 09/01/2019 11:39, Pavan Nikhilesh Bhagavatula:
> > From: Jerin Jacob <jerinj@marvell.com>
> > 
> > Introduce rte_cc_has_argument() Makefile helper to
> > check a given argument is support by the compiler.
> > 
> > Example Usage:
> > 
> > include $(RTE_SDK)/mk/rte.helper.mk
> > MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)
> > 
> > This would allow adding -mcpu=octeontx2 in MACHINE_CFLAGS
> > if it is only supported by the compiler. The use case for such
> > scheme is to enable the mcpu optimization if the compiler
> > supports else it needs to compile the source code without
> > any errors.
> > 
> > This patch also moves inclusion of toolchain's rte.vars.mk
> > to before the machine's rte.vars.mk inclusion to make
> > correct CC available for the cross compile case.
> > 
> > Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> > Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > ---
> > --- /dev/null
> > +++ b/mk/rte.helper.mk
> > @@ -0,0 +1,12 @@
> > +# SPDX-License-Identifier: BSD-3-Clause
> > +# Copyright(c) 2018 Marvell International Ltd
> > +
> > +# rte_cc_has_argument
> > +# Usage: MACHINE_CFLAGS += $(call rte_cc_has_argument, -mno-
> > avx512f)
> > +# Return the argument if the argument is supported by the
> > compiler.
> > +#
> > +define rte_cc_has_argument
> > +	$(shell $(CC) -Werror $(1) -c -x c /dev/null -o tmp$$ 2>
> > /dev/null && rm -f tmp$$ && echo $(1) | xargs echo -n)
> > +endef
> 
> What is tmp$$ ?

It is created per process with pid value.

> 
> If the command is interrupted in the middle, temp file is not
> cleaned.

Yes. I think we can move to RTE_OUTPUT. Even it is not cleaned 
then it is file, I think, that would be easiest solution.

> We could fix it with "trap".

Can we do it in Makefile? 

> Is it possible to just avoid creating a temporary file?

I tried it but gcc creates one.

> 
> 
> 

Re: [dpdk-dev] [EXT] Re: [PATCH v4 1/5] mk: introduce helper to check valid compiler argument

[Thomas Monjalon]

14/01/2019 12:56, Jerin Jacob Kollanukkaran:
> On Mon, 2019-01-14 at 12:35 +0100, Thomas Monjalon wrote:
> > -------------------------------------------------------------------
> > ---
> > 09/01/2019 11:39, Pavan Nikhilesh Bhagavatula:
> > > From: Jerin Jacob <jerinj@marvell.com>
> > > 
> > > Introduce rte_cc_has_argument() Makefile helper to
> > > check a given argument is support by the compiler.
> > > 
> > > Example Usage:
> > > 
> > > include $(RTE_SDK)/mk/rte.helper.mk
> > > MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)
> > > 
> > > This would allow adding -mcpu=octeontx2 in MACHINE_CFLAGS
> > > if it is only supported by the compiler. The use case for such
> > > scheme is to enable the mcpu optimization if the compiler
> > > supports else it needs to compile the source code without
> > > any errors.
> > > 
> > > This patch also moves inclusion of toolchain's rte.vars.mk
> > > to before the machine's rte.vars.mk inclusion to make
> > > correct CC available for the cross compile case.
> > > 
> > > Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> > > Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > > ---
> > > --- /dev/null
> > > +++ b/mk/rte.helper.mk
> > > @@ -0,0 +1,12 @@
> > > +# SPDX-License-Identifier: BSD-3-Clause
> > > +# Copyright(c) 2018 Marvell International Ltd
> > > +
> > > +# rte_cc_has_argument
> > > +# Usage: MACHINE_CFLAGS += $(call rte_cc_has_argument, -mno-
> > > avx512f)
> > > +# Return the argument if the argument is supported by the
> > > compiler.
> > > +#
> > > +define rte_cc_has_argument
> > > +	$(shell $(CC) -Werror $(1) -c -x c /dev/null -o tmp$$ 2>
> > > /dev/null && rm -f tmp$$ && echo $(1) | xargs echo -n)
> > > +endef
> > 
> > What is tmp$$ ?
> 
> It is created per process with pid value.

I see. The file is in current directory with name tmp + PID.

> > If the command is interrupted in the middle, temp file is not
> > cleaned.
> 
> Yes. I think we can move to RTE_OUTPUT. Even it is not cleaned 
> then it is file, I think, that would be easiest solution.
> 
> > We could fix it with "trap".
> 
> Can we do it in Makefile? 

Yes, it is just one more command separated with ;

> > Is it possible to just avoid creating a temporary file?
> 
> I tried it but gcc creates one.

It does not create a file in my test.

A better command is:
	$(CC) -E $(1) -xc /dev/null >/dev/null
Then you can just check the return value.

If you want rte_cc_has_argument returns a string or empty as true/false,
you can do this:
	$(CC) -E $(1) -xc /dev/null >/dev/null && echo $(1)

Re: [dpdk-dev] [PATCH v4 2/5] meson: add infra to support machine specific flags

[Phil Yang (Arm Technology China)]

Hi Pavan,

> -----Original Message-----
> From: dev <dev-bounces@dpdk.org> On Behalf Of Pavan Nikhilesh Bhagavatula
> Sent: Wednesday, January 9, 2019 6:40 PM
> To: jerinj@marvell.com; Gavin Hu (Arm Technology China)
> <Gavin.Hu@arm.com>; bruce.richardson@intel.com; thomas@monjalon.net
> Cc: dev@dpdk.org; Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>
> Subject: [dpdk-dev] [PATCH v4 2/5] meson: add infra to support machine specific
> flags
> 
> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> 
> Currently, RTE_* flags are set based on the implementer ID but there might be
> some micro arch specific differences from the same vendor eg. CACHE_LINESIZE.
> Add support to set micro arch specific flags.
> 
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> ---
>  config/arm/meson.build | 53 +++++++++++++++++++++++++-----------------
>  1 file changed, 32 insertions(+), 21 deletions(-)
> 
> diff --git a/config/arm/meson.build b/config/arm/meson.build index
> dae55d6b2..576363fc0 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -7,23 +7,6 @@ march_opt = '-march=@0@'.format(machine)
> 
>  arm_force_native_march = false
> 
> -machine_args_generic = [
> -	['default', ['-march=armv8-a+crc+crypto']],
> -	['native', ['-march=native']],
> -	['0xd03', ['-mcpu=cortex-a53']],
> -	['0xd04', ['-mcpu=cortex-a35']],
> -	['0xd07', ['-mcpu=cortex-a57']],
> -	['0xd08', ['-mcpu=cortex-a72']],
> -	['0xd09', ['-mcpu=cortex-a73']],
> -	['0xd0a', ['-mcpu=cortex-a75']],
> -]
> -machine_args_cavium = [
> -	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> -	['native', ['-march=native']],
> -	['0xa1', ['-mcpu=thunderxt88']],
> -	['0xa2', ['-mcpu=thunderxt81']],
> -	['0xa3', ['-mcpu=thunderxt83']]]
> -
>  flags_common_default = [
>  	# Accelarate rte_memcpy. Be sure to run unit test
> (memcpy_perf_autotest)
>  	# to determine the best threshold in code. Refer to notes in source file
> @@ -50,12 +33,10 @@ flags_generic = [
>  	['RTE_USE_C11_MEM_MODEL', true],
>  	['RTE_CACHE_LINE_SIZE', 128]]
>  flags_cavium = [
> -	['RTE_MACHINE', '"thunderx"'],
>  	['RTE_CACHE_LINE_SIZE', 128],
>  	['RTE_MAX_NUMA_NODES', 2],
>  	['RTE_MAX_LCORE', 96],
> -	['RTE_MAX_VFIO_GROUPS', 128],
> -	['RTE_USE_C11_MEM_MODEL', false]]
> +	['RTE_MAX_VFIO_GROUPS', 128]]
>  flags_dpaa = [
>  	['RTE_MACHINE', '"dpaa"'],
>  	['RTE_USE_C11_MEM_MODEL', true],
> @@ -69,6 +50,27 @@ flags_dpaa2 = [
>  	['RTE_MAX_NUMA_NODES', 1],
>  	['RTE_MAX_LCORE', 16],
>  	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
> +flags_default_extra = []
> +flags_thunderx_extra = [
> +	['RTE_MACHINE', '"thunderx"'],
> +	['RTE_USE_C11_MEM_MODEL', false]]
> +
> +machine_args_generic = [
> +	['default', ['-march=armv8-a+crc+crypto']],
> +	['native', ['-march=native']],
> +	['0xd03', ['-mcpu=cortex-a53']],
> +	['0xd04', ['-mcpu=cortex-a35']],
> +	['0xd07', ['-mcpu=cortex-a57']],
> +	['0xd08', ['-mcpu=cortex-a72']],
> +	['0xd09', ['-mcpu=cortex-a73']],
> +	['0xd0a', ['-mcpu=cortex-a75']]]
> +
> +machine_args_cavium = [
> +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> +	['native', ['-march=native']],
> +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
> +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
> +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
> 
>  ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
> impl_generic = ['Generic armv8', flags_generic, machine_args_generic] @@ -
> 157,10 +159,19 @@ else
>  	foreach marg: machine[2]
>  		if marg[0] == impl_pn
>  			foreach f: marg[1]
> -				machine_args += f
> +				if cc.has_argument(f)
> +					machine_args += f
> +				endif
>  			endforeach
>  		endif
>  	endforeach
> +
> +	# Apply any extra machine specific flags.
> +	foreach flag: marg.get(2, flags_default_extra)
> +		if flag.length() > 0
> +			dpdk_conf.set(flag[0], flag[1])
> +		endif
> +	endforeach

I think this loop should put inside the 'if marg[0] == impl_pn' condition.
The right logic should be:
If marg[0] == impl_pn
	# update machine_args
	# Apply any extra machine specific flags
endif

I tested this patch on thunderx2, but it set the octeontx2 extra flags into the rte_build_config.h. Because octeontx2 is the last item of 'machine_args_cavium' table.

>  endif
>  message(machine_args)
> 
> --
> 2.20.1

Thanks,
Phil Yang.

Re: [dpdk-dev] [EXT] RE: [PATCH v4 2/5] meson: add infra to support machine specific flags

[Pavan Nikhilesh Bhagavatula]

Hi Phil,

On Tue, 2019-02-12 at 08:06 +0000, Phil Yang (Arm Technology China)
wrote:
> External Email
> 
> -------------------------------------------------------------------
> ---
> Hi Pavan,
> 
> > -----Original Message-----
> > From: dev <dev-bounces@dpdk.org> On Behalf Of Pavan Nikhilesh
> > Bhagavatula
> > Sent: Wednesday, January 9, 2019 6:40 PM
> > To: jerinj@marvell.com; Gavin Hu (Arm Technology China)
> > <Gavin.Hu@arm.com>; bruce.richardson@intel.com; thomas@monjalon.net
> > Cc: dev@dpdk.org; Pavan Nikhilesh Bhagavatula <
> > pbhagavatula@marvell.com>
> > Subject: [dpdk-dev] [PATCH v4 2/5] meson: add infra to support
> > machine specific
> > flags
> > 
> > From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > 
> > Currently, RTE_* flags are set based on the implementer ID but
> > there might be
> > some micro arch specific differences from the same vendor eg.
> > CACHE_LINESIZE.
> > Add support to set micro arch specific flags.
> > 
> > Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> > Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > ---
> >  config/arm/meson.build | 53 +++++++++++++++++++++++++-------------
> > ----
> >  1 file changed, 32 insertions(+), 21 deletions(-)
> > 
> > diff --git a/config/arm/meson.build b/config/arm/meson.build index
> > dae55d6b2..576363fc0 100644
> > --- a/config/arm/meson.build
> > +++ b/config/arm/meson.build
> > @@ -7,23 +7,6 @@ march_opt = '-march=@0@'.format(machine)
> > 
> >  arm_force_native_march = false
> > 
> > -machine_args_generic = [
> > -	['default', ['-march=armv8-a+crc+crypto']],
> > -	['native', ['-march=native']],
> > -	['0xd03', ['-mcpu=cortex-a53']],
> > -	['0xd04', ['-mcpu=cortex-a35']],
> > -	['0xd07', ['-mcpu=cortex-a57']],
> > -	['0xd08', ['-mcpu=cortex-a72']],
> > -	['0xd09', ['-mcpu=cortex-a73']],
> > -	['0xd0a', ['-mcpu=cortex-a75']],
> > -]
> > -machine_args_cavium = [
> > -	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> > -	['native', ['-march=native']],
> > -	['0xa1', ['-mcpu=thunderxt88']],
> > -	['0xa2', ['-mcpu=thunderxt81']],
> > -	['0xa3', ['-mcpu=thunderxt83']]]
> > -
> >  flags_common_default = [
> >  	# Accelarate rte_memcpy. Be sure to run unit test
> > (memcpy_perf_autotest)
> >  	# to determine the best threshold in code. Refer to notes in
> > source file
> > @@ -50,12 +33,10 @@ flags_generic = [
> >  	['RTE_USE_C11_MEM_MODEL', true],
> >  	['RTE_CACHE_LINE_SIZE', 128]]
> >  flags_cavium = [
> > -	['RTE_MACHINE', '"thunderx"'],
> >  	['RTE_CACHE_LINE_SIZE', 128],
> >  	['RTE_MAX_NUMA_NODES', 2],
> >  	['RTE_MAX_LCORE', 96],
> > -	['RTE_MAX_VFIO_GROUPS', 128],
> > -	['RTE_USE_C11_MEM_MODEL', false]]
> > +	['RTE_MAX_VFIO_GROUPS', 128]]
> >  flags_dpaa = [
> >  	['RTE_MACHINE', '"dpaa"'],
> >  	['RTE_USE_C11_MEM_MODEL', true],
> > @@ -69,6 +50,27 @@ flags_dpaa2 = [
> >  	['RTE_MAX_NUMA_NODES', 1],
> >  	['RTE_MAX_LCORE', 16],
> >  	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
> > +flags_default_extra = []
> > +flags_thunderx_extra = [
> > +	['RTE_MACHINE', '"thunderx"'],
> > +	['RTE_USE_C11_MEM_MODEL', false]]
> > +
> > +machine_args_generic = [
> > +	['default', ['-march=armv8-a+crc+crypto']],
> > +	['native', ['-march=native']],
> > +	['0xd03', ['-mcpu=cortex-a53']],
> > +	['0xd04', ['-mcpu=cortex-a35']],
> > +	['0xd07', ['-mcpu=cortex-a57']],
> > +	['0xd08', ['-mcpu=cortex-a72']],
> > +	['0xd09', ['-mcpu=cortex-a73']],
> > +	['0xd0a', ['-mcpu=cortex-a75']]]
> > +
> > +machine_args_cavium = [
> > +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> > +	['native', ['-march=native']],
> > +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
> > +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
> > +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
> > 
> >  ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-
> > 5321)
> > impl_generic = ['Generic armv8', flags_generic,
> > machine_args_generic] @@ -
> > 157,10 +159,19 @@ else
> >  	foreach marg: machine[2]
> >  		if marg[0] == impl_pn
> >  			foreach f: marg[1]
> > -				machine_args += f
> > +				if cc.has_argument(f)
> > +					machine_args += f
> > +				endif
> >  			endforeach
> >  		endif
> >  	endforeach
> > +
> > +	# Apply any extra machine specific flags.
> > +	foreach flag: marg.get(2, flags_default_extra)
> > +		if flag.length() > 0
> > +			dpdk_conf.set(flag[0], flag[1])
> > +		endif
> > +	endforeach
> 
> I think this loop should put inside the 'if marg[0] == impl_pn'
> condition.
> The right logic should be:
> If marg[0] == impl_pn
> 	# update machine_args
> 	# Apply any extra machine specific flags
> endif

Yes, you are correct I will modify this in the next version.

Thanks,
Pavan.
> 
> I tested this patch on thunderx2, but it set the octeontx2 extra
> flags into the rte_build_config.h. Because octeontx2 is the last item
> of 'machine_args_cavium' table.
> 
> >  endif
> >  message(machine_args)
> > 
> > --
> > 2.20.1
> 
> Thanks,
> Phil Yang.

Re: [dpdk-dev] [PATCH v4 4/5] config: add octeontx2 machine config

[Phil Yang (Arm Technology China)]

Hi Jerin/Pavan,

> -----Original Message-----
> From: dev <dev-bounces@dpdk.org> On Behalf Of Pavan Nikhilesh Bhagavatula
> Sent: Wednesday, January 9, 2019 6:40 PM
> To: jerinj@marvell.com; Gavin Hu (Arm Technology China)
> <Gavin.Hu@arm.com>; bruce.richardson@intel.com; thomas@monjalon.net
> Cc: dev@dpdk.org; Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>
> Subject: [dpdk-dev] [PATCH v4 4/5] config: add octeontx2 machine config
> 
> From: Jerin Jacob <jerinj@marvell.com>
> 
> Optimized configuration for Marvell octeontx2 SoC. Update meson build to
> support Marvell octeontx2 SoC.
> 
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> ---
>  config/arm/meson.build                        | 10 +++++-
>  config/defconfig_arm64-octeontx2-linuxapp-gcc | 18 ++++++++++
>  mk/machine/octeontx2/rte.vars.mk              | 34 +++++++++++++++++++
>  3 files changed, 61 insertions(+), 1 deletion(-)  create mode 100644
> config/defconfig_arm64-octeontx2-linuxapp-gcc
>  create mode 100644 mk/machine/octeontx2/rte.vars.mk
> 
> diff --git a/config/arm/meson.build b/config/arm/meson.build index
> aca285b6a..8086357a1 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -60,6 +60,13 @@ flags_thunderx2_extra = [
>  	['RTE_MAX_NUMA_NODES', 2],
>  	['RTE_MAX_LCORE', 256],
>  	['RTE_USE_C11_MEM_MODEL', true]]
> +flags_octeontx2_extra = [
> +	['RTE_MACHINE', '"octeontx2"'],
> +	['RTE_MAX_NUMA_NODES', 1],
> +	['RTE_MAX_LCORE', 24],
> +	['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
> +	['RTE_LIBRTE_VHOST_NUMA', false],
> +	['RTE_EAL_IGB_UIO', false]]
> 
>  machine_args_generic = [
>  	['default', ['-march=armv8-a+crc+crypto']], @@ -77,7 +84,8 @@
> machine_args_cavium = [
>  	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
>  	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
>  	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
> -	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
> +	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra],
> +	['0xb2', ['-mcpu=octeontx2'], flags_octeontx2_extra]]
> 
>  ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
> impl_generic = ['Generic armv8', flags_generic, machine_args_generic] diff --git
> a/config/defconfig_arm64-octeontx2-linuxapp-gcc b/config/defconfig_arm64-
> octeontx2-linuxapp-gcc
> new file mode 100644
> index 000000000..9a99eada1
> --- /dev/null
> +++ b/config/defconfig_arm64-octeontx2-linuxapp-gcc
> @@ -0,0 +1,18 @@
> +# SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2018 Marvell
> +International Ltd #
> +
> +#include "defconfig_arm64-armv8a-linuxapp-gcc"
> +
> +CONFIG_RTE_MACHINE="octeontx2"
> +
> +CONFIG_RTE_CACHE_LINE_SIZE=128
> +CONFIG_RTE_MAX_NUMA_NODES=1
> +CONFIG_RTE_MAX_LCORE=24
> +
> +# Doesn't support NUMA
> +CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
> +CONFIG_RTE_LIBRTE_VHOST_NUMA=n
> +
> +# Recommend to use VFIO as co-processors needs SMMU/IOMMU
> +CONFIG_RTE_EAL_IGB_UIO=n
> diff --git a/mk/machine/octeontx2/rte.vars.mk
> b/mk/machine/octeontx2/rte.vars.mk
> new file mode 100644
> index 000000000..e209cf492
> --- /dev/null
> +++ b/mk/machine/octeontx2/rte.vars.mk
> @@ -0,0 +1,34 @@
> +# SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2018 Marvell
> +International Ltd #
> +
> +#
> +# machine:
> +#
> +#   - can define ARCH variable (overridden by cmdline value)
> +#   - can define CROSS variable (overridden by cmdline value)
> +#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
> +#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
> +#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
> +#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
> +#     overrides the one defined in arch.
> +#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
> +#     overrides the one defined in arch.
> +#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
> +#     overrides the one defined in arch.
> +#   - may override any previously defined variable
> +#
> +
> +# ARCH =
> +# CROSS =
> +# MACHINE_CFLAGS =
> +# MACHINE_LDFLAGS =
> +# MACHINE_ASFLAGS =
> +# CPU_CFLAGS =
> +# CPU_LDFLAGS =
> +# CPU_ASFLAGS =
> +
> +include $(RTE_SDK)/mk/rte.helper.mk
> +
> +MACHINE_CFLAGS += $(call rte_cc_has_argument,
> +-march=armv8.2-a+crc+crypto+lse) MACHINE_CFLAGS += $(call
> +rte_cc_has_argument, -mcpu=octeontx2)

Why do you choose to expose armv8.2-a flag other than using armv8a combine with the extension flags here?
The value 'armv8.2-a' implies 'armv8.1-a' and enables compiler support for the ARMv8.2-A architecture extensions. And the 'lse' extension is the default feature for 'armv8.1-a'. So it seems there is no need to specify 'armv8.2-a' with 'lse'.

According to the meson build code, the default -march config for Cavium is 'armv8-a'. So I think it seems better to keep 'armv8-a' here and add flags for the specific extensions.
The same for thunderx2 configuration.

> --
> 2.20.1

Thanks,
Phil Yang

[dpdk-dev] [PATCH v5 1/4] mk: introduce helper to check valid compiler argument

[Jerin Jacob Kollanukkaran]

Introduce rte_cc_has_argument() Makefile helper to
check a given argument is support by the compiler.

Example Usage:

include $(RTE_SDK)/mk/rte.helper.mk
MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)

This would allow adding -mcpu=octeontx2 in MACHINE_CFLAGS
if it is only supported by the compiler. The use case for such
scheme is to enable the mcpu optimization if the compiler
supports else it needs to compile the source code without
any errors.

This patch also moves inclusion of toolchain's rte.vars.mk
to before the machine's rte.vars.mk inclusion to make
correct CC available for the cross compile case.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---

Change history of this series:

v2 Changes:
 - Add meson build support.

v3 Changes:
 - Squash meson build support into config support for thunderx2/octeontx2.

v4 Changes:
 - Fix incorrect signoff marrvell -> marvell.

v5 Changes:
 - Fix incorrect meson flag parsing(Phil Yang)
 - Squash meson cross build patch(5/5) into configuration update patches for
 thunderx2(3/5) and octeontx2(4/5)(Thomas)
 - Changed octeontx2's march as armv8-a and added the extension required
   instead of armv8-2a(Phil Yang)
 - Improved rte_cc_has_argument() implementaion by removing the temp
   file(Thomas)

---
 mk/rte.helper.mk              | 10 ++++++++++
 mk/target/generic/rte.vars.mk | 22 +++++++++++-----------
 2 files changed, 21 insertions(+), 11 deletions(-)
 create mode 100644 mk/rte.helper.mk

diff --git a/mk/rte.helper.mk b/mk/rte.helper.mk
new file mode 100644
index 000000000..6e7fd03d7
--- /dev/null
+++ b/mk/rte.helper.mk
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+
+# rte_cc_has_argument
+# Usage: MACHINE_CFLAGS += $(call rte_cc_has_argument, -mno-avx512f)
+# Return the argument if the argument is supported by the compiler.
+#
+define rte_cc_has_argument
+	$(shell $(CC) -E $(1) -xc /dev/null 1>/dev/null 2>/dev/null && echo $(1))
+endef
diff --git a/mk/target/generic/rte.vars.mk b/mk/target/generic/rte.vars.mk
index dd149acc9..25a578ad7 100644
--- a/mk/target/generic/rte.vars.mk
+++ b/mk/target/generic/rte.vars.mk
@@ -7,6 +7,17 @@
 # executive environment.
 #
 
+#
+# toolchain:
+#
+#   - define CC, LD, AR, AS, ...
+#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
+#   - may override any previously defined variable
+#
+include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
+
 #
 # machine:
 #
@@ -45,17 +56,6 @@ endif
 #
 include $(RTE_SDK)/mk/arch/$(RTE_ARCH)/rte.vars.mk
 
-#
-# toolchain:
-#
-#   - define CC, LD, AR, AS, ...
-#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
-#   - may override any previously defined variable
-#
-include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
-
 #
 # exec-env:
 #
-- 
2.20.1

[dpdk-dev] [PATCH v5 2/4] meson: add infra to support machine specific flags

[Jerin Jacob Kollanukkaran]

From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Currently, RTE_* flags are set based on the implementer ID but there might
be some micro arch specific differences from the same vendor
eg. CACHE_LINESIZE. Add support to set micro arch specific flags.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
---
 config/arm/meson.build | 54 +++++++++++++++++++++++++-----------------
 1 file changed, 32 insertions(+), 22 deletions(-)

diff --git a/config/arm/meson.build b/config/arm/meson.build
index dae55d6b2..7eb6f5c99 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -7,23 +7,6 @@ march_opt = '-march=@0@'.format(machine)
 
 arm_force_native_march = false
 
-machine_args_generic = [
-	['default', ['-march=armv8-a+crc+crypto']],
-	['native', ['-march=native']],
-	['0xd03', ['-mcpu=cortex-a53']],
-	['0xd04', ['-mcpu=cortex-a35']],
-	['0xd07', ['-mcpu=cortex-a57']],
-	['0xd08', ['-mcpu=cortex-a72']],
-	['0xd09', ['-mcpu=cortex-a73']],
-	['0xd0a', ['-mcpu=cortex-a75']],
-]
-machine_args_cavium = [
-	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
-	['native', ['-march=native']],
-	['0xa1', ['-mcpu=thunderxt88']],
-	['0xa2', ['-mcpu=thunderxt81']],
-	['0xa3', ['-mcpu=thunderxt83']]]
-
 flags_common_default = [
 	# Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
 	# to determine the best threshold in code. Refer to notes in source file
@@ -50,12 +33,10 @@ flags_generic = [
 	['RTE_USE_C11_MEM_MODEL', true],
 	['RTE_CACHE_LINE_SIZE', 128]]
 flags_cavium = [
-	['RTE_MACHINE', '"thunderx"'],
 	['RTE_CACHE_LINE_SIZE', 128],
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 96],
-	['RTE_MAX_VFIO_GROUPS', 128],
-	['RTE_USE_C11_MEM_MODEL', false]]
+	['RTE_MAX_VFIO_GROUPS', 128]]
 flags_dpaa = [
 	['RTE_MACHINE', '"dpaa"'],
 	['RTE_USE_C11_MEM_MODEL', true],
@@ -69,6 +50,27 @@ flags_dpaa2 = [
 	['RTE_MAX_NUMA_NODES', 1],
 	['RTE_MAX_LCORE', 16],
 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
+flags_default_extra = []
+flags_thunderx_extra = [
+	['RTE_MACHINE', '"thunderx"'],
+	['RTE_USE_C11_MEM_MODEL', false]]
+
+machine_args_generic = [
+	['default', ['-march=armv8-a+crc+crypto']],
+	['native', ['-march=native']],
+	['0xd03', ['-mcpu=cortex-a53']],
+	['0xd04', ['-mcpu=cortex-a35']],
+	['0xd07', ['-mcpu=cortex-a57']],
+	['0xd08', ['-mcpu=cortex-a72']],
+	['0xd09', ['-mcpu=cortex-a73']],
+	['0xd0a', ['-mcpu=cortex-a75']]]
+
+machine_args_cavium = [
+	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
+	['native', ['-march=native']],
+	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
+	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
@@ -156,8 +158,16 @@ else
 	endif
 	foreach marg: machine[2]
 		if marg[0] == impl_pn
-			foreach f: marg[1]
-				machine_args += f
+			foreach flag: marg[1]
+				if cc.has_argument(flag)
+					machine_args += flag
+				endif
+			endforeach
+			# Apply any extra machine specific flags.
+			foreach flag: marg.get(2, flags_default_extra)
+				if flag.length() > 0
+					dpdk_conf.set(flag[0], flag[1])
+				endif
 			endforeach
 		endif
 	endforeach
-- 
2.20.1

[dpdk-dev] [PATCH v5 3/4] config: add thunderx2 machine config

[Jerin Jacob Kollanukkaran]

Optimized configuration for Marvell thunderx2 SoC.
Updated meson build to support Marvell thunderx2 SoC.
Added meson cross compile target.

Product details are here:

https://www.marvell.com/server-processors/thunderx2-arm-processors/

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
 config/arm/arm64_thunderx2_linuxapp_gcc       | 15 ++++++++
 config/arm/meson.build                        |  9 ++++-
 config/defconfig_arm64-thunderx2-linuxapp-gcc | 11 ++++++
 mk/machine/thunderx2/rte.vars.mk              | 34 +++++++++++++++++++
 4 files changed, 68 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/arm64_thunderx2_linuxapp_gcc
 create mode 100644 config/defconfig_arm64-thunderx2-linuxapp-gcc
 create mode 100644 mk/machine/thunderx2/rte.vars.mk

diff --git a/config/arm/arm64_thunderx2_linuxapp_gcc b/config/arm/arm64_thunderx2_linuxapp_gcc
new file mode 100644
index 000000000..48b07a40c
--- /dev/null
+++ b/config/arm/arm64_thunderx2_linuxapp_gcc
@@ -0,0 +1,15 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x43'
+implementor_pn = '0xaf'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 7eb6f5c99..f34913291 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -54,6 +54,12 @@ flags_default_extra = []
 flags_thunderx_extra = [
 	['RTE_MACHINE', '"thunderx"'],
 	['RTE_USE_C11_MEM_MODEL', false]]
+flags_thunderx2_extra = [
+	['RTE_MACHINE', '"thunderx2"'],
+	['RTE_CACHE_LINE_SIZE', 64],
+	['RTE_MAX_NUMA_NODES', 2],
+	['RTE_MAX_LCORE', 256],
+	['RTE_USE_C11_MEM_MODEL', true]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -70,7 +76,8 @@ machine_args_cavium = [
 	['native', ['-march=native']],
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
-	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-thunderx2-linuxapp-gcc b/config/defconfig_arm64-thunderx2-linuxapp-gcc
new file mode 100644
index 000000000..27db58e50
--- /dev/null
+++ b/config/defconfig_arm64-thunderx2-linuxapp-gcc
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linuxapp-gcc"
+
+CONFIG_RTE_MACHINE="thunderx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=64
+CONFIG_RTE_MAX_NUMA_NODES=2
+CONFIG_RTE_MAX_LCORE=256
diff --git a/mk/machine/thunderx2/rte.vars.mk b/mk/machine/thunderx2/rte.vars.mk
new file mode 100644
index 000000000..b80dc8680
--- /dev/null
+++ b/mk/machine/thunderx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.1-a+crc+crypto)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=thunderx2t99)
-- 
2.20.1

[dpdk-dev] [PATCH v5 4/4] config: add octeontx2 machine config

[Jerin Jacob Kollanukkaran]

Optimized configuration for Marvell octeontx2 SoC.
Updated meson build to support Marvell octeontx2 SoC.
Added meson cross build target for octeontx2.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
 config/arm/arm64_octeontx2_linuxapp_gcc       | 15 ++++++++
 config/arm/meson.build                        |  9 ++++-
 config/defconfig_arm64-octeontx2-linuxapp-gcc | 18 ++++++++++
 mk/machine/octeontx2/rte.vars.mk              | 34 +++++++++++++++++++
 4 files changed, 75 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/arm64_octeontx2_linuxapp_gcc
 create mode 100644 config/defconfig_arm64-octeontx2-linuxapp-gcc
 create mode 100644 mk/machine/octeontx2/rte.vars.mk

diff --git a/config/arm/arm64_octeontx2_linuxapp_gcc b/config/arm/arm64_octeontx2_linuxapp_gcc
new file mode 100644
index 000000000..7a6429b1b
--- /dev/null
+++ b/config/arm/arm64_octeontx2_linuxapp_gcc
@@ -0,0 +1,15 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x43'
+implementor_pn = '0xb2'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index f34913291..5edaeec13 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -60,6 +60,12 @@ flags_thunderx2_extra = [
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 256],
 	['RTE_USE_C11_MEM_MODEL', true]]
+flags_octeontx2_extra = [
+	['RTE_MACHINE', '"octeontx2"'],
+	['RTE_MAX_NUMA_NODES', 1],
+	['RTE_MAX_LCORE', 24],
+	['RTE_EAL_IGB_UIO', false],
+	['RTE_USE_C11_MEM_MODEL', true]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -77,7 +83,8 @@ machine_args_cavium = [
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
 	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
-	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra],
+	['0xb2', ['-mcpu=octeontx2'], flags_octeontx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-octeontx2-linuxapp-gcc b/config/defconfig_arm64-octeontx2-linuxapp-gcc
new file mode 100644
index 000000000..9a99eada1
--- /dev/null
+++ b/config/defconfig_arm64-octeontx2-linuxapp-gcc
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linuxapp-gcc"
+
+CONFIG_RTE_MACHINE="octeontx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=128
+CONFIG_RTE_MAX_NUMA_NODES=1
+CONFIG_RTE_MAX_LCORE=24
+
+# Doesn't support NUMA
+CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
+CONFIG_RTE_LIBRTE_VHOST_NUMA=n
+
+# Recommend to use VFIO as co-processors needs SMMU/IOMMU
+CONFIG_RTE_EAL_IGB_UIO=n
diff --git a/mk/machine/octeontx2/rte.vars.mk b/mk/machine/octeontx2/rte.vars.mk
new file mode 100644
index 000000000..e0a7498a3
--- /dev/null
+++ b/mk/machine/octeontx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8-a+crc+crypto+lse)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)
-- 
2.20.1

[dpdk-dev] [PATCH v6 1/4] mk: introduce helper to check valid compiler argument

[Jerin Jacob Kollanukkaran]

From: Jerin Jacob <jerinj@marvell.com>

Introduce rte_cc_has_argument() Makefile helper to
check a given argument is support by the compiler.

Example Usage:

include $(RTE_SDK)/mk/rte.helper.mk
MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)

This would allow adding -mcpu=octeontx2 in MACHINE_CFLAGS
if it is only supported by the compiler. The use case for such
scheme is to enable the mcpu optimization if the compiler
supports else it needs to compile the source code without
any errors.

This patch also moves inclusion of toolchain's rte.vars.mk
to before the machine's rte.vars.mk inclusion to make
correct CC available for the cross compile case.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---

Change history of this series:

v2 Changes:
 - Add meson build support.

v3 Changes:
 - Squash meson build support into config support for thunderx2/octeontx2.

v4 Changes:
 - Fix incorrect signoff marrvell -> marvell.

v5 Changes:
 - Fix incorrect meson flag parsing(Phil Yang)
 - Squash meson cross build patch(5/5) into configuration update patches for
 thunderx2(3/5) and octeontx2(4/5)(Thomas)
 - Changed octeontx2's march as armv8-a and added the extension required
   instead of armv8-2a(Phil Yang)
 - Improved rte_cc_has_argument() implementaion by removing the temp
   file(Thomas)

v6 Changes:
 - Rework to change the config files to sync with "mk: use linux and freebsd in config names"
 - Fix the following error with latest gcc by fixing the mcpu type
   cc1: error: switch -mcpu=armv8.2-a conflicts with -march=armv8-a switch 

---
 mk/rte.helper.mk              | 10 ++++++++++
 mk/target/generic/rte.vars.mk | 22 +++++++++++-----------
 2 files changed, 21 insertions(+), 11 deletions(-)
 create mode 100644 mk/rte.helper.mk

diff --git a/mk/rte.helper.mk b/mk/rte.helper.mk
new file mode 100644
index 000000000..6e7fd03d7
--- /dev/null
+++ b/mk/rte.helper.mk
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+
+# rte_cc_has_argument
+# Usage: MACHINE_CFLAGS += $(call rte_cc_has_argument, -mno-avx512f)
+# Return the argument if the argument is supported by the compiler.
+#
+define rte_cc_has_argument
+	$(shell $(CC) -E $(1) -xc /dev/null 1>/dev/null 2>/dev/null && echo $(1))
+endef
diff --git a/mk/target/generic/rte.vars.mk b/mk/target/generic/rte.vars.mk
index dd149acc9..25a578ad7 100644
--- a/mk/target/generic/rte.vars.mk
+++ b/mk/target/generic/rte.vars.mk
@@ -7,6 +7,17 @@
 # executive environment.
 #
 
+#
+# toolchain:
+#
+#   - define CC, LD, AR, AS, ...
+#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
+#   - may override any previously defined variable
+#
+include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
+
 #
 # machine:
 #
@@ -45,17 +56,6 @@ endif
 #
 include $(RTE_SDK)/mk/arch/$(RTE_ARCH)/rte.vars.mk
 
-#
-# toolchain:
-#
-#   - define CC, LD, AR, AS, ...
-#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
-#   - may override any previously defined variable
-#
-include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
-
 #
 # exec-env:
 #
-- 
2.21.0

[dpdk-dev] [PATCH v6 1/4] mk: introduce helper to check valid compiler argument

[Jerin Jacob Kollanukkaran]

From: Jerin Jacob <jerinj@marvell.com>

Introduce rte_cc_has_argument() Makefile helper to
check a given argument is support by the compiler.

Example Usage:

include $(RTE_SDK)/mk/rte.helper.mk
MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)

This would allow adding -mcpu=octeontx2 in MACHINE_CFLAGS
if it is only supported by the compiler. The use case for such
scheme is to enable the mcpu optimization if the compiler
supports else it needs to compile the source code without
any errors.

This patch also moves inclusion of toolchain's rte.vars.mk
to before the machine's rte.vars.mk inclusion to make
correct CC available for the cross compile case.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---

Change history of this series:

v2 Changes:
 - Add meson build support.

v3 Changes:
 - Squash meson build support into config support for thunderx2/octeontx2.

v4 Changes:
 - Fix incorrect signoff marrvell -> marvell.

v5 Changes:
 - Fix incorrect meson flag parsing(Phil Yang)
 - Squash meson cross build patch(5/5) into configuration update patches for
 thunderx2(3/5) and octeontx2(4/5)(Thomas)
 - Changed octeontx2's march as armv8-a and added the extension required
   instead of armv8-2a(Phil Yang)
 - Improved rte_cc_has_argument() implementaion by removing the temp
   file(Thomas)

v6 Changes:
 - Rework to change the config files to sync with "mk: use linux and freebsd in config names"
 - Fix the following error with latest gcc by fixing the mcpu type
   cc1: error: switch -mcpu=armv8.2-a conflicts with -march=armv8-a switch 

---
 mk/rte.helper.mk              | 10 ++++++++++
 mk/target/generic/rte.vars.mk | 22 +++++++++++-----------
 2 files changed, 21 insertions(+), 11 deletions(-)
 create mode 100644 mk/rte.helper.mk

diff --git a/mk/rte.helper.mk b/mk/rte.helper.mk
new file mode 100644
index 000000000..6e7fd03d7
--- /dev/null
+++ b/mk/rte.helper.mk
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+
+# rte_cc_has_argument
+# Usage: MACHINE_CFLAGS += $(call rte_cc_has_argument, -mno-avx512f)
+# Return the argument if the argument is supported by the compiler.
+#
+define rte_cc_has_argument
+	$(shell $(CC) -E $(1) -xc /dev/null 1>/dev/null 2>/dev/null && echo $(1))
+endef
diff --git a/mk/target/generic/rte.vars.mk b/mk/target/generic/rte.vars.mk
index dd149acc9..25a578ad7 100644
--- a/mk/target/generic/rte.vars.mk
+++ b/mk/target/generic/rte.vars.mk
@@ -7,6 +7,17 @@
 # executive environment.
 #
 
+#
+# toolchain:
+#
+#   - define CC, LD, AR, AS, ...
+#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
+#   - may override any previously defined variable
+#
+include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
+
 #
 # machine:
 #
@@ -45,17 +56,6 @@ endif
 #
 include $(RTE_SDK)/mk/arch/$(RTE_ARCH)/rte.vars.mk
 
-#
-# toolchain:
-#
-#   - define CC, LD, AR, AS, ...
-#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
-#   - may override any previously defined variable
-#
-include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
-
 #
 # exec-env:
 #
-- 
2.21.0

[dpdk-dev] [PATCH v6 2/4] meson: add infra to support machine specific flags

[Jerin Jacob Kollanukkaran]

From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Currently, RTE_* flags are set based on the implementer ID but there might
be some micro arch specific differences from the same vendor
eg. CACHE_LINESIZE. Add support to set micro arch specific flags.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
---
 config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++-----
 1 file changed, 32 insertions(+), 5 deletions(-)

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 8e892fa77..3db6d6445 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -52,12 +52,10 @@ flags_generic = [
 	['RTE_USE_C11_MEM_MODEL', true],
 	['RTE_CACHE_LINE_SIZE', 128]]
 flags_cavium = [
-	['RTE_MACHINE', '"thunderx"'],
 	['RTE_CACHE_LINE_SIZE', 128],
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 96],
-	['RTE_MAX_VFIO_GROUPS', 128],
-	['RTE_USE_C11_MEM_MODEL', false]]
+	['RTE_MAX_VFIO_GROUPS', 128]]
 flags_dpaa = [
 	['RTE_MACHINE', '"dpaa"'],
 	['RTE_USE_C11_MEM_MODEL', true],
@@ -71,6 +69,27 @@ flags_dpaa2 = [
 	['RTE_MAX_NUMA_NODES', 1],
 	['RTE_MAX_LCORE', 16],
 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
+flags_default_extra = []
+flags_thunderx_extra = [
+	['RTE_MACHINE', '"thunderx"'],
+	['RTE_USE_C11_MEM_MODEL', false]]
+
+machine_args_generic = [
+	['default', ['-march=armv8-a+crc+crypto']],
+	['native', ['-march=native']],
+	['0xd03', ['-mcpu=cortex-a53']],
+	['0xd04', ['-mcpu=cortex-a35']],
+	['0xd07', ['-mcpu=cortex-a57']],
+	['0xd08', ['-mcpu=cortex-a72']],
+	['0xd09', ['-mcpu=cortex-a73']],
+	['0xd0a', ['-mcpu=cortex-a75']]]
+
+machine_args_cavium = [
+	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
+	['native', ['-march=native']],
+	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
+	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
@@ -157,8 +176,16 @@ else
 	endif
 	foreach marg: machine[2]
 		if marg[0] == impl_pn
-			foreach f: marg[1]
-				machine_args += f
+			foreach flag: marg[1]
+				if cc.has_argument(flag)
+					machine_args += flag
+				endif
+			endforeach
+			# Apply any extra machine specific flags.
+			foreach flag: marg.get(2, flags_default_extra)
+				if flag.length() > 0
+					dpdk_conf.set(flag[0], flag[1])
+				endif
 			endforeach
 		endif
 	endforeach
-- 
2.21.0

[dpdk-dev] [PATCH v6 2/4] meson: add infra to support machine specific flags

[Jerin Jacob Kollanukkaran]

From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Currently, RTE_* flags are set based on the implementer ID but there might
be some micro arch specific differences from the same vendor
eg. CACHE_LINESIZE. Add support to set micro arch specific flags.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
---
 config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++-----
 1 file changed, 32 insertions(+), 5 deletions(-)

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 8e892fa77..3db6d6445 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -52,12 +52,10 @@ flags_generic = [
 	['RTE_USE_C11_MEM_MODEL', true],
 	['RTE_CACHE_LINE_SIZE', 128]]
 flags_cavium = [
-	['RTE_MACHINE', '"thunderx"'],
 	['RTE_CACHE_LINE_SIZE', 128],
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 96],
-	['RTE_MAX_VFIO_GROUPS', 128],
-	['RTE_USE_C11_MEM_MODEL', false]]
+	['RTE_MAX_VFIO_GROUPS', 128]]
 flags_dpaa = [
 	['RTE_MACHINE', '"dpaa"'],
 	['RTE_USE_C11_MEM_MODEL', true],
@@ -71,6 +69,27 @@ flags_dpaa2 = [
 	['RTE_MAX_NUMA_NODES', 1],
 	['RTE_MAX_LCORE', 16],
 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
+flags_default_extra = []
+flags_thunderx_extra = [
+	['RTE_MACHINE', '"thunderx"'],
+	['RTE_USE_C11_MEM_MODEL', false]]
+
+machine_args_generic = [
+	['default', ['-march=armv8-a+crc+crypto']],
+	['native', ['-march=native']],
+	['0xd03', ['-mcpu=cortex-a53']],
+	['0xd04', ['-mcpu=cortex-a35']],
+	['0xd07', ['-mcpu=cortex-a57']],
+	['0xd08', ['-mcpu=cortex-a72']],
+	['0xd09', ['-mcpu=cortex-a73']],
+	['0xd0a', ['-mcpu=cortex-a75']]]
+
+machine_args_cavium = [
+	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
+	['native', ['-march=native']],
+	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
+	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
@@ -157,8 +176,16 @@ else
 	endif
 	foreach marg: machine[2]
 		if marg[0] == impl_pn
-			foreach f: marg[1]
-				machine_args += f
+			foreach flag: marg[1]
+				if cc.has_argument(flag)
+					machine_args += flag
+				endif
+			endforeach
+			# Apply any extra machine specific flags.
+			foreach flag: marg.get(2, flags_default_extra)
+				if flag.length() > 0
+					dpdk_conf.set(flag[0], flag[1])
+				endif
 			endforeach
 		endif
 	endforeach
-- 
2.21.0

[dpdk-dev] [PATCH v6 3/4] config: add thunderx2 machine config

[Jerin Jacob Kollanukkaran]

From: Jerin Jacob <jerinj@marvell.com>

Optimized configuration for Marvell thunderx2 SoC.
Updated meson build to support Marvell thunderx2 SoC.
Added meson cross compile target.

Product details are here:

https://www.marvell.com/server-processors/thunderx2-arm-processors/

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
 config/arm/arm64_thunderx2_linux_gcc          | 15 ++++++++
 config/arm/meson.build                        |  9 ++++-
 config/defconfig_arm64-thunderx2-linux-gcc    |  1 +
 config/defconfig_arm64-thunderx2-linuxapp-gcc | 11 ++++++
 mk/machine/thunderx2/rte.vars.mk              | 34 +++++++++++++++++++
 5 files changed, 69 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/arm64_thunderx2_linux_gcc
 create mode 120000 config/defconfig_arm64-thunderx2-linux-gcc
 create mode 100644 config/defconfig_arm64-thunderx2-linuxapp-gcc
 create mode 100644 mk/machine/thunderx2/rte.vars.mk

diff --git a/config/arm/arm64_thunderx2_linux_gcc b/config/arm/arm64_thunderx2_linux_gcc
new file mode 100644
index 000000000..48b07a40c
--- /dev/null
+++ b/config/arm/arm64_thunderx2_linux_gcc
@@ -0,0 +1,15 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x43'
+implementor_pn = '0xaf'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 3db6d6445..5c391ed3c 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -73,6 +73,12 @@ flags_default_extra = []
 flags_thunderx_extra = [
 	['RTE_MACHINE', '"thunderx"'],
 	['RTE_USE_C11_MEM_MODEL', false]]
+flags_thunderx2_extra = [
+	['RTE_MACHINE', '"thunderx2"'],
+	['RTE_CACHE_LINE_SIZE', 64],
+	['RTE_MAX_NUMA_NODES', 2],
+	['RTE_MAX_LCORE', 256],
+	['RTE_USE_C11_MEM_MODEL', true]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -89,7 +95,8 @@ machine_args_cavium = [
 	['native', ['-march=native']],
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
-	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-thunderx2-linux-gcc b/config/defconfig_arm64-thunderx2-linux-gcc
new file mode 120000
index 000000000..b40a760b1
--- /dev/null
+++ b/config/defconfig_arm64-thunderx2-linux-gcc
@@ -0,0 +1 @@
+defconfig_arm64-thunderx2-linuxapp-gcc
\ No newline at end of file
diff --git a/config/defconfig_arm64-thunderx2-linuxapp-gcc b/config/defconfig_arm64-thunderx2-linuxapp-gcc
new file mode 100644
index 000000000..cc5c64ba0
--- /dev/null
+++ b/config/defconfig_arm64-thunderx2-linuxapp-gcc
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linux-gcc"
+
+CONFIG_RTE_MACHINE="thunderx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=64
+CONFIG_RTE_MAX_NUMA_NODES=2
+CONFIG_RTE_MAX_LCORE=256
diff --git a/mk/machine/thunderx2/rte.vars.mk b/mk/machine/thunderx2/rte.vars.mk
new file mode 100644
index 000000000..b80dc8680
--- /dev/null
+++ b/mk/machine/thunderx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.1-a+crc+crypto)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=thunderx2t99)
-- 
2.21.0

[dpdk-dev] [PATCH v6 3/4] config: add thunderx2 machine config

[Jerin Jacob Kollanukkaran]

From: Jerin Jacob <jerinj@marvell.com>

Optimized configuration for Marvell thunderx2 SoC.
Updated meson build to support Marvell thunderx2 SoC.
Added meson cross compile target.

Product details are here:

https://www.marvell.com/server-processors/thunderx2-arm-processors/

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
 config/arm/arm64_thunderx2_linux_gcc          | 15 ++++++++
 config/arm/meson.build                        |  9 ++++-
 config/defconfig_arm64-thunderx2-linux-gcc    |  1 +
 config/defconfig_arm64-thunderx2-linuxapp-gcc | 11 ++++++
 mk/machine/thunderx2/rte.vars.mk              | 34 +++++++++++++++++++
 5 files changed, 69 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/arm64_thunderx2_linux_gcc
 create mode 120000 config/defconfig_arm64-thunderx2-linux-gcc
 create mode 100644 config/defconfig_arm64-thunderx2-linuxapp-gcc
 create mode 100644 mk/machine/thunderx2/rte.vars.mk

diff --git a/config/arm/arm64_thunderx2_linux_gcc b/config/arm/arm64_thunderx2_linux_gcc
new file mode 100644
index 000000000..48b07a40c
--- /dev/null
+++ b/config/arm/arm64_thunderx2_linux_gcc
@@ -0,0 +1,15 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x43'
+implementor_pn = '0xaf'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 3db6d6445..5c391ed3c 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -73,6 +73,12 @@ flags_default_extra = []
 flags_thunderx_extra = [
 	['RTE_MACHINE', '"thunderx"'],
 	['RTE_USE_C11_MEM_MODEL', false]]
+flags_thunderx2_extra = [
+	['RTE_MACHINE', '"thunderx2"'],
+	['RTE_CACHE_LINE_SIZE', 64],
+	['RTE_MAX_NUMA_NODES', 2],
+	['RTE_MAX_LCORE', 256],
+	['RTE_USE_C11_MEM_MODEL', true]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -89,7 +95,8 @@ machine_args_cavium = [
 	['native', ['-march=native']],
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
-	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-thunderx2-linux-gcc b/config/defconfig_arm64-thunderx2-linux-gcc
new file mode 120000
index 000000000..b40a760b1
--- /dev/null
+++ b/config/defconfig_arm64-thunderx2-linux-gcc
@@ -0,0 +1 @@
+defconfig_arm64-thunderx2-linuxapp-gcc
\ No newline at end of file
diff --git a/config/defconfig_arm64-thunderx2-linuxapp-gcc b/config/defconfig_arm64-thunderx2-linuxapp-gcc
new file mode 100644
index 000000000..cc5c64ba0
--- /dev/null
+++ b/config/defconfig_arm64-thunderx2-linuxapp-gcc
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linux-gcc"
+
+CONFIG_RTE_MACHINE="thunderx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=64
+CONFIG_RTE_MAX_NUMA_NODES=2
+CONFIG_RTE_MAX_LCORE=256
diff --git a/mk/machine/thunderx2/rte.vars.mk b/mk/machine/thunderx2/rte.vars.mk
new file mode 100644
index 000000000..b80dc8680
--- /dev/null
+++ b/mk/machine/thunderx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.1-a+crc+crypto)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=thunderx2t99)
-- 
2.21.0

[dpdk-dev] [PATCH v6 4/4] config: add octeontx2 machine config

[Jerin Jacob Kollanukkaran]

From: Jerin Jacob <jerinj@marvell.com>

Optimized configuration for Marvell octeontx2 SoC.
Updated meson build to support Marvell octeontx2 SoC.
Added meson cross build target for octeontx2.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
 config/arm/arm64_octeontx2_linux_gcc          | 15 ++++++++
 config/arm/meson.build                        |  9 ++++-
 config/defconfig_arm64-octeontx2-linux-gcc    |  1 +
 config/defconfig_arm64-octeontx2-linuxapp-gcc | 18 ++++++++++
 mk/machine/octeontx2/rte.vars.mk              | 34 +++++++++++++++++++
 5 files changed, 76 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/arm64_octeontx2_linux_gcc
 create mode 120000 config/defconfig_arm64-octeontx2-linux-gcc
 create mode 100644 config/defconfig_arm64-octeontx2-linuxapp-gcc
 create mode 100644 mk/machine/octeontx2/rte.vars.mk

diff --git a/config/arm/arm64_octeontx2_linux_gcc b/config/arm/arm64_octeontx2_linux_gcc
new file mode 100644
index 000000000..7a6429b1b
--- /dev/null
+++ b/config/arm/arm64_octeontx2_linux_gcc
@@ -0,0 +1,15 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x43'
+implementor_pn = '0xb2'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 5c391ed3c..87ae40c24 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -79,6 +79,12 @@ flags_thunderx2_extra = [
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 256],
 	['RTE_USE_C11_MEM_MODEL', true]]
+flags_octeontx2_extra = [
+	['RTE_MACHINE', '"octeontx2"'],
+	['RTE_MAX_NUMA_NODES', 1],
+	['RTE_MAX_LCORE', 24],
+	['RTE_EAL_IGB_UIO', false],
+	['RTE_USE_C11_MEM_MODEL', true]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -96,7 +102,8 @@ machine_args_cavium = [
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
 	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
-	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra],
+	['0xb2', ['-mcpu=octeontx2'], flags_octeontx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-octeontx2-linux-gcc b/config/defconfig_arm64-octeontx2-linux-gcc
new file mode 120000
index 000000000..e25150531
--- /dev/null
+++ b/config/defconfig_arm64-octeontx2-linux-gcc
@@ -0,0 +1 @@
+defconfig_arm64-octeontx2-linuxapp-gcc
\ No newline at end of file
diff --git a/config/defconfig_arm64-octeontx2-linuxapp-gcc b/config/defconfig_arm64-octeontx2-linuxapp-gcc
new file mode 100644
index 000000000..9eae84538
--- /dev/null
+++ b/config/defconfig_arm64-octeontx2-linuxapp-gcc
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linux-gcc"
+
+CONFIG_RTE_MACHINE="octeontx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=128
+CONFIG_RTE_MAX_NUMA_NODES=1
+CONFIG_RTE_MAX_LCORE=24
+
+# Doesn't support NUMA
+CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
+CONFIG_RTE_LIBRTE_VHOST_NUMA=n
+
+# Recommend to use VFIO as co-processors needs SMMU/IOMMU
+CONFIG_RTE_EAL_IGB_UIO=n
diff --git a/mk/machine/octeontx2/rte.vars.mk b/mk/machine/octeontx2/rte.vars.mk
new file mode 100644
index 000000000..cbec7f14d
--- /dev/null
+++ b/mk/machine/octeontx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=-mcpu=armv8.2-a+crc+crypto+lse)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)
-- 
2.21.0

[dpdk-dev] [PATCH v6 4/4] config: add octeontx2 machine config

[Jerin Jacob Kollanukkaran]

From: Jerin Jacob <jerinj@marvell.com>

Optimized configuration for Marvell octeontx2 SoC.
Updated meson build to support Marvell octeontx2 SoC.
Added meson cross build target for octeontx2.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
 config/arm/arm64_octeontx2_linux_gcc          | 15 ++++++++
 config/arm/meson.build                        |  9 ++++-
 config/defconfig_arm64-octeontx2-linux-gcc    |  1 +
 config/defconfig_arm64-octeontx2-linuxapp-gcc | 18 ++++++++++
 mk/machine/octeontx2/rte.vars.mk              | 34 +++++++++++++++++++
 5 files changed, 76 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/arm64_octeontx2_linux_gcc
 create mode 120000 config/defconfig_arm64-octeontx2-linux-gcc
 create mode 100644 config/defconfig_arm64-octeontx2-linuxapp-gcc
 create mode 100644 mk/machine/octeontx2/rte.vars.mk

diff --git a/config/arm/arm64_octeontx2_linux_gcc b/config/arm/arm64_octeontx2_linux_gcc
new file mode 100644
index 000000000..7a6429b1b
--- /dev/null
+++ b/config/arm/arm64_octeontx2_linux_gcc
@@ -0,0 +1,15 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x43'
+implementor_pn = '0xb2'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 5c391ed3c..87ae40c24 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -79,6 +79,12 @@ flags_thunderx2_extra = [
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 256],
 	['RTE_USE_C11_MEM_MODEL', true]]
+flags_octeontx2_extra = [
+	['RTE_MACHINE', '"octeontx2"'],
+	['RTE_MAX_NUMA_NODES', 1],
+	['RTE_MAX_LCORE', 24],
+	['RTE_EAL_IGB_UIO', false],
+	['RTE_USE_C11_MEM_MODEL', true]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -96,7 +102,8 @@ machine_args_cavium = [
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
 	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
-	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra],
+	['0xb2', ['-mcpu=octeontx2'], flags_octeontx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-octeontx2-linux-gcc b/config/defconfig_arm64-octeontx2-linux-gcc
new file mode 120000
index 000000000..e25150531
--- /dev/null
+++ b/config/defconfig_arm64-octeontx2-linux-gcc
@@ -0,0 +1 @@
+defconfig_arm64-octeontx2-linuxapp-gcc
\ No newline at end of file
diff --git a/config/defconfig_arm64-octeontx2-linuxapp-gcc b/config/defconfig_arm64-octeontx2-linuxapp-gcc
new file mode 100644
index 000000000..9eae84538
--- /dev/null
+++ b/config/defconfig_arm64-octeontx2-linuxapp-gcc
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linux-gcc"
+
+CONFIG_RTE_MACHINE="octeontx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=128
+CONFIG_RTE_MAX_NUMA_NODES=1
+CONFIG_RTE_MAX_LCORE=24
+
+# Doesn't support NUMA
+CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
+CONFIG_RTE_LIBRTE_VHOST_NUMA=n
+
+# Recommend to use VFIO as co-processors needs SMMU/IOMMU
+CONFIG_RTE_EAL_IGB_UIO=n
diff --git a/mk/machine/octeontx2/rte.vars.mk b/mk/machine/octeontx2/rte.vars.mk
new file mode 100644
index 000000000..cbec7f14d
--- /dev/null
+++ b/mk/machine/octeontx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=-mcpu=armv8.2-a+crc+crypto+lse)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)
-- 
2.21.0

Re: [dpdk-dev] [PATCH v6 2/4] meson: add infra to support machine specific flags

[Bruce Richardson]

On Mon, Mar 18, 2019 at 04:50:16PM +0000, Jerin Jacob Kollanukkaran wrote:
> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> 
> Currently, RTE_* flags are set based on the implementer ID but there might
> be some micro arch specific differences from the same vendor
> eg. CACHE_LINESIZE. Add support to set micro arch specific flags.
> 
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> ---
>  config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++-----
>  1 file changed, 32 insertions(+), 5 deletions(-)
> 
This looks ok to me, but I think review and ack from another Arm vendor
would be good to have.

/Bruce

Re: [dpdk-dev] [PATCH v6 2/4] meson: add infra to support machine specific flags

[Bruce Richardson]

On Mon, Mar 18, 2019 at 04:50:16PM +0000, Jerin Jacob Kollanukkaran wrote:
> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> 
> Currently, RTE_* flags are set based on the implementer ID but there might
> be some micro arch specific differences from the same vendor
> eg. CACHE_LINESIZE. Add support to set micro arch specific flags.
> 
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> ---
>  config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++-----
>  1 file changed, 32 insertions(+), 5 deletions(-)
> 
This looks ok to me, but I think review and ack from another Arm vendor
would be good to have.

/Bruce

Re: [dpdk-dev] [PATCH v5 1/4] mk: introduce helper to check valid compiler argument

[Phil Yang (Arm Technology China)]

> -----Original Message-----
> From: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
> Sent: Monday, February 25, 2019 2:11 AM
> To: thomas@monjalon.net
> Cc: dev@dpdk.org; Phil Yang (Arm Technology China) <Phil.Yang@arm.com>;
> bruce.richardson@intel.com; jerinj@marvell.com; Pavan Nikhilesh
> Bhagavatula <pbhagavatula@marvell.com>
> Subject: [dpdk-dev] [PATCH v5 1/4] mk: introduce helper to check valid
> compiler argument
> 
> Introduce rte_cc_has_argument() Makefile helper to check a given argument is
> support by the compiler.
> 
> Example Usage:
> 
> include $(RTE_SDK)/mk/rte.helper.mk
> MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)
> 
> This would allow adding -mcpu=octeontx2 in MACHINE_CFLAGS if it is only
> supported by the compiler. The use case for such scheme is to enable the
> mcpu optimization if the compiler supports else it needs to compile the
> source code without any errors.
> 
> This patch also moves inclusion of toolchain's rte.vars.mk to before the
> machine's rte.vars.mk inclusion to make correct CC available for the cross
> compile case.
> 
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> ---
> 
> Change history of this series:
> 
> v2 Changes:
>  - Add meson build support.
> 
> v3 Changes:
>  - Squash meson build support into config support for thunderx2/octeontx2.
> 
> v4 Changes:
>  - Fix incorrect signoff marrvell -> marvell.
> 
> v5 Changes:
>  - Fix incorrect meson flag parsing(Phil Yang)
>  - Squash meson cross build patch(5/5) into configuration update patches for
>  thunderx2(3/5) and octeontx2(4/5)(Thomas)
>  - Changed octeontx2's march as armv8-a and added the extension required
>    instead of armv8-2a(Phil Yang)
>  - Improved rte_cc_has_argument() implementaion by removing the temp
>    file(Thomas)
> 
> ---
>  mk/rte.helper.mk              | 10 ++++++++++
>  mk/target/generic/rte.vars.mk | 22 +++++++++++-----------
>  2 files changed, 21 insertions(+), 11 deletions(-)  create mode 100644
> mk/rte.helper.mk
> 
> diff --git a/mk/rte.helper.mk b/mk/rte.helper.mk new file mode 100644 index
> 000000000..6e7fd03d7
> --- /dev/null
> +++ b/mk/rte.helper.mk
> @@ -0,0 +1,10 @@
> +# SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2018 Marvell
> +International Ltd
> +
> +# rte_cc_has_argument
> +# Usage: MACHINE_CFLAGS += $(call rte_cc_has_argument, -mno-avx512f) #
> +Return the argument if the argument is supported by the compiler.
> +#
> +define rte_cc_has_argument
> +	$(shell $(CC) -E $(1) -xc /dev/null 1>/dev/null 2>/dev/null && echo
> +$(1)) endef
> diff --git a/mk/target/generic/rte.vars.mk b/mk/target/generic/rte.vars.mk
> index dd149acc9..25a578ad7 100644
> --- a/mk/target/generic/rte.vars.mk
> +++ b/mk/target/generic/rte.vars.mk
> @@ -7,6 +7,17 @@
>  # executive environment.
>  #
> 
> +#
> +# toolchain:
> +#
> +#   - define CC, LD, AR, AS, ...
> +#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
> +#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
> +#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
> +#   - may override any previously defined variable
> +#
> +include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
> +
>  #
>  # machine:
>  #
> @@ -45,17 +56,6 @@ endif
>  #
>  include $(RTE_SDK)/mk/arch/$(RTE_ARCH)/rte.vars.mk
> 
> -#
> -# toolchain:
> -#
> -#   - define CC, LD, AR, AS, ...
> -#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
> -#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
> -#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
> -#   - may override any previously defined variable
> -#
> -include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
> -
>  #
>  # exec-env:
>  #
> --
> 2.20.1

Reviewed-by: Phil Yang <phil.yang@arm.com>
For this patch set.

Thanks,
Phil

Re: [dpdk-dev] [PATCH v5 1/4] mk: introduce helper to check valid compiler argument

[Phil Yang (Arm Technology China)]

> -----Original Message-----
> From: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
> Sent: Monday, February 25, 2019 2:11 AM
> To: thomas@monjalon.net
> Cc: dev@dpdk.org; Phil Yang (Arm Technology China) <Phil.Yang@arm.com>;
> bruce.richardson@intel.com; jerinj@marvell.com; Pavan Nikhilesh
> Bhagavatula <pbhagavatula@marvell.com>
> Subject: [dpdk-dev] [PATCH v5 1/4] mk: introduce helper to check valid
> compiler argument
> 
> Introduce rte_cc_has_argument() Makefile helper to check a given argument is
> support by the compiler.
> 
> Example Usage:
> 
> include $(RTE_SDK)/mk/rte.helper.mk
> MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)
> 
> This would allow adding -mcpu=octeontx2 in MACHINE_CFLAGS if it is only
> supported by the compiler. The use case for such scheme is to enable the
> mcpu optimization if the compiler supports else it needs to compile the
> source code without any errors.
> 
> This patch also moves inclusion of toolchain's rte.vars.mk to before the
> machine's rte.vars.mk inclusion to make correct CC available for the cross
> compile case.
> 
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> ---
> 
> Change history of this series:
> 
> v2 Changes:
>  - Add meson build support.
> 
> v3 Changes:
>  - Squash meson build support into config support for thunderx2/octeontx2.
> 
> v4 Changes:
>  - Fix incorrect signoff marrvell -> marvell.
> 
> v5 Changes:
>  - Fix incorrect meson flag parsing(Phil Yang)
>  - Squash meson cross build patch(5/5) into configuration update patches for
>  thunderx2(3/5) and octeontx2(4/5)(Thomas)
>  - Changed octeontx2's march as armv8-a and added the extension required
>    instead of armv8-2a(Phil Yang)
>  - Improved rte_cc_has_argument() implementaion by removing the temp
>    file(Thomas)
> 
> ---
>  mk/rte.helper.mk              | 10 ++++++++++
>  mk/target/generic/rte.vars.mk | 22 +++++++++++-----------
>  2 files changed, 21 insertions(+), 11 deletions(-)  create mode 100644
> mk/rte.helper.mk
> 
> diff --git a/mk/rte.helper.mk b/mk/rte.helper.mk new file mode 100644 index
> 000000000..6e7fd03d7
> --- /dev/null
> +++ b/mk/rte.helper.mk
> @@ -0,0 +1,10 @@
> +# SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2018 Marvell
> +International Ltd
> +
> +# rte_cc_has_argument
> +# Usage: MACHINE_CFLAGS += $(call rte_cc_has_argument, -mno-avx512f) #
> +Return the argument if the argument is supported by the compiler.
> +#
> +define rte_cc_has_argument
> +	$(shell $(CC) -E $(1) -xc /dev/null 1>/dev/null 2>/dev/null && echo
> +$(1)) endef
> diff --git a/mk/target/generic/rte.vars.mk b/mk/target/generic/rte.vars.mk
> index dd149acc9..25a578ad7 100644
> --- a/mk/target/generic/rte.vars.mk
> +++ b/mk/target/generic/rte.vars.mk
> @@ -7,6 +7,17 @@
>  # executive environment.
>  #
> 
> +#
> +# toolchain:
> +#
> +#   - define CC, LD, AR, AS, ...
> +#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
> +#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
> +#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
> +#   - may override any previously defined variable
> +#
> +include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
> +
>  #
>  # machine:
>  #
> @@ -45,17 +56,6 @@ endif
>  #
>  include $(RTE_SDK)/mk/arch/$(RTE_ARCH)/rte.vars.mk
> 
> -#
> -# toolchain:
> -#
> -#   - define CC, LD, AR, AS, ...
> -#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
> -#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
> -#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
> -#   - may override any previously defined variable
> -#
> -include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
> -
>  #
>  # exec-env:
>  #
> --
> 2.20.1

Reviewed-by: Phil Yang <phil.yang@arm.com>
For this patch set.

Thanks,
Phil

Re: [dpdk-dev] [PATCH v6 2/4] meson: add infra to support machine specific flags

[Thomas Monjalon]

19/03/2019 10:40, Bruce Richardson:
> On Mon, Mar 18, 2019 at 04:50:16PM +0000, Jerin Jacob Kollanukkaran wrote:
> > From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > 
> > Currently, RTE_* flags are set based on the implementer ID but there might
> > be some micro arch specific differences from the same vendor
> > eg. CACHE_LINESIZE. Add support to set micro arch specific flags.
> > 
> > Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> > ---
> >  config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++-----
> >  1 file changed, 32 insertions(+), 5 deletions(-)
> > 
> This looks ok to me, but I think review and ack from another Arm vendor
> would be good to have.

Adding Cc's for more reviews

Re: [dpdk-dev] [PATCH v6 2/4] meson: add infra to support machine specific flags

[Thomas Monjalon]

19/03/2019 10:40, Bruce Richardson:
> On Mon, Mar 18, 2019 at 04:50:16PM +0000, Jerin Jacob Kollanukkaran wrote:
> > From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > 
> > Currently, RTE_* flags are set based on the implementer ID but there might
> > be some micro arch specific differences from the same vendor
> > eg. CACHE_LINESIZE. Add support to set micro arch specific flags.
> > 
> > Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> > ---
> >  config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++-----
> >  1 file changed, 32 insertions(+), 5 deletions(-)
> > 
> This looks ok to me, but I think review and ack from another Arm vendor
> would be good to have.

Adding Cc's for more reviews

Re: [dpdk-dev] [PATCH v6 3/4] config: add thunderx2 machine config

[Gavin Hu (Arm Technology China)]

> -----Original Message-----
> From: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
> Sent: Tuesday, March 19, 2019 12:50 AM
> To: thomas@monjalon.net
> Cc: dev@dpdk.org; Gavin Hu (Arm Technology China) <Gavin.Hu@arm.com>;
> jerinj@marvell.com; Pavan Nikhilesh Bhagavatula
> <pbhagavatula@marvell.com>
> Subject: [dpdk-dev] [PATCH v6 3/4] config: add thunderx2 machine config
>
> From: Jerin Jacob <jerinj@marvell.com>
>
> Optimized configuration for Marvell thunderx2 SoC.
> Updated meson build to support Marvell thunderx2 SoC.
> Added meson cross compile target.
>
> Product details are here:
>
> https://www.marvell.com/server-processors/thunderx2-arm-processors/
>
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> ---
>  config/arm/arm64_thunderx2_linux_gcc          | 15 ++++++++
>  config/arm/meson.build                        |  9 ++++-
>  config/defconfig_arm64-thunderx2-linux-gcc    |  1 +
>  config/defconfig_arm64-thunderx2-linuxapp-gcc | 11 ++++++
>  mk/machine/thunderx2/rte.vars.mk              | 34 +++++++++++++++++++
>  5 files changed, 69 insertions(+), 1 deletion(-)
>  create mode 100644 config/arm/arm64_thunderx2_linux_gcc
>  create mode 120000 config/defconfig_arm64-thunderx2-linux-gcc
>  create mode 100644 config/defconfig_arm64-thunderx2-linuxapp-gcc
>  create mode 100644 mk/machine/thunderx2/rte.vars.mk
>
> diff --git a/config/arm/arm64_thunderx2_linux_gcc
> b/config/arm/arm64_thunderx2_linux_gcc
> new file mode 100644
> index 000000000..48b07a40c
> --- /dev/null
> +++ b/config/arm/arm64_thunderx2_linux_gcc
> @@ -0,0 +1,15 @@
> +[binaries]
> +c = 'aarch64-linux-gnu-gcc'
> +cpp = 'aarch64-linux-gnu-cpp'
> +ar = 'aarch64-linux-gnu-gcc-ar'
> +strip = 'aarch64-linux-gnu-strip'
> +
> +[host_machine]
> +system = 'linux'
> +cpu_family = 'aarch64'
> +cpu = 'armv8-a'
> +endian = 'little'
> +
> +[properties]
> +implementor_id = '0x43'
> +implementor_pn = '0xaf'
> diff --git a/config/arm/meson.build b/config/arm/meson.build
> index 3db6d6445..5c391ed3c 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -73,6 +73,12 @@ flags_default_extra = []
>  flags_thunderx_extra = [
>  ['RTE_MACHINE', '"thunderx"'],
>  ['RTE_USE_C11_MEM_MODEL', false]]
> +flags_thunderx2_extra = [
> +['RTE_MACHINE', '"thunderx2"'],
> +['RTE_CACHE_LINE_SIZE', 64],
> +['RTE_MAX_NUMA_NODES', 2],
> +['RTE_MAX_LCORE', 256],
> +['RTE_USE_C11_MEM_MODEL', true]]
>
>  machine_args_generic = [
>  ['default', ['-march=armv8-a+crc+crypto']],
> @@ -89,7 +95,8 @@ machine_args_cavium = [
>  ['native', ['-march=native']],
>  ['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
>  ['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
> -['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
> +['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
> +['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
>
>  ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
>  impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
> diff --git a/config/defconfig_arm64-thunderx2-linux-gcc
> b/config/defconfig_arm64-thunderx2-linux-gcc
> new file mode 120000
> index 000000000..b40a760b1
> --- /dev/null
> +++ b/config/defconfig_arm64-thunderx2-linux-gcc
> @@ -0,0 +1 @@
> +defconfig_arm64-thunderx2-linuxapp-gcc
> \ No newline at end of file
> diff --git a/config/defconfig_arm64-thunderx2-linuxapp-gcc
> b/config/defconfig_arm64-thunderx2-linuxapp-gcc
> new file mode 100644
> index 000000000..cc5c64ba0
> --- /dev/null
> +++ b/config/defconfig_arm64-thunderx2-linuxapp-gcc
> @@ -0,0 +1,11 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(c) 2018 Marvell International Ltd
> +#
> +
> +#include "defconfig_arm64-armv8a-linux-gcc"
> +
> +CONFIG_RTE_MACHINE="thunderx2"
> +
> +CONFIG_RTE_CACHE_LINE_SIZE=64
> +CONFIG_RTE_MAX_NUMA_NODES=2
> +CONFIG_RTE_MAX_LCORE=256
> diff --git a/mk/machine/thunderx2/rte.vars.mk
> b/mk/machine/thunderx2/rte.vars.mk
> new file mode 100644
> index 000000000..b80dc8680
> --- /dev/null
> +++ b/mk/machine/thunderx2/rte.vars.mk
> @@ -0,0 +1,34 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(c) 2018 Marvell International Ltd
> +#
> +
> +#
> +# machine:
> +#
> +#   - can define ARCH variable (overridden by cmdline value)
> +#   - can define CROSS variable (overridden by cmdline value)
> +#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
> +#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
> +#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
> +#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
> +#     overrides the one defined in arch.
> +#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
> +#     overrides the one defined in arch.
> +#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
> +#     overrides the one defined in arch.
> +#   - may override any previously defined variable
> +#
> +
> +# ARCH =
> +# CROSS =
> +# MACHINE_CFLAGS =
> +# MACHINE_LDFLAGS =
> +# MACHINE_ASFLAGS =
> +# CPU_CFLAGS =
> +# CPU_LDFLAGS =
> +# CPU_ASFLAGS =
> +
> +include $(RTE_SDK)/mk/rte.helper.mk
> +
> +MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.1-
> a+crc+crypto)
> +MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=thunderx2t99)
> --
> 2.21.0

Reviewed-by: Gavin Hu <gavin.hu@arm.com>

IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

Re: [dpdk-dev] [PATCH v6 3/4] config: add thunderx2 machine config

[Gavin Hu (Arm Technology China)]

> -----Original Message-----
> From: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
> Sent: Tuesday, March 19, 2019 12:50 AM
> To: thomas@monjalon.net
> Cc: dev@dpdk.org; Gavin Hu (Arm Technology China) <Gavin.Hu@arm.com>;
> jerinj@marvell.com; Pavan Nikhilesh Bhagavatula
> <pbhagavatula@marvell.com>
> Subject: [dpdk-dev] [PATCH v6 3/4] config: add thunderx2 machine config
>
> From: Jerin Jacob <jerinj@marvell.com>
>
> Optimized configuration for Marvell thunderx2 SoC.
> Updated meson build to support Marvell thunderx2 SoC.
> Added meson cross compile target.
>
> Product details are here:
>
> https://www.marvell.com/server-processors/thunderx2-arm-processors/
>
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> ---
>  config/arm/arm64_thunderx2_linux_gcc          | 15 ++++++++
>  config/arm/meson.build                        |  9 ++++-
>  config/defconfig_arm64-thunderx2-linux-gcc    |  1 +
>  config/defconfig_arm64-thunderx2-linuxapp-gcc | 11 ++++++
>  mk/machine/thunderx2/rte.vars.mk              | 34 +++++++++++++++++++
>  5 files changed, 69 insertions(+), 1 deletion(-)
>  create mode 100644 config/arm/arm64_thunderx2_linux_gcc
>  create mode 120000 config/defconfig_arm64-thunderx2-linux-gcc
>  create mode 100644 config/defconfig_arm64-thunderx2-linuxapp-gcc
>  create mode 100644 mk/machine/thunderx2/rte.vars.mk
>
> diff --git a/config/arm/arm64_thunderx2_linux_gcc
> b/config/arm/arm64_thunderx2_linux_gcc
> new file mode 100644
> index 000000000..48b07a40c
> --- /dev/null
> +++ b/config/arm/arm64_thunderx2_linux_gcc
> @@ -0,0 +1,15 @@
> +[binaries]
> +c = 'aarch64-linux-gnu-gcc'
> +cpp = 'aarch64-linux-gnu-cpp'
> +ar = 'aarch64-linux-gnu-gcc-ar'
> +strip = 'aarch64-linux-gnu-strip'
> +
> +[host_machine]
> +system = 'linux'
> +cpu_family = 'aarch64'
> +cpu = 'armv8-a'
> +endian = 'little'
> +
> +[properties]
> +implementor_id = '0x43'
> +implementor_pn = '0xaf'
> diff --git a/config/arm/meson.build b/config/arm/meson.build
> index 3db6d6445..5c391ed3c 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -73,6 +73,12 @@ flags_default_extra = []
>  flags_thunderx_extra = [
>  ['RTE_MACHINE', '"thunderx"'],
>  ['RTE_USE_C11_MEM_MODEL', false]]
> +flags_thunderx2_extra = [
> +['RTE_MACHINE', '"thunderx2"'],
> +['RTE_CACHE_LINE_SIZE', 64],
> +['RTE_MAX_NUMA_NODES', 2],
> +['RTE_MAX_LCORE', 256],
> +['RTE_USE_C11_MEM_MODEL', true]]
>
>  machine_args_generic = [
>  ['default', ['-march=armv8-a+crc+crypto']],
> @@ -89,7 +95,8 @@ machine_args_cavium = [
>  ['native', ['-march=native']],
>  ['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
>  ['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
> -['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
> +['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
> +['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
>
>  ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
>  impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
> diff --git a/config/defconfig_arm64-thunderx2-linux-gcc
> b/config/defconfig_arm64-thunderx2-linux-gcc
> new file mode 120000
> index 000000000..b40a760b1
> --- /dev/null
> +++ b/config/defconfig_arm64-thunderx2-linux-gcc
> @@ -0,0 +1 @@
> +defconfig_arm64-thunderx2-linuxapp-gcc
> \ No newline at end of file
> diff --git a/config/defconfig_arm64-thunderx2-linuxapp-gcc
> b/config/defconfig_arm64-thunderx2-linuxapp-gcc
> new file mode 100644
> index 000000000..cc5c64ba0
> --- /dev/null
> +++ b/config/defconfig_arm64-thunderx2-linuxapp-gcc
> @@ -0,0 +1,11 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(c) 2018 Marvell International Ltd
> +#
> +
> +#include "defconfig_arm64-armv8a-linux-gcc"
> +
> +CONFIG_RTE_MACHINE="thunderx2"
> +
> +CONFIG_RTE_CACHE_LINE_SIZE=64
> +CONFIG_RTE_MAX_NUMA_NODES=2
> +CONFIG_RTE_MAX_LCORE=256
> diff --git a/mk/machine/thunderx2/rte.vars.mk
> b/mk/machine/thunderx2/rte.vars.mk
> new file mode 100644
> index 000000000..b80dc8680
> --- /dev/null
> +++ b/mk/machine/thunderx2/rte.vars.mk
> @@ -0,0 +1,34 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(c) 2018 Marvell International Ltd
> +#
> +
> +#
> +# machine:
> +#
> +#   - can define ARCH variable (overridden by cmdline value)
> +#   - can define CROSS variable (overridden by cmdline value)
> +#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
> +#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
> +#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
> +#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
> +#     overrides the one defined in arch.
> +#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
> +#     overrides the one defined in arch.
> +#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
> +#     overrides the one defined in arch.
> +#   - may override any previously defined variable
> +#
> +
> +# ARCH =
> +# CROSS =
> +# MACHINE_CFLAGS =
> +# MACHINE_LDFLAGS =
> +# MACHINE_ASFLAGS =
> +# CPU_CFLAGS =
> +# CPU_LDFLAGS =
> +# CPU_ASFLAGS =
> +
> +include $(RTE_SDK)/mk/rte.helper.mk
> +
> +MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.1-
> a+crc+crypto)
> +MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=thunderx2t99)
> --
> 2.21.0

Reviewed-by: Gavin Hu <gavin.hu@arm.com>

IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

Re: [dpdk-dev] [PATCH v6 4/4] config: add octeontx2 machine config

[Gavin Hu (Arm Technology China)]

> -----Original Message-----
> From: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
> Sent: Tuesday, March 19, 2019 12:50 AM
> To: thomas@monjalon.net
> Cc: dev@dpdk.org; Gavin Hu (Arm Technology China) <Gavin.Hu@arm.com>;
> jerinj@marvell.com; Pavan Nikhilesh Bhagavatula
> <pbhagavatula@marvell.com>
> Subject: [dpdk-dev] [PATCH v6 4/4] config: add octeontx2 machine config
>
> From: Jerin Jacob <jerinj@marvell.com>
>
> Optimized configuration for Marvell octeontx2 SoC.
> Updated meson build to support Marvell octeontx2 SoC.
> Added meson cross build target for octeontx2.
>
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> ---
>  config/arm/arm64_octeontx2_linux_gcc          | 15 ++++++++
>  config/arm/meson.build                        |  9 ++++-
>  config/defconfig_arm64-octeontx2-linux-gcc    |  1 +
>  config/defconfig_arm64-octeontx2-linuxapp-gcc | 18 ++++++++++
>  mk/machine/octeontx2/rte.vars.mk              | 34 +++++++++++++++++++
>  5 files changed, 76 insertions(+), 1 deletion(-)
>  create mode 100644 config/arm/arm64_octeontx2_linux_gcc
>  create mode 120000 config/defconfig_arm64-octeontx2-linux-gcc
>  create mode 100644 config/defconfig_arm64-octeontx2-linuxapp-gcc
>  create mode 100644 mk/machine/octeontx2/rte.vars.mk
>
> diff --git a/config/arm/arm64_octeontx2_linux_gcc
> b/config/arm/arm64_octeontx2_linux_gcc
> new file mode 100644
> index 000000000..7a6429b1b
> --- /dev/null
> +++ b/config/arm/arm64_octeontx2_linux_gcc
> @@ -0,0 +1,15 @@
> +[binaries]
> +c = 'aarch64-linux-gnu-gcc'
> +cpp = 'aarch64-linux-gnu-cpp'
> +ar = 'aarch64-linux-gnu-gcc-ar'
> +strip = 'aarch64-linux-gnu-strip'
> +
> +[host_machine]
> +system = 'linux'
> +cpu_family = 'aarch64'
> +cpu = 'armv8-a'
> +endian = 'little'
> +
> +[properties]
> +implementor_id = '0x43'
> +implementor_pn = '0xb2'
> diff --git a/config/arm/meson.build b/config/arm/meson.build
> index 5c391ed3c..87ae40c24 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -79,6 +79,12 @@ flags_thunderx2_extra = [
>  ['RTE_MAX_NUMA_NODES', 2],
>  ['RTE_MAX_LCORE', 256],
>  ['RTE_USE_C11_MEM_MODEL', true]]
> +flags_octeontx2_extra = [
> +['RTE_MACHINE', '"octeontx2"'],
> +['RTE_MAX_NUMA_NODES', 1],
> +['RTE_MAX_LCORE', 24],
> +['RTE_EAL_IGB_UIO', false],
> +['RTE_USE_C11_MEM_MODEL', true]]
>
>  machine_args_generic = [
>  ['default', ['-march=armv8-a+crc+crypto']],
> @@ -96,7 +102,8 @@ machine_args_cavium = [
>  ['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
>  ['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
>  ['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
> -['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
> +['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra],
> +['0xb2', ['-mcpu=octeontx2'], flags_octeontx2_extra]]
>
>  ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
>  impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
> diff --git a/config/defconfig_arm64-octeontx2-linux-gcc
> b/config/defconfig_arm64-octeontx2-linux-gcc
> new file mode 120000
> index 000000000..e25150531
> --- /dev/null
> +++ b/config/defconfig_arm64-octeontx2-linux-gcc
> @@ -0,0 +1 @@
> +defconfig_arm64-octeontx2-linuxapp-gcc
> \ No newline at end of file
> diff --git a/config/defconfig_arm64-octeontx2-linuxapp-gcc
> b/config/defconfig_arm64-octeontx2-linuxapp-gcc
> new file mode 100644
> index 000000000..9eae84538
> --- /dev/null
> +++ b/config/defconfig_arm64-octeontx2-linuxapp-gcc
> @@ -0,0 +1,18 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(c) 2018 Marvell International Ltd
> +#
> +
> +#include "defconfig_arm64-armv8a-linux-gcc"
> +
> +CONFIG_RTE_MACHINE="octeontx2"
> +
> +CONFIG_RTE_CACHE_LINE_SIZE=128
> +CONFIG_RTE_MAX_NUMA_NODES=1
> +CONFIG_RTE_MAX_LCORE=24
> +
> +# Doesn't support NUMA
> +CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
> +CONFIG_RTE_LIBRTE_VHOST_NUMA=n
> +
> +# Recommend to use VFIO as co-processors needs SMMU/IOMMU
> +CONFIG_RTE_EAL_IGB_UIO=n
> diff --git a/mk/machine/octeontx2/rte.vars.mk
> b/mk/machine/octeontx2/rte.vars.mk
> new file mode 100644
> index 000000000..cbec7f14d
> --- /dev/null
> +++ b/mk/machine/octeontx2/rte.vars.mk
> @@ -0,0 +1,34 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(c) 2018 Marvell International Ltd
> +#
> +
> +#
> +# machine:
> +#
> +#   - can define ARCH variable (overridden by cmdline value)
> +#   - can define CROSS variable (overridden by cmdline value)
> +#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
> +#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
> +#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
> +#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
> +#     overrides the one defined in arch.
> +#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
> +#     overrides the one defined in arch.
> +#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
> +#     overrides the one defined in arch.
> +#   - may override any previously defined variable
> +#
> +
> +# ARCH =
> +# CROSS =
> +# MACHINE_CFLAGS =
> +# MACHINE_LDFLAGS =
> +# MACHINE_ASFLAGS =
> +# CPU_CFLAGS =
> +# CPU_LDFLAGS =
> +# CPU_ASFLAGS =
> +
> +include $(RTE_SDK)/mk/rte.helper.mk
> +
> +MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=-
> mcpu=armv8.2-a+crc+crypto+lse)
> +MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)
> --
> 2.21.0

Reviewed-by: Gavin Hu <gavin.hu@arm.com>
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

Re: [dpdk-dev] [PATCH v6 4/4] config: add octeontx2 machine config

[Gavin Hu (Arm Technology China)]

> -----Original Message-----
> From: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
> Sent: Tuesday, March 19, 2019 12:50 AM
> To: thomas@monjalon.net
> Cc: dev@dpdk.org; Gavin Hu (Arm Technology China) <Gavin.Hu@arm.com>;
> jerinj@marvell.com; Pavan Nikhilesh Bhagavatula
> <pbhagavatula@marvell.com>
> Subject: [dpdk-dev] [PATCH v6 4/4] config: add octeontx2 machine config
>
> From: Jerin Jacob <jerinj@marvell.com>
>
> Optimized configuration for Marvell octeontx2 SoC.
> Updated meson build to support Marvell octeontx2 SoC.
> Added meson cross build target for octeontx2.
>
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> ---
>  config/arm/arm64_octeontx2_linux_gcc          | 15 ++++++++
>  config/arm/meson.build                        |  9 ++++-
>  config/defconfig_arm64-octeontx2-linux-gcc    |  1 +
>  config/defconfig_arm64-octeontx2-linuxapp-gcc | 18 ++++++++++
>  mk/machine/octeontx2/rte.vars.mk              | 34 +++++++++++++++++++
>  5 files changed, 76 insertions(+), 1 deletion(-)
>  create mode 100644 config/arm/arm64_octeontx2_linux_gcc
>  create mode 120000 config/defconfig_arm64-octeontx2-linux-gcc
>  create mode 100644 config/defconfig_arm64-octeontx2-linuxapp-gcc
>  create mode 100644 mk/machine/octeontx2/rte.vars.mk
>
> diff --git a/config/arm/arm64_octeontx2_linux_gcc
> b/config/arm/arm64_octeontx2_linux_gcc
> new file mode 100644
> index 000000000..7a6429b1b
> --- /dev/null
> +++ b/config/arm/arm64_octeontx2_linux_gcc
> @@ -0,0 +1,15 @@
> +[binaries]
> +c = 'aarch64-linux-gnu-gcc'
> +cpp = 'aarch64-linux-gnu-cpp'
> +ar = 'aarch64-linux-gnu-gcc-ar'
> +strip = 'aarch64-linux-gnu-strip'
> +
> +[host_machine]
> +system = 'linux'
> +cpu_family = 'aarch64'
> +cpu = 'armv8-a'
> +endian = 'little'
> +
> +[properties]
> +implementor_id = '0x43'
> +implementor_pn = '0xb2'
> diff --git a/config/arm/meson.build b/config/arm/meson.build
> index 5c391ed3c..87ae40c24 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -79,6 +79,12 @@ flags_thunderx2_extra = [
>  ['RTE_MAX_NUMA_NODES', 2],
>  ['RTE_MAX_LCORE', 256],
>  ['RTE_USE_C11_MEM_MODEL', true]]
> +flags_octeontx2_extra = [
> +['RTE_MACHINE', '"octeontx2"'],
> +['RTE_MAX_NUMA_NODES', 1],
> +['RTE_MAX_LCORE', 24],
> +['RTE_EAL_IGB_UIO', false],
> +['RTE_USE_C11_MEM_MODEL', true]]
>
>  machine_args_generic = [
>  ['default', ['-march=armv8-a+crc+crypto']],
> @@ -96,7 +102,8 @@ machine_args_cavium = [
>  ['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
>  ['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
>  ['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
> -['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
> +['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra],
> +['0xb2', ['-mcpu=octeontx2'], flags_octeontx2_extra]]
>
>  ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
>  impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
> diff --git a/config/defconfig_arm64-octeontx2-linux-gcc
> b/config/defconfig_arm64-octeontx2-linux-gcc
> new file mode 120000
> index 000000000..e25150531
> --- /dev/null
> +++ b/config/defconfig_arm64-octeontx2-linux-gcc
> @@ -0,0 +1 @@
> +defconfig_arm64-octeontx2-linuxapp-gcc
> \ No newline at end of file
> diff --git a/config/defconfig_arm64-octeontx2-linuxapp-gcc
> b/config/defconfig_arm64-octeontx2-linuxapp-gcc
> new file mode 100644
> index 000000000..9eae84538
> --- /dev/null
> +++ b/config/defconfig_arm64-octeontx2-linuxapp-gcc
> @@ -0,0 +1,18 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(c) 2018 Marvell International Ltd
> +#
> +
> +#include "defconfig_arm64-armv8a-linux-gcc"
> +
> +CONFIG_RTE_MACHINE="octeontx2"
> +
> +CONFIG_RTE_CACHE_LINE_SIZE=128
> +CONFIG_RTE_MAX_NUMA_NODES=1
> +CONFIG_RTE_MAX_LCORE=24
> +
> +# Doesn't support NUMA
> +CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
> +CONFIG_RTE_LIBRTE_VHOST_NUMA=n
> +
> +# Recommend to use VFIO as co-processors needs SMMU/IOMMU
> +CONFIG_RTE_EAL_IGB_UIO=n
> diff --git a/mk/machine/octeontx2/rte.vars.mk
> b/mk/machine/octeontx2/rte.vars.mk
> new file mode 100644
> index 000000000..cbec7f14d
> --- /dev/null
> +++ b/mk/machine/octeontx2/rte.vars.mk
> @@ -0,0 +1,34 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(c) 2018 Marvell International Ltd
> +#
> +
> +#
> +# machine:
> +#
> +#   - can define ARCH variable (overridden by cmdline value)
> +#   - can define CROSS variable (overridden by cmdline value)
> +#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
> +#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
> +#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
> +#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
> +#     overrides the one defined in arch.
> +#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
> +#     overrides the one defined in arch.
> +#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
> +#     overrides the one defined in arch.
> +#   - may override any previously defined variable
> +#
> +
> +# ARCH =
> +# CROSS =
> +# MACHINE_CFLAGS =
> +# MACHINE_LDFLAGS =
> +# MACHINE_ASFLAGS =
> +# CPU_CFLAGS =
> +# CPU_LDFLAGS =
> +# CPU_ASFLAGS =
> +
> +include $(RTE_SDK)/mk/rte.helper.mk
> +
> +MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=-
> mcpu=armv8.2-a+crc+crypto+lse)
> +MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)
> --
> 2.21.0

Reviewed-by: Gavin Hu <gavin.hu@arm.com>
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

Re: [dpdk-dev] [PATCH v6 3/4] config: add thunderx2 machine config

[Thomas Monjalon]

18/03/2019 17:50, Jerin Jacob Kollanukkaran:
> From: Jerin Jacob <jerinj@marvell.com>
> 
> Optimized configuration for Marvell thunderx2 SoC.
> Updated meson build to support Marvell thunderx2 SoC.
> Added meson cross compile target.
> 
> Product details are here:
> 
> https://www.marvell.com/server-processors/thunderx2-arm-processors/
> 
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>

I see a very strange error when compiling with meson:

In file included from /usr/include/inttypes.h:27,
                 from /usr/include/pcap/pcap-inttypes.h:114,
                 from /usr/include/pcap/pcap.h:74,
                 from /usr/include/pcap.h:43,
                 from ../drivers/net/pcap/rte_eth_pcap.c:19:
/usr/include/stdint.h:109: error: "__INT64_C" redefined [-Werror]

Could we try to debug it and merge these patches in -rc2?

Re: [dpdk-dev] [PATCH v6 3/4] config: add thunderx2 machine config

[Thomas Monjalon]

18/03/2019 17:50, Jerin Jacob Kollanukkaran:
> From: Jerin Jacob <jerinj@marvell.com>
> 
> Optimized configuration for Marvell thunderx2 SoC.
> Updated meson build to support Marvell thunderx2 SoC.
> Added meson cross compile target.
> 
> Product details are here:
> 
> https://www.marvell.com/server-processors/thunderx2-arm-processors/
> 
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>

I see a very strange error when compiling with meson:

In file included from /usr/include/inttypes.h:27,
                 from /usr/include/pcap/pcap-inttypes.h:114,
                 from /usr/include/pcap/pcap.h:74,
                 from /usr/include/pcap.h:43,
                 from ../drivers/net/pcap/rte_eth_pcap.c:19:
/usr/include/stdint.h:109: error: "__INT64_C" redefined [-Werror]

Could we try to debug it and merge these patches in -rc2?

Re: [dpdk-dev] [PATCH v6 3/4] config: add thunderx2 machine config

[Jerin Jacob Kollanukkaran]

> -----Original Message-----
> From: Thomas Monjalon <thomas@monjalon.net>
> Sent: Friday, April 5, 2019 11:43 PM
> To: Jerin Jacob Kollanukkaran <jerinj@marvell.com>; Pavan Nikhilesh
> Bhagavatula <pbhagavatula@marvell.com>
> Cc: dev@dpdk.org; gavin.hu@arm.com
> Subject: Re: [dpdk-dev] [PATCH v6 3/4] config: add thunderx2 machine
> config
> 
> 18/03/2019 17:50, Jerin Jacob Kollanukkaran:
> > From: Jerin Jacob <jerinj@marvell.com>
> >
> > Optimized configuration for Marvell thunderx2 SoC.
> > Updated meson build to support Marvell thunderx2 SoC.
> > Added meson cross compile target.
> >
> > Product details are here:
> >
> > https://www.marvell.com/server-processors/thunderx2-arm-processors/
> >
> > Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> > Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> 
> I see a very strange error when compiling with meson:
> 
> In file included from /usr/include/inttypes.h:27,
>                  from /usr/include/pcap/pcap-inttypes.h:114,
>                  from /usr/include/pcap/pcap.h:74,
>                  from /usr/include/pcap.h:43,
>                  from ../drivers/net/pcap/rte_eth_pcap.c:19:
> /usr/include/stdint.h:109: error: "__INT64_C" redefined [-Werror]
> 
> Could we try to debug it and merge these patches in -rc2?


Could you please give more details to reproduce this issue
Compiler version - gcc or clang version? 
Build - Native or cross ?
Build OS ?
Meson and Ninja - Versions?
The command use to reproduce this issue as we are not able to get this Issue in our local setup? 


> 

Re: [dpdk-dev] [PATCH v6 3/4] config: add thunderx2 machine config

[Jerin Jacob Kollanukkaran]

> -----Original Message-----
> From: Thomas Monjalon <thomas@monjalon.net>
> Sent: Friday, April 5, 2019 11:43 PM
> To: Jerin Jacob Kollanukkaran <jerinj@marvell.com>; Pavan Nikhilesh
> Bhagavatula <pbhagavatula@marvell.com>
> Cc: dev@dpdk.org; gavin.hu@arm.com
> Subject: Re: [dpdk-dev] [PATCH v6 3/4] config: add thunderx2 machine
> config
> 
> 18/03/2019 17:50, Jerin Jacob Kollanukkaran:
> > From: Jerin Jacob <jerinj@marvell.com>
> >
> > Optimized configuration for Marvell thunderx2 SoC.
> > Updated meson build to support Marvell thunderx2 SoC.
> > Added meson cross compile target.
> >
> > Product details are here:
> >
> > https://www.marvell.com/server-processors/thunderx2-arm-processors/
> >
> > Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> > Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> 
> I see a very strange error when compiling with meson:
> 
> In file included from /usr/include/inttypes.h:27,
>                  from /usr/include/pcap/pcap-inttypes.h:114,
>                  from /usr/include/pcap/pcap.h:74,
>                  from /usr/include/pcap.h:43,
>                  from ../drivers/net/pcap/rte_eth_pcap.c:19:
> /usr/include/stdint.h:109: error: "__INT64_C" redefined [-Werror]
> 
> Could we try to debug it and merge these patches in -rc2?


Could you please give more details to reproduce this issue
Compiler version - gcc or clang version? 
Build - Native or cross ?
Build OS ?
Meson and Ninja - Versions?
The command use to reproduce this issue as we are not able to get this Issue in our local setup? 


> 

Re: [dpdk-dev] [PATCH v6 3/4] config: add thunderx2 machine config

[Thomas Monjalon]

05/04/2019 20:47, Jerin Jacob Kollanukkaran:
> From: Thomas Monjalon <thomas@monjalon.net>
> > 18/03/2019 17:50, Jerin Jacob Kollanukkaran:
> > > From: Jerin Jacob <jerinj@marvell.com>
> > >
> > > Optimized configuration for Marvell thunderx2 SoC.
> > > Updated meson build to support Marvell thunderx2 SoC.
> > > Added meson cross compile target.
> > >
> > > Product details are here:
> > >
> > > https://www.marvell.com/server-processors/thunderx2-arm-processors/
> > >
> > > Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> > > Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > 
> > I see a very strange error when compiling with meson:
> > 
> > In file included from /usr/include/inttypes.h:27,
> >                  from /usr/include/pcap/pcap-inttypes.h:114,
> >                  from /usr/include/pcap/pcap.h:74,
> >                  from /usr/include/pcap.h:43,
> >                  from ../drivers/net/pcap/rte_eth_pcap.c:19:
> > /usr/include/stdint.h:109: error: "__INT64_C" redefined [-Werror]
> > 
> > Could we try to debug it and merge these patches in -rc2?
> 
> Could you please give more details to reproduce this issue

First of all, we need to understand why it is getting pcap includes
from the native system while compiling for thunderx2.

> Compiler version - gcc or clang version?

aarch64-linux-gnu-gcc (GCC) 8.3.0

> Build - Native or cross ?

cross-compilation

> Build OS ?

My host is an archlinux

> Meson and Ninja - Versions?

meson 0.49.2
ninja 1.9.0

> The command use to reproduce this issue as we are not able to get this Issue in our local setup? 

I just run devtools/test-meson-builds.sh
and it compiles for config/arm/arm64_thunderx_linux_gcc
because I have an Arm toolchain installed.

Re: [dpdk-dev] [PATCH v6 3/4] config: add thunderx2 machine config

[Thomas Monjalon]

05/04/2019 20:47, Jerin Jacob Kollanukkaran:
> From: Thomas Monjalon <thomas@monjalon.net>
> > 18/03/2019 17:50, Jerin Jacob Kollanukkaran:
> > > From: Jerin Jacob <jerinj@marvell.com>
> > >
> > > Optimized configuration for Marvell thunderx2 SoC.
> > > Updated meson build to support Marvell thunderx2 SoC.
> > > Added meson cross compile target.
> > >
> > > Product details are here:
> > >
> > > https://www.marvell.com/server-processors/thunderx2-arm-processors/
> > >
> > > Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> > > Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > 
> > I see a very strange error when compiling with meson:
> > 
> > In file included from /usr/include/inttypes.h:27,
> >                  from /usr/include/pcap/pcap-inttypes.h:114,
> >                  from /usr/include/pcap/pcap.h:74,
> >                  from /usr/include/pcap.h:43,
> >                  from ../drivers/net/pcap/rte_eth_pcap.c:19:
> > /usr/include/stdint.h:109: error: "__INT64_C" redefined [-Werror]
> > 
> > Could we try to debug it and merge these patches in -rc2?
> 
> Could you please give more details to reproduce this issue

First of all, we need to understand why it is getting pcap includes
from the native system while compiling for thunderx2.

> Compiler version - gcc or clang version?

aarch64-linux-gnu-gcc (GCC) 8.3.0

> Build - Native or cross ?

cross-compilation

> Build OS ?

My host is an archlinux

> Meson and Ninja - Versions?

meson 0.49.2
ninja 1.9.0

> The command use to reproduce this issue as we are not able to get this Issue in our local setup? 

I just run devtools/test-meson-builds.sh
and it compiles for config/arm/arm64_thunderx_linux_gcc
because I have an Arm toolchain installed.

Re: [dpdk-dev] [PATCH v6 3/4] config: add thunderx2 machine config

[Jerin Jacob Kollanukkaran]

On Fri, 2019-04-05 at 21:09 +0200, Thomas Monjalon wrote:
> 05/04/2019 20:47, Jerin Jacob Kollanukkaran:
> > From: Thomas Monjalon <thomas@monjalon.net>
> > > 18/03/2019 17:50, Jerin Jacob Kollanukkaran:
> > > > From: Jerin Jacob <jerinj@marvell.com>
> > > > 
> > > > Optimized configuration for Marvell thunderx2 SoC.
> > > > Updated meson build to support Marvell thunderx2 SoC.
> > > > Added meson cross compile target.
> > > > 
> > > > Product details are here:
> > > > 
> > > > https://www.marvell.com/server-processors/thunderx2-arm-processors/
> > > > 
> > > > Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> > > > Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > > 
> > > I see a very strange error when compiling with meson:
> > > 

cross compiling config files needs an update since
"build: improve pcap dependency handling" changeset.

I will spin another version to fix this.

> > > In file included from /usr/include/inttypes.h:27,
> > >                  from /usr/include/pcap/pcap-inttypes.h:114,
> > >                  from /usr/include/pcap/pcap.h:74,
> > >                  from /usr/include/pcap.h:43,
> > >                  from ../drivers/net/pcap/rte_eth_pcap.c:19:
> > > /usr/include/stdint.h:109: error: "__INT64_C" redefined [-Werror]
> > > 
> > > Could we try to debug it and merge these patches in -rc2?
> > 

Re: [dpdk-dev] [PATCH v6 3/4] config: add thunderx2 machine config

[Jerin Jacob Kollanukkaran]

On Fri, 2019-04-05 at 21:09 +0200, Thomas Monjalon wrote:
> 05/04/2019 20:47, Jerin Jacob Kollanukkaran:
> > From: Thomas Monjalon <thomas@monjalon.net>
> > > 18/03/2019 17:50, Jerin Jacob Kollanukkaran:
> > > > From: Jerin Jacob <jerinj@marvell.com>
> > > > 
> > > > Optimized configuration for Marvell thunderx2 SoC.
> > > > Updated meson build to support Marvell thunderx2 SoC.
> > > > Added meson cross compile target.
> > > > 
> > > > Product details are here:
> > > > 
> > > > https://www.marvell.com/server-processors/thunderx2-arm-processors/
> > > > 
> > > > Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> > > > Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > > 
> > > I see a very strange error when compiling with meson:
> > > 

cross compiling config files needs an update since
"build: improve pcap dependency handling" changeset.

I will spin another version to fix this.

> > > In file included from /usr/include/inttypes.h:27,
> > >                  from /usr/include/pcap/pcap-inttypes.h:114,
> > >                  from /usr/include/pcap/pcap.h:74,
> > >                  from /usr/include/pcap.h:43,
> > >                  from ../drivers/net/pcap/rte_eth_pcap.c:19:
> > > /usr/include/stdint.h:109: error: "__INT64_C" redefined [-Werror]
> > > 
> > > Could we try to debug it and merge these patches in -rc2?
> > 

[dpdk-dev] [PATCH v7 1/4] mk: introduce helper to check valid compiler argument

[jerinjacobk]

From: Jerin Jacob <jerinj@marvell.com>

Introduce rte_cc_has_argument() Makefile helper to
check a given argument is support by the compiler.

Example Usage:

include $(RTE_SDK)/mk/rte.helper.mk
MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)

This would allow adding -mcpu=octeontx2 in MACHINE_CFLAGS
if it is only supported by the compiler. The use case for such
scheme is to enable the mcpu optimization if the compiler
supports else it needs to compile the source code without
any errors.

This patch also moves inclusion of toolchain's rte.vars.mk
to before the machine's rte.vars.mk inclusion to make
correct CC available for the cross compile case.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---

Change history of this series:

v7 Changes:
 - Updated cross compile config files align with 
"build: improve pcap dependency handling" changeset to fix build issue with meson

 - Some compiler needs the following depended patch to compile with meson
   http://patches.dpdk.org/patch/52367/

v6 Changes:
 - Rework to change the config files to sync with "mk: use linux and freebsd in config names"
 - Fix the following error with latest gcc by fixing the mcpu type
   cc1: error: switch -mcpu=armv8.2-a conflicts with -march=armv8-a switch 

v5 Changes:
 - Fix incorrect meson flag parsing(Phil Yang)
 - Squash meson cross build patch(5/5) into configuration update patches for
 thunderx2(3/5) and octeontx2(4/5)(Thomas)
 - Changed octeontx2's march as armv8-a and added the extension required
   instead of armv8-2a(Phil Yang)
 - Improved rte_cc_has_argument() implementaion by removing the temp
   file(Thomas)

v4 Changes:
 - Fix incorrect signoff marrvell -> marvell.

v3 Changes:
 - Squash meson build support into config support for thunderx2/octeontx2.

v2 Changes:
 - Add meson build support.

---
 mk/rte.helper.mk              | 10 ++++++++++
 mk/target/generic/rte.vars.mk | 22 +++++++++++-----------
 2 files changed, 21 insertions(+), 11 deletions(-)
 create mode 100644 mk/rte.helper.mk

diff --git a/mk/rte.helper.mk b/mk/rte.helper.mk
new file mode 100644
index 000000000..6e7fd03d7
--- /dev/null
+++ b/mk/rte.helper.mk
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+
+# rte_cc_has_argument
+# Usage: MACHINE_CFLAGS += $(call rte_cc_has_argument, -mno-avx512f)
+# Return the argument if the argument is supported by the compiler.
+#
+define rte_cc_has_argument
+	$(shell $(CC) -E $(1) -xc /dev/null 1>/dev/null 2>/dev/null && echo $(1))
+endef
diff --git a/mk/target/generic/rte.vars.mk b/mk/target/generic/rte.vars.mk
index dd149acc9..25a578ad7 100644
--- a/mk/target/generic/rte.vars.mk
+++ b/mk/target/generic/rte.vars.mk
@@ -7,6 +7,17 @@
 # executive environment.
 #
 
+#
+# toolchain:
+#
+#   - define CC, LD, AR, AS, ...
+#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
+#   - may override any previously defined variable
+#
+include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
+
 #
 # machine:
 #
@@ -45,17 +56,6 @@ endif
 #
 include $(RTE_SDK)/mk/arch/$(RTE_ARCH)/rte.vars.mk
 
-#
-# toolchain:
-#
-#   - define CC, LD, AR, AS, ...
-#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
-#   - may override any previously defined variable
-#
-include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
-
 #
 # exec-env:
 #
-- 
2.21.0

[dpdk-dev] [PATCH v7 1/4] mk: introduce helper to check valid compiler argument

[jerinjacobk]

From: Jerin Jacob <jerinj@marvell.com>

Introduce rte_cc_has_argument() Makefile helper to
check a given argument is support by the compiler.

Example Usage:

include $(RTE_SDK)/mk/rte.helper.mk
MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)

This would allow adding -mcpu=octeontx2 in MACHINE_CFLAGS
if it is only supported by the compiler. The use case for such
scheme is to enable the mcpu optimization if the compiler
supports else it needs to compile the source code without
any errors.

This patch also moves inclusion of toolchain's rte.vars.mk
to before the machine's rte.vars.mk inclusion to make
correct CC available for the cross compile case.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---

Change history of this series:

v7 Changes:
 - Updated cross compile config files align with 
"build: improve pcap dependency handling" changeset to fix build issue with meson

 - Some compiler needs the following depended patch to compile with meson
   http://patches.dpdk.org/patch/52367/

v6 Changes:
 - Rework to change the config files to sync with "mk: use linux and freebsd in config names"
 - Fix the following error with latest gcc by fixing the mcpu type
   cc1: error: switch -mcpu=armv8.2-a conflicts with -march=armv8-a switch 

v5 Changes:
 - Fix incorrect meson flag parsing(Phil Yang)
 - Squash meson cross build patch(5/5) into configuration update patches for
 thunderx2(3/5) and octeontx2(4/5)(Thomas)
 - Changed octeontx2's march as armv8-a and added the extension required
   instead of armv8-2a(Phil Yang)
 - Improved rte_cc_has_argument() implementaion by removing the temp
   file(Thomas)

v4 Changes:
 - Fix incorrect signoff marrvell -> marvell.

v3 Changes:
 - Squash meson build support into config support for thunderx2/octeontx2.

v2 Changes:
 - Add meson build support.

---
 mk/rte.helper.mk              | 10 ++++++++++
 mk/target/generic/rte.vars.mk | 22 +++++++++++-----------
 2 files changed, 21 insertions(+), 11 deletions(-)
 create mode 100644 mk/rte.helper.mk

diff --git a/mk/rte.helper.mk b/mk/rte.helper.mk
new file mode 100644
index 000000000..6e7fd03d7
--- /dev/null
+++ b/mk/rte.helper.mk
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+
+# rte_cc_has_argument
+# Usage: MACHINE_CFLAGS += $(call rte_cc_has_argument, -mno-avx512f)
+# Return the argument if the argument is supported by the compiler.
+#
+define rte_cc_has_argument
+	$(shell $(CC) -E $(1) -xc /dev/null 1>/dev/null 2>/dev/null && echo $(1))
+endef
diff --git a/mk/target/generic/rte.vars.mk b/mk/target/generic/rte.vars.mk
index dd149acc9..25a578ad7 100644
--- a/mk/target/generic/rte.vars.mk
+++ b/mk/target/generic/rte.vars.mk
@@ -7,6 +7,17 @@
 # executive environment.
 #
 
+#
+# toolchain:
+#
+#   - define CC, LD, AR, AS, ...
+#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
+#   - may override any previously defined variable
+#
+include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
+
 #
 # machine:
 #
@@ -45,17 +56,6 @@ endif
 #
 include $(RTE_SDK)/mk/arch/$(RTE_ARCH)/rte.vars.mk
 
-#
-# toolchain:
-#
-#   - define CC, LD, AR, AS, ...
-#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
-#   - may override any previously defined variable
-#
-include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
-
 #
 # exec-env:
 #
-- 
2.21.0

[dpdk-dev] [PATCH v7 2/4] meson: add infra to support machine specific flags

[jerinjacobk]

From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Currently, RTE_* flags are set based on the implementer ID but there might
be some micro arch specific differences from the same vendor
eg. CACHE_LINESIZE. Add support to set micro arch specific flags.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
---
 config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++-----
 1 file changed, 32 insertions(+), 5 deletions(-)

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 170a4981a..8de3f3e3a 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -52,12 +52,10 @@ flags_generic = [
 	['RTE_USE_C11_MEM_MODEL', true],
 	['RTE_CACHE_LINE_SIZE', 128]]
 flags_cavium = [
-	['RTE_MACHINE', '"thunderx"'],
 	['RTE_CACHE_LINE_SIZE', 128],
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 96],
-	['RTE_MAX_VFIO_GROUPS', 128],
-	['RTE_USE_C11_MEM_MODEL', false]]
+	['RTE_MAX_VFIO_GROUPS', 128]]
 flags_dpaa = [
 	['RTE_MACHINE', '"dpaa"'],
 	['RTE_USE_C11_MEM_MODEL', true],
@@ -71,6 +69,27 @@ flags_dpaa2 = [
 	['RTE_MAX_NUMA_NODES', 1],
 	['RTE_MAX_LCORE', 16],
 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
+flags_default_extra = []
+flags_thunderx_extra = [
+	['RTE_MACHINE', '"thunderx"'],
+	['RTE_USE_C11_MEM_MODEL', false]]
+
+machine_args_generic = [
+	['default', ['-march=armv8-a+crc+crypto']],
+	['native', ['-march=native']],
+	['0xd03', ['-mcpu=cortex-a53']],
+	['0xd04', ['-mcpu=cortex-a35']],
+	['0xd07', ['-mcpu=cortex-a57']],
+	['0xd08', ['-mcpu=cortex-a72']],
+	['0xd09', ['-mcpu=cortex-a73']],
+	['0xd0a', ['-mcpu=cortex-a75']]]
+
+machine_args_cavium = [
+	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
+	['native', ['-march=native']],
+	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
+	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
@@ -157,8 +176,16 @@ else
 	endif
 	foreach marg: machine[2]
 		if marg[0] == impl_pn
-			foreach f: marg[1]
-				machine_args += f
+			foreach flag: marg[1]
+				if cc.has_argument(flag)
+					machine_args += flag
+				endif
+			endforeach
+			# Apply any extra machine specific flags.
+			foreach flag: marg.get(2, flags_default_extra)
+				if flag.length() > 0
+					dpdk_conf.set(flag[0], flag[1])
+				endif
 			endforeach
 		endif
 	endforeach
-- 
2.21.0

[dpdk-dev] [PATCH v7 2/4] meson: add infra to support machine specific flags

[jerinjacobk]

From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Currently, RTE_* flags are set based on the implementer ID but there might
be some micro arch specific differences from the same vendor
eg. CACHE_LINESIZE. Add support to set micro arch specific flags.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
---
 config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++-----
 1 file changed, 32 insertions(+), 5 deletions(-)

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 170a4981a..8de3f3e3a 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -52,12 +52,10 @@ flags_generic = [
 	['RTE_USE_C11_MEM_MODEL', true],
 	['RTE_CACHE_LINE_SIZE', 128]]
 flags_cavium = [
-	['RTE_MACHINE', '"thunderx"'],
 	['RTE_CACHE_LINE_SIZE', 128],
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 96],
-	['RTE_MAX_VFIO_GROUPS', 128],
-	['RTE_USE_C11_MEM_MODEL', false]]
+	['RTE_MAX_VFIO_GROUPS', 128]]
 flags_dpaa = [
 	['RTE_MACHINE', '"dpaa"'],
 	['RTE_USE_C11_MEM_MODEL', true],
@@ -71,6 +69,27 @@ flags_dpaa2 = [
 	['RTE_MAX_NUMA_NODES', 1],
 	['RTE_MAX_LCORE', 16],
 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
+flags_default_extra = []
+flags_thunderx_extra = [
+	['RTE_MACHINE', '"thunderx"'],
+	['RTE_USE_C11_MEM_MODEL', false]]
+
+machine_args_generic = [
+	['default', ['-march=armv8-a+crc+crypto']],
+	['native', ['-march=native']],
+	['0xd03', ['-mcpu=cortex-a53']],
+	['0xd04', ['-mcpu=cortex-a35']],
+	['0xd07', ['-mcpu=cortex-a57']],
+	['0xd08', ['-mcpu=cortex-a72']],
+	['0xd09', ['-mcpu=cortex-a73']],
+	['0xd0a', ['-mcpu=cortex-a75']]]
+
+machine_args_cavium = [
+	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
+	['native', ['-march=native']],
+	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
+	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
@@ -157,8 +176,16 @@ else
 	endif
 	foreach marg: machine[2]
 		if marg[0] == impl_pn
-			foreach f: marg[1]
-				machine_args += f
+			foreach flag: marg[1]
+				if cc.has_argument(flag)
+					machine_args += flag
+				endif
+			endforeach
+			# Apply any extra machine specific flags.
+			foreach flag: marg.get(2, flags_default_extra)
+				if flag.length() > 0
+					dpdk_conf.set(flag[0], flag[1])
+				endif
 			endforeach
 		endif
 	endforeach
-- 
2.21.0

[dpdk-dev] [PATCH v7 3/4] config: add thunderx2 machine config

[jerinjacobk]

From: Jerin Jacob <jerinj@marvell.com>

Optimized configuration for Marvell thunderx2 SoC.
Updated meson build to support Marvell thunderx2 SoC.
Added meson cross compile target.

Product details are here:

https://www.marvell.com/server-processors/thunderx2-arm-processors/

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
---
 config/arm/arm64_thunderx2_linux_gcc          | 16 +++++++++
 config/arm/meson.build                        |  9 ++++-
 config/defconfig_arm64-thunderx2-linux-gcc    |  1 +
 config/defconfig_arm64-thunderx2-linuxapp-gcc | 11 ++++++
 mk/machine/thunderx2/rte.vars.mk              | 34 +++++++++++++++++++
 5 files changed, 70 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/arm64_thunderx2_linux_gcc
 create mode 120000 config/defconfig_arm64-thunderx2-linux-gcc
 create mode 100644 config/defconfig_arm64-thunderx2-linuxapp-gcc
 create mode 100644 mk/machine/thunderx2/rte.vars.mk

diff --git a/config/arm/arm64_thunderx2_linux_gcc b/config/arm/arm64_thunderx2_linux_gcc
new file mode 100644
index 000000000..0dc275644
--- /dev/null
+++ b/config/arm/arm64_thunderx2_linux_gcc
@@ -0,0 +1,16 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x43'
+implementor_pn = '0xaf'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 8de3f3e3a..9282bbf33 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -73,6 +73,12 @@ flags_default_extra = []
 flags_thunderx_extra = [
 	['RTE_MACHINE', '"thunderx"'],
 	['RTE_USE_C11_MEM_MODEL', false]]
+flags_thunderx2_extra = [
+	['RTE_MACHINE', '"thunderx2"'],
+	['RTE_CACHE_LINE_SIZE', 64],
+	['RTE_MAX_NUMA_NODES', 2],
+	['RTE_MAX_LCORE', 256],
+	['RTE_USE_C11_MEM_MODEL', true]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -89,7 +95,8 @@ machine_args_cavium = [
 	['native', ['-march=native']],
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
-	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-thunderx2-linux-gcc b/config/defconfig_arm64-thunderx2-linux-gcc
new file mode 120000
index 000000000..b40a760b1
--- /dev/null
+++ b/config/defconfig_arm64-thunderx2-linux-gcc
@@ -0,0 +1 @@
+defconfig_arm64-thunderx2-linuxapp-gcc
\ No newline at end of file
diff --git a/config/defconfig_arm64-thunderx2-linuxapp-gcc b/config/defconfig_arm64-thunderx2-linuxapp-gcc
new file mode 100644
index 000000000..cc5c64ba0
--- /dev/null
+++ b/config/defconfig_arm64-thunderx2-linuxapp-gcc
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linux-gcc"
+
+CONFIG_RTE_MACHINE="thunderx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=64
+CONFIG_RTE_MAX_NUMA_NODES=2
+CONFIG_RTE_MAX_LCORE=256
diff --git a/mk/machine/thunderx2/rte.vars.mk b/mk/machine/thunderx2/rte.vars.mk
new file mode 100644
index 000000000..b80dc8680
--- /dev/null
+++ b/mk/machine/thunderx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.1-a+crc+crypto)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=thunderx2t99)
-- 
2.21.0

[dpdk-dev] [PATCH v7 3/4] config: add thunderx2 machine config

[jerinjacobk]

From: Jerin Jacob <jerinj@marvell.com>

Optimized configuration for Marvell thunderx2 SoC.
Updated meson build to support Marvell thunderx2 SoC.
Added meson cross compile target.

Product details are here:

https://www.marvell.com/server-processors/thunderx2-arm-processors/

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
---
 config/arm/arm64_thunderx2_linux_gcc          | 16 +++++++++
 config/arm/meson.build                        |  9 ++++-
 config/defconfig_arm64-thunderx2-linux-gcc    |  1 +
 config/defconfig_arm64-thunderx2-linuxapp-gcc | 11 ++++++
 mk/machine/thunderx2/rte.vars.mk              | 34 +++++++++++++++++++
 5 files changed, 70 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/arm64_thunderx2_linux_gcc
 create mode 120000 config/defconfig_arm64-thunderx2-linux-gcc
 create mode 100644 config/defconfig_arm64-thunderx2-linuxapp-gcc
 create mode 100644 mk/machine/thunderx2/rte.vars.mk

diff --git a/config/arm/arm64_thunderx2_linux_gcc b/config/arm/arm64_thunderx2_linux_gcc
new file mode 100644
index 000000000..0dc275644
--- /dev/null
+++ b/config/arm/arm64_thunderx2_linux_gcc
@@ -0,0 +1,16 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x43'
+implementor_pn = '0xaf'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 8de3f3e3a..9282bbf33 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -73,6 +73,12 @@ flags_default_extra = []
 flags_thunderx_extra = [
 	['RTE_MACHINE', '"thunderx"'],
 	['RTE_USE_C11_MEM_MODEL', false]]
+flags_thunderx2_extra = [
+	['RTE_MACHINE', '"thunderx2"'],
+	['RTE_CACHE_LINE_SIZE', 64],
+	['RTE_MAX_NUMA_NODES', 2],
+	['RTE_MAX_LCORE', 256],
+	['RTE_USE_C11_MEM_MODEL', true]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -89,7 +95,8 @@ machine_args_cavium = [
 	['native', ['-march=native']],
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
-	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-thunderx2-linux-gcc b/config/defconfig_arm64-thunderx2-linux-gcc
new file mode 120000
index 000000000..b40a760b1
--- /dev/null
+++ b/config/defconfig_arm64-thunderx2-linux-gcc
@@ -0,0 +1 @@
+defconfig_arm64-thunderx2-linuxapp-gcc
\ No newline at end of file
diff --git a/config/defconfig_arm64-thunderx2-linuxapp-gcc b/config/defconfig_arm64-thunderx2-linuxapp-gcc
new file mode 100644
index 000000000..cc5c64ba0
--- /dev/null
+++ b/config/defconfig_arm64-thunderx2-linuxapp-gcc
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linux-gcc"
+
+CONFIG_RTE_MACHINE="thunderx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=64
+CONFIG_RTE_MAX_NUMA_NODES=2
+CONFIG_RTE_MAX_LCORE=256
diff --git a/mk/machine/thunderx2/rte.vars.mk b/mk/machine/thunderx2/rte.vars.mk
new file mode 100644
index 000000000..b80dc8680
--- /dev/null
+++ b/mk/machine/thunderx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.1-a+crc+crypto)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=thunderx2t99)
-- 
2.21.0

[dpdk-dev] [PATCH v7 4/4] config: add octeontx2 machine config

[jerinjacobk]

From: Jerin Jacob <jerinj@marvell.com>

Optimized configuration for Marvell octeontx2 SoC.
Updated meson build to support Marvell octeontx2 SoC.
Added meson cross build target for octeontx2.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
---
 config/arm/arm64_octeontx2_linux_gcc          | 16 +++++++++
 config/arm/meson.build                        |  9 ++++-
 config/defconfig_arm64-octeontx2-linux-gcc    |  1 +
 config/defconfig_arm64-octeontx2-linuxapp-gcc | 18 ++++++++++
 mk/machine/octeontx2/rte.vars.mk              | 34 +++++++++++++++++++
 5 files changed, 77 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/arm64_octeontx2_linux_gcc
 create mode 120000 config/defconfig_arm64-octeontx2-linux-gcc
 create mode 100644 config/defconfig_arm64-octeontx2-linuxapp-gcc
 create mode 100644 mk/machine/octeontx2/rte.vars.mk

diff --git a/config/arm/arm64_octeontx2_linux_gcc b/config/arm/arm64_octeontx2_linux_gcc
new file mode 100644
index 000000000..e2c0b8f72
--- /dev/null
+++ b/config/arm/arm64_octeontx2_linux_gcc
@@ -0,0 +1,16 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x43'
+implementor_pn = '0xb2'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 9282bbf33..0d76b2554 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -79,6 +79,12 @@ flags_thunderx2_extra = [
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 256],
 	['RTE_USE_C11_MEM_MODEL', true]]
+flags_octeontx2_extra = [
+	['RTE_MACHINE', '"octeontx2"'],
+	['RTE_MAX_NUMA_NODES', 1],
+	['RTE_MAX_LCORE', 24],
+	['RTE_EAL_IGB_UIO', false],
+	['RTE_USE_C11_MEM_MODEL', true]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -96,7 +102,8 @@ machine_args_cavium = [
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
 	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
-	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra],
+	['0xb2', ['-mcpu=octeontx2'], flags_octeontx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-octeontx2-linux-gcc b/config/defconfig_arm64-octeontx2-linux-gcc
new file mode 120000
index 000000000..e25150531
--- /dev/null
+++ b/config/defconfig_arm64-octeontx2-linux-gcc
@@ -0,0 +1 @@
+defconfig_arm64-octeontx2-linuxapp-gcc
\ No newline at end of file
diff --git a/config/defconfig_arm64-octeontx2-linuxapp-gcc b/config/defconfig_arm64-octeontx2-linuxapp-gcc
new file mode 100644
index 000000000..9eae84538
--- /dev/null
+++ b/config/defconfig_arm64-octeontx2-linuxapp-gcc
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linux-gcc"
+
+CONFIG_RTE_MACHINE="octeontx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=128
+CONFIG_RTE_MAX_NUMA_NODES=1
+CONFIG_RTE_MAX_LCORE=24
+
+# Doesn't support NUMA
+CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
+CONFIG_RTE_LIBRTE_VHOST_NUMA=n
+
+# Recommend to use VFIO as co-processors needs SMMU/IOMMU
+CONFIG_RTE_EAL_IGB_UIO=n
diff --git a/mk/machine/octeontx2/rte.vars.mk b/mk/machine/octeontx2/rte.vars.mk
new file mode 100644
index 000000000..cbec7f14d
--- /dev/null
+++ b/mk/machine/octeontx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=-mcpu=armv8.2-a+crc+crypto+lse)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)
-- 
2.21.0

[dpdk-dev] [PATCH v7 4/4] config: add octeontx2 machine config

[jerinjacobk]

From: Jerin Jacob <jerinj@marvell.com>

Optimized configuration for Marvell octeontx2 SoC.
Updated meson build to support Marvell octeontx2 SoC.
Added meson cross build target for octeontx2.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
---
 config/arm/arm64_octeontx2_linux_gcc          | 16 +++++++++
 config/arm/meson.build                        |  9 ++++-
 config/defconfig_arm64-octeontx2-linux-gcc    |  1 +
 config/defconfig_arm64-octeontx2-linuxapp-gcc | 18 ++++++++++
 mk/machine/octeontx2/rte.vars.mk              | 34 +++++++++++++++++++
 5 files changed, 77 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/arm64_octeontx2_linux_gcc
 create mode 120000 config/defconfig_arm64-octeontx2-linux-gcc
 create mode 100644 config/defconfig_arm64-octeontx2-linuxapp-gcc
 create mode 100644 mk/machine/octeontx2/rte.vars.mk

diff --git a/config/arm/arm64_octeontx2_linux_gcc b/config/arm/arm64_octeontx2_linux_gcc
new file mode 100644
index 000000000..e2c0b8f72
--- /dev/null
+++ b/config/arm/arm64_octeontx2_linux_gcc
@@ -0,0 +1,16 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x43'
+implementor_pn = '0xb2'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 9282bbf33..0d76b2554 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -79,6 +79,12 @@ flags_thunderx2_extra = [
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 256],
 	['RTE_USE_C11_MEM_MODEL', true]]
+flags_octeontx2_extra = [
+	['RTE_MACHINE', '"octeontx2"'],
+	['RTE_MAX_NUMA_NODES', 1],
+	['RTE_MAX_LCORE', 24],
+	['RTE_EAL_IGB_UIO', false],
+	['RTE_USE_C11_MEM_MODEL', true]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -96,7 +102,8 @@ machine_args_cavium = [
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
 	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
-	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra],
+	['0xb2', ['-mcpu=octeontx2'], flags_octeontx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-octeontx2-linux-gcc b/config/defconfig_arm64-octeontx2-linux-gcc
new file mode 120000
index 000000000..e25150531
--- /dev/null
+++ b/config/defconfig_arm64-octeontx2-linux-gcc
@@ -0,0 +1 @@
+defconfig_arm64-octeontx2-linuxapp-gcc
\ No newline at end of file
diff --git a/config/defconfig_arm64-octeontx2-linuxapp-gcc b/config/defconfig_arm64-octeontx2-linuxapp-gcc
new file mode 100644
index 000000000..9eae84538
--- /dev/null
+++ b/config/defconfig_arm64-octeontx2-linuxapp-gcc
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linux-gcc"
+
+CONFIG_RTE_MACHINE="octeontx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=128
+CONFIG_RTE_MAX_NUMA_NODES=1
+CONFIG_RTE_MAX_LCORE=24
+
+# Doesn't support NUMA
+CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
+CONFIG_RTE_LIBRTE_VHOST_NUMA=n
+
+# Recommend to use VFIO as co-processors needs SMMU/IOMMU
+CONFIG_RTE_EAL_IGB_UIO=n
diff --git a/mk/machine/octeontx2/rte.vars.mk b/mk/machine/octeontx2/rte.vars.mk
new file mode 100644
index 000000000..cbec7f14d
--- /dev/null
+++ b/mk/machine/octeontx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=-mcpu=armv8.2-a+crc+crypto+lse)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)
-- 
2.21.0

Re: [dpdk-dev] [PATCH v7 3/4] config: add thunderx2 machine config

[Thomas Monjalon]

06/04/2019 16:27, jerinjacobk@gmail.com:
> --- /dev/null
> +++ b/config/arm/arm64_thunderx2_linux_gcc
> @@ -0,0 +1,16 @@
> +[binaries]
> +c = 'aarch64-linux-gnu-gcc'
> +cpp = 'aarch64-linux-gnu-cpp'
> +ar = 'aarch64-linux-gnu-gcc-ar'
> +strip = 'aarch64-linux-gnu-strip'
> +pcap-config = ''

Strangely, I still see the same issue:

In file included from /usr/include/inttypes.h:27,
                 from /usr/include/pcap/pcap-inttypes.h:114,
                 from /usr/include/pcap/pcap.h:74,
                 from /usr/include/pcap.h:43,
                 from ../drivers/net/pcap/rte_eth_pcap.c:19:
/usr/include/stdint.h:109: error: "__INT64_C" redefined [-Werror]

How may I help to debug it?

Re: [dpdk-dev] [PATCH v7 3/4] config: add thunderx2 machine config

[Thomas Monjalon]

06/04/2019 16:27, jerinjacobk@gmail.com:
> --- /dev/null
> +++ b/config/arm/arm64_thunderx2_linux_gcc
> @@ -0,0 +1,16 @@
> +[binaries]
> +c = 'aarch64-linux-gnu-gcc'
> +cpp = 'aarch64-linux-gnu-cpp'
> +ar = 'aarch64-linux-gnu-gcc-ar'
> +strip = 'aarch64-linux-gnu-strip'
> +pcap-config = ''

Strangely, I still see the same issue:

In file included from /usr/include/inttypes.h:27,
                 from /usr/include/pcap/pcap-inttypes.h:114,
                 from /usr/include/pcap/pcap.h:74,
                 from /usr/include/pcap.h:43,
                 from ../drivers/net/pcap/rte_eth_pcap.c:19:
/usr/include/stdint.h:109: error: "__INT64_C" redefined [-Werror]

How may I help to debug it?

Re: [dpdk-dev] [PATCH v7 3/4] config: add thunderx2 machine config

[Thomas Monjalon]

08/04/2019 12:32, Thomas Monjalon:
> 06/04/2019 16:27, jerinjacobk@gmail.com:
> > --- /dev/null
> > +++ b/config/arm/arm64_thunderx2_linux_gcc
> > @@ -0,0 +1,16 @@
> > +[binaries]
> > +c = 'aarch64-linux-gnu-gcc'
> > +cpp = 'aarch64-linux-gnu-cpp'
> > +ar = 'aarch64-linux-gnu-gcc-ar'
> > +strip = 'aarch64-linux-gnu-strip'
> > +pcap-config = ''
> 
> Strangely, I still see the same issue:
> 
> In file included from /usr/include/inttypes.h:27,
>                  from /usr/include/pcap/pcap-inttypes.h:114,
>                  from /usr/include/pcap/pcap.h:74,
>                  from /usr/include/pcap.h:43,
>                  from ../drivers/net/pcap/rte_eth_pcap.c:19:
> /usr/include/stdint.h:109: error: "__INT64_C" redefined [-Werror]
> 
> How may I help to debug it?

Thanks Bruce for telling me to remove the build directory.
Now it works!

Re: [dpdk-dev] [PATCH v7 3/4] config: add thunderx2 machine config

[Thomas Monjalon]

08/04/2019 12:32, Thomas Monjalon:
> 06/04/2019 16:27, jerinjacobk@gmail.com:
> > --- /dev/null
> > +++ b/config/arm/arm64_thunderx2_linux_gcc
> > @@ -0,0 +1,16 @@
> > +[binaries]
> > +c = 'aarch64-linux-gnu-gcc'
> > +cpp = 'aarch64-linux-gnu-cpp'
> > +ar = 'aarch64-linux-gnu-gcc-ar'
> > +strip = 'aarch64-linux-gnu-strip'
> > +pcap-config = ''
> 
> Strangely, I still see the same issue:
> 
> In file included from /usr/include/inttypes.h:27,
>                  from /usr/include/pcap/pcap-inttypes.h:114,
>                  from /usr/include/pcap/pcap.h:74,
>                  from /usr/include/pcap.h:43,
>                  from ../drivers/net/pcap/rte_eth_pcap.c:19:
> /usr/include/stdint.h:109: error: "__INT64_C" redefined [-Werror]
> 
> How may I help to debug it?

Thanks Bruce for telling me to remove the build directory.
Now it works!

Re: [dpdk-dev] [PATCH v7 3/4] config: add thunderx2 machine config

[Bruce Richardson]

On Mon, Apr 08, 2019 at 02:05:00PM +0200, Thomas Monjalon wrote:
> 08/04/2019 12:32, Thomas Monjalon:
> > 06/04/2019 16:27, jerinjacobk@gmail.com:
> > > --- /dev/null
> > > +++ b/config/arm/arm64_thunderx2_linux_gcc
> > > @@ -0,0 +1,16 @@
> > > +[binaries]
> > > +c = 'aarch64-linux-gnu-gcc'
> > > +cpp = 'aarch64-linux-gnu-cpp'
> > > +ar = 'aarch64-linux-gnu-gcc-ar'
> > > +strip = 'aarch64-linux-gnu-strip'
> > > +pcap-config = ''
> > 
> > Strangely, I still see the same issue:
> > 
> > In file included from /usr/include/inttypes.h:27,
> >                  from /usr/include/pcap/pcap-inttypes.h:114,
> >                  from /usr/include/pcap/pcap.h:74,
> >                  from /usr/include/pcap.h:43,
> >                  from ../drivers/net/pcap/rte_eth_pcap.c:19:
> > /usr/include/stdint.h:109: error: "__INT64_C" redefined [-Werror]
> > 
> > How may I help to debug it?
> 
> Thanks Bruce for telling me to remove the build directory.
> Now it works!
> 
For reference, official documentation on this point - unlike most things in
meson, changing the cross-build file does require you to start from scratch
with a new build folder.

https://mesonbuild.com/Cross-compilation.html#changing-cross-file-settings

/Bruce

Re: [dpdk-dev] [PATCH v7 3/4] config: add thunderx2 machine config

[Bruce Richardson]

On Mon, Apr 08, 2019 at 02:05:00PM +0200, Thomas Monjalon wrote:
> 08/04/2019 12:32, Thomas Monjalon:
> > 06/04/2019 16:27, jerinjacobk@gmail.com:
> > > --- /dev/null
> > > +++ b/config/arm/arm64_thunderx2_linux_gcc
> > > @@ -0,0 +1,16 @@
> > > +[binaries]
> > > +c = 'aarch64-linux-gnu-gcc'
> > > +cpp = 'aarch64-linux-gnu-cpp'
> > > +ar = 'aarch64-linux-gnu-gcc-ar'
> > > +strip = 'aarch64-linux-gnu-strip'
> > > +pcap-config = ''
> > 
> > Strangely, I still see the same issue:
> > 
> > In file included from /usr/include/inttypes.h:27,
> >                  from /usr/include/pcap/pcap-inttypes.h:114,
> >                  from /usr/include/pcap/pcap.h:74,
> >                  from /usr/include/pcap.h:43,
> >                  from ../drivers/net/pcap/rte_eth_pcap.c:19:
> > /usr/include/stdint.h:109: error: "__INT64_C" redefined [-Werror]
> > 
> > How may I help to debug it?
> 
> Thanks Bruce for telling me to remove the build directory.
> Now it works!
> 
For reference, official documentation on this point - unlike most things in
meson, changing the cross-build file does require you to start from scratch
with a new build folder.

https://mesonbuild.com/Cross-compilation.html#changing-cross-file-settings

/Bruce

Re: [dpdk-dev] [PATCH v7 2/4] meson: add infra to support machine specific flags

[Yongseok Koh]

> On Apr 6, 2019, at 7:27 AM, jerinjacobk@gmail.com wrote:
> 
> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> 
> Currently, RTE_* flags are set based on the implementer ID but there might
> be some micro arch specific differences from the same vendor
> eg. CACHE_LINESIZE. Add support to set micro arch specific flags.
> 
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> ---
> config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++-----
> 1 file changed, 32 insertions(+), 5 deletions(-)
> 
> diff --git a/config/arm/meson.build b/config/arm/meson.build
> index 170a4981a..8de3f3e3a 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -52,12 +52,10 @@ flags_generic = [
> 	['RTE_USE_C11_MEM_MODEL', true],
> 	['RTE_CACHE_LINE_SIZE', 128]]
> flags_cavium = [
> -	['RTE_MACHINE', '"thunderx"'],
> 	['RTE_CACHE_LINE_SIZE', 128],
> 	['RTE_MAX_NUMA_NODES', 2],
> 	['RTE_MAX_LCORE', 96],
> -	['RTE_MAX_VFIO_GROUPS', 128],
> -	['RTE_USE_C11_MEM_MODEL', false]]
> +	['RTE_MAX_VFIO_GROUPS', 128]]
> flags_dpaa = [
> 	['RTE_MACHINE', '"dpaa"'],
> 	['RTE_USE_C11_MEM_MODEL', true],
> @@ -71,6 +69,27 @@ flags_dpaa2 = [
> 	['RTE_MAX_NUMA_NODES', 1],
> 	['RTE_MAX_LCORE', 16],
> 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
> +flags_default_extra = []
> +flags_thunderx_extra = [
> +	['RTE_MACHINE', '"thunderx"'],
> +	['RTE_USE_C11_MEM_MODEL', false]]
> +
> +machine_args_generic = [
> +	['default', ['-march=armv8-a+crc+crypto']],
> +	['native', ['-march=native']],
> +	['0xd03', ['-mcpu=cortex-a53']],
> +	['0xd04', ['-mcpu=cortex-a35']],
> +	['0xd07', ['-mcpu=cortex-a57']],
> +	['0xd08', ['-mcpu=cortex-a72']],
> +	['0xd09', ['-mcpu=cortex-a73']],
> +	['0xd0a', ['-mcpu=cortex-a75']]]
> +
> +machine_args_cavium = [
> +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> +	['native', ['-march=native']],
> +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
> +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
> +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]

Looks like there's a mistake in rebasing it?
You should've removed machine_args_generic and machine_args_cavium
in the beginning of this file.

Other than that, it looks good to me.

BTW, thanks for the patch. I raised this issue before and I was supposed to
make the change but you have taken it.

Yongseok

> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
> impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
> @@ -157,8 +176,16 @@ else
> 	endif
> 	foreach marg: machine[2]
> 		if marg[0] == impl_pn
> -			foreach f: marg[1]
> -				machine_args += f
> +			foreach flag: marg[1]
> +				if cc.has_argument(flag)
> +					machine_args += flag
> +				endif
> +			endforeach
> +			# Apply any extra machine specific flags.
> +			foreach flag: marg.get(2, flags_default_extra)
> +				if flag.length() > 0
> +					dpdk_conf.set(flag[0], flag[1])
> +				endif
> 			endforeach
> 		endif
> 	endforeach
> -- 
> 2.21.0
> 

Re: [dpdk-dev] [PATCH v7 2/4] meson: add infra to support machine specific flags

[Yongseok Koh]

> On Apr 6, 2019, at 7:27 AM, jerinjacobk@gmail.com wrote:
> 
> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> 
> Currently, RTE_* flags are set based on the implementer ID but there might
> be some micro arch specific differences from the same vendor
> eg. CACHE_LINESIZE. Add support to set micro arch specific flags.
> 
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> ---
> config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++-----
> 1 file changed, 32 insertions(+), 5 deletions(-)
> 
> diff --git a/config/arm/meson.build b/config/arm/meson.build
> index 170a4981a..8de3f3e3a 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -52,12 +52,10 @@ flags_generic = [
> 	['RTE_USE_C11_MEM_MODEL', true],
> 	['RTE_CACHE_LINE_SIZE', 128]]
> flags_cavium = [
> -	['RTE_MACHINE', '"thunderx"'],
> 	['RTE_CACHE_LINE_SIZE', 128],
> 	['RTE_MAX_NUMA_NODES', 2],
> 	['RTE_MAX_LCORE', 96],
> -	['RTE_MAX_VFIO_GROUPS', 128],
> -	['RTE_USE_C11_MEM_MODEL', false]]
> +	['RTE_MAX_VFIO_GROUPS', 128]]
> flags_dpaa = [
> 	['RTE_MACHINE', '"dpaa"'],
> 	['RTE_USE_C11_MEM_MODEL', true],
> @@ -71,6 +69,27 @@ flags_dpaa2 = [
> 	['RTE_MAX_NUMA_NODES', 1],
> 	['RTE_MAX_LCORE', 16],
> 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
> +flags_default_extra = []
> +flags_thunderx_extra = [
> +	['RTE_MACHINE', '"thunderx"'],
> +	['RTE_USE_C11_MEM_MODEL', false]]
> +
> +machine_args_generic = [
> +	['default', ['-march=armv8-a+crc+crypto']],
> +	['native', ['-march=native']],
> +	['0xd03', ['-mcpu=cortex-a53']],
> +	['0xd04', ['-mcpu=cortex-a35']],
> +	['0xd07', ['-mcpu=cortex-a57']],
> +	['0xd08', ['-mcpu=cortex-a72']],
> +	['0xd09', ['-mcpu=cortex-a73']],
> +	['0xd0a', ['-mcpu=cortex-a75']]]
> +
> +machine_args_cavium = [
> +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> +	['native', ['-march=native']],
> +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
> +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
> +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]

Looks like there's a mistake in rebasing it?
You should've removed machine_args_generic and machine_args_cavium
in the beginning of this file.

Other than that, it looks good to me.

BTW, thanks for the patch. I raised this issue before and I was supposed to
make the change but you have taken it.

Yongseok

> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
> impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
> @@ -157,8 +176,16 @@ else
> 	endif
> 	foreach marg: machine[2]
> 		if marg[0] == impl_pn
> -			foreach f: marg[1]
> -				machine_args += f
> +			foreach flag: marg[1]
> +				if cc.has_argument(flag)
> +					machine_args += flag
> +				endif
> +			endforeach
> +			# Apply any extra machine specific flags.
> +			foreach flag: marg.get(2, flags_default_extra)
> +				if flag.length() > 0
> +					dpdk_conf.set(flag[0], flag[1])
> +				endif
> 			endforeach
> 		endif
> 	endforeach
> -- 
> 2.21.0
> 

Re: [dpdk-dev] [PATCH v7 2/4] meson: add infra to support machine specific flags

[Yongseok Koh]

> On Apr 9, 2019, at 5:40 PM, Yongseok Koh <yskoh@mellanox.com> wrote:
> 
>> 
>> On Apr 6, 2019, at 7:27 AM, jerinjacobk@gmail.com wrote:
>> 
>> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
>> 
>> Currently, RTE_* flags are set based on the implementer ID but there might
>> be some micro arch specific differences from the same vendor
>> eg. CACHE_LINESIZE. Add support to set micro arch specific flags.
>> 
>> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
>> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
>> ---
>> config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++-----
>> 1 file changed, 32 insertions(+), 5 deletions(-)
>> 
>> diff --git a/config/arm/meson.build b/config/arm/meson.build
>> index 170a4981a..8de3f3e3a 100644
>> --- a/config/arm/meson.build
>> +++ b/config/arm/meson.build
>> @@ -52,12 +52,10 @@ flags_generic = [
>> 	['RTE_USE_C11_MEM_MODEL', true],
>> 	['RTE_CACHE_LINE_SIZE', 128]]
>> flags_cavium = [
>> -	['RTE_MACHINE', '"thunderx"'],
>> 	['RTE_CACHE_LINE_SIZE', 128],
>> 	['RTE_MAX_NUMA_NODES', 2],
>> 	['RTE_MAX_LCORE', 96],
>> -	['RTE_MAX_VFIO_GROUPS', 128],
>> -	['RTE_USE_C11_MEM_MODEL', false]]
>> +	['RTE_MAX_VFIO_GROUPS', 128]]
>> flags_dpaa = [
>> 	['RTE_MACHINE', '"dpaa"'],
>> 	['RTE_USE_C11_MEM_MODEL', true],
>> @@ -71,6 +69,27 @@ flags_dpaa2 = [
>> 	['RTE_MAX_NUMA_NODES', 1],
>> 	['RTE_MAX_LCORE', 16],
>> 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
>> +flags_default_extra = []
>> +flags_thunderx_extra = [
>> +	['RTE_MACHINE', '"thunderx"'],
>> +	['RTE_USE_C11_MEM_MODEL', false]]
>> +
>> +machine_args_generic = [
>> +	['default', ['-march=armv8-a+crc+crypto']],
>> +	['native', ['-march=native']],
>> +	['0xd03', ['-mcpu=cortex-a53']],
>> +	['0xd04', ['-mcpu=cortex-a35']],
>> +	['0xd07', ['-mcpu=cortex-a57']],
>> +	['0xd08', ['-mcpu=cortex-a72']],
>> +	['0xd09', ['-mcpu=cortex-a73']],
>> +	['0xd0a', ['-mcpu=cortex-a75']]]
>> +
>> +machine_args_cavium = [
>> +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
>> +	['native', ['-march=native']],
>> +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
>> +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
>> +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
> 
> Looks like there's a mistake in rebasing it?
> You should've removed machine_args_generic and machine_args_cavium
> in the beginning of this file.
> 
> Other than that, it looks good to me.
> 
> BTW, thanks for the patch. I raised this issue before and I was supposed to
> make the change but you have taken it.
> 
> Yongseok
> 
>> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
>> impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
>> @@ -157,8 +176,16 @@ else
>> 	endif
>> 	foreach marg: machine[2]
>> 		if marg[0] == impl_pn
>> -			foreach f: marg[1]
>> -				machine_args += f
>> +			foreach flag: marg[1]
>> +				if cc.has_argument(flag)
>> +					machine_args += flag
>> +				endif
>> +			endforeach
>> +			# Apply any extra machine specific flags.
>> +			foreach flag: marg.get(2, flags_default_extra)
>> +				if flag.length() > 0
>> +					dpdk_conf.set(flag[0], flag[1])
>> +				endif

And setting the extra flags doesn't work well with gcc < 7 because of the following,

        # Primary part number based mcpu flags are supported
        # for gcc versions > 7
        if cc.version().version_compare(
                        '<7.0') or cmd_output.length() == 0
                if not meson.is_cross_build() and arm_force_native_march == true
                        impl_pn = 'native'
                else
                        impl_pn = 'default'
                endif
        endif

Thanks,
Yongseok

>> 			endforeach
>> 		endif
>> 	endforeach
>> -- 
>> 2.21.0

Re: [dpdk-dev] [PATCH v7 2/4] meson: add infra to support machine specific flags

[Yongseok Koh]

> On Apr 9, 2019, at 5:40 PM, Yongseok Koh <yskoh@mellanox.com> wrote:
> 
>> 
>> On Apr 6, 2019, at 7:27 AM, jerinjacobk@gmail.com wrote:
>> 
>> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
>> 
>> Currently, RTE_* flags are set based on the implementer ID but there might
>> be some micro arch specific differences from the same vendor
>> eg. CACHE_LINESIZE. Add support to set micro arch specific flags.
>> 
>> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
>> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
>> ---
>> config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++-----
>> 1 file changed, 32 insertions(+), 5 deletions(-)
>> 
>> diff --git a/config/arm/meson.build b/config/arm/meson.build
>> index 170a4981a..8de3f3e3a 100644
>> --- a/config/arm/meson.build
>> +++ b/config/arm/meson.build
>> @@ -52,12 +52,10 @@ flags_generic = [
>> 	['RTE_USE_C11_MEM_MODEL', true],
>> 	['RTE_CACHE_LINE_SIZE', 128]]
>> flags_cavium = [
>> -	['RTE_MACHINE', '"thunderx"'],
>> 	['RTE_CACHE_LINE_SIZE', 128],
>> 	['RTE_MAX_NUMA_NODES', 2],
>> 	['RTE_MAX_LCORE', 96],
>> -	['RTE_MAX_VFIO_GROUPS', 128],
>> -	['RTE_USE_C11_MEM_MODEL', false]]
>> +	['RTE_MAX_VFIO_GROUPS', 128]]
>> flags_dpaa = [
>> 	['RTE_MACHINE', '"dpaa"'],
>> 	['RTE_USE_C11_MEM_MODEL', true],
>> @@ -71,6 +69,27 @@ flags_dpaa2 = [
>> 	['RTE_MAX_NUMA_NODES', 1],
>> 	['RTE_MAX_LCORE', 16],
>> 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
>> +flags_default_extra = []
>> +flags_thunderx_extra = [
>> +	['RTE_MACHINE', '"thunderx"'],
>> +	['RTE_USE_C11_MEM_MODEL', false]]
>> +
>> +machine_args_generic = [
>> +	['default', ['-march=armv8-a+crc+crypto']],
>> +	['native', ['-march=native']],
>> +	['0xd03', ['-mcpu=cortex-a53']],
>> +	['0xd04', ['-mcpu=cortex-a35']],
>> +	['0xd07', ['-mcpu=cortex-a57']],
>> +	['0xd08', ['-mcpu=cortex-a72']],
>> +	['0xd09', ['-mcpu=cortex-a73']],
>> +	['0xd0a', ['-mcpu=cortex-a75']]]
>> +
>> +machine_args_cavium = [
>> +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
>> +	['native', ['-march=native']],
>> +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
>> +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
>> +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
> 
> Looks like there's a mistake in rebasing it?
> You should've removed machine_args_generic and machine_args_cavium
> in the beginning of this file.
> 
> Other than that, it looks good to me.
> 
> BTW, thanks for the patch. I raised this issue before and I was supposed to
> make the change but you have taken it.
> 
> Yongseok
> 
>> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
>> impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
>> @@ -157,8 +176,16 @@ else
>> 	endif
>> 	foreach marg: machine[2]
>> 		if marg[0] == impl_pn
>> -			foreach f: marg[1]
>> -				machine_args += f
>> +			foreach flag: marg[1]
>> +				if cc.has_argument(flag)
>> +					machine_args += flag
>> +				endif
>> +			endforeach
>> +			# Apply any extra machine specific flags.
>> +			foreach flag: marg.get(2, flags_default_extra)
>> +				if flag.length() > 0
>> +					dpdk_conf.set(flag[0], flag[1])
>> +				endif

And setting the extra flags doesn't work well with gcc < 7 because of the following,

        # Primary part number based mcpu flags are supported
        # for gcc versions > 7
        if cc.version().version_compare(
                        '<7.0') or cmd_output.length() == 0
                if not meson.is_cross_build() and arm_force_native_march == true
                        impl_pn = 'native'
                else
                        impl_pn = 'default'
                endif
        endif

Thanks,
Yongseok

>> 			endforeach
>> 		endif
>> 	endforeach
>> -- 
>> 2.21.0

Re: [dpdk-dev] [PATCH v7 4/4] config: add octeontx2 machine config

[Thomas Monjalon]

06/04/2019 16:27, jerinjacobk@gmail.com:
> From: Jerin Jacob <jerinj@marvell.com>
> 
> Optimized configuration for Marvell octeontx2 SoC.
> Updated meson build to support Marvell octeontx2 SoC.
> Added meson cross build target for octeontx2.

I see this error with meson when compiling softnic for octeontx2:

-c ../drivers/net/softnic/rte_eth_softnic_action.c
{standard input}: Assembler messages:
{standard input}:16: Error: selected processor does not support `crc32cx w3,w3,x0'
{standard input}:38: Error: selected processor does not support `crc32cx w1,w1,x3'
{standard input}:44: Error: selected processor does not support `crc32cx w0,w0,x4'
{standard input}:69: Error: selected processor does not support `crc32cx w2,w2,x3'
...

Re: [dpdk-dev] [PATCH v7 4/4] config: add octeontx2 machine config

[Thomas Monjalon]

06/04/2019 16:27, jerinjacobk@gmail.com:
> From: Jerin Jacob <jerinj@marvell.com>
> 
> Optimized configuration for Marvell octeontx2 SoC.
> Updated meson build to support Marvell octeontx2 SoC.
> Added meson cross build target for octeontx2.

I see this error with meson when compiling softnic for octeontx2:

-c ../drivers/net/softnic/rte_eth_softnic_action.c
{standard input}: Assembler messages:
{standard input}:16: Error: selected processor does not support `crc32cx w3,w3,x0'
{standard input}:38: Error: selected processor does not support `crc32cx w1,w1,x3'
{standard input}:44: Error: selected processor does not support `crc32cx w0,w0,x4'
{standard input}:69: Error: selected processor does not support `crc32cx w2,w2,x3'
...

Re: [dpdk-dev] [PATCH v7 4/4] config: add octeontx2 machine config

[Jerin Jacob Kollanukkaran]

On Wed, 2019-04-10 at 14:48 +0200, Thomas Monjalon wrote:
> 06/04/2019 16:27, jerinjacobk@gmail.com:
> > From: Jerin Jacob <jerinj@marvell.com>
> > 
> > Optimized configuration for Marvell octeontx2 SoC.
> > Updated meson build to support Marvell octeontx2 SoC.
> > Added meson cross build target for octeontx2.
> 
> I see this error with meson when compiling softnic for octeontx2:
> 
> -c ../drivers/net/softnic/rte_eth_softnic_action.c
> {standard input}: Assembler messages:
> {standard input}:16: Error: selected processor does not support
> `crc32cx w3,w3,x0'
> {standard input}:38: Error: selected processor does not support
> `crc32cx w1,w1,x3'
> {standard input}:44: Error: selected processor does not support
> `crc32cx w0,w0,x4'
> {standard input}:69: Error: selected processor does not support
> `crc32cx w2,w2,x3'
> ...

I have seen it too. Fix is here

Snippet from cover letter:

v7 Changes:

- Some compiler needs the following depended patch to compile with
meson 
http://patches.dpdk.org/patch/52367/


> 

Re: [dpdk-dev] [PATCH v7 4/4] config: add octeontx2 machine config

[Jerin Jacob Kollanukkaran]

On Wed, 2019-04-10 at 14:48 +0200, Thomas Monjalon wrote:
> 06/04/2019 16:27, jerinjacobk@gmail.com:
> > From: Jerin Jacob <jerinj@marvell.com>
> > 
> > Optimized configuration for Marvell octeontx2 SoC.
> > Updated meson build to support Marvell octeontx2 SoC.
> > Added meson cross build target for octeontx2.
> 
> I see this error with meson when compiling softnic for octeontx2:
> 
> -c ../drivers/net/softnic/rte_eth_softnic_action.c
> {standard input}: Assembler messages:
> {standard input}:16: Error: selected processor does not support
> `crc32cx w3,w3,x0'
> {standard input}:38: Error: selected processor does not support
> `crc32cx w1,w1,x3'
> {standard input}:44: Error: selected processor does not support
> `crc32cx w0,w0,x4'
> {standard input}:69: Error: selected processor does not support
> `crc32cx w2,w2,x3'
> ...

I have seen it too. Fix is here

Snippet from cover letter:

v7 Changes:

- Some compiler needs the following depended patch to compile with
meson 
http://patches.dpdk.org/patch/52367/


> 

Re: [dpdk-dev] [PATCH v7 2/4] meson: add infra to support machine specific flags

[Pavan Nikhilesh Bhagavatula]

>-----Original Message-----
>From: Yongseok Koh <yskoh@mellanox.com>
>Sent: Wednesday, April 10, 2019 7:45 AM
>To: jerinjacobk@gmail.com; Pavan Nikhilesh Bhagavatula
><pbhagavatula@marvell.com>
>Cc: Thomas Monjalon <thomas@monjalon.net>; dev <dev@dpdk.org>; Jerin
>Jacob Kollanukkaran <jerinj@marvell.com>
>Subject: [EXT] Re: [dpdk-dev] [PATCH v7 2/4] meson: add infra to support
>machine specific flags
>
>External Email
>
>----------------------------------------------------------------------
>
>> On Apr 9, 2019, at 5:40 PM, Yongseok Koh <yskoh@mellanox.com> wrote:
>>
>>>
>>> On Apr 6, 2019, at 7:27 AM, jerinjacobk@gmail.com wrote:
>>>
>>> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
>>>
>>> Currently, RTE_* flags are set based on the implementer ID but there
>>> might be some micro arch specific differences from the same vendor
>>> eg. CACHE_LINESIZE. Add support to set micro arch specific flags.
>>>
>>> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
>>> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
>>> ---
>>> config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++-----
>>> 1 file changed, 32 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/config/arm/meson.build b/config/arm/meson.build index
>>> 170a4981a..8de3f3e3a 100644
>>> --- a/config/arm/meson.build
>>> +++ b/config/arm/meson.build
>>> @@ -52,12 +52,10 @@ flags_generic = [
>>> 	['RTE_USE_C11_MEM_MODEL', true],
>>> 	['RTE_CACHE_LINE_SIZE', 128]]
>>> flags_cavium = [
>>> -	['RTE_MACHINE', '"thunderx"'],
>>> 	['RTE_CACHE_LINE_SIZE', 128],
>>> 	['RTE_MAX_NUMA_NODES', 2],
>>> 	['RTE_MAX_LCORE', 96],
>>> -	['RTE_MAX_VFIO_GROUPS', 128],
>>> -	['RTE_USE_C11_MEM_MODEL', false]]
>>> +	['RTE_MAX_VFIO_GROUPS', 128]]
>>> flags_dpaa = [
>>> 	['RTE_MACHINE', '"dpaa"'],
>>> 	['RTE_USE_C11_MEM_MODEL', true],
>>> @@ -71,6 +69,27 @@ flags_dpaa2 = [
>>> 	['RTE_MAX_NUMA_NODES', 1],
>>> 	['RTE_MAX_LCORE', 16],
>>> 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
>>> +flags_default_extra = []
>>> +flags_thunderx_extra = [
>>> +	['RTE_MACHINE', '"thunderx"'],
>>> +	['RTE_USE_C11_MEM_MODEL', false]]
>>> +
>>> +machine_args_generic = [
>>> +	['default', ['-march=armv8-a+crc+crypto']],
>>> +	['native', ['-march=native']],
>>> +	['0xd03', ['-mcpu=cortex-a53']],
>>> +	['0xd04', ['-mcpu=cortex-a35']],
>>> +	['0xd07', ['-mcpu=cortex-a57']],
>>> +	['0xd08', ['-mcpu=cortex-a72']],
>>> +	['0xd09', ['-mcpu=cortex-a73']],
>>> +	['0xd0a', ['-mcpu=cortex-a75']]]
>>> +
>>> +machine_args_cavium = [
>>> +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
>>> +	['native', ['-march=native']],
>>> +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
>>> +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
>>> +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
>>
>> Looks like there's a mistake in rebasing it?

Seems so will send out v8.

>> You should've removed machine_args_generic and machine_args_cavium in
>> the beginning of this file.
>>
>> Other than that, it looks good to me.
>>
>> BTW, thanks for the patch. I raised this issue before and I was
>> supposed to make the change but you have taken it.
>>
>> Yongseok
>>
>>> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page
>>> G7-5321) impl_generic = ['Generic armv8', flags_generic,
>>> machine_args_generic] @@ -157,8 +176,16 @@ else
>>> 	endif
>>> 	foreach marg: machine[2]
>>> 		if marg[0] == impl_pn
>>> -			foreach f: marg[1]
>>> -				machine_args += f
>>> +			foreach flag: marg[1]
>>> +				if cc.has_argument(flag)
>>> +					machine_args += flag
>>> +				endif
>>> +			endforeach
>>> +			# Apply any extra machine specific flags.
>>> +			foreach flag: marg.get(2, flags_default_extra)
>>> +				if flag.length() > 0
>>> +					dpdk_conf.set(flag[0], flag[1])
>>> +				endif
>
>And setting the extra flags doesn't work well with gcc < 7 because of the
>following,

Extra flags aren't set in this case  as the third variable in the list is missing when 'native' or 'default' is selected
generic= 
        ['default', ['-march=armv8-a+crc+crypto']],
        ['native', ['-march=native']]
cavium=
        ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
        ['native', ['-march=native']]

And marg.get falls back to flags_default_extra = [].

>
>        # Primary part number based mcpu flags are supported
>        # for gcc versions > 7
>        if cc.version().version_compare(
>                        '<7.0') or cmd_output.length() == 0
>                if not meson.is_cross_build() and arm_force_native_march == true
>                        impl_pn = 'native'
>                else
>                        impl_pn = 'default'
>                endif
>        endif
>
>Thanks,
>Yongseok
>
>>> 			endforeach
>>> 		endif
>>> 	endforeach
>>> --
>>> 2.21.0

Re: [dpdk-dev] [PATCH v7 2/4] meson: add infra to support machine specific flags

[Pavan Nikhilesh Bhagavatula]

>-----Original Message-----
>From: Yongseok Koh <yskoh@mellanox.com>
>Sent: Wednesday, April 10, 2019 7:45 AM
>To: jerinjacobk@gmail.com; Pavan Nikhilesh Bhagavatula
><pbhagavatula@marvell.com>
>Cc: Thomas Monjalon <thomas@monjalon.net>; dev <dev@dpdk.org>; Jerin
>Jacob Kollanukkaran <jerinj@marvell.com>
>Subject: [EXT] Re: [dpdk-dev] [PATCH v7 2/4] meson: add infra to support
>machine specific flags
>
>External Email
>
>----------------------------------------------------------------------
>
>> On Apr 9, 2019, at 5:40 PM, Yongseok Koh <yskoh@mellanox.com> wrote:
>>
>>>
>>> On Apr 6, 2019, at 7:27 AM, jerinjacobk@gmail.com wrote:
>>>
>>> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
>>>
>>> Currently, RTE_* flags are set based on the implementer ID but there
>>> might be some micro arch specific differences from the same vendor
>>> eg. CACHE_LINESIZE. Add support to set micro arch specific flags.
>>>
>>> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
>>> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
>>> ---
>>> config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++-----
>>> 1 file changed, 32 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/config/arm/meson.build b/config/arm/meson.build index
>>> 170a4981a..8de3f3e3a 100644
>>> --- a/config/arm/meson.build
>>> +++ b/config/arm/meson.build
>>> @@ -52,12 +52,10 @@ flags_generic = [
>>> 	['RTE_USE_C11_MEM_MODEL', true],
>>> 	['RTE_CACHE_LINE_SIZE', 128]]
>>> flags_cavium = [
>>> -	['RTE_MACHINE', '"thunderx"'],
>>> 	['RTE_CACHE_LINE_SIZE', 128],
>>> 	['RTE_MAX_NUMA_NODES', 2],
>>> 	['RTE_MAX_LCORE', 96],
>>> -	['RTE_MAX_VFIO_GROUPS', 128],
>>> -	['RTE_USE_C11_MEM_MODEL', false]]
>>> +	['RTE_MAX_VFIO_GROUPS', 128]]
>>> flags_dpaa = [
>>> 	['RTE_MACHINE', '"dpaa"'],
>>> 	['RTE_USE_C11_MEM_MODEL', true],
>>> @@ -71,6 +69,27 @@ flags_dpaa2 = [
>>> 	['RTE_MAX_NUMA_NODES', 1],
>>> 	['RTE_MAX_LCORE', 16],
>>> 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
>>> +flags_default_extra = []
>>> +flags_thunderx_extra = [
>>> +	['RTE_MACHINE', '"thunderx"'],
>>> +	['RTE_USE_C11_MEM_MODEL', false]]
>>> +
>>> +machine_args_generic = [
>>> +	['default', ['-march=armv8-a+crc+crypto']],
>>> +	['native', ['-march=native']],
>>> +	['0xd03', ['-mcpu=cortex-a53']],
>>> +	['0xd04', ['-mcpu=cortex-a35']],
>>> +	['0xd07', ['-mcpu=cortex-a57']],
>>> +	['0xd08', ['-mcpu=cortex-a72']],
>>> +	['0xd09', ['-mcpu=cortex-a73']],
>>> +	['0xd0a', ['-mcpu=cortex-a75']]]
>>> +
>>> +machine_args_cavium = [
>>> +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
>>> +	['native', ['-march=native']],
>>> +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
>>> +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
>>> +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
>>
>> Looks like there's a mistake in rebasing it?

Seems so will send out v8.

>> You should've removed machine_args_generic and machine_args_cavium in
>> the beginning of this file.
>>
>> Other than that, it looks good to me.
>>
>> BTW, thanks for the patch. I raised this issue before and I was
>> supposed to make the change but you have taken it.
>>
>> Yongseok
>>
>>> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page
>>> G7-5321) impl_generic = ['Generic armv8', flags_generic,
>>> machine_args_generic] @@ -157,8 +176,16 @@ else
>>> 	endif
>>> 	foreach marg: machine[2]
>>> 		if marg[0] == impl_pn
>>> -			foreach f: marg[1]
>>> -				machine_args += f
>>> +			foreach flag: marg[1]
>>> +				if cc.has_argument(flag)
>>> +					machine_args += flag
>>> +				endif
>>> +			endforeach
>>> +			# Apply any extra machine specific flags.
>>> +			foreach flag: marg.get(2, flags_default_extra)
>>> +				if flag.length() > 0
>>> +					dpdk_conf.set(flag[0], flag[1])
>>> +				endif
>
>And setting the extra flags doesn't work well with gcc < 7 because of the
>following,

Extra flags aren't set in this case  as the third variable in the list is missing when 'native' or 'default' is selected
generic= 
        ['default', ['-march=armv8-a+crc+crypto']],
        ['native', ['-march=native']]
cavium=
        ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
        ['native', ['-march=native']]

And marg.get falls back to flags_default_extra = [].

>
>        # Primary part number based mcpu flags are supported
>        # for gcc versions > 7
>        if cc.version().version_compare(
>                        '<7.0') or cmd_output.length() == 0
>                if not meson.is_cross_build() and arm_force_native_march == true
>                        impl_pn = 'native'
>                else
>                        impl_pn = 'default'
>                endif
>        endif
>
>Thanks,
>Yongseok
>
>>> 			endforeach
>>> 		endif
>>> 	endforeach
>>> --
>>> 2.21.0

[dpdk-dev] [PATCH v8 1/4] mk: introduce helper to check valid compiler argument

[jerinjacobk]

From: Jerin Jacob <jerinj@marvell.com>

Introduce rte_cc_has_argument() Makefile helper to
check a given argument is support by the compiler.

Example Usage:

include $(RTE_SDK)/mk/rte.helper.mk
MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)

This would allow adding -mcpu=octeontx2 in MACHINE_CFLAGS
if it is only supported by the compiler. The use case for such
scheme is to enable the mcpu optimization if the compiler
supports else it needs to compile the source code without
any errors.

This patch also moves inclusion of toolchain's rte.vars.mk
to before the machine's rte.vars.mk inclusion to make
correct CC available for the cross compile case.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
Change history of this series:

v8 Changes:
 - Remove redudant lists (rebase aritfacts). (Yongseok Koh)
 
v7 Changes:
 - Updated cross compile config files align with 
 "build: improve pcap dependency handling" changeset to fix build issue with meson
 - Some compiler needs the following depended patch to compile with meson
   http://patches.dpdk.org/patch/52367/

v6 Changes:
 - Rework to change the config files to sync with "mk: use linux and freebsd in config names"
 - Fix the following error with latest gcc by fixing the mcpu type
   cc1: error: switch -mcpu=armv8.2-a conflicts with -march=armv8-a switch 

v5 Changes:
 - Fix incorrect meson flag parsing(Phil Yang)
 - Squash meson cross build patch(5/5) into configuration update patches for
 thunderx2(3/5) and octeontx2(4/5)(Thomas)
 - Changed octeontx2's march as armv8-a and added the extension required
   instead of armv8-2a(Phil Yang)
 - Improved rte_cc_has_argument() implementaion by removing the temp
   file(Thomas)

v4 Changes:
 - Fix incorrect signoff marrvell -> marvell.

v3 Changes:
 - Squash meson build support into config support for thunderx2/octeontx2.

v2 Changes:
 - Add meson build support.

---
 mk/rte.helper.mk              | 10 ++++++++++
 mk/target/generic/rte.vars.mk | 22 +++++++++++-----------
 2 files changed, 21 insertions(+), 11 deletions(-)
 create mode 100644 mk/rte.helper.mk

diff --git a/mk/rte.helper.mk b/mk/rte.helper.mk
new file mode 100644
index 000000000..6e7fd03d7
--- /dev/null
+++ b/mk/rte.helper.mk
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+
+# rte_cc_has_argument
+# Usage: MACHINE_CFLAGS += $(call rte_cc_has_argument, -mno-avx512f)
+# Return the argument if the argument is supported by the compiler.
+#
+define rte_cc_has_argument
+	$(shell $(CC) -E $(1) -xc /dev/null 1>/dev/null 2>/dev/null && echo $(1))
+endef
diff --git a/mk/target/generic/rte.vars.mk b/mk/target/generic/rte.vars.mk
index dd149acc9..25a578ad7 100644
--- a/mk/target/generic/rte.vars.mk
+++ b/mk/target/generic/rte.vars.mk
@@ -7,6 +7,17 @@
 # executive environment.
 #
 
+#
+# toolchain:
+#
+#   - define CC, LD, AR, AS, ...
+#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
+#   - may override any previously defined variable
+#
+include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
+
 #
 # machine:
 #
@@ -45,17 +56,6 @@ endif
 #
 include $(RTE_SDK)/mk/arch/$(RTE_ARCH)/rte.vars.mk
 
-#
-# toolchain:
-#
-#   - define CC, LD, AR, AS, ...
-#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
-#   - may override any previously defined variable
-#
-include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
-
 #
 # exec-env:
 #
-- 
2.21.0

[dpdk-dev] [PATCH v8 1/4] mk: introduce helper to check valid compiler argument

[jerinjacobk]

From: Jerin Jacob <jerinj@marvell.com>

Introduce rte_cc_has_argument() Makefile helper to
check a given argument is support by the compiler.

Example Usage:

include $(RTE_SDK)/mk/rte.helper.mk
MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)

This would allow adding -mcpu=octeontx2 in MACHINE_CFLAGS
if it is only supported by the compiler. The use case for such
scheme is to enable the mcpu optimization if the compiler
supports else it needs to compile the source code without
any errors.

This patch also moves inclusion of toolchain's rte.vars.mk
to before the machine's rte.vars.mk inclusion to make
correct CC available for the cross compile case.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
Change history of this series:

v8 Changes:
 - Remove redudant lists (rebase aritfacts). (Yongseok Koh)
 
v7 Changes:
 - Updated cross compile config files align with 
 "build: improve pcap dependency handling" changeset to fix build issue with meson
 - Some compiler needs the following depended patch to compile with meson
   http://patches.dpdk.org/patch/52367/

v6 Changes:
 - Rework to change the config files to sync with "mk: use linux and freebsd in config names"
 - Fix the following error with latest gcc by fixing the mcpu type
   cc1: error: switch -mcpu=armv8.2-a conflicts with -march=armv8-a switch 

v5 Changes:
 - Fix incorrect meson flag parsing(Phil Yang)
 - Squash meson cross build patch(5/5) into configuration update patches for
 thunderx2(3/5) and octeontx2(4/5)(Thomas)
 - Changed octeontx2's march as armv8-a and added the extension required
   instead of armv8-2a(Phil Yang)
 - Improved rte_cc_has_argument() implementaion by removing the temp
   file(Thomas)

v4 Changes:
 - Fix incorrect signoff marrvell -> marvell.

v3 Changes:
 - Squash meson build support into config support for thunderx2/octeontx2.

v2 Changes:
 - Add meson build support.

---
 mk/rte.helper.mk              | 10 ++++++++++
 mk/target/generic/rte.vars.mk | 22 +++++++++++-----------
 2 files changed, 21 insertions(+), 11 deletions(-)
 create mode 100644 mk/rte.helper.mk

diff --git a/mk/rte.helper.mk b/mk/rte.helper.mk
new file mode 100644
index 000000000..6e7fd03d7
--- /dev/null
+++ b/mk/rte.helper.mk
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+
+# rte_cc_has_argument
+# Usage: MACHINE_CFLAGS += $(call rte_cc_has_argument, -mno-avx512f)
+# Return the argument if the argument is supported by the compiler.
+#
+define rte_cc_has_argument
+	$(shell $(CC) -E $(1) -xc /dev/null 1>/dev/null 2>/dev/null && echo $(1))
+endef
diff --git a/mk/target/generic/rte.vars.mk b/mk/target/generic/rte.vars.mk
index dd149acc9..25a578ad7 100644
--- a/mk/target/generic/rte.vars.mk
+++ b/mk/target/generic/rte.vars.mk
@@ -7,6 +7,17 @@
 # executive environment.
 #
 
+#
+# toolchain:
+#
+#   - define CC, LD, AR, AS, ...
+#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
+#   - may override any previously defined variable
+#
+include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
+
 #
 # machine:
 #
@@ -45,17 +56,6 @@ endif
 #
 include $(RTE_SDK)/mk/arch/$(RTE_ARCH)/rte.vars.mk
 
-#
-# toolchain:
-#
-#   - define CC, LD, AR, AS, ...
-#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
-#   - may override any previously defined variable
-#
-include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
-
 #
 # exec-env:
 #
-- 
2.21.0

[dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[jerinjacobk]

From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Currently, RTE_* flags are set based on the implementer ID but there might
be some micro arch specific differences from the same vendor
eg. CACHE_LINESIZE. Add support to set micro arch specific flags.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
---
 config/arm/meson.build | 56 ++++++++++++++++++++++++------------------
 1 file changed, 32 insertions(+), 24 deletions(-)

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 170a4981a..24bce2b39 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -7,25 +7,6 @@ march_opt = '-march=@0@'.format(machine)
 
 arm_force_native_march = false
 
-machine_args_generic = [
-	['default', ['-march=armv8-a+crc+crypto']],
-	['native', ['-march=native']],
-	['0xd03', ['-mcpu=cortex-a53']],
-	['0xd04', ['-mcpu=cortex-a35']],
-	['0xd05', ['-mcpu=cortex-a55']],
-	['0xd07', ['-mcpu=cortex-a57']],
-	['0xd08', ['-mcpu=cortex-a72']],
-	['0xd09', ['-mcpu=cortex-a73']],
-	['0xd0a', ['-mcpu=cortex-a75']],
-	['0xd0b', ['-mcpu=cortex-a76']],
-]
-machine_args_cavium = [
-	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
-	['native', ['-march=native']],
-	['0xa1', ['-mcpu=thunderxt88']],
-	['0xa2', ['-mcpu=thunderxt81']],
-	['0xa3', ['-mcpu=thunderxt83']]]
-
 flags_common_default = [
 	# Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
 	# to determine the best threshold in code. Refer to notes in source file
@@ -52,12 +33,10 @@ flags_generic = [
 	['RTE_USE_C11_MEM_MODEL', true],
 	['RTE_CACHE_LINE_SIZE', 128]]
 flags_cavium = [
-	['RTE_MACHINE', '"thunderx"'],
 	['RTE_CACHE_LINE_SIZE', 128],
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 96],
-	['RTE_MAX_VFIO_GROUPS', 128],
-	['RTE_USE_C11_MEM_MODEL', false]]
+	['RTE_MAX_VFIO_GROUPS', 128]]
 flags_dpaa = [
 	['RTE_MACHINE', '"dpaa"'],
 	['RTE_USE_C11_MEM_MODEL', true],
@@ -71,6 +50,27 @@ flags_dpaa2 = [
 	['RTE_MAX_NUMA_NODES', 1],
 	['RTE_MAX_LCORE', 16],
 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
+flags_default_extra = []
+flags_thunderx_extra = [
+	['RTE_MACHINE', '"thunderx"'],
+	['RTE_USE_C11_MEM_MODEL', false]]
+
+machine_args_generic = [
+	['default', ['-march=armv8-a+crc+crypto']],
+	['native', ['-march=native']],
+	['0xd03', ['-mcpu=cortex-a53']],
+	['0xd04', ['-mcpu=cortex-a35']],
+	['0xd07', ['-mcpu=cortex-a57']],
+	['0xd08', ['-mcpu=cortex-a72']],
+	['0xd09', ['-mcpu=cortex-a73']],
+	['0xd0a', ['-mcpu=cortex-a75']]]
+
+machine_args_cavium = [
+	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
+	['native', ['-march=native']],
+	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
+	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
@@ -157,8 +157,16 @@ else
 	endif
 	foreach marg: machine[2]
 		if marg[0] == impl_pn
-			foreach f: marg[1]
-				machine_args += f
+			foreach flag: marg[1]
+				if cc.has_argument(flag)
+					machine_args += flag
+				endif
+			endforeach
+			# Apply any extra machine specific flags.
+			foreach flag: marg.get(2, flags_default_extra)
+				if flag.length() > 0
+					dpdk_conf.set(flag[0], flag[1])
+				endif
 			endforeach
 		endif
 	endforeach
-- 
2.21.0

[dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[jerinjacobk]

From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Currently, RTE_* flags are set based on the implementer ID but there might
be some micro arch specific differences from the same vendor
eg. CACHE_LINESIZE. Add support to set micro arch specific flags.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
---
 config/arm/meson.build | 56 ++++++++++++++++++++++++------------------
 1 file changed, 32 insertions(+), 24 deletions(-)

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 170a4981a..24bce2b39 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -7,25 +7,6 @@ march_opt = '-march=@0@'.format(machine)
 
 arm_force_native_march = false
 
-machine_args_generic = [
-	['default', ['-march=armv8-a+crc+crypto']],
-	['native', ['-march=native']],
-	['0xd03', ['-mcpu=cortex-a53']],
-	['0xd04', ['-mcpu=cortex-a35']],
-	['0xd05', ['-mcpu=cortex-a55']],
-	['0xd07', ['-mcpu=cortex-a57']],
-	['0xd08', ['-mcpu=cortex-a72']],
-	['0xd09', ['-mcpu=cortex-a73']],
-	['0xd0a', ['-mcpu=cortex-a75']],
-	['0xd0b', ['-mcpu=cortex-a76']],
-]
-machine_args_cavium = [
-	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
-	['native', ['-march=native']],
-	['0xa1', ['-mcpu=thunderxt88']],
-	['0xa2', ['-mcpu=thunderxt81']],
-	['0xa3', ['-mcpu=thunderxt83']]]
-
 flags_common_default = [
 	# Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
 	# to determine the best threshold in code. Refer to notes in source file
@@ -52,12 +33,10 @@ flags_generic = [
 	['RTE_USE_C11_MEM_MODEL', true],
 	['RTE_CACHE_LINE_SIZE', 128]]
 flags_cavium = [
-	['RTE_MACHINE', '"thunderx"'],
 	['RTE_CACHE_LINE_SIZE', 128],
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 96],
-	['RTE_MAX_VFIO_GROUPS', 128],
-	['RTE_USE_C11_MEM_MODEL', false]]
+	['RTE_MAX_VFIO_GROUPS', 128]]
 flags_dpaa = [
 	['RTE_MACHINE', '"dpaa"'],
 	['RTE_USE_C11_MEM_MODEL', true],
@@ -71,6 +50,27 @@ flags_dpaa2 = [
 	['RTE_MAX_NUMA_NODES', 1],
 	['RTE_MAX_LCORE', 16],
 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
+flags_default_extra = []
+flags_thunderx_extra = [
+	['RTE_MACHINE', '"thunderx"'],
+	['RTE_USE_C11_MEM_MODEL', false]]
+
+machine_args_generic = [
+	['default', ['-march=armv8-a+crc+crypto']],
+	['native', ['-march=native']],
+	['0xd03', ['-mcpu=cortex-a53']],
+	['0xd04', ['-mcpu=cortex-a35']],
+	['0xd07', ['-mcpu=cortex-a57']],
+	['0xd08', ['-mcpu=cortex-a72']],
+	['0xd09', ['-mcpu=cortex-a73']],
+	['0xd0a', ['-mcpu=cortex-a75']]]
+
+machine_args_cavium = [
+	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
+	['native', ['-march=native']],
+	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
+	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
@@ -157,8 +157,16 @@ else
 	endif
 	foreach marg: machine[2]
 		if marg[0] == impl_pn
-			foreach f: marg[1]
-				machine_args += f
+			foreach flag: marg[1]
+				if cc.has_argument(flag)
+					machine_args += flag
+				endif
+			endforeach
+			# Apply any extra machine specific flags.
+			foreach flag: marg.get(2, flags_default_extra)
+				if flag.length() > 0
+					dpdk_conf.set(flag[0], flag[1])
+				endif
 			endforeach
 		endif
 	endforeach
-- 
2.21.0

[dpdk-dev] [PATCH v8 3/4] config: add thunderx2 machine config

[jerinjacobk]

From: Jerin Jacob <jerinj@marvell.com>

Optimized configuration for Marvell thunderx2 SoC.
Updated meson build to support Marvell thunderx2 SoC.
Added meson cross compile target.

Product details are here:

https://www.marvell.com/server-processors/thunderx2-arm-processors/

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
---
 config/arm/arm64_thunderx2_linux_gcc          | 16 +++++++++
 config/arm/meson.build                        |  9 ++++-
 config/defconfig_arm64-thunderx2-linux-gcc    |  1 +
 config/defconfig_arm64-thunderx2-linuxapp-gcc | 11 ++++++
 mk/machine/thunderx2/rte.vars.mk              | 34 +++++++++++++++++++
 5 files changed, 70 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/arm64_thunderx2_linux_gcc
 create mode 120000 config/defconfig_arm64-thunderx2-linux-gcc
 create mode 100644 config/defconfig_arm64-thunderx2-linuxapp-gcc
 create mode 100644 mk/machine/thunderx2/rte.vars.mk

diff --git a/config/arm/arm64_thunderx2_linux_gcc b/config/arm/arm64_thunderx2_linux_gcc
new file mode 100644
index 000000000..0dc275644
--- /dev/null
+++ b/config/arm/arm64_thunderx2_linux_gcc
@@ -0,0 +1,16 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x43'
+implementor_pn = '0xaf'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 24bce2b39..3220b584f 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -54,6 +54,12 @@ flags_default_extra = []
 flags_thunderx_extra = [
 	['RTE_MACHINE', '"thunderx"'],
 	['RTE_USE_C11_MEM_MODEL', false]]
+flags_thunderx2_extra = [
+	['RTE_MACHINE', '"thunderx2"'],
+	['RTE_CACHE_LINE_SIZE', 64],
+	['RTE_MAX_NUMA_NODES', 2],
+	['RTE_MAX_LCORE', 256],
+	['RTE_USE_C11_MEM_MODEL', true]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -70,7 +76,8 @@ machine_args_cavium = [
 	['native', ['-march=native']],
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
-	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-thunderx2-linux-gcc b/config/defconfig_arm64-thunderx2-linux-gcc
new file mode 120000
index 000000000..b40a760b1
--- /dev/null
+++ b/config/defconfig_arm64-thunderx2-linux-gcc
@@ -0,0 +1 @@
+defconfig_arm64-thunderx2-linuxapp-gcc
\ No newline at end of file
diff --git a/config/defconfig_arm64-thunderx2-linuxapp-gcc b/config/defconfig_arm64-thunderx2-linuxapp-gcc
new file mode 100644
index 000000000..cc5c64ba0
--- /dev/null
+++ b/config/defconfig_arm64-thunderx2-linuxapp-gcc
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linux-gcc"
+
+CONFIG_RTE_MACHINE="thunderx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=64
+CONFIG_RTE_MAX_NUMA_NODES=2
+CONFIG_RTE_MAX_LCORE=256
diff --git a/mk/machine/thunderx2/rte.vars.mk b/mk/machine/thunderx2/rte.vars.mk
new file mode 100644
index 000000000..b80dc8680
--- /dev/null
+++ b/mk/machine/thunderx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.1-a+crc+crypto)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=thunderx2t99)
-- 
2.21.0

[dpdk-dev] [PATCH v8 3/4] config: add thunderx2 machine config

[jerinjacobk]

From: Jerin Jacob <jerinj@marvell.com>

Optimized configuration for Marvell thunderx2 SoC.
Updated meson build to support Marvell thunderx2 SoC.
Added meson cross compile target.

Product details are here:

https://www.marvell.com/server-processors/thunderx2-arm-processors/

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
---
 config/arm/arm64_thunderx2_linux_gcc          | 16 +++++++++
 config/arm/meson.build                        |  9 ++++-
 config/defconfig_arm64-thunderx2-linux-gcc    |  1 +
 config/defconfig_arm64-thunderx2-linuxapp-gcc | 11 ++++++
 mk/machine/thunderx2/rte.vars.mk              | 34 +++++++++++++++++++
 5 files changed, 70 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/arm64_thunderx2_linux_gcc
 create mode 120000 config/defconfig_arm64-thunderx2-linux-gcc
 create mode 100644 config/defconfig_arm64-thunderx2-linuxapp-gcc
 create mode 100644 mk/machine/thunderx2/rte.vars.mk

diff --git a/config/arm/arm64_thunderx2_linux_gcc b/config/arm/arm64_thunderx2_linux_gcc
new file mode 100644
index 000000000..0dc275644
--- /dev/null
+++ b/config/arm/arm64_thunderx2_linux_gcc
@@ -0,0 +1,16 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x43'
+implementor_pn = '0xaf'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 24bce2b39..3220b584f 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -54,6 +54,12 @@ flags_default_extra = []
 flags_thunderx_extra = [
 	['RTE_MACHINE', '"thunderx"'],
 	['RTE_USE_C11_MEM_MODEL', false]]
+flags_thunderx2_extra = [
+	['RTE_MACHINE', '"thunderx2"'],
+	['RTE_CACHE_LINE_SIZE', 64],
+	['RTE_MAX_NUMA_NODES', 2],
+	['RTE_MAX_LCORE', 256],
+	['RTE_USE_C11_MEM_MODEL', true]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -70,7 +76,8 @@ machine_args_cavium = [
 	['native', ['-march=native']],
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
-	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-thunderx2-linux-gcc b/config/defconfig_arm64-thunderx2-linux-gcc
new file mode 120000
index 000000000..b40a760b1
--- /dev/null
+++ b/config/defconfig_arm64-thunderx2-linux-gcc
@@ -0,0 +1 @@
+defconfig_arm64-thunderx2-linuxapp-gcc
\ No newline at end of file
diff --git a/config/defconfig_arm64-thunderx2-linuxapp-gcc b/config/defconfig_arm64-thunderx2-linuxapp-gcc
new file mode 100644
index 000000000..cc5c64ba0
--- /dev/null
+++ b/config/defconfig_arm64-thunderx2-linuxapp-gcc
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linux-gcc"
+
+CONFIG_RTE_MACHINE="thunderx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=64
+CONFIG_RTE_MAX_NUMA_NODES=2
+CONFIG_RTE_MAX_LCORE=256
diff --git a/mk/machine/thunderx2/rte.vars.mk b/mk/machine/thunderx2/rte.vars.mk
new file mode 100644
index 000000000..b80dc8680
--- /dev/null
+++ b/mk/machine/thunderx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.1-a+crc+crypto)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=thunderx2t99)
-- 
2.21.0

[dpdk-dev] [PATCH v8 4/4] config: add octeontx2 machine config

[jerinjacobk]

From: Jerin Jacob <jerinj@marvell.com>

Optimized configuration for Marvell octeontx2 SoC.
Updated meson build to support Marvell octeontx2 SoC.
Added meson cross build target for octeontx2.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
---
 config/arm/arm64_octeontx2_linux_gcc          | 16 +++++++++
 config/arm/meson.build                        |  9 ++++-
 config/defconfig_arm64-octeontx2-linux-gcc    |  1 +
 config/defconfig_arm64-octeontx2-linuxapp-gcc | 18 ++++++++++
 mk/machine/octeontx2/rte.vars.mk              | 34 +++++++++++++++++++
 5 files changed, 77 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/arm64_octeontx2_linux_gcc
 create mode 120000 config/defconfig_arm64-octeontx2-linux-gcc
 create mode 100644 config/defconfig_arm64-octeontx2-linuxapp-gcc
 create mode 100644 mk/machine/octeontx2/rte.vars.mk

diff --git a/config/arm/arm64_octeontx2_linux_gcc b/config/arm/arm64_octeontx2_linux_gcc
new file mode 100644
index 000000000..e2c0b8f72
--- /dev/null
+++ b/config/arm/arm64_octeontx2_linux_gcc
@@ -0,0 +1,16 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x43'
+implementor_pn = '0xb2'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 3220b584f..0708bc64a 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -60,6 +60,12 @@ flags_thunderx2_extra = [
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 256],
 	['RTE_USE_C11_MEM_MODEL', true]]
+flags_octeontx2_extra = [
+	['RTE_MACHINE', '"octeontx2"'],
+	['RTE_MAX_NUMA_NODES', 1],
+	['RTE_MAX_LCORE', 24],
+	['RTE_EAL_IGB_UIO', false],
+	['RTE_USE_C11_MEM_MODEL', true]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -77,7 +83,8 @@ machine_args_cavium = [
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
 	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
-	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra],
+	['0xb2', ['-mcpu=octeontx2'], flags_octeontx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-octeontx2-linux-gcc b/config/defconfig_arm64-octeontx2-linux-gcc
new file mode 120000
index 000000000..e25150531
--- /dev/null
+++ b/config/defconfig_arm64-octeontx2-linux-gcc
@@ -0,0 +1 @@
+defconfig_arm64-octeontx2-linuxapp-gcc
\ No newline at end of file
diff --git a/config/defconfig_arm64-octeontx2-linuxapp-gcc b/config/defconfig_arm64-octeontx2-linuxapp-gcc
new file mode 100644
index 000000000..9eae84538
--- /dev/null
+++ b/config/defconfig_arm64-octeontx2-linuxapp-gcc
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linux-gcc"
+
+CONFIG_RTE_MACHINE="octeontx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=128
+CONFIG_RTE_MAX_NUMA_NODES=1
+CONFIG_RTE_MAX_LCORE=24
+
+# Doesn't support NUMA
+CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
+CONFIG_RTE_LIBRTE_VHOST_NUMA=n
+
+# Recommend to use VFIO as co-processors needs SMMU/IOMMU
+CONFIG_RTE_EAL_IGB_UIO=n
diff --git a/mk/machine/octeontx2/rte.vars.mk b/mk/machine/octeontx2/rte.vars.mk
new file mode 100644
index 000000000..cbec7f14d
--- /dev/null
+++ b/mk/machine/octeontx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=-mcpu=armv8.2-a+crc+crypto+lse)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)
-- 
2.21.0

[dpdk-dev] [PATCH v8 4/4] config: add octeontx2 machine config

[jerinjacobk]

From: Jerin Jacob <jerinj@marvell.com>

Optimized configuration for Marvell octeontx2 SoC.
Updated meson build to support Marvell octeontx2 SoC.
Added meson cross build target for octeontx2.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
---
 config/arm/arm64_octeontx2_linux_gcc          | 16 +++++++++
 config/arm/meson.build                        |  9 ++++-
 config/defconfig_arm64-octeontx2-linux-gcc    |  1 +
 config/defconfig_arm64-octeontx2-linuxapp-gcc | 18 ++++++++++
 mk/machine/octeontx2/rte.vars.mk              | 34 +++++++++++++++++++
 5 files changed, 77 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/arm64_octeontx2_linux_gcc
 create mode 120000 config/defconfig_arm64-octeontx2-linux-gcc
 create mode 100644 config/defconfig_arm64-octeontx2-linuxapp-gcc
 create mode 100644 mk/machine/octeontx2/rte.vars.mk

diff --git a/config/arm/arm64_octeontx2_linux_gcc b/config/arm/arm64_octeontx2_linux_gcc
new file mode 100644
index 000000000..e2c0b8f72
--- /dev/null
+++ b/config/arm/arm64_octeontx2_linux_gcc
@@ -0,0 +1,16 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x43'
+implementor_pn = '0xb2'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 3220b584f..0708bc64a 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -60,6 +60,12 @@ flags_thunderx2_extra = [
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 256],
 	['RTE_USE_C11_MEM_MODEL', true]]
+flags_octeontx2_extra = [
+	['RTE_MACHINE', '"octeontx2"'],
+	['RTE_MAX_NUMA_NODES', 1],
+	['RTE_MAX_LCORE', 24],
+	['RTE_EAL_IGB_UIO', false],
+	['RTE_USE_C11_MEM_MODEL', true]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -77,7 +83,8 @@ machine_args_cavium = [
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
 	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
-	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra],
+	['0xb2', ['-mcpu=octeontx2'], flags_octeontx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-octeontx2-linux-gcc b/config/defconfig_arm64-octeontx2-linux-gcc
new file mode 120000
index 000000000..e25150531
--- /dev/null
+++ b/config/defconfig_arm64-octeontx2-linux-gcc
@@ -0,0 +1 @@
+defconfig_arm64-octeontx2-linuxapp-gcc
\ No newline at end of file
diff --git a/config/defconfig_arm64-octeontx2-linuxapp-gcc b/config/defconfig_arm64-octeontx2-linuxapp-gcc
new file mode 100644
index 000000000..9eae84538
--- /dev/null
+++ b/config/defconfig_arm64-octeontx2-linuxapp-gcc
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linux-gcc"
+
+CONFIG_RTE_MACHINE="octeontx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=128
+CONFIG_RTE_MAX_NUMA_NODES=1
+CONFIG_RTE_MAX_LCORE=24
+
+# Doesn't support NUMA
+CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
+CONFIG_RTE_LIBRTE_VHOST_NUMA=n
+
+# Recommend to use VFIO as co-processors needs SMMU/IOMMU
+CONFIG_RTE_EAL_IGB_UIO=n
diff --git a/mk/machine/octeontx2/rte.vars.mk b/mk/machine/octeontx2/rte.vars.mk
new file mode 100644
index 000000000..cbec7f14d
--- /dev/null
+++ b/mk/machine/octeontx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=-mcpu=armv8.2-a+crc+crypto+lse)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)
-- 
2.21.0

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Yongseok Koh]

> On Apr 10, 2019, at 9:13 AM, jerinjacobk@gmail.com wrote:
> 
> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> 
> Currently, RTE_* flags are set based on the implementer ID but there might
> be some micro arch specific differences from the same vendor
> eg. CACHE_LINESIZE. Add support to set micro arch specific flags.
> 
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> ---
> config/arm/meson.build | 56 ++++++++++++++++++++++++------------------
> 1 file changed, 32 insertions(+), 24 deletions(-)
> 
> diff --git a/config/arm/meson.build b/config/arm/meson.build
> index 170a4981a..24bce2b39 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -7,25 +7,6 @@ march_opt = '-march=@0@'.format(machine)
> 
> arm_force_native_march = false
> 
> -machine_args_generic = [
> -	['default', ['-march=armv8-a+crc+crypto']],
> -	['native', ['-march=native']],
> -	['0xd03', ['-mcpu=cortex-a53']],
> -	['0xd04', ['-mcpu=cortex-a35']],
> -	['0xd05', ['-mcpu=cortex-a55']],
> -	['0xd07', ['-mcpu=cortex-a57']],
> -	['0xd08', ['-mcpu=cortex-a72']],
> -	['0xd09', ['-mcpu=cortex-a73']],
> -	['0xd0a', ['-mcpu=cortex-a75']],
> -	['0xd0b', ['-mcpu=cortex-a76']],
> -]
> -machine_args_cavium = [
> -	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> -	['native', ['-march=native']],
> -	['0xa1', ['-mcpu=thunderxt88']],
> -	['0xa2', ['-mcpu=thunderxt81']],
> -	['0xa3', ['-mcpu=thunderxt83']]]
> -
> flags_common_default = [
> 	# Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
> 	# to determine the best threshold in code. Refer to notes in source file
> @@ -52,12 +33,10 @@ flags_generic = [
> 	['RTE_USE_C11_MEM_MODEL', true],
> 	['RTE_CACHE_LINE_SIZE', 128]]
> flags_cavium = [
> -	['RTE_MACHINE', '"thunderx"'],
> 	['RTE_CACHE_LINE_SIZE', 128],
> 	['RTE_MAX_NUMA_NODES', 2],
> 	['RTE_MAX_LCORE', 96],
> -	['RTE_MAX_VFIO_GROUPS', 128],
> -	['RTE_USE_C11_MEM_MODEL', false]]
> +	['RTE_MAX_VFIO_GROUPS', 128]]
> flags_dpaa = [
> 	['RTE_MACHINE', '"dpaa"'],
> 	['RTE_USE_C11_MEM_MODEL', true],
> @@ -71,6 +50,27 @@ flags_dpaa2 = [
> 	['RTE_MAX_NUMA_NODES', 1],
> 	['RTE_MAX_LCORE', 16],
> 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
> +flags_default_extra = []
> +flags_thunderx_extra = [
> +	['RTE_MACHINE', '"thunderx"'],
> +	['RTE_USE_C11_MEM_MODEL', false]]
> +
> +machine_args_generic = [
> +	['default', ['-march=armv8-a+crc+crypto']],
> +	['native', ['-march=native']],
> +	['0xd03', ['-mcpu=cortex-a53']],
> +	['0xd04', ['-mcpu=cortex-a35']],
> +	['0xd07', ['-mcpu=cortex-a57']],
> +	['0xd08', ['-mcpu=cortex-a72']],
> +	['0xd09', ['-mcpu=cortex-a73']],
> +	['0xd0a', ['-mcpu=cortex-a75']]]
> +
> +machine_args_cavium = [
> +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> +	['native', ['-march=native']],
> +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
> +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
> +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
> 
> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
> impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
> @@ -157,8 +157,16 @@ else
> 	endif
> 	foreach marg: machine[2]
> 		if marg[0] == impl_pn
> -			foreach f: marg[1]
> -				machine_args += f
> +			foreach flag: marg[1]
> +				if cc.has_argument(flag)
> +					machine_args += flag
> +				endif
> +			endforeach
> +			# Apply any extra machine specific flags.
> +			foreach flag: marg.get(2, flags_default_extra)
> +				if flag.length() > 0
> +					dpdk_conf.set(flag[0], flag[1])
> +				endif

Let me continue the discussion from v7 here.
Seems I wan't clear enough.

Let me take an example. If the host is thunderx2 (0xaf) and compiler is older
than v7, flags_thunderx2_extra isn't set. This means, for example,
RTE_CACHE_LINE_SIZE will still be 128. Is that what you want?
RTE_CACHE_LINE_SIZE has nothing to do with compiler support and you might want
to set it regardless of gcc version. You could skip setting -mcpu with setting
the extra flags.

Thoughts?

Thanks,
Yongseok

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Yongseok Koh]

> On Apr 10, 2019, at 9:13 AM, jerinjacobk@gmail.com wrote:
> 
> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> 
> Currently, RTE_* flags are set based on the implementer ID but there might
> be some micro arch specific differences from the same vendor
> eg. CACHE_LINESIZE. Add support to set micro arch specific flags.
> 
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> ---
> config/arm/meson.build | 56 ++++++++++++++++++++++++------------------
> 1 file changed, 32 insertions(+), 24 deletions(-)
> 
> diff --git a/config/arm/meson.build b/config/arm/meson.build
> index 170a4981a..24bce2b39 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -7,25 +7,6 @@ march_opt = '-march=@0@'.format(machine)
> 
> arm_force_native_march = false
> 
> -machine_args_generic = [
> -	['default', ['-march=armv8-a+crc+crypto']],
> -	['native', ['-march=native']],
> -	['0xd03', ['-mcpu=cortex-a53']],
> -	['0xd04', ['-mcpu=cortex-a35']],
> -	['0xd05', ['-mcpu=cortex-a55']],
> -	['0xd07', ['-mcpu=cortex-a57']],
> -	['0xd08', ['-mcpu=cortex-a72']],
> -	['0xd09', ['-mcpu=cortex-a73']],
> -	['0xd0a', ['-mcpu=cortex-a75']],
> -	['0xd0b', ['-mcpu=cortex-a76']],
> -]
> -machine_args_cavium = [
> -	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> -	['native', ['-march=native']],
> -	['0xa1', ['-mcpu=thunderxt88']],
> -	['0xa2', ['-mcpu=thunderxt81']],
> -	['0xa3', ['-mcpu=thunderxt83']]]
> -
> flags_common_default = [
> 	# Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
> 	# to determine the best threshold in code. Refer to notes in source file
> @@ -52,12 +33,10 @@ flags_generic = [
> 	['RTE_USE_C11_MEM_MODEL', true],
> 	['RTE_CACHE_LINE_SIZE', 128]]
> flags_cavium = [
> -	['RTE_MACHINE', '"thunderx"'],
> 	['RTE_CACHE_LINE_SIZE', 128],
> 	['RTE_MAX_NUMA_NODES', 2],
> 	['RTE_MAX_LCORE', 96],
> -	['RTE_MAX_VFIO_GROUPS', 128],
> -	['RTE_USE_C11_MEM_MODEL', false]]
> +	['RTE_MAX_VFIO_GROUPS', 128]]
> flags_dpaa = [
> 	['RTE_MACHINE', '"dpaa"'],
> 	['RTE_USE_C11_MEM_MODEL', true],
> @@ -71,6 +50,27 @@ flags_dpaa2 = [
> 	['RTE_MAX_NUMA_NODES', 1],
> 	['RTE_MAX_LCORE', 16],
> 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
> +flags_default_extra = []
> +flags_thunderx_extra = [
> +	['RTE_MACHINE', '"thunderx"'],
> +	['RTE_USE_C11_MEM_MODEL', false]]
> +
> +machine_args_generic = [
> +	['default', ['-march=armv8-a+crc+crypto']],
> +	['native', ['-march=native']],
> +	['0xd03', ['-mcpu=cortex-a53']],
> +	['0xd04', ['-mcpu=cortex-a35']],
> +	['0xd07', ['-mcpu=cortex-a57']],
> +	['0xd08', ['-mcpu=cortex-a72']],
> +	['0xd09', ['-mcpu=cortex-a73']],
> +	['0xd0a', ['-mcpu=cortex-a75']]]
> +
> +machine_args_cavium = [
> +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> +	['native', ['-march=native']],
> +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
> +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
> +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
> 
> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
> impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
> @@ -157,8 +157,16 @@ else
> 	endif
> 	foreach marg: machine[2]
> 		if marg[0] == impl_pn
> -			foreach f: marg[1]
> -				machine_args += f
> +			foreach flag: marg[1]
> +				if cc.has_argument(flag)
> +					machine_args += flag
> +				endif
> +			endforeach
> +			# Apply any extra machine specific flags.
> +			foreach flag: marg.get(2, flags_default_extra)
> +				if flag.length() > 0
> +					dpdk_conf.set(flag[0], flag[1])
> +				endif

Let me continue the discussion from v7 here.
Seems I wan't clear enough.

Let me take an example. If the host is thunderx2 (0xaf) and compiler is older
than v7, flags_thunderx2_extra isn't set. This means, for example,
RTE_CACHE_LINE_SIZE will still be 128. Is that what you want?
RTE_CACHE_LINE_SIZE has nothing to do with compiler support and you might want
to set it regardless of gcc version. You could skip setting -mcpu with setting
the extra flags.

Thoughts?

Thanks,
Yongseok

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Pavan Nikhilesh Bhagavatula]

Hi Yongseok,

>-----Original Message-----
>From: Yongseok Koh <yskoh@mellanox.com>
>Sent: Wednesday, April 10, 2019 11:08 PM
>To: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>
>Cc: Thomas Monjalon <thomas@monjalon.net>; dev <dev@dpdk.org>; Jerin
>Jacob Kollanukkaran <jerinj@marvell.com>; jerinjacobk@gmail.com
>Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support
>machine specific flags
>
>External Email
>
>----------------------------------------------------------------------
>
>> On Apr 10, 2019, at 9:13 AM, jerinjacobk@gmail.com wrote:
>>
>> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
>>
>> Currently, RTE_* flags are set based on the implementer ID but there
>> might be some micro arch specific differences from the same vendor eg.
>> CACHE_LINESIZE. Add support to set micro arch specific flags.
>>
>> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
>> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
>> ---
>> config/arm/meson.build | 56 ++++++++++++++++++++++++------------------
>> 1 file changed, 32 insertions(+), 24 deletions(-)
>>
>> diff --git a/config/arm/meson.build b/config/arm/meson.build index
>> 170a4981a..24bce2b39 100644
>> --- a/config/arm/meson.build
>> +++ b/config/arm/meson.build
>> @@ -7,25 +7,6 @@ march_opt = '-march=@0@'.format(machine)
>>
>> arm_force_native_march = false
>>
>> -machine_args_generic = [
>> -	['default', ['-march=armv8-a+crc+crypto']],
>> -	['native', ['-march=native']],
>> -	['0xd03', ['-mcpu=cortex-a53']],
>> -	['0xd04', ['-mcpu=cortex-a35']],
>> -	['0xd05', ['-mcpu=cortex-a55']],
>> -	['0xd07', ['-mcpu=cortex-a57']],
>> -	['0xd08', ['-mcpu=cortex-a72']],
>> -	['0xd09', ['-mcpu=cortex-a73']],
>> -	['0xd0a', ['-mcpu=cortex-a75']],
>> -	['0xd0b', ['-mcpu=cortex-a76']],
>> -]
>> -machine_args_cavium = [
>> -	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
>> -	['native', ['-march=native']],
>> -	['0xa1', ['-mcpu=thunderxt88']],
>> -	['0xa2', ['-mcpu=thunderxt81']],
>> -	['0xa3', ['-mcpu=thunderxt83']]]
>> -
>> flags_common_default = [
>> 	# Accelarate rte_memcpy. Be sure to run unit test
>(memcpy_perf_autotest)
>> 	# to determine the best threshold in code. Refer to notes in source
>> file @@ -52,12 +33,10 @@ flags_generic = [
>> 	['RTE_USE_C11_MEM_MODEL', true],
>> 	['RTE_CACHE_LINE_SIZE', 128]]
>> flags_cavium = [
>> -	['RTE_MACHINE', '"thunderx"'],
>> 	['RTE_CACHE_LINE_SIZE', 128],
>> 	['RTE_MAX_NUMA_NODES', 2],
>> 	['RTE_MAX_LCORE', 96],
>> -	['RTE_MAX_VFIO_GROUPS', 128],
>> -	['RTE_USE_C11_MEM_MODEL', false]]
>> +	['RTE_MAX_VFIO_GROUPS', 128]]
>> flags_dpaa = [
>> 	['RTE_MACHINE', '"dpaa"'],
>> 	['RTE_USE_C11_MEM_MODEL', true],
>> @@ -71,6 +50,27 @@ flags_dpaa2 = [
>> 	['RTE_MAX_NUMA_NODES', 1],
>> 	['RTE_MAX_LCORE', 16],
>> 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
>> +flags_default_extra = []
>> +flags_thunderx_extra = [
>> +	['RTE_MACHINE', '"thunderx"'],
>> +	['RTE_USE_C11_MEM_MODEL', false]]
>> +
>> +machine_args_generic = [
>> +	['default', ['-march=armv8-a+crc+crypto']],
>> +	['native', ['-march=native']],
>> +	['0xd03', ['-mcpu=cortex-a53']],
>> +	['0xd04', ['-mcpu=cortex-a35']],
>> +	['0xd07', ['-mcpu=cortex-a57']],
>> +	['0xd08', ['-mcpu=cortex-a72']],
>> +	['0xd09', ['-mcpu=cortex-a73']],
>> +	['0xd0a', ['-mcpu=cortex-a75']]]
>> +
>> +machine_args_cavium = [
>> +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
>> +	['native', ['-march=native']],
>> +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
>> +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
>> +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
>>
>> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page
>> G7-5321) impl_generic = ['Generic armv8', flags_generic,
>> machine_args_generic] @@ -157,8 +157,16 @@ else
>> 	endif
>> 	foreach marg: machine[2]
>> 		if marg[0] == impl_pn
>> -			foreach f: marg[1]
>> -				machine_args += f
>> +			foreach flag: marg[1]
>> +				if cc.has_argument(flag)
>> +					machine_args += flag
>> +				endif
>> +			endforeach
>> +			# Apply any extra machine specific flags.
>> +			foreach flag: marg.get(2, flags_default_extra)
>> +				if flag.length() > 0
>> +					dpdk_conf.set(flag[0], flag[1])
>> +				endif
>
>Let me continue the discussion from v7 here.
>Seems I wan't clear enough.
>
>Let me take an example. If the host is thunderx2 (0xaf) and compiler is older
>than v7, flags_thunderx2_extra isn't set. This means, for example,
>RTE_CACHE_LINE_SIZE will still be 128. Is that what you want?
>RTE_CACHE_LINE_SIZE has nothing to do with compiler support and you might
>want to set it regardless of gcc version. You could skip setting -mcpu with setting
>the extra flags.
>

Thanks for the detailed explanation.
I think since we have the check to skip mcpu flag when cc doesn't support it (cc.has_argument(flag))
It will be safe to remove 
`
        # Primary part number based mcpu flags are supported
        # for gcc versions > 7
        if cc.version().version_compare(
                        '<7.0') or cmd_output.length() == 0
                if not meson.is_cross_build() and arm_force_native_march == true
                        impl_pn = 'native'
                else
                        impl_pn = 'default'
                endif
        endif
`

The command output check can also be removed as it is handled when calling the command script itself.

Thoughts?

PS. I think the safest way to set CACHELINE_SIZE is to read the cache type register[1] but sadly only few latest kernels 
have the support through sysfs (/sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size) 

>Thoughts?
>
>Thanks,
>Yongseok
>
>
>

Regards,
Pavan.

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Pavan Nikhilesh Bhagavatula]

Hi Yongseok,

>-----Original Message-----
>From: Yongseok Koh <yskoh@mellanox.com>
>Sent: Wednesday, April 10, 2019 11:08 PM
>To: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>
>Cc: Thomas Monjalon <thomas@monjalon.net>; dev <dev@dpdk.org>; Jerin
>Jacob Kollanukkaran <jerinj@marvell.com>; jerinjacobk@gmail.com
>Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support
>machine specific flags
>
>External Email
>
>----------------------------------------------------------------------
>
>> On Apr 10, 2019, at 9:13 AM, jerinjacobk@gmail.com wrote:
>>
>> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
>>
>> Currently, RTE_* flags are set based on the implementer ID but there
>> might be some micro arch specific differences from the same vendor eg.
>> CACHE_LINESIZE. Add support to set micro arch specific flags.
>>
>> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
>> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
>> ---
>> config/arm/meson.build | 56 ++++++++++++++++++++++++------------------
>> 1 file changed, 32 insertions(+), 24 deletions(-)
>>
>> diff --git a/config/arm/meson.build b/config/arm/meson.build index
>> 170a4981a..24bce2b39 100644
>> --- a/config/arm/meson.build
>> +++ b/config/arm/meson.build
>> @@ -7,25 +7,6 @@ march_opt = '-march=@0@'.format(machine)
>>
>> arm_force_native_march = false
>>
>> -machine_args_generic = [
>> -	['default', ['-march=armv8-a+crc+crypto']],
>> -	['native', ['-march=native']],
>> -	['0xd03', ['-mcpu=cortex-a53']],
>> -	['0xd04', ['-mcpu=cortex-a35']],
>> -	['0xd05', ['-mcpu=cortex-a55']],
>> -	['0xd07', ['-mcpu=cortex-a57']],
>> -	['0xd08', ['-mcpu=cortex-a72']],
>> -	['0xd09', ['-mcpu=cortex-a73']],
>> -	['0xd0a', ['-mcpu=cortex-a75']],
>> -	['0xd0b', ['-mcpu=cortex-a76']],
>> -]
>> -machine_args_cavium = [
>> -	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
>> -	['native', ['-march=native']],
>> -	['0xa1', ['-mcpu=thunderxt88']],
>> -	['0xa2', ['-mcpu=thunderxt81']],
>> -	['0xa3', ['-mcpu=thunderxt83']]]
>> -
>> flags_common_default = [
>> 	# Accelarate rte_memcpy. Be sure to run unit test
>(memcpy_perf_autotest)
>> 	# to determine the best threshold in code. Refer to notes in source
>> file @@ -52,12 +33,10 @@ flags_generic = [
>> 	['RTE_USE_C11_MEM_MODEL', true],
>> 	['RTE_CACHE_LINE_SIZE', 128]]
>> flags_cavium = [
>> -	['RTE_MACHINE', '"thunderx"'],
>> 	['RTE_CACHE_LINE_SIZE', 128],
>> 	['RTE_MAX_NUMA_NODES', 2],
>> 	['RTE_MAX_LCORE', 96],
>> -	['RTE_MAX_VFIO_GROUPS', 128],
>> -	['RTE_USE_C11_MEM_MODEL', false]]
>> +	['RTE_MAX_VFIO_GROUPS', 128]]
>> flags_dpaa = [
>> 	['RTE_MACHINE', '"dpaa"'],
>> 	['RTE_USE_C11_MEM_MODEL', true],
>> @@ -71,6 +50,27 @@ flags_dpaa2 = [
>> 	['RTE_MAX_NUMA_NODES', 1],
>> 	['RTE_MAX_LCORE', 16],
>> 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
>> +flags_default_extra = []
>> +flags_thunderx_extra = [
>> +	['RTE_MACHINE', '"thunderx"'],
>> +	['RTE_USE_C11_MEM_MODEL', false]]
>> +
>> +machine_args_generic = [
>> +	['default', ['-march=armv8-a+crc+crypto']],
>> +	['native', ['-march=native']],
>> +	['0xd03', ['-mcpu=cortex-a53']],
>> +	['0xd04', ['-mcpu=cortex-a35']],
>> +	['0xd07', ['-mcpu=cortex-a57']],
>> +	['0xd08', ['-mcpu=cortex-a72']],
>> +	['0xd09', ['-mcpu=cortex-a73']],
>> +	['0xd0a', ['-mcpu=cortex-a75']]]
>> +
>> +machine_args_cavium = [
>> +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
>> +	['native', ['-march=native']],
>> +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
>> +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
>> +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
>>
>> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page
>> G7-5321) impl_generic = ['Generic armv8', flags_generic,
>> machine_args_generic] @@ -157,8 +157,16 @@ else
>> 	endif
>> 	foreach marg: machine[2]
>> 		if marg[0] == impl_pn
>> -			foreach f: marg[1]
>> -				machine_args += f
>> +			foreach flag: marg[1]
>> +				if cc.has_argument(flag)
>> +					machine_args += flag
>> +				endif
>> +			endforeach
>> +			# Apply any extra machine specific flags.
>> +			foreach flag: marg.get(2, flags_default_extra)
>> +				if flag.length() > 0
>> +					dpdk_conf.set(flag[0], flag[1])
>> +				endif
>
>Let me continue the discussion from v7 here.
>Seems I wan't clear enough.
>
>Let me take an example. If the host is thunderx2 (0xaf) and compiler is older
>than v7, flags_thunderx2_extra isn't set. This means, for example,
>RTE_CACHE_LINE_SIZE will still be 128. Is that what you want?
>RTE_CACHE_LINE_SIZE has nothing to do with compiler support and you might
>want to set it regardless of gcc version. You could skip setting -mcpu with setting
>the extra flags.
>

Thanks for the detailed explanation.
I think since we have the check to skip mcpu flag when cc doesn't support it (cc.has_argument(flag))
It will be safe to remove 
`
        # Primary part number based mcpu flags are supported
        # for gcc versions > 7
        if cc.version().version_compare(
                        '<7.0') or cmd_output.length() == 0
                if not meson.is_cross_build() and arm_force_native_march == true
                        impl_pn = 'native'
                else
                        impl_pn = 'default'
                endif
        endif
`

The command output check can also be removed as it is handled when calling the command script itself.

Thoughts?

PS. I think the safest way to set CACHELINE_SIZE is to read the cache type register[1] but sadly only few latest kernels 
have the support through sysfs (/sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size) 

>Thoughts?
>
>Thanks,
>Yongseok
>
>
>

Regards,
Pavan.

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Yongseok Koh]

> On Apr 10, 2019, at 11:07 PM, Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com> wrote:
> 
> Hi Yongseok,
> 
>> -----Original Message-----
>> From: Yongseok Koh <yskoh@mellanox.com>
>> Sent: Wednesday, April 10, 2019 11:08 PM
>> To: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>
>> Cc: Thomas Monjalon <thomas@monjalon.net>; dev <dev@dpdk.org>; Jerin
>> Jacob Kollanukkaran <jerinj@marvell.com>; jerinjacobk@gmail.com
>> Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support
>> machine specific flags
>> 
>> External Email
>> 
>> ----------------------------------------------------------------------
>> 
>>> On Apr 10, 2019, at 9:13 AM, jerinjacobk@gmail.com wrote:
>>> 
>>> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
>>> 
>>> Currently, RTE_* flags are set based on the implementer ID but there
>>> might be some micro arch specific differences from the same vendor eg.
>>> CACHE_LINESIZE. Add support to set micro arch specific flags.
>>> 
>>> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
>>> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
>>> ---
>>> config/arm/meson.build | 56 ++++++++++++++++++++++++------------------
>>> 1 file changed, 32 insertions(+), 24 deletions(-)
>>> 
>>> diff --git a/config/arm/meson.build b/config/arm/meson.build index
>>> 170a4981a..24bce2b39 100644
>>> --- a/config/arm/meson.build
>>> +++ b/config/arm/meson.build
>>> @@ -7,25 +7,6 @@ march_opt = '-march=@0@'.format(machine)
>>> 
>>> arm_force_native_march = false
>>> 
>>> -machine_args_generic = [
>>> -	['default', ['-march=armv8-a+crc+crypto']],
>>> -	['native', ['-march=native']],
>>> -	['0xd03', ['-mcpu=cortex-a53']],
>>> -	['0xd04', ['-mcpu=cortex-a35']],
>>> -	['0xd05', ['-mcpu=cortex-a55']],
>>> -	['0xd07', ['-mcpu=cortex-a57']],
>>> -	['0xd08', ['-mcpu=cortex-a72']],
>>> -	['0xd09', ['-mcpu=cortex-a73']],
>>> -	['0xd0a', ['-mcpu=cortex-a75']],
>>> -	['0xd0b', ['-mcpu=cortex-a76']],
>>> -]
>>> -machine_args_cavium = [
>>> -	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
>>> -	['native', ['-march=native']],
>>> -	['0xa1', ['-mcpu=thunderxt88']],
>>> -	['0xa2', ['-mcpu=thunderxt81']],
>>> -	['0xa3', ['-mcpu=thunderxt83']]]
>>> -
>>> flags_common_default = [
>>> 	# Accelarate rte_memcpy. Be sure to run unit test
>> (memcpy_perf_autotest)
>>> 	# to determine the best threshold in code. Refer to notes in source
>>> file @@ -52,12 +33,10 @@ flags_generic = [
>>> 	['RTE_USE_C11_MEM_MODEL', true],
>>> 	['RTE_CACHE_LINE_SIZE', 128]]
>>> flags_cavium = [
>>> -	['RTE_MACHINE', '"thunderx"'],
>>> 	['RTE_CACHE_LINE_SIZE', 128],
>>> 	['RTE_MAX_NUMA_NODES', 2],
>>> 	['RTE_MAX_LCORE', 96],
>>> -	['RTE_MAX_VFIO_GROUPS', 128],
>>> -	['RTE_USE_C11_MEM_MODEL', false]]
>>> +	['RTE_MAX_VFIO_GROUPS', 128]]
>>> flags_dpaa = [
>>> 	['RTE_MACHINE', '"dpaa"'],
>>> 	['RTE_USE_C11_MEM_MODEL', true],
>>> @@ -71,6 +50,27 @@ flags_dpaa2 = [
>>> 	['RTE_MAX_NUMA_NODES', 1],
>>> 	['RTE_MAX_LCORE', 16],
>>> 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
>>> +flags_default_extra = []
>>> +flags_thunderx_extra = [
>>> +	['RTE_MACHINE', '"thunderx"'],
>>> +	['RTE_USE_C11_MEM_MODEL', false]]
>>> +
>>> +machine_args_generic = [
>>> +	['default', ['-march=armv8-a+crc+crypto']],
>>> +	['native', ['-march=native']],
>>> +	['0xd03', ['-mcpu=cortex-a53']],
>>> +	['0xd04', ['-mcpu=cortex-a35']],
>>> +	['0xd07', ['-mcpu=cortex-a57']],
>>> +	['0xd08', ['-mcpu=cortex-a72']],
>>> +	['0xd09', ['-mcpu=cortex-a73']],
>>> +	['0xd0a', ['-mcpu=cortex-a75']]]
>>> +
>>> +machine_args_cavium = [
>>> +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
>>> +	['native', ['-march=native']],
>>> +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
>>> +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
>>> +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
>>> 
>>> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page
>>> G7-5321) impl_generic = ['Generic armv8', flags_generic,
>>> machine_args_generic] @@ -157,8 +157,16 @@ else
>>> 	endif
>>> 	foreach marg: machine[2]
>>> 		if marg[0] == impl_pn
>>> -			foreach f: marg[1]
>>> -				machine_args += f
>>> +			foreach flag: marg[1]
>>> +				if cc.has_argument(flag)
>>> +					machine_args += flag
>>> +				endif
>>> +			endforeach
>>> +			# Apply any extra machine specific flags.
>>> +			foreach flag: marg.get(2, flags_default_extra)
>>> +				if flag.length() > 0
>>> +					dpdk_conf.set(flag[0], flag[1])
>>> +				endif
>> 
>> Let me continue the discussion from v7 here.
>> Seems I wan't clear enough.
>> 
>> Let me take an example. If the host is thunderx2 (0xaf) and compiler is older
>> than v7, flags_thunderx2_extra isn't set. This means, for example,
>> RTE_CACHE_LINE_SIZE will still be 128. Is that what you want?
>> RTE_CACHE_LINE_SIZE has nothing to do with compiler support and you might
>> want to set it regardless of gcc version. You could skip setting -mcpu with setting
>> the extra flags.
>> 
> 
> Thanks for the detailed explanation.
> I think since we have the check to skip mcpu flag when cc doesn't support it (cc.has_argument(flag))
> It will be safe to remove 
> `
>        # Primary part number based mcpu flags are supported
>        # for gcc versions > 7
>        if cc.version().version_compare(
>                        '<7.0') or cmd_output.length() == 0
>                if not meson.is_cross_build() and arm_force_native_march == true
>                        impl_pn = 'native'
>                else
>                        impl_pn = 'default'
>                endif
>        endif
> `

+1

> 
> The command output check can also be removed as it is handled when calling the command script itself.

+1

> 
> Thoughts?
> 
> PS. I think the safest way to set CACHELINE_SIZE is to read the cache type register[1] but sadly only few latest kernels 
> have the support through sysfs (/sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size) 

+1

In summary, +3. LoL

I'll also submit a patch to change the default cacheline size of cortex-a72 with the new flags_*_extra[]


thanks,
Yongseok

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Yongseok Koh]

> On Apr 10, 2019, at 11:07 PM, Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com> wrote:
> 
> Hi Yongseok,
> 
>> -----Original Message-----
>> From: Yongseok Koh <yskoh@mellanox.com>
>> Sent: Wednesday, April 10, 2019 11:08 PM
>> To: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>
>> Cc: Thomas Monjalon <thomas@monjalon.net>; dev <dev@dpdk.org>; Jerin
>> Jacob Kollanukkaran <jerinj@marvell.com>; jerinjacobk@gmail.com
>> Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support
>> machine specific flags
>> 
>> External Email
>> 
>> ----------------------------------------------------------------------
>> 
>>> On Apr 10, 2019, at 9:13 AM, jerinjacobk@gmail.com wrote:
>>> 
>>> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
>>> 
>>> Currently, RTE_* flags are set based on the implementer ID but there
>>> might be some micro arch specific differences from the same vendor eg.
>>> CACHE_LINESIZE. Add support to set micro arch specific flags.
>>> 
>>> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
>>> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
>>> ---
>>> config/arm/meson.build | 56 ++++++++++++++++++++++++------------------
>>> 1 file changed, 32 insertions(+), 24 deletions(-)
>>> 
>>> diff --git a/config/arm/meson.build b/config/arm/meson.build index
>>> 170a4981a..24bce2b39 100644
>>> --- a/config/arm/meson.build
>>> +++ b/config/arm/meson.build
>>> @@ -7,25 +7,6 @@ march_opt = '-march=@0@'.format(machine)
>>> 
>>> arm_force_native_march = false
>>> 
>>> -machine_args_generic = [
>>> -	['default', ['-march=armv8-a+crc+crypto']],
>>> -	['native', ['-march=native']],
>>> -	['0xd03', ['-mcpu=cortex-a53']],
>>> -	['0xd04', ['-mcpu=cortex-a35']],
>>> -	['0xd05', ['-mcpu=cortex-a55']],
>>> -	['0xd07', ['-mcpu=cortex-a57']],
>>> -	['0xd08', ['-mcpu=cortex-a72']],
>>> -	['0xd09', ['-mcpu=cortex-a73']],
>>> -	['0xd0a', ['-mcpu=cortex-a75']],
>>> -	['0xd0b', ['-mcpu=cortex-a76']],
>>> -]
>>> -machine_args_cavium = [
>>> -	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
>>> -	['native', ['-march=native']],
>>> -	['0xa1', ['-mcpu=thunderxt88']],
>>> -	['0xa2', ['-mcpu=thunderxt81']],
>>> -	['0xa3', ['-mcpu=thunderxt83']]]
>>> -
>>> flags_common_default = [
>>> 	# Accelarate rte_memcpy. Be sure to run unit test
>> (memcpy_perf_autotest)
>>> 	# to determine the best threshold in code. Refer to notes in source
>>> file @@ -52,12 +33,10 @@ flags_generic = [
>>> 	['RTE_USE_C11_MEM_MODEL', true],
>>> 	['RTE_CACHE_LINE_SIZE', 128]]
>>> flags_cavium = [
>>> -	['RTE_MACHINE', '"thunderx"'],
>>> 	['RTE_CACHE_LINE_SIZE', 128],
>>> 	['RTE_MAX_NUMA_NODES', 2],
>>> 	['RTE_MAX_LCORE', 96],
>>> -	['RTE_MAX_VFIO_GROUPS', 128],
>>> -	['RTE_USE_C11_MEM_MODEL', false]]
>>> +	['RTE_MAX_VFIO_GROUPS', 128]]
>>> flags_dpaa = [
>>> 	['RTE_MACHINE', '"dpaa"'],
>>> 	['RTE_USE_C11_MEM_MODEL', true],
>>> @@ -71,6 +50,27 @@ flags_dpaa2 = [
>>> 	['RTE_MAX_NUMA_NODES', 1],
>>> 	['RTE_MAX_LCORE', 16],
>>> 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
>>> +flags_default_extra = []
>>> +flags_thunderx_extra = [
>>> +	['RTE_MACHINE', '"thunderx"'],
>>> +	['RTE_USE_C11_MEM_MODEL', false]]
>>> +
>>> +machine_args_generic = [
>>> +	['default', ['-march=armv8-a+crc+crypto']],
>>> +	['native', ['-march=native']],
>>> +	['0xd03', ['-mcpu=cortex-a53']],
>>> +	['0xd04', ['-mcpu=cortex-a35']],
>>> +	['0xd07', ['-mcpu=cortex-a57']],
>>> +	['0xd08', ['-mcpu=cortex-a72']],
>>> +	['0xd09', ['-mcpu=cortex-a73']],
>>> +	['0xd0a', ['-mcpu=cortex-a75']]]
>>> +
>>> +machine_args_cavium = [
>>> +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
>>> +	['native', ['-march=native']],
>>> +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
>>> +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
>>> +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
>>> 
>>> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page
>>> G7-5321) impl_generic = ['Generic armv8', flags_generic,
>>> machine_args_generic] @@ -157,8 +157,16 @@ else
>>> 	endif
>>> 	foreach marg: machine[2]
>>> 		if marg[0] == impl_pn
>>> -			foreach f: marg[1]
>>> -				machine_args += f
>>> +			foreach flag: marg[1]
>>> +				if cc.has_argument(flag)
>>> +					machine_args += flag
>>> +				endif
>>> +			endforeach
>>> +			# Apply any extra machine specific flags.
>>> +			foreach flag: marg.get(2, flags_default_extra)
>>> +				if flag.length() > 0
>>> +					dpdk_conf.set(flag[0], flag[1])
>>> +				endif
>> 
>> Let me continue the discussion from v7 here.
>> Seems I wan't clear enough.
>> 
>> Let me take an example. If the host is thunderx2 (0xaf) and compiler is older
>> than v7, flags_thunderx2_extra isn't set. This means, for example,
>> RTE_CACHE_LINE_SIZE will still be 128. Is that what you want?
>> RTE_CACHE_LINE_SIZE has nothing to do with compiler support and you might
>> want to set it regardless of gcc version. You could skip setting -mcpu with setting
>> the extra flags.
>> 
> 
> Thanks for the detailed explanation.
> I think since we have the check to skip mcpu flag when cc doesn't support it (cc.has_argument(flag))
> It will be safe to remove 
> `
>        # Primary part number based mcpu flags are supported
>        # for gcc versions > 7
>        if cc.version().version_compare(
>                        '<7.0') or cmd_output.length() == 0
>                if not meson.is_cross_build() and arm_force_native_march == true
>                        impl_pn = 'native'
>                else
>                        impl_pn = 'default'
>                endif
>        endif
> `

+1

> 
> The command output check can also be removed as it is handled when calling the command script itself.

+1

> 
> Thoughts?
> 
> PS. I think the safest way to set CACHELINE_SIZE is to read the cache type register[1] but sadly only few latest kernels 
> have the support through sysfs (/sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size) 

+1

In summary, +3. LoL

I'll also submit a patch to change the default cacheline size of cortex-a72 with the new flags_*_extra[]


thanks,
Yongseok

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Thomas Monjalon]

10/04/2019 18:13, jerinjacobk@gmail.com:
> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> 
> Currently, RTE_* flags are set based on the implementer ID but there might
> be some micro arch specific differences from the same vendor
> eg. CACHE_LINESIZE. Add support to set micro arch specific flags.

I don't like how flags are set in config/arm/meson.build.
It is a real mess to find which flag applies to which machine.
Adding the flags_*_extra in the machine_args_* is adding more mess.

[...]
>  flags_common_default = [
>  	# Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
>  	# to determine the best threshold in code. Refer to notes in source file
> @@ -52,12 +33,10 @@ flags_generic = [
>  	['RTE_USE_C11_MEM_MODEL', true],
>  	['RTE_CACHE_LINE_SIZE', 128]]
>  flags_cavium = [
> -	['RTE_MACHINE', '"thunderx"'],
>  	['RTE_CACHE_LINE_SIZE', 128],
>  	['RTE_MAX_NUMA_NODES', 2],
>  	['RTE_MAX_LCORE', 96],
> -	['RTE_MAX_VFIO_GROUPS', 128],
> -	['RTE_USE_C11_MEM_MODEL', false]]
> +	['RTE_MAX_VFIO_GROUPS', 128]]
>  flags_dpaa = [
>  	['RTE_MACHINE', '"dpaa"'],
>  	['RTE_USE_C11_MEM_MODEL', true],
> @@ -71,6 +50,27 @@ flags_dpaa2 = [
>  	['RTE_MAX_NUMA_NODES', 1],
>  	['RTE_MAX_LCORE', 16],
>  	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
> +flags_default_extra = []
> +flags_thunderx_extra = [
> +	['RTE_MACHINE', '"thunderx"'],
> +	['RTE_USE_C11_MEM_MODEL', false]]
> +
> +machine_args_generic = [
> +	['default', ['-march=armv8-a+crc+crypto']],
> +	['native', ['-march=native']],
> +	['0xd03', ['-mcpu=cortex-a53']],
> +	['0xd04', ['-mcpu=cortex-a35']],
> +	['0xd07', ['-mcpu=cortex-a57']],
> +	['0xd08', ['-mcpu=cortex-a72']],
> +	['0xd09', ['-mcpu=cortex-a73']],
> +	['0xd0a', ['-mcpu=cortex-a75']]]
> +
> +machine_args_cavium = [
> +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> +	['native', ['-march=native']],
> +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
> +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
> +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]

I think we should have a simpler model.
We need only to know the machine name and get all the related machine config.
In native compilation, machine name is guessed from implementor id and pn
(from config/arm/armv8_machine.py). We can directly output the machine name
from this script and leave the naming logic in this script.
In the cross-compilation config files (config/arm/*),
we can just specify the machine name.
Then every machine config (machine_args and dpdk_conf) would be specified
in some arrays based on the machine name.
Of course, we can keep some common default values.

Thoughts?

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Thomas Monjalon]

10/04/2019 18:13, jerinjacobk@gmail.com:
> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> 
> Currently, RTE_* flags are set based on the implementer ID but there might
> be some micro arch specific differences from the same vendor
> eg. CACHE_LINESIZE. Add support to set micro arch specific flags.

I don't like how flags are set in config/arm/meson.build.
It is a real mess to find which flag applies to which machine.
Adding the flags_*_extra in the machine_args_* is adding more mess.

[...]
>  flags_common_default = [
>  	# Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
>  	# to determine the best threshold in code. Refer to notes in source file
> @@ -52,12 +33,10 @@ flags_generic = [
>  	['RTE_USE_C11_MEM_MODEL', true],
>  	['RTE_CACHE_LINE_SIZE', 128]]
>  flags_cavium = [
> -	['RTE_MACHINE', '"thunderx"'],
>  	['RTE_CACHE_LINE_SIZE', 128],
>  	['RTE_MAX_NUMA_NODES', 2],
>  	['RTE_MAX_LCORE', 96],
> -	['RTE_MAX_VFIO_GROUPS', 128],
> -	['RTE_USE_C11_MEM_MODEL', false]]
> +	['RTE_MAX_VFIO_GROUPS', 128]]
>  flags_dpaa = [
>  	['RTE_MACHINE', '"dpaa"'],
>  	['RTE_USE_C11_MEM_MODEL', true],
> @@ -71,6 +50,27 @@ flags_dpaa2 = [
>  	['RTE_MAX_NUMA_NODES', 1],
>  	['RTE_MAX_LCORE', 16],
>  	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
> +flags_default_extra = []
> +flags_thunderx_extra = [
> +	['RTE_MACHINE', '"thunderx"'],
> +	['RTE_USE_C11_MEM_MODEL', false]]
> +
> +machine_args_generic = [
> +	['default', ['-march=armv8-a+crc+crypto']],
> +	['native', ['-march=native']],
> +	['0xd03', ['-mcpu=cortex-a53']],
> +	['0xd04', ['-mcpu=cortex-a35']],
> +	['0xd07', ['-mcpu=cortex-a57']],
> +	['0xd08', ['-mcpu=cortex-a72']],
> +	['0xd09', ['-mcpu=cortex-a73']],
> +	['0xd0a', ['-mcpu=cortex-a75']]]
> +
> +machine_args_cavium = [
> +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> +	['native', ['-march=native']],
> +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
> +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
> +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]

I think we should have a simpler model.
We need only to know the machine name and get all the related machine config.
In native compilation, machine name is guessed from implementor id and pn
(from config/arm/armv8_machine.py). We can directly output the machine name
from this script and leave the naming logic in this script.
In the cross-compilation config files (config/arm/*),
we can just specify the machine name.
Then every machine config (machine_args and dpdk_conf) would be specified
in some arrays based on the machine name.
Of course, we can keep some common default values.

Thoughts?

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Yongseok Koh]

> On Apr 11, 2019, at 4:37 PM, Thomas Monjalon <thomas@monjalon.net> wrote:
> 
> 10/04/2019 18:13, jerinjacobk@gmail.com:
>> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
>> 
>> Currently, RTE_* flags are set based on the implementer ID but there might
>> be some micro arch specific differences from the same vendor
>> eg. CACHE_LINESIZE. Add support to set micro arch specific flags.
> 
> I don't like how flags are set in config/arm/meson.build.
> It is a real mess to find which flag applies to which machine.
> Adding the flags_*_extra in the machine_args_* is adding more mess.
> 
> [...]
>> flags_common_default = [
>> 	# Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
>> 	# to determine the best threshold in code. Refer to notes in source file
>> @@ -52,12 +33,10 @@ flags_generic = [
>> 	['RTE_USE_C11_MEM_MODEL', true],
>> 	['RTE_CACHE_LINE_SIZE', 128]]
>> flags_cavium = [
>> -	['RTE_MACHINE', '"thunderx"'],
>> 	['RTE_CACHE_LINE_SIZE', 128],
>> 	['RTE_MAX_NUMA_NODES', 2],
>> 	['RTE_MAX_LCORE', 96],
>> -	['RTE_MAX_VFIO_GROUPS', 128],
>> -	['RTE_USE_C11_MEM_MODEL', false]]
>> +	['RTE_MAX_VFIO_GROUPS', 128]]
>> flags_dpaa = [
>> 	['RTE_MACHINE', '"dpaa"'],
>> 	['RTE_USE_C11_MEM_MODEL', true],
>> @@ -71,6 +50,27 @@ flags_dpaa2 = [
>> 	['RTE_MAX_NUMA_NODES', 1],
>> 	['RTE_MAX_LCORE', 16],
>> 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
>> +flags_default_extra = []
>> +flags_thunderx_extra = [
>> +	['RTE_MACHINE', '"thunderx"'],
>> +	['RTE_USE_C11_MEM_MODEL', false]]
>> +
>> +machine_args_generic = [
>> +	['default', ['-march=armv8-a+crc+crypto']],
>> +	['native', ['-march=native']],
>> +	['0xd03', ['-mcpu=cortex-a53']],
>> +	['0xd04', ['-mcpu=cortex-a35']],
>> +	['0xd07', ['-mcpu=cortex-a57']],
>> +	['0xd08', ['-mcpu=cortex-a72']],
>> +	['0xd09', ['-mcpu=cortex-a73']],
>> +	['0xd0a', ['-mcpu=cortex-a75']]]
>> +
>> +machine_args_cavium = [
>> +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
>> +	['native', ['-march=native']],
>> +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
>> +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
>> +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
> 
> I think we should have a simpler model.
> We need only to know the machine name and get all the related machine config.
> In native compilation, machine name is guessed from implementor id and pn

It can be guessed unless machine name is specified as an option.
We can add machine_name option?
One observation. We do have machine option but it isn't used much for arm.
And in config/arm/meson.build, march_opt isn't used either.

> (from config/arm/armv8_machine.py). We can directly output the machine name
> from this script and leave the naming logic in this script.
> In the cross-compilation config files (config/arm/*),
> we can just specify the machine name.
> Then every machine config (machine_args and dpdk_conf) would be specified
> in some arrays based on the machine name.
> Of course, we can keep some common default values.
> 
> Thoughts?

Sounds like we can cleanly reorganize it with the suggestion.

Thanks,
Yongseok

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Yongseok Koh]

> On Apr 11, 2019, at 4:37 PM, Thomas Monjalon <thomas@monjalon.net> wrote:
> 
> 10/04/2019 18:13, jerinjacobk@gmail.com:
>> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
>> 
>> Currently, RTE_* flags are set based on the implementer ID but there might
>> be some micro arch specific differences from the same vendor
>> eg. CACHE_LINESIZE. Add support to set micro arch specific flags.
> 
> I don't like how flags are set in config/arm/meson.build.
> It is a real mess to find which flag applies to which machine.
> Adding the flags_*_extra in the machine_args_* is adding more mess.
> 
> [...]
>> flags_common_default = [
>> 	# Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
>> 	# to determine the best threshold in code. Refer to notes in source file
>> @@ -52,12 +33,10 @@ flags_generic = [
>> 	['RTE_USE_C11_MEM_MODEL', true],
>> 	['RTE_CACHE_LINE_SIZE', 128]]
>> flags_cavium = [
>> -	['RTE_MACHINE', '"thunderx"'],
>> 	['RTE_CACHE_LINE_SIZE', 128],
>> 	['RTE_MAX_NUMA_NODES', 2],
>> 	['RTE_MAX_LCORE', 96],
>> -	['RTE_MAX_VFIO_GROUPS', 128],
>> -	['RTE_USE_C11_MEM_MODEL', false]]
>> +	['RTE_MAX_VFIO_GROUPS', 128]]
>> flags_dpaa = [
>> 	['RTE_MACHINE', '"dpaa"'],
>> 	['RTE_USE_C11_MEM_MODEL', true],
>> @@ -71,6 +50,27 @@ flags_dpaa2 = [
>> 	['RTE_MAX_NUMA_NODES', 1],
>> 	['RTE_MAX_LCORE', 16],
>> 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
>> +flags_default_extra = []
>> +flags_thunderx_extra = [
>> +	['RTE_MACHINE', '"thunderx"'],
>> +	['RTE_USE_C11_MEM_MODEL', false]]
>> +
>> +machine_args_generic = [
>> +	['default', ['-march=armv8-a+crc+crypto']],
>> +	['native', ['-march=native']],
>> +	['0xd03', ['-mcpu=cortex-a53']],
>> +	['0xd04', ['-mcpu=cortex-a35']],
>> +	['0xd07', ['-mcpu=cortex-a57']],
>> +	['0xd08', ['-mcpu=cortex-a72']],
>> +	['0xd09', ['-mcpu=cortex-a73']],
>> +	['0xd0a', ['-mcpu=cortex-a75']]]
>> +
>> +machine_args_cavium = [
>> +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
>> +	['native', ['-march=native']],
>> +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
>> +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
>> +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
> 
> I think we should have a simpler model.
> We need only to know the machine name and get all the related machine config.
> In native compilation, machine name is guessed from implementor id and pn

It can be guessed unless machine name is specified as an option.
We can add machine_name option?
One observation. We do have machine option but it isn't used much for arm.
And in config/arm/meson.build, march_opt isn't used either.

> (from config/arm/armv8_machine.py). We can directly output the machine name
> from this script and leave the naming logic in this script.
> In the cross-compilation config files (config/arm/*),
> we can just specify the machine name.
> Then every machine config (machine_args and dpdk_conf) would be specified
> in some arrays based on the machine name.
> Of course, we can keep some common default values.
> 
> Thoughts?

Sounds like we can cleanly reorganize it with the suggestion.

Thanks,
Yongseok

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Yongseok Koh]

> On Apr 11, 2019, at 1:12 PM, Yongseok Koh <yskoh@mellanox.com> wrote:
> 
>> 
>> On Apr 10, 2019, at 11:07 PM, Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com> wrote:
>> 
>> Hi Yongseok,
>> 
>>> -----Original Message-----
>>> From: Yongseok Koh <yskoh@mellanox.com>
>>> Sent: Wednesday, April 10, 2019 11:08 PM
>>> To: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>
>>> Cc: Thomas Monjalon <thomas@monjalon.net>; dev <dev@dpdk.org>; Jerin
>>> Jacob Kollanukkaran <jerinj@marvell.com>; jerinjacobk@gmail.com
>>> Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support
>>> machine specific flags
>>> 
>>> External Email
>>> 
>>> ----------------------------------------------------------------------
>>> 
>>>> On Apr 10, 2019, at 9:13 AM, jerinjacobk@gmail.com wrote:
>>>> 
>>>> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
>>>> 
>>>> Currently, RTE_* flags are set based on the implementer ID but there
>>>> might be some micro arch specific differences from the same vendor eg.
>>>> CACHE_LINESIZE. Add support to set micro arch specific flags.
>>>> 
>>>> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
>>>> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
>>>> ---
>>>> config/arm/meson.build | 56 ++++++++++++++++++++++++------------------
>>>> 1 file changed, 32 insertions(+), 24 deletions(-)
>>>> 
>>>> diff --git a/config/arm/meson.build b/config/arm/meson.build index
>>>> 170a4981a..24bce2b39 100644
>>>> --- a/config/arm/meson.build
>>>> +++ b/config/arm/meson.build
>>>> @@ -7,25 +7,6 @@ march_opt = '-march=@0@'.format(machine)
>>>> 
>>>> arm_force_native_march = false
>>>> 
>>>> -machine_args_generic = [
>>>> -	['default', ['-march=armv8-a+crc+crypto']],
>>>> -	['native', ['-march=native']],
>>>> -	['0xd03', ['-mcpu=cortex-a53']],
>>>> -	['0xd04', ['-mcpu=cortex-a35']],
>>>> -	['0xd05', ['-mcpu=cortex-a55']],
>>>> -	['0xd07', ['-mcpu=cortex-a57']],
>>>> -	['0xd08', ['-mcpu=cortex-a72']],
>>>> -	['0xd09', ['-mcpu=cortex-a73']],
>>>> -	['0xd0a', ['-mcpu=cortex-a75']],
>>>> -	['0xd0b', ['-mcpu=cortex-a76']],
>>>> -]
>>>> -machine_args_cavium = [
>>>> -	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
>>>> -	['native', ['-march=native']],
>>>> -	['0xa1', ['-mcpu=thunderxt88']],
>>>> -	['0xa2', ['-mcpu=thunderxt81']],
>>>> -	['0xa3', ['-mcpu=thunderxt83']]]
>>>> -
>>>> flags_common_default = [
>>>> 	# Accelarate rte_memcpy. Be sure to run unit test
>>> (memcpy_perf_autotest)
>>>> 	# to determine the best threshold in code. Refer to notes in source
>>>> file @@ -52,12 +33,10 @@ flags_generic = [
>>>> 	['RTE_USE_C11_MEM_MODEL', true],
>>>> 	['RTE_CACHE_LINE_SIZE', 128]]
>>>> flags_cavium = [
>>>> -	['RTE_MACHINE', '"thunderx"'],
>>>> 	['RTE_CACHE_LINE_SIZE', 128],
>>>> 	['RTE_MAX_NUMA_NODES', 2],
>>>> 	['RTE_MAX_LCORE', 96],
>>>> -	['RTE_MAX_VFIO_GROUPS', 128],
>>>> -	['RTE_USE_C11_MEM_MODEL', false]]
>>>> +	['RTE_MAX_VFIO_GROUPS', 128]]
>>>> flags_dpaa = [
>>>> 	['RTE_MACHINE', '"dpaa"'],
>>>> 	['RTE_USE_C11_MEM_MODEL', true],
>>>> @@ -71,6 +50,27 @@ flags_dpaa2 = [
>>>> 	['RTE_MAX_NUMA_NODES', 1],
>>>> 	['RTE_MAX_LCORE', 16],
>>>> 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
>>>> +flags_default_extra = []
>>>> +flags_thunderx_extra = [
>>>> +	['RTE_MACHINE', '"thunderx"'],
>>>> +	['RTE_USE_C11_MEM_MODEL', false]]
>>>> +
>>>> +machine_args_generic = [
>>>> +	['default', ['-march=armv8-a+crc+crypto']],
>>>> +	['native', ['-march=native']],
>>>> +	['0xd03', ['-mcpu=cortex-a53']],
>>>> +	['0xd04', ['-mcpu=cortex-a35']],
>>>> +	['0xd07', ['-mcpu=cortex-a57']],
>>>> +	['0xd08', ['-mcpu=cortex-a72']],
>>>> +	['0xd09', ['-mcpu=cortex-a73']],
>>>> +	['0xd0a', ['-mcpu=cortex-a75']]]
>>>> +
>>>> +machine_args_cavium = [
>>>> +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
>>>> +	['native', ['-march=native']],
>>>> +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
>>>> +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
>>>> +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
>>>> 
>>>> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page
>>>> G7-5321) impl_generic = ['Generic armv8', flags_generic,
>>>> machine_args_generic] @@ -157,8 +157,16 @@ else
>>>> 	endif
>>>> 	foreach marg: machine[2]
>>>> 		if marg[0] == impl_pn
>>>> -			foreach f: marg[1]
>>>> -				machine_args += f
>>>> +			foreach flag: marg[1]
>>>> +				if cc.has_argument(flag)
>>>> +					machine_args += flag
>>>> +				endif
>>>> +			endforeach
>>>> +			# Apply any extra machine specific flags.
>>>> +			foreach flag: marg.get(2, flags_default_extra)
>>>> +				if flag.length() > 0
>>>> +					dpdk_conf.set(flag[0], flag[1])
>>>> +				endif
>>> 
>>> Let me continue the discussion from v7 here.
>>> Seems I wan't clear enough.
>>> 
>>> Let me take an example. If the host is thunderx2 (0xaf) and compiler is older
>>> than v7, flags_thunderx2_extra isn't set. This means, for example,
>>> RTE_CACHE_LINE_SIZE will still be 128. Is that what you want?
>>> RTE_CACHE_LINE_SIZE has nothing to do with compiler support and you might
>>> want to set it regardless of gcc version. You could skip setting -mcpu with setting
>>> the extra flags.
>>> 
>> 
>> Thanks for the detailed explanation.
>> I think since we have the check to skip mcpu flag when cc doesn't support it (cc.has_argument(flag))
>> It will be safe to remove 
>> `
>>       # Primary part number based mcpu flags are supported
>>       # for gcc versions > 7
>>       if cc.version().version_compare(
>>                       '<7.0') or cmd_output.length() == 0
>>               if not meson.is_cross_build() and arm_force_native_march == true
>>                       impl_pn = 'native'
>>               else
>>                       impl_pn = 'default'
>>               endif
>>       endif
>> `
> 
> +1

I've tested it but still have an issue with old gcc.
Even if -mcpu isn't set due to cc.has_argument(), -march isn't set either.
So, it spews error due to lack of CRC feature.
-march should have '+crc'. The error I got was:

> ninja: Entering directory `build'
> [942/1452] Compiling C object 'drivers/drivers...c@sta/net_softnic_rte_eth_softnic_action.c.o'.
> FAILED: drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic_action.c.o
> cc -Idrivers/drivers@@tmp_rte_pmd_softnic@sta -Idrivers -I../drivers -Idrivers/net/softnic -I../drivers/net/softnic -Ilib/librte_ethdev -I../lib/librte_ethdev -I. -I../ -Iconfig -I../config-Ilib/librte_eal/common/include -I../lib/librte_eal/common/include -I../lib/librte_eal/linux/eal/include -Ilib/librte_eal/common -I../lib/librte_eal/common -Ilib/librte_eal/
> common/include/arch/arm -I../lib/librte_eal/common/include/arch/arm -Ilib/librte_eal -I../lib/librte_eal -Ilib/librte_kvargs -I../lib/librte_kvargs -Ilib/librte_net -I../lib/librte_net -Ilib/librte_mbuf -I../lib/librte_mbuf -Ilib/librte_mempool -I../lib/librte_mempool -Ilib/librte_ring -I../lib/librte_ring -Ilib/librte_cmdline -I../lib/librte_cmdline -Ilib/lib
> rte_meter -I../lib/librte_meter -Idrivers/bus/pci -I../drivers/bus/pci -I../drivers/bus/pci/linux -Ilib/librte_pci -I../lib/librte_pci -Idrivers/bus/vdev -I../drivers/bus/vdev -Ilib/librte_pipeline -I../lib/librte_pipeline -Ilib/librte_port -I../lib/librte_port -Ilib/librte_sched -I../lib/librte_sched -Ilib/librte_ip_frag -I../lib/librte_ip_frag -Ilib/librte_h
> ash -I../lib/librte_hash -Ilib/librte_cryptodev -I../lib/librte_cryptodev -Ilib/librte_kni -I../lib/librte_kni -Ilib/librte_table -I../lib/librte_table -Ilib/librte_lpm -I../lib/librte_lpm -Ilib/librte_acl -I../lib/librte_acl -pipe -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -O3 -include rte_config.h -Wsign-compare -Wcast-qual -fPIC -D_GNU_SOURCE -DALLOW_EXPERI
> MENTAL_API  -MD -MQ 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic_action.c.o' -MF 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic_action.c.o.d' -o 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic_action.c.o' -c ../drivers/net/softnic/rte_eth_softnic_action.c
> {standard input}: Assembler messages:
> {standard input}:14: Error: selected processor does not support `crc32cx w3,w3,x0'
> {standard input}:37: Error: selected processor does not support `crc32cx w1,w1,x3'
> {standard input}:40: Error: selected processor does not support `crc32cx w0,w0,x2'


My machine has 0x41(Arm) and 0xd08(cortex-a72). gcc is '4.8.5 20150623 (Red Hat 4.8.5-28)'

Thanks,
Yongseok


> 
>> 
>> The command output check can also be removed as it is handled when calling the command script itself.
> 
> +1
> 
>> 
>> Thoughts?
>> 
>> PS. I think the safest way to set CACHELINE_SIZE is to read the cache type register[1] but sadly only few latest kernels 
>> have the support through sysfs (/sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size) 
> 
> +1
> 
> In summary, +3. LoL
> 
> I'll also submit a patch to change the default cacheline size of cortex-a72 with the new flags_*_extra[]
> 
> 
> thanks,
> Yongseok

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Yongseok Koh]

> On Apr 11, 2019, at 1:12 PM, Yongseok Koh <yskoh@mellanox.com> wrote:
> 
>> 
>> On Apr 10, 2019, at 11:07 PM, Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com> wrote:
>> 
>> Hi Yongseok,
>> 
>>> -----Original Message-----
>>> From: Yongseok Koh <yskoh@mellanox.com>
>>> Sent: Wednesday, April 10, 2019 11:08 PM
>>> To: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>
>>> Cc: Thomas Monjalon <thomas@monjalon.net>; dev <dev@dpdk.org>; Jerin
>>> Jacob Kollanukkaran <jerinj@marvell.com>; jerinjacobk@gmail.com
>>> Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support
>>> machine specific flags
>>> 
>>> External Email
>>> 
>>> ----------------------------------------------------------------------
>>> 
>>>> On Apr 10, 2019, at 9:13 AM, jerinjacobk@gmail.com wrote:
>>>> 
>>>> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
>>>> 
>>>> Currently, RTE_* flags are set based on the implementer ID but there
>>>> might be some micro arch specific differences from the same vendor eg.
>>>> CACHE_LINESIZE. Add support to set micro arch specific flags.
>>>> 
>>>> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
>>>> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
>>>> ---
>>>> config/arm/meson.build | 56 ++++++++++++++++++++++++------------------
>>>> 1 file changed, 32 insertions(+), 24 deletions(-)
>>>> 
>>>> diff --git a/config/arm/meson.build b/config/arm/meson.build index
>>>> 170a4981a..24bce2b39 100644
>>>> --- a/config/arm/meson.build
>>>> +++ b/config/arm/meson.build
>>>> @@ -7,25 +7,6 @@ march_opt = '-march=@0@'.format(machine)
>>>> 
>>>> arm_force_native_march = false
>>>> 
>>>> -machine_args_generic = [
>>>> -	['default', ['-march=armv8-a+crc+crypto']],
>>>> -	['native', ['-march=native']],
>>>> -	['0xd03', ['-mcpu=cortex-a53']],
>>>> -	['0xd04', ['-mcpu=cortex-a35']],
>>>> -	['0xd05', ['-mcpu=cortex-a55']],
>>>> -	['0xd07', ['-mcpu=cortex-a57']],
>>>> -	['0xd08', ['-mcpu=cortex-a72']],
>>>> -	['0xd09', ['-mcpu=cortex-a73']],
>>>> -	['0xd0a', ['-mcpu=cortex-a75']],
>>>> -	['0xd0b', ['-mcpu=cortex-a76']],
>>>> -]
>>>> -machine_args_cavium = [
>>>> -	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
>>>> -	['native', ['-march=native']],
>>>> -	['0xa1', ['-mcpu=thunderxt88']],
>>>> -	['0xa2', ['-mcpu=thunderxt81']],
>>>> -	['0xa3', ['-mcpu=thunderxt83']]]
>>>> -
>>>> flags_common_default = [
>>>> 	# Accelarate rte_memcpy. Be sure to run unit test
>>> (memcpy_perf_autotest)
>>>> 	# to determine the best threshold in code. Refer to notes in source
>>>> file @@ -52,12 +33,10 @@ flags_generic = [
>>>> 	['RTE_USE_C11_MEM_MODEL', true],
>>>> 	['RTE_CACHE_LINE_SIZE', 128]]
>>>> flags_cavium = [
>>>> -	['RTE_MACHINE', '"thunderx"'],
>>>> 	['RTE_CACHE_LINE_SIZE', 128],
>>>> 	['RTE_MAX_NUMA_NODES', 2],
>>>> 	['RTE_MAX_LCORE', 96],
>>>> -	['RTE_MAX_VFIO_GROUPS', 128],
>>>> -	['RTE_USE_C11_MEM_MODEL', false]]
>>>> +	['RTE_MAX_VFIO_GROUPS', 128]]
>>>> flags_dpaa = [
>>>> 	['RTE_MACHINE', '"dpaa"'],
>>>> 	['RTE_USE_C11_MEM_MODEL', true],
>>>> @@ -71,6 +50,27 @@ flags_dpaa2 = [
>>>> 	['RTE_MAX_NUMA_NODES', 1],
>>>> 	['RTE_MAX_LCORE', 16],
>>>> 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
>>>> +flags_default_extra = []
>>>> +flags_thunderx_extra = [
>>>> +	['RTE_MACHINE', '"thunderx"'],
>>>> +	['RTE_USE_C11_MEM_MODEL', false]]
>>>> +
>>>> +machine_args_generic = [
>>>> +	['default', ['-march=armv8-a+crc+crypto']],
>>>> +	['native', ['-march=native']],
>>>> +	['0xd03', ['-mcpu=cortex-a53']],
>>>> +	['0xd04', ['-mcpu=cortex-a35']],
>>>> +	['0xd07', ['-mcpu=cortex-a57']],
>>>> +	['0xd08', ['-mcpu=cortex-a72']],
>>>> +	['0xd09', ['-mcpu=cortex-a73']],
>>>> +	['0xd0a', ['-mcpu=cortex-a75']]]
>>>> +
>>>> +machine_args_cavium = [
>>>> +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
>>>> +	['native', ['-march=native']],
>>>> +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
>>>> +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
>>>> +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
>>>> 
>>>> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page
>>>> G7-5321) impl_generic = ['Generic armv8', flags_generic,
>>>> machine_args_generic] @@ -157,8 +157,16 @@ else
>>>> 	endif
>>>> 	foreach marg: machine[2]
>>>> 		if marg[0] == impl_pn
>>>> -			foreach f: marg[1]
>>>> -				machine_args += f
>>>> +			foreach flag: marg[1]
>>>> +				if cc.has_argument(flag)
>>>> +					machine_args += flag
>>>> +				endif
>>>> +			endforeach
>>>> +			# Apply any extra machine specific flags.
>>>> +			foreach flag: marg.get(2, flags_default_extra)
>>>> +				if flag.length() > 0
>>>> +					dpdk_conf.set(flag[0], flag[1])
>>>> +				endif
>>> 
>>> Let me continue the discussion from v7 here.
>>> Seems I wan't clear enough.
>>> 
>>> Let me take an example. If the host is thunderx2 (0xaf) and compiler is older
>>> than v7, flags_thunderx2_extra isn't set. This means, for example,
>>> RTE_CACHE_LINE_SIZE will still be 128. Is that what you want?
>>> RTE_CACHE_LINE_SIZE has nothing to do with compiler support and you might
>>> want to set it regardless of gcc version. You could skip setting -mcpu with setting
>>> the extra flags.
>>> 
>> 
>> Thanks for the detailed explanation.
>> I think since we have the check to skip mcpu flag when cc doesn't support it (cc.has_argument(flag))
>> It will be safe to remove 
>> `
>>       # Primary part number based mcpu flags are supported
>>       # for gcc versions > 7
>>       if cc.version().version_compare(
>>                       '<7.0') or cmd_output.length() == 0
>>               if not meson.is_cross_build() and arm_force_native_march == true
>>                       impl_pn = 'native'
>>               else
>>                       impl_pn = 'default'
>>               endif
>>       endif
>> `
> 
> +1

I've tested it but still have an issue with old gcc.
Even if -mcpu isn't set due to cc.has_argument(), -march isn't set either.
So, it spews error due to lack of CRC feature.
-march should have '+crc'. The error I got was:

> ninja: Entering directory `build'
> [942/1452] Compiling C object 'drivers/drivers...c@sta/net_softnic_rte_eth_softnic_action.c.o'.
> FAILED: drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic_action.c.o
> cc -Idrivers/drivers@@tmp_rte_pmd_softnic@sta -Idrivers -I../drivers -Idrivers/net/softnic -I../drivers/net/softnic -Ilib/librte_ethdev -I../lib/librte_ethdev -I. -I../ -Iconfig -I../config-Ilib/librte_eal/common/include -I../lib/librte_eal/common/include -I../lib/librte_eal/linux/eal/include -Ilib/librte_eal/common -I../lib/librte_eal/common -Ilib/librte_eal/
> common/include/arch/arm -I../lib/librte_eal/common/include/arch/arm -Ilib/librte_eal -I../lib/librte_eal -Ilib/librte_kvargs -I../lib/librte_kvargs -Ilib/librte_net -I../lib/librte_net -Ilib/librte_mbuf -I../lib/librte_mbuf -Ilib/librte_mempool -I../lib/librte_mempool -Ilib/librte_ring -I../lib/librte_ring -Ilib/librte_cmdline -I../lib/librte_cmdline -Ilib/lib
> rte_meter -I../lib/librte_meter -Idrivers/bus/pci -I../drivers/bus/pci -I../drivers/bus/pci/linux -Ilib/librte_pci -I../lib/librte_pci -Idrivers/bus/vdev -I../drivers/bus/vdev -Ilib/librte_pipeline -I../lib/librte_pipeline -Ilib/librte_port -I../lib/librte_port -Ilib/librte_sched -I../lib/librte_sched -Ilib/librte_ip_frag -I../lib/librte_ip_frag -Ilib/librte_h
> ash -I../lib/librte_hash -Ilib/librte_cryptodev -I../lib/librte_cryptodev -Ilib/librte_kni -I../lib/librte_kni -Ilib/librte_table -I../lib/librte_table -Ilib/librte_lpm -I../lib/librte_lpm -Ilib/librte_acl -I../lib/librte_acl -pipe -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -O3 -include rte_config.h -Wsign-compare -Wcast-qual -fPIC -D_GNU_SOURCE -DALLOW_EXPERI
> MENTAL_API  -MD -MQ 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic_action.c.o' -MF 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic_action.c.o.d' -o 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic_action.c.o' -c ../drivers/net/softnic/rte_eth_softnic_action.c
> {standard input}: Assembler messages:
> {standard input}:14: Error: selected processor does not support `crc32cx w3,w3,x0'
> {standard input}:37: Error: selected processor does not support `crc32cx w1,w1,x3'
> {standard input}:40: Error: selected processor does not support `crc32cx w0,w0,x2'


My machine has 0x41(Arm) and 0xd08(cortex-a72). gcc is '4.8.5 20150623 (Red Hat 4.8.5-28)'

Thanks,
Yongseok


> 
>> 
>> The command output check can also be removed as it is handled when calling the command script itself.
> 
> +1
> 
>> 
>> Thoughts?
>> 
>> PS. I think the safest way to set CACHELINE_SIZE is to read the cache type register[1] but sadly only few latest kernels 
>> have the support through sysfs (/sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size) 
> 
> +1
> 
> In summary, +3. LoL
> 
> I'll also submit a patch to change the default cacheline size of cortex-a72 with the new flags_*_extra[]
> 
> 
> thanks,
> Yongseok

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Jerin Jacob Kollanukkaran]

> -----Original Message-----
> From: Yongseok Koh <yskoh@mellanox.com>
> Sent: Friday, April 12, 2019 7:35 AM
> To: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>
> Cc: Thomas Monjalon <thomas@monjalon.net>; dev <dev@dpdk.org>; Jerin
> Jacob Kollanukkaran <jerinj@marvell.com>; jerinjacobk@gmail.com
> Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support
> machine specific flags
> 
> External Email
> 
> I've tested it but still have an issue with old gcc.
> Even if -mcpu isn't set due to cc.has_argument(), -march isn't set either.
> So, it spews error due to lack of CRC feature.
> -march should have '+crc'. The error I got was:
> 
> > ninja: Entering directory `build'
> > [942/1452] Compiling C object
> 'drivers/drivers...c@sta/net_softnic_rte_eth_softnic_action.c.o'.
> > FAILED:
> >
> drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic
> _a
> > ction.c.o cc -Idrivers/drivers@@tmp_rte_pmd_softnic@sta -Idrivers
> > -I../drivers -Idrivers/net/softnic -I../drivers/net/softnic
> > -Ilib/librte_ethdev -I../lib/librte_ethdev -I. -I../ -Iconfig
> > -I../config-Ilib/librte_eal/common/include
> > -I../lib/librte_eal/common/include
> > -I../lib/librte_eal/linux/eal/include -Ilib/librte_eal/common
> > -I../lib/librte_eal/common -Ilib/librte_eal/ common/include/arch/arm
> > -I../lib/librte_eal/common/include/arch/arm -Ilib/librte_eal
> > -I../lib/librte_eal -Ilib/librte_kvargs -I../lib/librte_kvargs
> > -Ilib/librte_net -I../lib/librte_net -Ilib/librte_mbuf
> > -I../lib/librte_mbuf -Ilib/librte_mempool -I../lib/librte_mempool
> > -Ilib/librte_ring -I../lib/librte_ring -Ilib/librte_cmdline
> > -I../lib/librte_cmdline -Ilib/lib rte_meter -I../lib/librte_meter
> > -Idrivers/bus/pci -I../drivers/bus/pci -I../drivers/bus/pci/linux
> > -Ilib/librte_pci -I../lib/librte_pci -Idrivers/bus/vdev
> > -I../drivers/bus/vdev -Ilib/librte_pipeline -I../lib/librte_pipeline
> > -Ilib/librte_port -I../lib/librte_port -Ilib/librte_sched
> > -I../lib/librte_sched -Ilib/librte_ip_frag -I../lib/librte_ip_frag
> > -Ilib/librte_h ash -I../lib/librte_hash -Ilib/librte_cryptodev
> > -I../lib/librte_cryptodev -Ilib/librte_kni -I../lib/librte_kni
> > -Ilib/librte_table -I../lib/librte_table -Ilib/librte_lpm
> > -I../lib/librte_lpm -Ilib/librte_acl -I../lib/librte_acl -pipe
> > -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -O3 -include rte_config.h
> > -Wsign-compare -Wcast-qual -fPIC -D_GNU_SOURCE -DALLOW_EXPERI
> > MENTAL_API  -MD -MQ
> >
> 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic
> _
> > action.c.o' -MF
> >
> 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic
> _
> > action.c.o.d' -o
> >
> 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic
> _
> > action.c.o' -c ../drivers/net/softnic/rte_eth_softnic_action.c
> > {standard input}: Assembler messages:
> > {standard input}:14: Error: selected processor does not support `crc32cx
> w3,w3,x0'
> > {standard input}:37: Error: selected processor does not support `crc32cx
> w1,w1,x3'
> > {standard input}:40: Error: selected processor does not support `crc32cx
> w0,w0,x2'
> 
> 
> My machine has 0x41(Arm) and 0xd08(cortex-a72). gcc is '4.8.5 20150623 (Red
> Hat 4.8.5-28)'

Are you testing with very latest master where the following patch available in build?
http://patches.dpdk.org/patch/52367/
It should fix that issue.


> 
> Thanks,
> Yongseok
> 
> 
> >
> >>
> >> The command output check can also be removed as it is handled when
> calling the command script itself.
> >
> > +1
> >
> >>
> >> Thoughts?
> >>
> >> PS. I think the safest way to set CACHELINE_SIZE is to read the cache
> >> type register[1] but sadly only few latest kernels have the support
> >> through sysfs
> >> (/sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size)
> >
> > +1
> >
> > In summary, +3. LoL
> >
> > I'll also submit a patch to change the default cacheline size of
> > cortex-a72 with the new flags_*_extra[]
> >
> >
> > thanks,
> > Yongseok

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Jerin Jacob Kollanukkaran]

> -----Original Message-----
> From: Yongseok Koh <yskoh@mellanox.com>
> Sent: Friday, April 12, 2019 7:35 AM
> To: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>
> Cc: Thomas Monjalon <thomas@monjalon.net>; dev <dev@dpdk.org>; Jerin
> Jacob Kollanukkaran <jerinj@marvell.com>; jerinjacobk@gmail.com
> Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support
> machine specific flags
> 
> External Email
> 
> I've tested it but still have an issue with old gcc.
> Even if -mcpu isn't set due to cc.has_argument(), -march isn't set either.
> So, it spews error due to lack of CRC feature.
> -march should have '+crc'. The error I got was:
> 
> > ninja: Entering directory `build'
> > [942/1452] Compiling C object
> 'drivers/drivers...c@sta/net_softnic_rte_eth_softnic_action.c.o'.
> > FAILED:
> >
> drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic
> _a
> > ction.c.o cc -Idrivers/drivers@@tmp_rte_pmd_softnic@sta -Idrivers
> > -I../drivers -Idrivers/net/softnic -I../drivers/net/softnic
> > -Ilib/librte_ethdev -I../lib/librte_ethdev -I. -I../ -Iconfig
> > -I../config-Ilib/librte_eal/common/include
> > -I../lib/librte_eal/common/include
> > -I../lib/librte_eal/linux/eal/include -Ilib/librte_eal/common
> > -I../lib/librte_eal/common -Ilib/librte_eal/ common/include/arch/arm
> > -I../lib/librte_eal/common/include/arch/arm -Ilib/librte_eal
> > -I../lib/librte_eal -Ilib/librte_kvargs -I../lib/librte_kvargs
> > -Ilib/librte_net -I../lib/librte_net -Ilib/librte_mbuf
> > -I../lib/librte_mbuf -Ilib/librte_mempool -I../lib/librte_mempool
> > -Ilib/librte_ring -I../lib/librte_ring -Ilib/librte_cmdline
> > -I../lib/librte_cmdline -Ilib/lib rte_meter -I../lib/librte_meter
> > -Idrivers/bus/pci -I../drivers/bus/pci -I../drivers/bus/pci/linux
> > -Ilib/librte_pci -I../lib/librte_pci -Idrivers/bus/vdev
> > -I../drivers/bus/vdev -Ilib/librte_pipeline -I../lib/librte_pipeline
> > -Ilib/librte_port -I../lib/librte_port -Ilib/librte_sched
> > -I../lib/librte_sched -Ilib/librte_ip_frag -I../lib/librte_ip_frag
> > -Ilib/librte_h ash -I../lib/librte_hash -Ilib/librte_cryptodev
> > -I../lib/librte_cryptodev -Ilib/librte_kni -I../lib/librte_kni
> > -Ilib/librte_table -I../lib/librte_table -Ilib/librte_lpm
> > -I../lib/librte_lpm -Ilib/librte_acl -I../lib/librte_acl -pipe
> > -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -O3 -include rte_config.h
> > -Wsign-compare -Wcast-qual -fPIC -D_GNU_SOURCE -DALLOW_EXPERI
> > MENTAL_API  -MD -MQ
> >
> 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic
> _
> > action.c.o' -MF
> >
> 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic
> _
> > action.c.o.d' -o
> >
> 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic
> _
> > action.c.o' -c ../drivers/net/softnic/rte_eth_softnic_action.c
> > {standard input}: Assembler messages:
> > {standard input}:14: Error: selected processor does not support `crc32cx
> w3,w3,x0'
> > {standard input}:37: Error: selected processor does not support `crc32cx
> w1,w1,x3'
> > {standard input}:40: Error: selected processor does not support `crc32cx
> w0,w0,x2'
> 
> 
> My machine has 0x41(Arm) and 0xd08(cortex-a72). gcc is '4.8.5 20150623 (Red
> Hat 4.8.5-28)'

Are you testing with very latest master where the following patch available in build?
http://patches.dpdk.org/patch/52367/
It should fix that issue.


> 
> Thanks,
> Yongseok
> 
> 
> >
> >>
> >> The command output check can also be removed as it is handled when
> calling the command script itself.
> >
> > +1
> >
> >>
> >> Thoughts?
> >>
> >> PS. I think the safest way to set CACHELINE_SIZE is to read the cache
> >> type register[1] but sadly only few latest kernels have the support
> >> through sysfs
> >> (/sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size)
> >
> > +1
> >
> > In summary, +3. LoL
> >
> > I'll also submit a patch to change the default cacheline size of
> > cortex-a72 with the new flags_*_extra[]
> >
> >
> > thanks,
> > Yongseok

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Yongseok Koh]

> On Apr 11, 2019, at 11:07 PM, Jerin Jacob Kollanukkaran <jerinj@marvell.com> wrote:
> 
> 
> 
>> -----Original Message-----
>> From: Yongseok Koh <yskoh@mellanox.com>
>> Sent: Friday, April 12, 2019 7:35 AM
>> To: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>
>> Cc: Thomas Monjalon <thomas@monjalon.net>; dev <dev@dpdk.org>; Jerin
>> Jacob Kollanukkaran <jerinj@marvell.com>; jerinjacobk@gmail.com
>> Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support
>> machine specific flags
>> 
>> External Email
>> 
>> I've tested it but still have an issue with old gcc.
>> Even if -mcpu isn't set due to cc.has_argument(), -march isn't set either.
>> So, it spews error due to lack of CRC feature.
>> -march should have '+crc'. The error I got was:
>> 
>>> ninja: Entering directory `build'
>>> [942/1452] Compiling C object
>> 'drivers/drivers...c@sta/net_softnic_rte_eth_softnic_action.c.o'.
>>> FAILED:
>>> 
>> drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic
>> _a
>>> ction.c.o cc -Idrivers/drivers@@tmp_rte_pmd_softnic@sta -Idrivers
>>> -I../drivers -Idrivers/net/softnic -I../drivers/net/softnic
>>> -Ilib/librte_ethdev -I../lib/librte_ethdev -I. -I../ -Iconfig
>>> -I../config-Ilib/librte_eal/common/include
>>> -I../lib/librte_eal/common/include
>>> -I../lib/librte_eal/linux/eal/include -Ilib/librte_eal/common
>>> -I../lib/librte_eal/common -Ilib/librte_eal/ common/include/arch/arm
>>> -I../lib/librte_eal/common/include/arch/arm -Ilib/librte_eal
>>> -I../lib/librte_eal -Ilib/librte_kvargs -I../lib/librte_kvargs
>>> -Ilib/librte_net -I../lib/librte_net -Ilib/librte_mbuf
>>> -I../lib/librte_mbuf -Ilib/librte_mempool -I../lib/librte_mempool
>>> -Ilib/librte_ring -I../lib/librte_ring -Ilib/librte_cmdline
>>> -I../lib/librte_cmdline -Ilib/lib rte_meter -I../lib/librte_meter
>>> -Idrivers/bus/pci -I../drivers/bus/pci -I../drivers/bus/pci/linux
>>> -Ilib/librte_pci -I../lib/librte_pci -Idrivers/bus/vdev
>>> -I../drivers/bus/vdev -Ilib/librte_pipeline -I../lib/librte_pipeline
>>> -Ilib/librte_port -I../lib/librte_port -Ilib/librte_sched
>>> -I../lib/librte_sched -Ilib/librte_ip_frag -I../lib/librte_ip_frag
>>> -Ilib/librte_h ash -I../lib/librte_hash -Ilib/librte_cryptodev
>>> -I../lib/librte_cryptodev -Ilib/librte_kni -I../lib/librte_kni
>>> -Ilib/librte_table -I../lib/librte_table -Ilib/librte_lpm
>>> -I../lib/librte_lpm -Ilib/librte_acl -I../lib/librte_acl -pipe
>>> -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -O3 -include rte_config.h
>>> -Wsign-compare -Wcast-qual -fPIC -D_GNU_SOURCE -DALLOW_EXPERI
>>> MENTAL_API  -MD -MQ
>>> 
>> 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic
>> _
>>> action.c.o' -MF
>>> 
>> 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic
>> _
>>> action.c.o.d' -o
>>> 
>> 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic
>> _
>>> action.c.o' -c ../drivers/net/softnic/rte_eth_softnic_action.c
>>> {standard input}: Assembler messages:
>>> {standard input}:14: Error: selected processor does not support `crc32cx
>> w3,w3,x0'
>>> {standard input}:37: Error: selected processor does not support `crc32cx
>> w1,w1,x3'
>>> {standard input}:40: Error: selected processor does not support `crc32cx
>> w0,w0,x2'
>> 
>> 
>> My machine has 0x41(Arm) and 0xd08(cortex-a72). gcc is '4.8.5 20150623 (Red
>> Hat 4.8.5-28)'
> 
> Are you testing with very latest master where the following patch available in build?
> https://eur03.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatches.dpdk.org%2Fpatch%2F52367%2F&amp;data=02%7C01%7Cyskoh%40mellanox.com%7C9adebf1529ab4bbc189708d6bf0d1d00%7Ca652971c7d2e4d9ba6a4d149256f461b%7C0%7C0%7C636906460384104429&amp;sdata=vG65lezE%2BZacEpn38cUoozwEYm%2BBUGvuYBQ2ToEKnSI%3D&amp;reserved=0
> It should fix that issue.

Thanks, that fixes the issue.
But I've encountered another one. Are you aware of this?

ninja: Entering directory `build'
[1151/1452] Compiling C object 'drivers/drivers@@tmp_r...d_octeontx_event@sta/event_octeontx_timvf_worker.c.o'.
FAILED: drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_timvf_worker.c.o
cc -Idrivers/drivers@@tmp_rte_pmd_octeontx_event@sta -Idrivers -I../drivers -Idrivers/event/octeontx -I../drivers/event/octeontx -Ilib/librte_eventdev -I../lib/librte_eventdev -I. -I../ -Iconfig -I../config -Ilib/librte_eal/common/include -I../lib/librte_eal/common/include -I../lib/librte_eal/linux/eal/include -Ilib/librte_eal/common -I../lib/librte_eal/common -Ilib/librte_eal/common/include/arch/arm -I../lib/librte_eal/co
mmon/include/arch/arm -Ilib/librte_eal -I../lib/librte_eal -Ilib/librte_kvargs -I../lib/librte_kvargs -Ilib/librte_ring -I../lib/librte_ring -Ilib/librte_ethdev -I../lib/librte_ethdev -Ilib/librte_net -I../lib/librte_net -Ilib/librte_mbuf -I../lib/librte_mbuf -Ilib/librte_mempool -I../lib/librte_mempool -Ilib/librte_cmdline -I../lib/librte_cmdline -Ilib/librte_meter -I../lib/librte_meter -Ilib/librte_hash -I../lib/librte_h
ash -Ilib/librte_timer -I../lib/librte_timer -Ilib/librte_cryptodev -I../lib/librte_cryptodev -Idrivers/common/octeontx -I../drivers/common/octeontx -Idrivers/mempool/octeontx -I../drivers/mempool/octeontx -Idrivers/bus/pci -I../drivers/bus/pci -I../drivers/bus/pci/linux -Ilib/librte_pci -I../lib/librte_pci -Idrivers/bus/vdev -I../drivers/bus/vdev -Idrivers/net/octeontx -I../drivers/net/octeontx -Idrivers/net/octeontx/base
 -I../drivers/net/octeontx/base -pipe -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -O3 -include rte_config.h -Wsign-compare -Wcast-qual -fPIC -D_GNU_SOURCE -DALLOW_EXPERIMENTAL_API  -MD -MQ 'drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_timvf_worker.c.o' -MF 'drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_timvf_worker.c.o.d' -o 'drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_t
imvf_worker.c.o' -c ../drivers/event/octeontx/timvf_worker.c
../drivers/event/octeontx/timvf_worker.c: In function ‘timvf_timer_arm_burst_sp’:
../drivers/event/octeontx/timvf_worker.c:88:1: error: could not split insn
 }
 ^
(insn 95 98 99 (parallel [
            (set (reg:DI 3 x3 [orig:98 D.8656 ] [98])
                (mem/v:DI (reg/f:DI 21 x21 [orig:88 D.8662 ] [88]) [-1  S8 A64]))
            (set (mem/v:DI (reg/f:DI 21 x21 [orig:88 D.8662 ] [88]) [-1  S8 A64])
                (unspec_volatile:DI [
                        (plus:DI (mem/v:DI (reg/f:DI 21 x21 [orig:88 D.8662 ] [88]) [-1  S8 A64])
                            (const_int -281474976710656 [0xffff000000000000]))
                        (const_int 0 [0])
                    ] UNSPECV_ATOMIC_OP))
            (clobber (reg:CC 66 cc))
            (clobber (reg:DI 0 x0))
            (clobber (reg:SI 1 x1))
        ]) ../drivers/event/octeontx/timvf_worker.h:95 1832 {atomic_fetch_adddi}
     (expr_list:REG_UNUSED (reg:CC 66 cc)
        (expr_list:REG_UNUSED (reg:SI 1 x1)
            (expr_list:REG_UNUSED (reg:DI 0 x0)
                (nil)))))
../drivers/event/octeontx/timvf_worker.c:88:1: internal compiler error: in final_scan_insn, at final.c:2897
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
{standard input}: Assembler messages:
{standard input}: Error: open CFI at the end of file; missing .cfi_endproc directive
Preprocessed source stored into /tmp/ccnQRbOm.out file, please attach this to your bugreport.
[1168/1452] Compiling C object 'drivers/drivers@@tmp_r...ntx_crypto@sta/crypto_octeontx_otx_cryptodev_ops.c.o'.
ninja: build stopped: subcommand failed.

Thanks
Yongseok

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Yongseok Koh]

> On Apr 11, 2019, at 11:07 PM, Jerin Jacob Kollanukkaran <jerinj@marvell.com> wrote:
> 
> 
> 
>> -----Original Message-----
>> From: Yongseok Koh <yskoh@mellanox.com>
>> Sent: Friday, April 12, 2019 7:35 AM
>> To: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>
>> Cc: Thomas Monjalon <thomas@monjalon.net>; dev <dev@dpdk.org>; Jerin
>> Jacob Kollanukkaran <jerinj@marvell.com>; jerinjacobk@gmail.com
>> Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support
>> machine specific flags
>> 
>> External Email
>> 
>> I've tested it but still have an issue with old gcc.
>> Even if -mcpu isn't set due to cc.has_argument(), -march isn't set either.
>> So, it spews error due to lack of CRC feature.
>> -march should have '+crc'. The error I got was:
>> 
>>> ninja: Entering directory `build'
>>> [942/1452] Compiling C object
>> 'drivers/drivers...c@sta/net_softnic_rte_eth_softnic_action.c.o'.
>>> FAILED:
>>> 
>> drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic
>> _a
>>> ction.c.o cc -Idrivers/drivers@@tmp_rte_pmd_softnic@sta -Idrivers
>>> -I../drivers -Idrivers/net/softnic -I../drivers/net/softnic
>>> -Ilib/librte_ethdev -I../lib/librte_ethdev -I. -I../ -Iconfig
>>> -I../config-Ilib/librte_eal/common/include
>>> -I../lib/librte_eal/common/include
>>> -I../lib/librte_eal/linux/eal/include -Ilib/librte_eal/common
>>> -I../lib/librte_eal/common -Ilib/librte_eal/ common/include/arch/arm
>>> -I../lib/librte_eal/common/include/arch/arm -Ilib/librte_eal
>>> -I../lib/librte_eal -Ilib/librte_kvargs -I../lib/librte_kvargs
>>> -Ilib/librte_net -I../lib/librte_net -Ilib/librte_mbuf
>>> -I../lib/librte_mbuf -Ilib/librte_mempool -I../lib/librte_mempool
>>> -Ilib/librte_ring -I../lib/librte_ring -Ilib/librte_cmdline
>>> -I../lib/librte_cmdline -Ilib/lib rte_meter -I../lib/librte_meter
>>> -Idrivers/bus/pci -I../drivers/bus/pci -I../drivers/bus/pci/linux
>>> -Ilib/librte_pci -I../lib/librte_pci -Idrivers/bus/vdev
>>> -I../drivers/bus/vdev -Ilib/librte_pipeline -I../lib/librte_pipeline
>>> -Ilib/librte_port -I../lib/librte_port -Ilib/librte_sched
>>> -I../lib/librte_sched -Ilib/librte_ip_frag -I../lib/librte_ip_frag
>>> -Ilib/librte_h ash -I../lib/librte_hash -Ilib/librte_cryptodev
>>> -I../lib/librte_cryptodev -Ilib/librte_kni -I../lib/librte_kni
>>> -Ilib/librte_table -I../lib/librte_table -Ilib/librte_lpm
>>> -I../lib/librte_lpm -Ilib/librte_acl -I../lib/librte_acl -pipe
>>> -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -O3 -include rte_config.h
>>> -Wsign-compare -Wcast-qual -fPIC -D_GNU_SOURCE -DALLOW_EXPERI
>>> MENTAL_API  -MD -MQ
>>> 
>> 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic
>> _
>>> action.c.o' -MF
>>> 
>> 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic
>> _
>>> action.c.o.d' -o
>>> 
>> 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic
>> _
>>> action.c.o' -c ../drivers/net/softnic/rte_eth_softnic_action.c
>>> {standard input}: Assembler messages:
>>> {standard input}:14: Error: selected processor does not support `crc32cx
>> w3,w3,x0'
>>> {standard input}:37: Error: selected processor does not support `crc32cx
>> w1,w1,x3'
>>> {standard input}:40: Error: selected processor does not support `crc32cx
>> w0,w0,x2'
>> 
>> 
>> My machine has 0x41(Arm) and 0xd08(cortex-a72). gcc is '4.8.5 20150623 (Red
>> Hat 4.8.5-28)'
> 
> Are you testing with very latest master where the following patch available in build?
> https://eur03.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatches.dpdk.org%2Fpatch%2F52367%2F&amp;data=02%7C01%7Cyskoh%40mellanox.com%7C9adebf1529ab4bbc189708d6bf0d1d00%7Ca652971c7d2e4d9ba6a4d149256f461b%7C0%7C0%7C636906460384104429&amp;sdata=vG65lezE%2BZacEpn38cUoozwEYm%2BBUGvuYBQ2ToEKnSI%3D&amp;reserved=0
> It should fix that issue.

Thanks, that fixes the issue.
But I've encountered another one. Are you aware of this?

ninja: Entering directory `build'
[1151/1452] Compiling C object 'drivers/drivers@@tmp_r...d_octeontx_event@sta/event_octeontx_timvf_worker.c.o'.
FAILED: drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_timvf_worker.c.o
cc -Idrivers/drivers@@tmp_rte_pmd_octeontx_event@sta -Idrivers -I../drivers -Idrivers/event/octeontx -I../drivers/event/octeontx -Ilib/librte_eventdev -I../lib/librte_eventdev -I. -I../ -Iconfig -I../config -Ilib/librte_eal/common/include -I../lib/librte_eal/common/include -I../lib/librte_eal/linux/eal/include -Ilib/librte_eal/common -I../lib/librte_eal/common -Ilib/librte_eal/common/include/arch/arm -I../lib/librte_eal/co
mmon/include/arch/arm -Ilib/librte_eal -I../lib/librte_eal -Ilib/librte_kvargs -I../lib/librte_kvargs -Ilib/librte_ring -I../lib/librte_ring -Ilib/librte_ethdev -I../lib/librte_ethdev -Ilib/librte_net -I../lib/librte_net -Ilib/librte_mbuf -I../lib/librte_mbuf -Ilib/librte_mempool -I../lib/librte_mempool -Ilib/librte_cmdline -I../lib/librte_cmdline -Ilib/librte_meter -I../lib/librte_meter -Ilib/librte_hash -I../lib/librte_h
ash -Ilib/librte_timer -I../lib/librte_timer -Ilib/librte_cryptodev -I../lib/librte_cryptodev -Idrivers/common/octeontx -I../drivers/common/octeontx -Idrivers/mempool/octeontx -I../drivers/mempool/octeontx -Idrivers/bus/pci -I../drivers/bus/pci -I../drivers/bus/pci/linux -Ilib/librte_pci -I../lib/librte_pci -Idrivers/bus/vdev -I../drivers/bus/vdev -Idrivers/net/octeontx -I../drivers/net/octeontx -Idrivers/net/octeontx/base
 -I../drivers/net/octeontx/base -pipe -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -O3 -include rte_config.h -Wsign-compare -Wcast-qual -fPIC -D_GNU_SOURCE -DALLOW_EXPERIMENTAL_API  -MD -MQ 'drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_timvf_worker.c.o' -MF 'drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_timvf_worker.c.o.d' -o 'drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_t
imvf_worker.c.o' -c ../drivers/event/octeontx/timvf_worker.c
../drivers/event/octeontx/timvf_worker.c: In function ‘timvf_timer_arm_burst_sp’:
../drivers/event/octeontx/timvf_worker.c:88:1: error: could not split insn
 }
 ^
(insn 95 98 99 (parallel [
            (set (reg:DI 3 x3 [orig:98 D.8656 ] [98])
                (mem/v:DI (reg/f:DI 21 x21 [orig:88 D.8662 ] [88]) [-1  S8 A64]))
            (set (mem/v:DI (reg/f:DI 21 x21 [orig:88 D.8662 ] [88]) [-1  S8 A64])
                (unspec_volatile:DI [
                        (plus:DI (mem/v:DI (reg/f:DI 21 x21 [orig:88 D.8662 ] [88]) [-1  S8 A64])
                            (const_int -281474976710656 [0xffff000000000000]))
                        (const_int 0 [0])
                    ] UNSPECV_ATOMIC_OP))
            (clobber (reg:CC 66 cc))
            (clobber (reg:DI 0 x0))
            (clobber (reg:SI 1 x1))
        ]) ../drivers/event/octeontx/timvf_worker.h:95 1832 {atomic_fetch_adddi}
     (expr_list:REG_UNUSED (reg:CC 66 cc)
        (expr_list:REG_UNUSED (reg:SI 1 x1)
            (expr_list:REG_UNUSED (reg:DI 0 x0)
                (nil)))))
../drivers/event/octeontx/timvf_worker.c:88:1: internal compiler error: in final_scan_insn, at final.c:2897
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
{standard input}: Assembler messages:
{standard input}: Error: open CFI at the end of file; missing .cfi_endproc directive
Preprocessed source stored into /tmp/ccnQRbOm.out file, please attach this to your bugreport.
[1168/1452] Compiling C object 'drivers/drivers@@tmp_r...ntx_crypto@sta/crypto_octeontx_otx_cryptodev_ops.c.o'.
ninja: build stopped: subcommand failed.

Thanks
Yongseok

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Jerin Jacob Kollanukkaran]

> -----Original Message-----
> From: Yongseok Koh <yskoh@mellanox.com>
> Sent: Friday, April 12, 2019 12:14 PM
> To: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
> Cc: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>; Thomas
> Monjalon <thomas@monjalon.net>; dev <dev@dpdk.org>;
> jerinjacobk@gmail.com
> Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support
> machine specific flags
> 
> 
> Thanks, that fixes the issue.
> But I've encountered another one. Are you aware of this?

Yes. It is a compiler bug. This patch set is NOT introducing this.

Fixed same on legacy build with arm64 . If you are using < 4.8.6 compiler
For meson, this patched needs to be ported to meson

$ git show f3af3e44a444cdfe3fa7b3e2c042be351401eb23
commit f3af3e44a444cdfe3fa7b3e2c042be351401eb23
Author: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Date:   Mon Sep 3 15:01:10 2018 +0530

    mk: disable OcteonTx for buggy compilers only on arm64
    
    Disable octeontx for gcc 4.8.5 as the compiler is emitting "internal
    compiler error" for aarch64. The GCC "internal compiler error" was
    observed only for arm64 architecture so disable the PMD only
    for arm64.
    
    Fixes: 4f760550a093 ("mk: disable OcteonTx for buggy compilers")
    Cc: stable@dpdk.org
    
    Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
    Acked-by: Ferruh Yigit <ferruh.yigit@intel.com>

> 
> ninja: Entering directory `build'
> [1151/1452] Compiling C object
> 'drivers/drivers@@tmp_r...d_octeontx_event@sta/event_octeontx_timvf_
> worker.c.o'.
> FAILED:
> drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_ti
> mvf_worker.c.o
> cc -Idrivers/drivers@@tmp_rte_pmd_octeontx_event@sta -Idrivers -
> I../drivers -Idrivers/event/octeontx -I../drivers/event/octeontx -
> Ilib/librte_eventdev -I../lib/librte_eventdev -I. -I../ -Iconfig -I../config -
> Ilib/librte_eal/common/include -I../lib/librte_eal/common/include -
> I../lib/librte_eal/linux/eal/include -Ilib/librte_eal/common -
> I../lib/librte_eal/common -Ilib/librte_eal/common/include/arch/arm -
> I../lib/librte_eal/co mmon/include/arch/arm -Ilib/librte_eal -I../lib/librte_eal
> -Ilib/librte_kvargs -I../lib/librte_kvargs -Ilib/librte_ring -I../lib/librte_ring -
> Ilib/librte_ethdev -I../lib/librte_ethdev -Ilib/librte_net -I../lib/librte_net -
> Ilib/librte_mbuf -I../lib/librte_mbuf -Ilib/librte_mempool -
> I../lib/librte_mempool -Ilib/librte_cmdline -I../lib/librte_cmdline -
> Ilib/librte_meter -I../lib/librte_meter -Ilib/librte_hash -I../lib/librte_h ash -
> Ilib/librte_timer -I../lib/librte_timer -Ilib/librte_cryptodev -
> I../lib/librte_cryptodev -Idrivers/common/octeontx -
> I../drivers/common/octeontx -Idrivers/mempool/octeontx -
> I../drivers/mempool/octeontx -Idrivers/bus/pci -I../drivers/bus/pci -
> I../drivers/bus/pci/linux -Ilib/librte_pci -I../lib/librte_pci -Idrivers/bus/vdev -
> I../drivers/bus/vdev -Idrivers/net/octeontx -I../drivers/net/octeontx -
> Idrivers/net/octeontx/base  -I../drivers/net/octeontx/base -pipe -
> D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -O3 -include rte_config.h -
> Wsign-compare -Wcast-qual -fPIC -D_GNU_SOURCE -
> DALLOW_EXPERIMENTAL_API  -MD -MQ
> 'drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_ti
> mvf_worker.c.o' -MF
> 'drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_ti
> mvf_worker.c.o.d' -o
> 'drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_t
> imvf_worker.c.o' -c ../drivers/event/octeontx/timvf_worker.c
> ../drivers/event/octeontx/timvf_worker.c: In function
> ‘timvf_timer_arm_burst_sp’:
> ../drivers/event/octeontx/timvf_worker.c:88:1: error: could not split insn  }
> ^ (insn 95 98 99 (parallel [
>             (set (reg:DI 3 x3 [orig:98 D.8656 ] [98])
>                 (mem/v:DI (reg/f:DI 21 x21 [orig:88 D.8662 ] [88]) [-1  S8 A64]))
>             (set (mem/v:DI (reg/f:DI 21 x21 [orig:88 D.8662 ] [88]) [-1  S8 A64])
>                 (unspec_volatile:DI [
>                         (plus:DI (mem/v:DI (reg/f:DI 21 x21 [orig:88 D.8662 ] [88]) [-1  S8
> A64])
>                             (const_int -281474976710656 [0xffff000000000000]))
>                         (const_int 0 [0])
>                     ] UNSPECV_ATOMIC_OP))
>             (clobber (reg:CC 66 cc))
>             (clobber (reg:DI 0 x0))
>             (clobber (reg:SI 1 x1))
>         ]) ../drivers/event/octeontx/timvf_worker.h:95 1832
> {atomic_fetch_adddi}
>      (expr_list:REG_UNUSED (reg:CC 66 cc)
>         (expr_list:REG_UNUSED (reg:SI 1 x1)
>             (expr_list:REG_UNUSED (reg:DI 0 x0)
>                 (nil)))))
> ../drivers/event/octeontx/timvf_worker.c:88:1: internal compiler error: in
> final_scan_insn, at final.c:2897 Please submit a full bug report, with
> preprocessed source if appropriate.
> See <http://bugzilla.redhat.com/bugzilla> for instructions.
> {standard input}: Assembler messages:
> {standard input}: Error: open CFI at the end of file; missing .cfi_endproc
> directive Preprocessed source stored into /tmp/ccnQRbOm.out file, please
> attach this to your bugreport.
> [1168/1452] Compiling C object
> 'drivers/drivers@@tmp_r...ntx_crypto@sta/crypto_octeontx_otx_cryptode
> v_ops.c.o'.
> ninja: build stopped: subcommand failed.
> 
> Thanks
> Yongseok

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Jerin Jacob Kollanukkaran]

> -----Original Message-----
> From: Yongseok Koh <yskoh@mellanox.com>
> Sent: Friday, April 12, 2019 12:14 PM
> To: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
> Cc: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>; Thomas
> Monjalon <thomas@monjalon.net>; dev <dev@dpdk.org>;
> jerinjacobk@gmail.com
> Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support
> machine specific flags
> 
> 
> Thanks, that fixes the issue.
> But I've encountered another one. Are you aware of this?

Yes. It is a compiler bug. This patch set is NOT introducing this.

Fixed same on legacy build with arm64 . If you are using < 4.8.6 compiler
For meson, this patched needs to be ported to meson

$ git show f3af3e44a444cdfe3fa7b3e2c042be351401eb23
commit f3af3e44a444cdfe3fa7b3e2c042be351401eb23
Author: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Date:   Mon Sep 3 15:01:10 2018 +0530

    mk: disable OcteonTx for buggy compilers only on arm64
    
    Disable octeontx for gcc 4.8.5 as the compiler is emitting "internal
    compiler error" for aarch64. The GCC "internal compiler error" was
    observed only for arm64 architecture so disable the PMD only
    for arm64.
    
    Fixes: 4f760550a093 ("mk: disable OcteonTx for buggy compilers")
    Cc: stable@dpdk.org
    
    Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
    Acked-by: Ferruh Yigit <ferruh.yigit@intel.com>

> 
> ninja: Entering directory `build'
> [1151/1452] Compiling C object
> 'drivers/drivers@@tmp_r...d_octeontx_event@sta/event_octeontx_timvf_
> worker.c.o'.
> FAILED:
> drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_ti
> mvf_worker.c.o
> cc -Idrivers/drivers@@tmp_rte_pmd_octeontx_event@sta -Idrivers -
> I../drivers -Idrivers/event/octeontx -I../drivers/event/octeontx -
> Ilib/librte_eventdev -I../lib/librte_eventdev -I. -I../ -Iconfig -I../config -
> Ilib/librte_eal/common/include -I../lib/librte_eal/common/include -
> I../lib/librte_eal/linux/eal/include -Ilib/librte_eal/common -
> I../lib/librte_eal/common -Ilib/librte_eal/common/include/arch/arm -
> I../lib/librte_eal/co mmon/include/arch/arm -Ilib/librte_eal -I../lib/librte_eal
> -Ilib/librte_kvargs -I../lib/librte_kvargs -Ilib/librte_ring -I../lib/librte_ring -
> Ilib/librte_ethdev -I../lib/librte_ethdev -Ilib/librte_net -I../lib/librte_net -
> Ilib/librte_mbuf -I../lib/librte_mbuf -Ilib/librte_mempool -
> I../lib/librte_mempool -Ilib/librte_cmdline -I../lib/librte_cmdline -
> Ilib/librte_meter -I../lib/librte_meter -Ilib/librte_hash -I../lib/librte_h ash -
> Ilib/librte_timer -I../lib/librte_timer -Ilib/librte_cryptodev -
> I../lib/librte_cryptodev -Idrivers/common/octeontx -
> I../drivers/common/octeontx -Idrivers/mempool/octeontx -
> I../drivers/mempool/octeontx -Idrivers/bus/pci -I../drivers/bus/pci -
> I../drivers/bus/pci/linux -Ilib/librte_pci -I../lib/librte_pci -Idrivers/bus/vdev -
> I../drivers/bus/vdev -Idrivers/net/octeontx -I../drivers/net/octeontx -
> Idrivers/net/octeontx/base  -I../drivers/net/octeontx/base -pipe -
> D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -O3 -include rte_config.h -
> Wsign-compare -Wcast-qual -fPIC -D_GNU_SOURCE -
> DALLOW_EXPERIMENTAL_API  -MD -MQ
> 'drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_ti
> mvf_worker.c.o' -MF
> 'drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_ti
> mvf_worker.c.o.d' -o
> 'drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_t
> imvf_worker.c.o' -c ../drivers/event/octeontx/timvf_worker.c
> ../drivers/event/octeontx/timvf_worker.c: In function
> ‘timvf_timer_arm_burst_sp’:
> ../drivers/event/octeontx/timvf_worker.c:88:1: error: could not split insn  }
> ^ (insn 95 98 99 (parallel [
>             (set (reg:DI 3 x3 [orig:98 D.8656 ] [98])
>                 (mem/v:DI (reg/f:DI 21 x21 [orig:88 D.8662 ] [88]) [-1  S8 A64]))
>             (set (mem/v:DI (reg/f:DI 21 x21 [orig:88 D.8662 ] [88]) [-1  S8 A64])
>                 (unspec_volatile:DI [
>                         (plus:DI (mem/v:DI (reg/f:DI 21 x21 [orig:88 D.8662 ] [88]) [-1  S8
> A64])
>                             (const_int -281474976710656 [0xffff000000000000]))
>                         (const_int 0 [0])
>                     ] UNSPECV_ATOMIC_OP))
>             (clobber (reg:CC 66 cc))
>             (clobber (reg:DI 0 x0))
>             (clobber (reg:SI 1 x1))
>         ]) ../drivers/event/octeontx/timvf_worker.h:95 1832
> {atomic_fetch_adddi}
>      (expr_list:REG_UNUSED (reg:CC 66 cc)
>         (expr_list:REG_UNUSED (reg:SI 1 x1)
>             (expr_list:REG_UNUSED (reg:DI 0 x0)
>                 (nil)))))
> ../drivers/event/octeontx/timvf_worker.c:88:1: internal compiler error: in
> final_scan_insn, at final.c:2897 Please submit a full bug report, with
> preprocessed source if appropriate.
> See <http://bugzilla.redhat.com/bugzilla> for instructions.
> {standard input}: Assembler messages:
> {standard input}: Error: open CFI at the end of file; missing .cfi_endproc
> directive Preprocessed source stored into /tmp/ccnQRbOm.out file, please
> attach this to your bugreport.
> [1168/1452] Compiling C object
> 'drivers/drivers@@tmp_r...ntx_crypto@sta/crypto_octeontx_otx_cryptode
> v_ops.c.o'.
> ninja: build stopped: subcommand failed.
> 
> Thanks
> Yongseok

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Yongseok Koh]

> On Apr 11, 2019, at 11:43 PM, Yongseok Koh <yskoh@mellanox.com> wrote:
> 
> 
>> On Apr 11, 2019, at 11:07 PM, Jerin Jacob Kollanukkaran <jerinj@marvell.com> wrote:
>> 
>> 
>> 
>>> -----Original Message-----
>>> From: Yongseok Koh <yskoh@mellanox.com>
>>> Sent: Friday, April 12, 2019 7:35 AM
>>> To: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>
>>> Cc: Thomas Monjalon <thomas@monjalon.net>; dev <dev@dpdk.org>; Jerin
>>> Jacob Kollanukkaran <jerinj@marvell.com>; jerinjacobk@gmail.com
>>> Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support
>>> machine specific flags
>>> 
>>> External Email
>>> 
>>> I've tested it but still have an issue with old gcc.
>>> Even if -mcpu isn't set due to cc.has_argument(), -march isn't set either.
>>> So, it spews error due to lack of CRC feature.
>>> -march should have '+crc'. The error I got was:
>>> 
>>>> ninja: Entering directory `build'
>>>> [942/1452] Compiling C object
>>> 'drivers/drivers...c@sta/net_softnic_rte_eth_softnic_action.c.o'.
>>>> FAILED:
>>>> 
>>> drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic
>>> _a
>>>> ction.c.o cc -Idrivers/drivers@@tmp_rte_pmd_softnic@sta -Idrivers
>>>> -I../drivers -Idrivers/net/softnic -I../drivers/net/softnic
>>>> -Ilib/librte_ethdev -I../lib/librte_ethdev -I. -I../ -Iconfig
>>>> -I../config-Ilib/librte_eal/common/include
>>>> -I../lib/librte_eal/common/include
>>>> -I../lib/librte_eal/linux/eal/include -Ilib/librte_eal/common
>>>> -I../lib/librte_eal/common -Ilib/librte_eal/ common/include/arch/arm
>>>> -I../lib/librte_eal/common/include/arch/arm -Ilib/librte_eal
>>>> -I../lib/librte_eal -Ilib/librte_kvargs -I../lib/librte_kvargs
>>>> -Ilib/librte_net -I../lib/librte_net -Ilib/librte_mbuf
>>>> -I../lib/librte_mbuf -Ilib/librte_mempool -I../lib/librte_mempool
>>>> -Ilib/librte_ring -I../lib/librte_ring -Ilib/librte_cmdline
>>>> -I../lib/librte_cmdline -Ilib/lib rte_meter -I../lib/librte_meter
>>>> -Idrivers/bus/pci -I../drivers/bus/pci -I../drivers/bus/pci/linux
>>>> -Ilib/librte_pci -I../lib/librte_pci -Idrivers/bus/vdev
>>>> -I../drivers/bus/vdev -Ilib/librte_pipeline -I../lib/librte_pipeline
>>>> -Ilib/librte_port -I../lib/librte_port -Ilib/librte_sched
>>>> -I../lib/librte_sched -Ilib/librte_ip_frag -I../lib/librte_ip_frag
>>>> -Ilib/librte_h ash -I../lib/librte_hash -Ilib/librte_cryptodev
>>>> -I../lib/librte_cryptodev -Ilib/librte_kni -I../lib/librte_kni
>>>> -Ilib/librte_table -I../lib/librte_table -Ilib/librte_lpm
>>>> -I../lib/librte_lpm -Ilib/librte_acl -I../lib/librte_acl -pipe
>>>> -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -O3 -include rte_config.h
>>>> -Wsign-compare -Wcast-qual -fPIC -D_GNU_SOURCE -DALLOW_EXPERI
>>>> MENTAL_API  -MD -MQ
>>>> 
>>> 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic
>>> _
>>>> action.c.o' -MF
>>>> 
>>> 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic
>>> _
>>>> action.c.o.d' -o
>>>> 
>>> 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic
>>> _
>>>> action.c.o' -c ../drivers/net/softnic/rte_eth_softnic_action.c
>>>> {standard input}: Assembler messages:
>>>> {standard input}:14: Error: selected processor does not support `crc32cx
>>> w3,w3,x0'
>>>> {standard input}:37: Error: selected processor does not support `crc32cx
>>> w1,w1,x3'
>>>> {standard input}:40: Error: selected processor does not support `crc32cx
>>> w0,w0,x2'
>>> 
>>> 
>>> My machine has 0x41(Arm) and 0xd08(cortex-a72). gcc is '4.8.5 20150623 (Red
>>> Hat 4.8.5-28)'
>> 
>> Are you testing with very latest master where the following patch available in build?
>> https://eur03.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatches.dpdk.org%2Fpatch%2F52367%2F&amp;data=02%7C01%7Cyskoh%40mellanox.com%7C5909260f30a64e07a95108d6bf123bde%7Ca652971c7d2e4d9ba6a4d149256f461b%7C0%7C0%7C636906482386596820&amp;sdata=4%2BfRfELXK37SNY4wdFNGPF8lpU7S3DEfPoDfAH5K7GE%3D&amp;reserved=0
>> It should fix that issue.
> 
> Thanks, that fixes the issue.
> But I've encountered another one. Are you aware of this?
> 
> ninja: Entering directory `build'
> [1151/1452] Compiling C object 'drivers/drivers@@tmp_r...d_octeontx_event@sta/event_octeontx_timvf_worker.c.o'.
> FAILED: drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_timvf_worker.c.o
> cc -Idrivers/drivers@@tmp_rte_pmd_octeontx_event@sta -Idrivers -I../drivers -Idrivers/event/octeontx -I../drivers/event/octeontx -Ilib/librte_eventdev -I../lib/librte_eventdev -I. -I../ -Iconfig -I../config -Ilib/librte_eal/common/include -I../lib/librte_eal/common/include -I../lib/librte_eal/linux/eal/include -Ilib/librte_eal/common -I../lib/librte_eal/common -Ilib/librte_eal/common/include/arch/arm -I../lib/librte_eal/co
> mmon/include/arch/arm -Ilib/librte_eal -I../lib/librte_eal -Ilib/librte_kvargs -I../lib/librte_kvargs -Ilib/librte_ring -I../lib/librte_ring -Ilib/librte_ethdev -I../lib/librte_ethdev -Ilib/librte_net -I../lib/librte_net -Ilib/librte_mbuf -I../lib/librte_mbuf -Ilib/librte_mempool -I../lib/librte_mempool -Ilib/librte_cmdline -I../lib/librte_cmdline -Ilib/librte_meter -I../lib/librte_meter -Ilib/librte_hash -I../lib/librte_h
> ash -Ilib/librte_timer -I../lib/librte_timer -Ilib/librte_cryptodev -I../lib/librte_cryptodev -Idrivers/common/octeontx -I../drivers/common/octeontx -Idrivers/mempool/octeontx -I../drivers/mempool/octeontx -Idrivers/bus/pci -I../drivers/bus/pci -I../drivers/bus/pci/linux -Ilib/librte_pci -I../lib/librte_pci -Idrivers/bus/vdev -I../drivers/bus/vdev -Idrivers/net/octeontx -I../drivers/net/octeontx -Idrivers/net/octeontx/base
> -I../drivers/net/octeontx/base -pipe -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -O3 -include rte_config.h -Wsign-compare -Wcast-qual -fPIC -D_GNU_SOURCE -DALLOW_EXPERIMENTAL_API  -MD -MQ 'drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_timvf_worker.c.o' -MF 'drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_timvf_worker.c.o.d' -o 'drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_t
> imvf_worker.c.o' -c ../drivers/event/octeontx/timvf_worker.c
> ../drivers/event/octeontx/timvf_worker.c: In function ‘timvf_timer_arm_burst_sp’:
> ../drivers/event/octeontx/timvf_worker.c:88:1: error: could not split insn
> }
> ^
> (insn 95 98 99 (parallel [
>            (set (reg:DI 3 x3 [orig:98 D.8656 ] [98])
>                (mem/v:DI (reg/f:DI 21 x21 [orig:88 D.8662 ] [88]) [-1  S8 A64]))
>            (set (mem/v:DI (reg/f:DI 21 x21 [orig:88 D.8662 ] [88]) [-1  S8 A64])
>                (unspec_volatile:DI [
>                        (plus:DI (mem/v:DI (reg/f:DI 21 x21 [orig:88 D.8662 ] [88]) [-1  S8 A64])
>                            (const_int -281474976710656 [0xffff000000000000]))
>                        (const_int 0 [0])
>                    ] UNSPECV_ATOMIC_OP))
>            (clobber (reg:CC 66 cc))
>            (clobber (reg:DI 0 x0))
>            (clobber (reg:SI 1 x1))
>        ]) ../drivers/event/octeontx/timvf_worker.h:95 1832 {atomic_fetch_adddi}
>     (expr_list:REG_UNUSED (reg:CC 66 cc)
>        (expr_list:REG_UNUSED (reg:SI 1 x1)
>            (expr_list:REG_UNUSED (reg:DI 0 x0)
>                (nil)))))
> ../drivers/event/octeontx/timvf_worker.c:88:1: internal compiler error: in final_scan_insn, at final.c:2897
> Please submit a full bug report,
> with preprocessed source if appropriate.
> See <https://eur03.safelinks.protection.outlook.com/?url=http%3A%2F%2Fbugzilla.redhat.com%2Fbugzilla&amp;data=02%7C01%7Cyskoh%40mellanox.com%7C5909260f30a64e07a95108d6bf123bde%7Ca652971c7d2e4d9ba6a4d149256f461b%7C0%7C0%7C636906482386596820&amp;sdata=2AH1gInkxui7UEDb7LLNppMxDEaf%2F5N5TEHhDRTSDJY%3D&amp;reserved=0> for instructions.
> {standard input}: Assembler messages:
> {standard input}: Error: open CFI at the end of file; missing .cfi_endproc directive
> Preprocessed source stored into /tmp/ccnQRbOm.out file, please attach this to your bugreport.
> [1168/1452] Compiling C object 'drivers/drivers@@tmp_r...ntx_crypto@sta/crypto_octeontx_otx_cryptodev_ops.c.o'.
> ninja: build stopped: subcommand failed.


One more issue.
With gcc7.2, crypto isn't enabled if -mcpu is set.
How about thunderx/octeon?
Looks it should be like -mcpu=cortex-a72+crypto
I'll take care of this in a separate patch.
Because I want to add a new option to control it.
The reason is a binary having crypto support can't be run on a cpu w/o crypto extension, it is panicked.
And -mcpu=cortex-a72 includes 'crc' support by default.


Thanks,
Yongseok

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Yongseok Koh]

> On Apr 11, 2019, at 11:43 PM, Yongseok Koh <yskoh@mellanox.com> wrote:
> 
> 
>> On Apr 11, 2019, at 11:07 PM, Jerin Jacob Kollanukkaran <jerinj@marvell.com> wrote:
>> 
>> 
>> 
>>> -----Original Message-----
>>> From: Yongseok Koh <yskoh@mellanox.com>
>>> Sent: Friday, April 12, 2019 7:35 AM
>>> To: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>
>>> Cc: Thomas Monjalon <thomas@monjalon.net>; dev <dev@dpdk.org>; Jerin
>>> Jacob Kollanukkaran <jerinj@marvell.com>; jerinjacobk@gmail.com
>>> Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support
>>> machine specific flags
>>> 
>>> External Email
>>> 
>>> I've tested it but still have an issue with old gcc.
>>> Even if -mcpu isn't set due to cc.has_argument(), -march isn't set either.
>>> So, it spews error due to lack of CRC feature.
>>> -march should have '+crc'. The error I got was:
>>> 
>>>> ninja: Entering directory `build'
>>>> [942/1452] Compiling C object
>>> 'drivers/drivers...c@sta/net_softnic_rte_eth_softnic_action.c.o'.
>>>> FAILED:
>>>> 
>>> drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic
>>> _a
>>>> ction.c.o cc -Idrivers/drivers@@tmp_rte_pmd_softnic@sta -Idrivers
>>>> -I../drivers -Idrivers/net/softnic -I../drivers/net/softnic
>>>> -Ilib/librte_ethdev -I../lib/librte_ethdev -I. -I../ -Iconfig
>>>> -I../config-Ilib/librte_eal/common/include
>>>> -I../lib/librte_eal/common/include
>>>> -I../lib/librte_eal/linux/eal/include -Ilib/librte_eal/common
>>>> -I../lib/librte_eal/common -Ilib/librte_eal/ common/include/arch/arm
>>>> -I../lib/librte_eal/common/include/arch/arm -Ilib/librte_eal
>>>> -I../lib/librte_eal -Ilib/librte_kvargs -I../lib/librte_kvargs
>>>> -Ilib/librte_net -I../lib/librte_net -Ilib/librte_mbuf
>>>> -I../lib/librte_mbuf -Ilib/librte_mempool -I../lib/librte_mempool
>>>> -Ilib/librte_ring -I../lib/librte_ring -Ilib/librte_cmdline
>>>> -I../lib/librte_cmdline -Ilib/lib rte_meter -I../lib/librte_meter
>>>> -Idrivers/bus/pci -I../drivers/bus/pci -I../drivers/bus/pci/linux
>>>> -Ilib/librte_pci -I../lib/librte_pci -Idrivers/bus/vdev
>>>> -I../drivers/bus/vdev -Ilib/librte_pipeline -I../lib/librte_pipeline
>>>> -Ilib/librte_port -I../lib/librte_port -Ilib/librte_sched
>>>> -I../lib/librte_sched -Ilib/librte_ip_frag -I../lib/librte_ip_frag
>>>> -Ilib/librte_h ash -I../lib/librte_hash -Ilib/librte_cryptodev
>>>> -I../lib/librte_cryptodev -Ilib/librte_kni -I../lib/librte_kni
>>>> -Ilib/librte_table -I../lib/librte_table -Ilib/librte_lpm
>>>> -I../lib/librte_lpm -Ilib/librte_acl -I../lib/librte_acl -pipe
>>>> -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -O3 -include rte_config.h
>>>> -Wsign-compare -Wcast-qual -fPIC -D_GNU_SOURCE -DALLOW_EXPERI
>>>> MENTAL_API  -MD -MQ
>>>> 
>>> 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic
>>> _
>>>> action.c.o' -MF
>>>> 
>>> 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic
>>> _
>>>> action.c.o.d' -o
>>>> 
>>> 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_softnic
>>> _
>>>> action.c.o' -c ../drivers/net/softnic/rte_eth_softnic_action.c
>>>> {standard input}: Assembler messages:
>>>> {standard input}:14: Error: selected processor does not support `crc32cx
>>> w3,w3,x0'
>>>> {standard input}:37: Error: selected processor does not support `crc32cx
>>> w1,w1,x3'
>>>> {standard input}:40: Error: selected processor does not support `crc32cx
>>> w0,w0,x2'
>>> 
>>> 
>>> My machine has 0x41(Arm) and 0xd08(cortex-a72). gcc is '4.8.5 20150623 (Red
>>> Hat 4.8.5-28)'
>> 
>> Are you testing with very latest master where the following patch available in build?
>> https://eur03.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatches.dpdk.org%2Fpatch%2F52367%2F&amp;data=02%7C01%7Cyskoh%40mellanox.com%7C5909260f30a64e07a95108d6bf123bde%7Ca652971c7d2e4d9ba6a4d149256f461b%7C0%7C0%7C636906482386596820&amp;sdata=4%2BfRfELXK37SNY4wdFNGPF8lpU7S3DEfPoDfAH5K7GE%3D&amp;reserved=0
>> It should fix that issue.
> 
> Thanks, that fixes the issue.
> But I've encountered another one. Are you aware of this?
> 
> ninja: Entering directory `build'
> [1151/1452] Compiling C object 'drivers/drivers@@tmp_r...d_octeontx_event@sta/event_octeontx_timvf_worker.c.o'.
> FAILED: drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_timvf_worker.c.o
> cc -Idrivers/drivers@@tmp_rte_pmd_octeontx_event@sta -Idrivers -I../drivers -Idrivers/event/octeontx -I../drivers/event/octeontx -Ilib/librte_eventdev -I../lib/librte_eventdev -I. -I../ -Iconfig -I../config -Ilib/librte_eal/common/include -I../lib/librte_eal/common/include -I../lib/librte_eal/linux/eal/include -Ilib/librte_eal/common -I../lib/librte_eal/common -Ilib/librte_eal/common/include/arch/arm -I../lib/librte_eal/co
> mmon/include/arch/arm -Ilib/librte_eal -I../lib/librte_eal -Ilib/librte_kvargs -I../lib/librte_kvargs -Ilib/librte_ring -I../lib/librte_ring -Ilib/librte_ethdev -I../lib/librte_ethdev -Ilib/librte_net -I../lib/librte_net -Ilib/librte_mbuf -I../lib/librte_mbuf -Ilib/librte_mempool -I../lib/librte_mempool -Ilib/librte_cmdline -I../lib/librte_cmdline -Ilib/librte_meter -I../lib/librte_meter -Ilib/librte_hash -I../lib/librte_h
> ash -Ilib/librte_timer -I../lib/librte_timer -Ilib/librte_cryptodev -I../lib/librte_cryptodev -Idrivers/common/octeontx -I../drivers/common/octeontx -Idrivers/mempool/octeontx -I../drivers/mempool/octeontx -Idrivers/bus/pci -I../drivers/bus/pci -I../drivers/bus/pci/linux -Ilib/librte_pci -I../lib/librte_pci -Idrivers/bus/vdev -I../drivers/bus/vdev -Idrivers/net/octeontx -I../drivers/net/octeontx -Idrivers/net/octeontx/base
> -I../drivers/net/octeontx/base -pipe -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -O3 -include rte_config.h -Wsign-compare -Wcast-qual -fPIC -D_GNU_SOURCE -DALLOW_EXPERIMENTAL_API  -MD -MQ 'drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_timvf_worker.c.o' -MF 'drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_timvf_worker.c.o.d' -o 'drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_t
> imvf_worker.c.o' -c ../drivers/event/octeontx/timvf_worker.c
> ../drivers/event/octeontx/timvf_worker.c: In function ‘timvf_timer_arm_burst_sp’:
> ../drivers/event/octeontx/timvf_worker.c:88:1: error: could not split insn
> }
> ^
> (insn 95 98 99 (parallel [
>            (set (reg:DI 3 x3 [orig:98 D.8656 ] [98])
>                (mem/v:DI (reg/f:DI 21 x21 [orig:88 D.8662 ] [88]) [-1  S8 A64]))
>            (set (mem/v:DI (reg/f:DI 21 x21 [orig:88 D.8662 ] [88]) [-1  S8 A64])
>                (unspec_volatile:DI [
>                        (plus:DI (mem/v:DI (reg/f:DI 21 x21 [orig:88 D.8662 ] [88]) [-1  S8 A64])
>                            (const_int -281474976710656 [0xffff000000000000]))
>                        (const_int 0 [0])
>                    ] UNSPECV_ATOMIC_OP))
>            (clobber (reg:CC 66 cc))
>            (clobber (reg:DI 0 x0))
>            (clobber (reg:SI 1 x1))
>        ]) ../drivers/event/octeontx/timvf_worker.h:95 1832 {atomic_fetch_adddi}
>     (expr_list:REG_UNUSED (reg:CC 66 cc)
>        (expr_list:REG_UNUSED (reg:SI 1 x1)
>            (expr_list:REG_UNUSED (reg:DI 0 x0)
>                (nil)))))
> ../drivers/event/octeontx/timvf_worker.c:88:1: internal compiler error: in final_scan_insn, at final.c:2897
> Please submit a full bug report,
> with preprocessed source if appropriate.
> See <https://eur03.safelinks.protection.outlook.com/?url=http%3A%2F%2Fbugzilla.redhat.com%2Fbugzilla&amp;data=02%7C01%7Cyskoh%40mellanox.com%7C5909260f30a64e07a95108d6bf123bde%7Ca652971c7d2e4d9ba6a4d149256f461b%7C0%7C0%7C636906482386596820&amp;sdata=2AH1gInkxui7UEDb7LLNppMxDEaf%2F5N5TEHhDRTSDJY%3D&amp;reserved=0> for instructions.
> {standard input}: Assembler messages:
> {standard input}: Error: open CFI at the end of file; missing .cfi_endproc directive
> Preprocessed source stored into /tmp/ccnQRbOm.out file, please attach this to your bugreport.
> [1168/1452] Compiling C object 'drivers/drivers@@tmp_r...ntx_crypto@sta/crypto_octeontx_otx_cryptodev_ops.c.o'.
> ninja: build stopped: subcommand failed.


One more issue.
With gcc7.2, crypto isn't enabled if -mcpu is set.
How about thunderx/octeon?
Looks it should be like -mcpu=cortex-a72+crypto
I'll take care of this in a separate patch.
Because I want to add a new option to control it.
The reason is a binary having crypto support can't be run on a cpu w/o crypto extension, it is panicked.
And -mcpu=cortex-a72 includes 'crc' support by default.


Thanks,
Yongseok

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Jerin Jacob Kollanukkaran]

> -----Original Message-----
> From: Thomas Monjalon <thomas@monjalon.net>
> Sent: Friday, April 12, 2019 5:07 AM
> To: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>; Jerin Jacob
> Kollanukkaran <jerinj@marvell.com>
> Cc: dev@dpdk.org; jerinjacobk@gmail.com; yskoh@mellanox.com;
> bruce.richardson@intel.com
> Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine
> specific flags
> 
> 10/04/2019 18:13, jerinjacobk@gmail.com:
> > From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> >
> > Currently, RTE_* flags are set based on the implementer ID but there
> > might be some micro arch specific differences from the same vendor eg.
> > CACHE_LINESIZE. Add support to set micro arch specific flags.
> 
> I don't like how flags are set in config/arm/meson.build.
> It is a real mess to find which flag applies to which machine.
> Adding the flags_*_extra in the machine_args_* is adding more mess.
> 
> [...]
> >  flags_common_default = [
> >  	# Accelarate rte_memcpy. Be sure to run unit test
> (memcpy_perf_autotest)
> >  	# to determine the best threshold in code. Refer to notes in source
> > file @@ -52,12 +33,10 @@ flags_generic = [
> >  	['RTE_USE_C11_MEM_MODEL', true],
> >  	['RTE_CACHE_LINE_SIZE', 128]]
> >  flags_cavium = [
> > -	['RTE_MACHINE', '"thunderx"'],
> >  	['RTE_CACHE_LINE_SIZE', 128],
> >  	['RTE_MAX_NUMA_NODES', 2],
> >  	['RTE_MAX_LCORE', 96],
> > -	['RTE_MAX_VFIO_GROUPS', 128],
> > -	['RTE_USE_C11_MEM_MODEL', false]]
> > +	['RTE_MAX_VFIO_GROUPS', 128]]
> >  flags_dpaa = [
> >  	['RTE_MACHINE', '"dpaa"'],
> >  	['RTE_USE_C11_MEM_MODEL', true],
> > @@ -71,6 +50,27 @@ flags_dpaa2 = [
> >  	['RTE_MAX_NUMA_NODES', 1],
> >  	['RTE_MAX_LCORE', 16],
> >  	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
> > +flags_default_extra = []
> > +flags_thunderx_extra = [
> > +	['RTE_MACHINE', '"thunderx"'],
> > +	['RTE_USE_C11_MEM_MODEL', false]]
> > +
> > +machine_args_generic = [
> > +	['default', ['-march=armv8-a+crc+crypto']],
> > +	['native', ['-march=native']],
> > +	['0xd03', ['-mcpu=cortex-a53']],
> > +	['0xd04', ['-mcpu=cortex-a35']],
> > +	['0xd07', ['-mcpu=cortex-a57']],
> > +	['0xd08', ['-mcpu=cortex-a72']],
> > +	['0xd09', ['-mcpu=cortex-a73']],
> > +	['0xd0a', ['-mcpu=cortex-a75']]]
> > +
> > +machine_args_cavium = [
> > +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> > +	['native', ['-march=native']],
> > +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
> > +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
> > +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
> 
> I think we should have a simpler model.
> We need only to know the machine name and get all the related machine
> config.
> In native compilation, machine name is guessed from implementor id and pn
> (from config/arm/armv8_machine.py). We can directly output the machine
> name from this script and leave the naming logic in this script.
> In the cross-compilation config files (config/arm/*), we can just specify the
> machine name.
> Then every machine config (machine_args and dpdk_conf) would be
> specified in some arrays based on the machine name.
> Of course, we can keep some common default values.

Thomas,

This patch was around last three months. It reached upto v8.
I think, in that last minute for RC2, We cannot take major rework on this as it needs to tested for
Other arm64 platform too. It was pulled out from RC1 because other pcap issue from meson.
Now its not fair to say to rework the meson stuff now.
I suggest to take other rework in next release.


> 
> Thoughts?
> 

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Jerin Jacob Kollanukkaran]

> -----Original Message-----
> From: Thomas Monjalon <thomas@monjalon.net>
> Sent: Friday, April 12, 2019 5:07 AM
> To: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>; Jerin Jacob
> Kollanukkaran <jerinj@marvell.com>
> Cc: dev@dpdk.org; jerinjacobk@gmail.com; yskoh@mellanox.com;
> bruce.richardson@intel.com
> Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine
> specific flags
> 
> 10/04/2019 18:13, jerinjacobk@gmail.com:
> > From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> >
> > Currently, RTE_* flags are set based on the implementer ID but there
> > might be some micro arch specific differences from the same vendor eg.
> > CACHE_LINESIZE. Add support to set micro arch specific flags.
> 
> I don't like how flags are set in config/arm/meson.build.
> It is a real mess to find which flag applies to which machine.
> Adding the flags_*_extra in the machine_args_* is adding more mess.
> 
> [...]
> >  flags_common_default = [
> >  	# Accelarate rte_memcpy. Be sure to run unit test
> (memcpy_perf_autotest)
> >  	# to determine the best threshold in code. Refer to notes in source
> > file @@ -52,12 +33,10 @@ flags_generic = [
> >  	['RTE_USE_C11_MEM_MODEL', true],
> >  	['RTE_CACHE_LINE_SIZE', 128]]
> >  flags_cavium = [
> > -	['RTE_MACHINE', '"thunderx"'],
> >  	['RTE_CACHE_LINE_SIZE', 128],
> >  	['RTE_MAX_NUMA_NODES', 2],
> >  	['RTE_MAX_LCORE', 96],
> > -	['RTE_MAX_VFIO_GROUPS', 128],
> > -	['RTE_USE_C11_MEM_MODEL', false]]
> > +	['RTE_MAX_VFIO_GROUPS', 128]]
> >  flags_dpaa = [
> >  	['RTE_MACHINE', '"dpaa"'],
> >  	['RTE_USE_C11_MEM_MODEL', true],
> > @@ -71,6 +50,27 @@ flags_dpaa2 = [
> >  	['RTE_MAX_NUMA_NODES', 1],
> >  	['RTE_MAX_LCORE', 16],
> >  	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
> > +flags_default_extra = []
> > +flags_thunderx_extra = [
> > +	['RTE_MACHINE', '"thunderx"'],
> > +	['RTE_USE_C11_MEM_MODEL', false]]
> > +
> > +machine_args_generic = [
> > +	['default', ['-march=armv8-a+crc+crypto']],
> > +	['native', ['-march=native']],
> > +	['0xd03', ['-mcpu=cortex-a53']],
> > +	['0xd04', ['-mcpu=cortex-a35']],
> > +	['0xd07', ['-mcpu=cortex-a57']],
> > +	['0xd08', ['-mcpu=cortex-a72']],
> > +	['0xd09', ['-mcpu=cortex-a73']],
> > +	['0xd0a', ['-mcpu=cortex-a75']]]
> > +
> > +machine_args_cavium = [
> > +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> > +	['native', ['-march=native']],
> > +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
> > +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
> > +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
> 
> I think we should have a simpler model.
> We need only to know the machine name and get all the related machine
> config.
> In native compilation, machine name is guessed from implementor id and pn
> (from config/arm/armv8_machine.py). We can directly output the machine
> name from this script and leave the naming logic in this script.
> In the cross-compilation config files (config/arm/*), we can just specify the
> machine name.
> Then every machine config (machine_args and dpdk_conf) would be
> specified in some arrays based on the machine name.
> Of course, we can keep some common default values.

Thomas,

This patch was around last three months. It reached upto v8.
I think, in that last minute for RC2, We cannot take major rework on this as it needs to tested for
Other arm64 platform too. It was pulled out from RC1 because other pcap issue from meson.
Now its not fair to say to rework the meson stuff now.
I suggest to take other rework in next release.


> 
> Thoughts?
> 

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Yongseok Koh]

> On Apr 12, 2019, at 12:00 AM, Jerin Jacob Kollanukkaran <jerinj@marvell.com> wrote:
> 
>> -----Original Message-----
>> From: Yongseok Koh <yskoh@mellanox.com>
>> Sent: Friday, April 12, 2019 12:14 PM
>> To: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
>> Cc: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>; Thomas
>> Monjalon <thomas@monjalon.net>; dev <dev@dpdk.org>;
>> jerinjacobk@gmail.com
>> Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support
>> machine specific flags
>> 
>> 
>> Thanks, that fixes the issue.
>> But I've encountered another one. Are you aware of this?
> 
> Yes. It is a compiler bug. This patch set is NOT introducing this.
> 
> Fixed same on legacy build with arm64 . If you are using < 4.8.6 compiler
> For meson, this patched needs to be ported to meson

Okay, I've ported it. Will submit it soon.

Yongseok


> 
> $ git show f3af3e44a444cdfe3fa7b3e2c042be351401eb23
> commit f3af3e44a444cdfe3fa7b3e2c042be351401eb23
> Author: Jerin Jacob <jerin.jacob@caviumnetworks.com>
> Date:   Mon Sep 3 15:01:10 2018 +0530
> 
>    mk: disable OcteonTx for buggy compilers only on arm64
> 
>    Disable octeontx for gcc 4.8.5 as the compiler is emitting "internal
>    compiler error" for aarch64. The GCC "internal compiler error" was
>    observed only for arm64 architecture so disable the PMD only
>    for arm64.
> 
>    Fixes: 4f760550a093 ("mk: disable OcteonTx for buggy compilers")
>    Cc: stable@dpdk.org
> 
>    Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
>    Acked-by: Ferruh Yigit <ferruh.yigit@intel.com>
> 
>> 
>> ninja: Entering directory `build'
>> [1151/1452] Compiling C object
>> 'drivers/drivers@@tmp_r...d_octeontx_event@sta/event_octeontx_timvf_
>> worker.c.o'.
>> FAILED:
>> drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_ti
>> mvf_worker.c.o
>> cc -Idrivers/drivers@@tmp_rte_pmd_octeontx_event@sta -Idrivers -
>> I../drivers -Idrivers/event/octeontx -I../drivers/event/octeontx -
>> Ilib/librte_eventdev -I../lib/librte_eventdev -I. -I../ -Iconfig -I../config -
>> Ilib/librte_eal/common/include -I../lib/librte_eal/common/include -
>> I../lib/librte_eal/linux/eal/include -Ilib/librte_eal/common -
>> I../lib/librte_eal/common -Ilib/librte_eal/common/include/arch/arm -
>> I../lib/librte_eal/co mmon/include/arch/arm -Ilib/librte_eal -I../lib/librte_eal
>> -Ilib/librte_kvargs -I../lib/librte_kvargs -Ilib/librte_ring -I../lib/librte_ring -
>> Ilib/librte_ethdev -I../lib/librte_ethdev -Ilib/librte_net -I../lib/librte_net -
>> Ilib/librte_mbuf -I../lib/librte_mbuf -Ilib/librte_mempool -
>> I../lib/librte_mempool -Ilib/librte_cmdline -I../lib/librte_cmdline -
>> Ilib/librte_meter -I../lib/librte_meter -Ilib/librte_hash -I../lib/librte_h ash -
>> Ilib/librte_timer -I../lib/librte_timer -Ilib/librte_cryptodev -
>> I../lib/librte_cryptodev -Idrivers/common/octeontx -
>> I../drivers/common/octeontx -Idrivers/mempool/octeontx -
>> I../drivers/mempool/octeontx -Idrivers/bus/pci -I../drivers/bus/pci -
>> I../drivers/bus/pci/linux -Ilib/librte_pci -I../lib/librte_pci -Idrivers/bus/vdev -
>> I../drivers/bus/vdev -Idrivers/net/octeontx -I../drivers/net/octeontx -
>> Idrivers/net/octeontx/base  -I../drivers/net/octeontx/base -pipe -
>> D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -O3 -include rte_config.h -
>> Wsign-compare -Wcast-qual -fPIC -D_GNU_SOURCE -
>> DALLOW_EXPERIMENTAL_API  -MD -MQ
>> 'drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_ti
>> mvf_worker.c.o' -MF
>> 'drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_ti
>> mvf_worker.c.o.d' -o
>> 'drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_t
>> imvf_worker.c.o' -c ../drivers/event/octeontx/timvf_worker.c
>> ../drivers/event/octeontx/timvf_worker.c: In function
>> ‘timvf_timer_arm_burst_sp’:
>> ../drivers/event/octeontx/timvf_worker.c:88:1: error: could not split insn  }
>> ^ (insn 95 98 99 (parallel [
>>            (set (reg:DI 3 x3 [orig:98 D.8656 ] [98])
>>                (mem/v:DI (reg/f:DI 21 x21 [orig:88 D.8662 ] [88]) [-1  S8 A64]))
>>            (set (mem/v:DI (reg/f:DI 21 x21 [orig:88 D.8662 ] [88]) [-1  S8 A64])
>>                (unspec_volatile:DI [
>>                        (plus:DI (mem/v:DI (reg/f:DI 21 x21 [orig:88 D.8662 ] [88]) [-1  S8
>> A64])
>>                            (const_int -281474976710656 [0xffff000000000000]))
>>                        (const_int 0 [0])
>>                    ] UNSPECV_ATOMIC_OP))
>>            (clobber (reg:CC 66 cc))
>>            (clobber (reg:DI 0 x0))
>>            (clobber (reg:SI 1 x1))
>>        ]) ../drivers/event/octeontx/timvf_worker.h:95 1832
>> {atomic_fetch_adddi}
>>     (expr_list:REG_UNUSED (reg:CC 66 cc)
>>        (expr_list:REG_UNUSED (reg:SI 1 x1)
>>            (expr_list:REG_UNUSED (reg:DI 0 x0)
>>                (nil)))))
>> ../drivers/event/octeontx/timvf_worker.c:88:1: internal compiler error: in
>> final_scan_insn, at final.c:2897 Please submit a full bug report, with
>> preprocessed source if appropriate.
>> See <https://eur03.safelinks.protection.outlook.com/?url=http%3A%2F%2Fbugzilla.redhat.com%2Fbugzilla&amp;data=02%7C01%7Cyskoh%40mellanox.com%7C557fa46858104e15443508d6bf1494e9%7Ca652971c7d2e4d9ba6a4d149256f461b%7C0%7C0%7C636906492451079366&amp;sdata=EpdRkARHJDQCd6LRSe7gWjCghjIec%2Fx%2BJjbJiDNEYm4%3D&amp;reserved=0> for instructions.
>> {standard input}: Assembler messages:
>> {standard input}: Error: open CFI at the end of file; missing .cfi_endproc
>> directive Preprocessed source stored into /tmp/ccnQRbOm.out file, please
>> attach this to your bugreport.
>> [1168/1452] Compiling C object
>> 'drivers/drivers@@tmp_r...ntx_crypto@sta/crypto_octeontx_otx_cryptode
>> v_ops.c.o'.
>> ninja: build stopped: subcommand failed.
>> 
>> Thanks
>> Yongseok
> 

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Yongseok Koh]

> On Apr 12, 2019, at 12:00 AM, Jerin Jacob Kollanukkaran <jerinj@marvell.com> wrote:
> 
>> -----Original Message-----
>> From: Yongseok Koh <yskoh@mellanox.com>
>> Sent: Friday, April 12, 2019 12:14 PM
>> To: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
>> Cc: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>; Thomas
>> Monjalon <thomas@monjalon.net>; dev <dev@dpdk.org>;
>> jerinjacobk@gmail.com
>> Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support
>> machine specific flags
>> 
>> 
>> Thanks, that fixes the issue.
>> But I've encountered another one. Are you aware of this?
> 
> Yes. It is a compiler bug. This patch set is NOT introducing this.
> 
> Fixed same on legacy build with arm64 . If you are using < 4.8.6 compiler
> For meson, this patched needs to be ported to meson

Okay, I've ported it. Will submit it soon.

Yongseok


> 
> $ git show f3af3e44a444cdfe3fa7b3e2c042be351401eb23
> commit f3af3e44a444cdfe3fa7b3e2c042be351401eb23
> Author: Jerin Jacob <jerin.jacob@caviumnetworks.com>
> Date:   Mon Sep 3 15:01:10 2018 +0530
> 
>    mk: disable OcteonTx for buggy compilers only on arm64
> 
>    Disable octeontx for gcc 4.8.5 as the compiler is emitting "internal
>    compiler error" for aarch64. The GCC "internal compiler error" was
>    observed only for arm64 architecture so disable the PMD only
>    for arm64.
> 
>    Fixes: 4f760550a093 ("mk: disable OcteonTx for buggy compilers")
>    Cc: stable@dpdk.org
> 
>    Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
>    Acked-by: Ferruh Yigit <ferruh.yigit@intel.com>
> 
>> 
>> ninja: Entering directory `build'
>> [1151/1452] Compiling C object
>> 'drivers/drivers@@tmp_r...d_octeontx_event@sta/event_octeontx_timvf_
>> worker.c.o'.
>> FAILED:
>> drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_ti
>> mvf_worker.c.o
>> cc -Idrivers/drivers@@tmp_rte_pmd_octeontx_event@sta -Idrivers -
>> I../drivers -Idrivers/event/octeontx -I../drivers/event/octeontx -
>> Ilib/librte_eventdev -I../lib/librte_eventdev -I. -I../ -Iconfig -I../config -
>> Ilib/librte_eal/common/include -I../lib/librte_eal/common/include -
>> I../lib/librte_eal/linux/eal/include -Ilib/librte_eal/common -
>> I../lib/librte_eal/common -Ilib/librte_eal/common/include/arch/arm -
>> I../lib/librte_eal/co mmon/include/arch/arm -Ilib/librte_eal -I../lib/librte_eal
>> -Ilib/librte_kvargs -I../lib/librte_kvargs -Ilib/librte_ring -I../lib/librte_ring -
>> Ilib/librte_ethdev -I../lib/librte_ethdev -Ilib/librte_net -I../lib/librte_net -
>> Ilib/librte_mbuf -I../lib/librte_mbuf -Ilib/librte_mempool -
>> I../lib/librte_mempool -Ilib/librte_cmdline -I../lib/librte_cmdline -
>> Ilib/librte_meter -I../lib/librte_meter -Ilib/librte_hash -I../lib/librte_h ash -
>> Ilib/librte_timer -I../lib/librte_timer -Ilib/librte_cryptodev -
>> I../lib/librte_cryptodev -Idrivers/common/octeontx -
>> I../drivers/common/octeontx -Idrivers/mempool/octeontx -
>> I../drivers/mempool/octeontx -Idrivers/bus/pci -I../drivers/bus/pci -
>> I../drivers/bus/pci/linux -Ilib/librte_pci -I../lib/librte_pci -Idrivers/bus/vdev -
>> I../drivers/bus/vdev -Idrivers/net/octeontx -I../drivers/net/octeontx -
>> Idrivers/net/octeontx/base  -I../drivers/net/octeontx/base -pipe -
>> D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -O3 -include rte_config.h -
>> Wsign-compare -Wcast-qual -fPIC -D_GNU_SOURCE -
>> DALLOW_EXPERIMENTAL_API  -MD -MQ
>> 'drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_ti
>> mvf_worker.c.o' -MF
>> 'drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_ti
>> mvf_worker.c.o.d' -o
>> 'drivers/drivers@@tmp_rte_pmd_octeontx_event@sta/event_octeontx_t
>> imvf_worker.c.o' -c ../drivers/event/octeontx/timvf_worker.c
>> ../drivers/event/octeontx/timvf_worker.c: In function
>> ‘timvf_timer_arm_burst_sp’:
>> ../drivers/event/octeontx/timvf_worker.c:88:1: error: could not split insn  }
>> ^ (insn 95 98 99 (parallel [
>>            (set (reg:DI 3 x3 [orig:98 D.8656 ] [98])
>>                (mem/v:DI (reg/f:DI 21 x21 [orig:88 D.8662 ] [88]) [-1  S8 A64]))
>>            (set (mem/v:DI (reg/f:DI 21 x21 [orig:88 D.8662 ] [88]) [-1  S8 A64])
>>                (unspec_volatile:DI [
>>                        (plus:DI (mem/v:DI (reg/f:DI 21 x21 [orig:88 D.8662 ] [88]) [-1  S8
>> A64])
>>                            (const_int -281474976710656 [0xffff000000000000]))
>>                        (const_int 0 [0])
>>                    ] UNSPECV_ATOMIC_OP))
>>            (clobber (reg:CC 66 cc))
>>            (clobber (reg:DI 0 x0))
>>            (clobber (reg:SI 1 x1))
>>        ]) ../drivers/event/octeontx/timvf_worker.h:95 1832
>> {atomic_fetch_adddi}
>>     (expr_list:REG_UNUSED (reg:CC 66 cc)
>>        (expr_list:REG_UNUSED (reg:SI 1 x1)
>>            (expr_list:REG_UNUSED (reg:DI 0 x0)
>>                (nil)))))
>> ../drivers/event/octeontx/timvf_worker.c:88:1: internal compiler error: in
>> final_scan_insn, at final.c:2897 Please submit a full bug report, with
>> preprocessed source if appropriate.
>> See <https://eur03.safelinks.protection.outlook.com/?url=http%3A%2F%2Fbugzilla.redhat.com%2Fbugzilla&amp;data=02%7C01%7Cyskoh%40mellanox.com%7C557fa46858104e15443508d6bf1494e9%7Ca652971c7d2e4d9ba6a4d149256f461b%7C0%7C0%7C636906492451079366&amp;sdata=EpdRkARHJDQCd6LRSe7gWjCghjIec%2Fx%2BJjbJiDNEYm4%3D&amp;reserved=0> for instructions.
>> {standard input}: Assembler messages:
>> {standard input}: Error: open CFI at the end of file; missing .cfi_endproc
>> directive Preprocessed source stored into /tmp/ccnQRbOm.out file, please
>> attach this to your bugreport.
>> [1168/1452] Compiling C object
>> 'drivers/drivers@@tmp_r...ntx_crypto@sta/crypto_octeontx_otx_cryptode
>> v_ops.c.o'.
>> ninja: build stopped: subcommand failed.
>> 
>> Thanks
>> Yongseok
> 

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Jerin Jacob Kollanukkaran]

> -----Original Message-----
> From: Yongseok Koh <yskoh@mellanox.com>
> Sent: Friday, April 12, 2019 12:39 PM
> To: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
> Cc: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>; Thomas
> Monjalon <thomas@monjalon.net>; dev <dev@dpdk.org>;
> jerinjacobk@gmail.com
> Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support
> machine specific flags
> 
> 
> 
> One more issue.
> With gcc7.2, crypto isn't enabled if -mcpu is set.
> How about thunderx/octeon?

It is enabled when when mcpu=thunderxt88 is provided.
In default case, it picks up -march=armv8-a+crc+crypto if mpcu is not matching. 
So I don’t see any issue.

> Looks it should be like -mcpu=cortex-a72+crypto I'll take care of this in a

mcpu should be enough. Looks like like it a compiler bug, Is cortex-a72 available with out crypto?
mcpu suppose to tune for specific cpu.


> separate patch.
> Because I want to add a new option to control it.
> The reason is a binary having crypto support can't be run on a cpu w/o crypto
> extension, it is panicked.
> And -mcpu=cortex-a72 includes 'crc' support by default.

I suggest to add config/arm/arm64_a72_linux_gcc, If we need to catch all this issue in
cross compilation otherwise it will come only on native compilation on that specific board.
Now the devtools/test-meson-builds.sh goes over all the config/arm/* on the native compilation 
On arm64 board and x86. If you need set compiler test for a72 then please add the cross compile config.


> 
> 
> Thanks,
> Yongseok
> 

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Jerin Jacob Kollanukkaran]

> -----Original Message-----
> From: Yongseok Koh <yskoh@mellanox.com>
> Sent: Friday, April 12, 2019 12:39 PM
> To: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
> Cc: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>; Thomas
> Monjalon <thomas@monjalon.net>; dev <dev@dpdk.org>;
> jerinjacobk@gmail.com
> Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support
> machine specific flags
> 
> 
> 
> One more issue.
> With gcc7.2, crypto isn't enabled if -mcpu is set.
> How about thunderx/octeon?

It is enabled when when mcpu=thunderxt88 is provided.
In default case, it picks up -march=armv8-a+crc+crypto if mpcu is not matching. 
So I don’t see any issue.

> Looks it should be like -mcpu=cortex-a72+crypto I'll take care of this in a

mcpu should be enough. Looks like like it a compiler bug, Is cortex-a72 available with out crypto?
mcpu suppose to tune for specific cpu.


> separate patch.
> Because I want to add a new option to control it.
> The reason is a binary having crypto support can't be run on a cpu w/o crypto
> extension, it is panicked.
> And -mcpu=cortex-a72 includes 'crc' support by default.

I suggest to add config/arm/arm64_a72_linux_gcc, If we need to catch all this issue in
cross compilation otherwise it will come only on native compilation on that specific board.
Now the devtools/test-meson-builds.sh goes over all the config/arm/* on the native compilation 
On arm64 board and x86. If you need set compiler test for a72 then please add the cross compile config.


> 
> 
> Thanks,
> Yongseok
> 

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Yongseok Koh]

> On Apr 12, 2019, at 12:35 AM, Jerin Jacob Kollanukkaran <jerinj@marvell.com> wrote:
> 
> 
> 
>> -----Original Message-----
>> From: Yongseok Koh <yskoh@mellanox.com>
>> Sent: Friday, April 12, 2019 12:39 PM
>> To: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
>> Cc: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>; Thomas
>> Monjalon <thomas@monjalon.net>; dev <dev@dpdk.org>;
>> jerinjacobk@gmail.com
>> Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support
>> machine specific flags
>> 
>> 
>> 
>> One more issue.
>> With gcc7.2, crypto isn't enabled if -mcpu is set.
>> How about thunderx/octeon?
> 
> It is enabled when when mcpu=thunderxt88 is provided.
> In default case, it picks up -march=armv8-a+crc+crypto if mpcu is not matching. 
> So I don’t see any issue.
> 
>> Looks it should be like -mcpu=cortex-a72+crypto I'll take care of this in a
> 
> mcpu should be enough. Looks like like it a compiler bug, Is cortex-a72 available with out crypto?
> mcpu suppose to tune for specific cpu.

Yes, Mellanox BlueField is designed based on a72 and there are two variants in production.
One with crypto, the other w/o crypto. That might be the reason why -mcpu=cortex-a72
doesn't enable crypto by default.

>> separate patch.
>> Because I want to add a new option to control it.
>> The reason is a binary having crypto support can't be run on a cpu w/o crypto
>> extension, it is panicked.
>> And -mcpu=cortex-a72 includes 'crc' support by default.
> 
> I suggest to add config/arm/arm64_a72_linux_gcc, If we need to catch all this issue in
> cross compilation otherwise it will come only on native compilation on that specific board.
> Now the devtools/test-meson-builds.sh goes over all the config/arm/* on the native compilation 
> On arm64 board and x86. If you need set compiler test for a72 then please add the cross compile config.

Yes, I'm going to add config/arm/arm64_bluefield_linux_gcc soon. Patch is ready now.

Thanks,
Yongseok

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Yongseok Koh]

> On Apr 12, 2019, at 12:35 AM, Jerin Jacob Kollanukkaran <jerinj@marvell.com> wrote:
> 
> 
> 
>> -----Original Message-----
>> From: Yongseok Koh <yskoh@mellanox.com>
>> Sent: Friday, April 12, 2019 12:39 PM
>> To: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
>> Cc: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>; Thomas
>> Monjalon <thomas@monjalon.net>; dev <dev@dpdk.org>;
>> jerinjacobk@gmail.com
>> Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support
>> machine specific flags
>> 
>> 
>> 
>> One more issue.
>> With gcc7.2, crypto isn't enabled if -mcpu is set.
>> How about thunderx/octeon?
> 
> It is enabled when when mcpu=thunderxt88 is provided.
> In default case, it picks up -march=armv8-a+crc+crypto if mpcu is not matching. 
> So I don’t see any issue.
> 
>> Looks it should be like -mcpu=cortex-a72+crypto I'll take care of this in a
> 
> mcpu should be enough. Looks like like it a compiler bug, Is cortex-a72 available with out crypto?
> mcpu suppose to tune for specific cpu.

Yes, Mellanox BlueField is designed based on a72 and there are two variants in production.
One with crypto, the other w/o crypto. That might be the reason why -mcpu=cortex-a72
doesn't enable crypto by default.

>> separate patch.
>> Because I want to add a new option to control it.
>> The reason is a binary having crypto support can't be run on a cpu w/o crypto
>> extension, it is panicked.
>> And -mcpu=cortex-a72 includes 'crc' support by default.
> 
> I suggest to add config/arm/arm64_a72_linux_gcc, If we need to catch all this issue in
> cross compilation otherwise it will come only on native compilation on that specific board.
> Now the devtools/test-meson-builds.sh goes over all the config/arm/* on the native compilation 
> On arm64 board and x86. If you need set compiler test for a72 then please add the cross compile config.

Yes, I'm going to add config/arm/arm64_bluefield_linux_gcc soon. Patch is ready now.

Thanks,
Yongseok

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Thomas Monjalon]

12/04/2019 09:12, Jerin Jacob Kollanukkaran:
> From: Thomas Monjalon <thomas@monjalon.net>
> > 10/04/2019 18:13, jerinjacobk@gmail.com:
> > > From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > >
> > > Currently, RTE_* flags are set based on the implementer ID but there
> > > might be some micro arch specific differences from the same vendor eg.
> > > CACHE_LINESIZE. Add support to set micro arch specific flags.
> > 
> > I don't like how flags are set in config/arm/meson.build.
> > It is a real mess to find which flag applies to which machine.
> > Adding the flags_*_extra in the machine_args_* is adding more mess.
> > 
> > [...]
> > >  flags_common_default = [
> > >  	# Accelarate rte_memcpy. Be sure to run unit test
> > (memcpy_perf_autotest)
> > >  	# to determine the best threshold in code. Refer to notes in source
> > > file @@ -52,12 +33,10 @@ flags_generic = [
> > >  	['RTE_USE_C11_MEM_MODEL', true],
> > >  	['RTE_CACHE_LINE_SIZE', 128]]
> > >  flags_cavium = [
> > > -	['RTE_MACHINE', '"thunderx"'],
> > >  	['RTE_CACHE_LINE_SIZE', 128],
> > >  	['RTE_MAX_NUMA_NODES', 2],
> > >  	['RTE_MAX_LCORE', 96],
> > > -	['RTE_MAX_VFIO_GROUPS', 128],
> > > -	['RTE_USE_C11_MEM_MODEL', false]]
> > > +	['RTE_MAX_VFIO_GROUPS', 128]]
> > >  flags_dpaa = [
> > >  	['RTE_MACHINE', '"dpaa"'],
> > >  	['RTE_USE_C11_MEM_MODEL', true],
> > > @@ -71,6 +50,27 @@ flags_dpaa2 = [
> > >  	['RTE_MAX_NUMA_NODES', 1],
> > >  	['RTE_MAX_LCORE', 16],
> > >  	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
> > > +flags_default_extra = []
> > > +flags_thunderx_extra = [
> > > +	['RTE_MACHINE', '"thunderx"'],
> > > +	['RTE_USE_C11_MEM_MODEL', false]]
> > > +
> > > +machine_args_generic = [
> > > +	['default', ['-march=armv8-a+crc+crypto']],
> > > +	['native', ['-march=native']],
> > > +	['0xd03', ['-mcpu=cortex-a53']],
> > > +	['0xd04', ['-mcpu=cortex-a35']],
> > > +	['0xd07', ['-mcpu=cortex-a57']],
> > > +	['0xd08', ['-mcpu=cortex-a72']],
> > > +	['0xd09', ['-mcpu=cortex-a73']],
> > > +	['0xd0a', ['-mcpu=cortex-a75']]]
> > > +
> > > +machine_args_cavium = [
> > > +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> > > +	['native', ['-march=native']],
> > > +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
> > > +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
> > > +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
> > 
> > I think we should have a simpler model.
> > We need only to know the machine name and get all the related machine
> > config.
> > In native compilation, machine name is guessed from implementor id and pn
> > (from config/arm/armv8_machine.py). We can directly output the machine
> > name from this script and leave the naming logic in this script.
> > In the cross-compilation config files (config/arm/*), we can just specify the
> > machine name.
> > Then every machine config (machine_args and dpdk_conf) would be
> > specified in some arrays based on the machine name.
> > Of course, we can keep some common default values.
> 
> Thomas,
> 
> This patch was around last three months. It reached upto v8.
> I think, in that last minute for RC2, We cannot take major rework on this as it needs to tested for
> Other arm64 platform too. It was pulled out from RC1 because other pcap issue from meson.
> Now its not fair to say to rework the meson stuff now.
> I suggest to take other rework in next release.

I was not confortable with this patch without being able to say why.
Yesterday I spent more time to understand and see what may be improved.
I agree it is late, so it won't block this patch for 19.05.
Do you agree this file can be improved?
Please would you like to look at reworking during next cycle?
Thanks

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Thomas Monjalon]

12/04/2019 09:12, Jerin Jacob Kollanukkaran:
> From: Thomas Monjalon <thomas@monjalon.net>
> > 10/04/2019 18:13, jerinjacobk@gmail.com:
> > > From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > >
> > > Currently, RTE_* flags are set based on the implementer ID but there
> > > might be some micro arch specific differences from the same vendor eg.
> > > CACHE_LINESIZE. Add support to set micro arch specific flags.
> > 
> > I don't like how flags are set in config/arm/meson.build.
> > It is a real mess to find which flag applies to which machine.
> > Adding the flags_*_extra in the machine_args_* is adding more mess.
> > 
> > [...]
> > >  flags_common_default = [
> > >  	# Accelarate rte_memcpy. Be sure to run unit test
> > (memcpy_perf_autotest)
> > >  	# to determine the best threshold in code. Refer to notes in source
> > > file @@ -52,12 +33,10 @@ flags_generic = [
> > >  	['RTE_USE_C11_MEM_MODEL', true],
> > >  	['RTE_CACHE_LINE_SIZE', 128]]
> > >  flags_cavium = [
> > > -	['RTE_MACHINE', '"thunderx"'],
> > >  	['RTE_CACHE_LINE_SIZE', 128],
> > >  	['RTE_MAX_NUMA_NODES', 2],
> > >  	['RTE_MAX_LCORE', 96],
> > > -	['RTE_MAX_VFIO_GROUPS', 128],
> > > -	['RTE_USE_C11_MEM_MODEL', false]]
> > > +	['RTE_MAX_VFIO_GROUPS', 128]]
> > >  flags_dpaa = [
> > >  	['RTE_MACHINE', '"dpaa"'],
> > >  	['RTE_USE_C11_MEM_MODEL', true],
> > > @@ -71,6 +50,27 @@ flags_dpaa2 = [
> > >  	['RTE_MAX_NUMA_NODES', 1],
> > >  	['RTE_MAX_LCORE', 16],
> > >  	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
> > > +flags_default_extra = []
> > > +flags_thunderx_extra = [
> > > +	['RTE_MACHINE', '"thunderx"'],
> > > +	['RTE_USE_C11_MEM_MODEL', false]]
> > > +
> > > +machine_args_generic = [
> > > +	['default', ['-march=armv8-a+crc+crypto']],
> > > +	['native', ['-march=native']],
> > > +	['0xd03', ['-mcpu=cortex-a53']],
> > > +	['0xd04', ['-mcpu=cortex-a35']],
> > > +	['0xd07', ['-mcpu=cortex-a57']],
> > > +	['0xd08', ['-mcpu=cortex-a72']],
> > > +	['0xd09', ['-mcpu=cortex-a73']],
> > > +	['0xd0a', ['-mcpu=cortex-a75']]]
> > > +
> > > +machine_args_cavium = [
> > > +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> > > +	['native', ['-march=native']],
> > > +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
> > > +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
> > > +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
> > 
> > I think we should have a simpler model.
> > We need only to know the machine name and get all the related machine
> > config.
> > In native compilation, machine name is guessed from implementor id and pn
> > (from config/arm/armv8_machine.py). We can directly output the machine
> > name from this script and leave the naming logic in this script.
> > In the cross-compilation config files (config/arm/*), we can just specify the
> > machine name.
> > Then every machine config (machine_args and dpdk_conf) would be
> > specified in some arrays based on the machine name.
> > Of course, we can keep some common default values.
> 
> Thomas,
> 
> This patch was around last three months. It reached upto v8.
> I think, in that last minute for RC2, We cannot take major rework on this as it needs to tested for
> Other arm64 platform too. It was pulled out from RC1 because other pcap issue from meson.
> Now its not fair to say to rework the meson stuff now.
> I suggest to take other rework in next release.

I was not confortable with this patch without being able to say why.
Yesterday I spent more time to understand and see what may be improved.
I agree it is late, so it won't block this patch for 19.05.
Do you agree this file can be improved?
Please would you like to look at reworking during next cycle?
Thanks

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Jerin Jacob Kollanukkaran]

> > > > +machine_args_cavium = [
> > > > +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> > > > +	['native', ['-march=native']],
> > > > +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
> > > > +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
> > > > +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
> > >
> > > I think we should have a simpler model.
> > > We need only to know the machine name and get all the related
> > > machine config.
> > > In native compilation, machine name is guessed from implementor id
> > > and pn (from config/arm/armv8_machine.py). We can directly output
> > > the machine name from this script and leave the naming logic in this script.
> > > In the cross-compilation config files (config/arm/*), we can just
> > > specify the machine name.
> > > Then every machine config (machine_args and dpdk_conf) would be
> > > specified in some arrays based on the machine name.
> > > Of course, we can keep some common default values.
> >
> > Thomas,
> >
> > This patch was around last three months. It reached upto v8.
> > I think, in that last minute for RC2, We cannot take major rework on
> > this as it needs to tested for Other arm64 platform too. It was pulled out from
> RC1 because other pcap issue from meson.
> > Now its not fair to say to rework the meson stuff now.
> > I suggest to take other rework in next release.
> 
> I was not confortable with this patch without being able to say why.
> Yesterday I spent more time to understand and see what may be improved.
> I agree it is late, so it won't block this patch for 19.05.
> Do you agree this file can be improved?

Moving to  the all to static config file is an option but we lose the flexibility
of runtime detecting the options and few of them are probing at runtime based
on gcc versions and mcpu combination etc.
I am not expert in meson area and not sure meson/python has better data strcture for this other than
list/array combo. If Bruce has any feedback on this, then we
will try to prototype it.






> Please would you like to look at reworking during next cycle?
> Thanks
> 

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Jerin Jacob Kollanukkaran]

> > > > +machine_args_cavium = [
> > > > +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> > > > +	['native', ['-march=native']],
> > > > +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
> > > > +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
> > > > +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
> > >
> > > I think we should have a simpler model.
> > > We need only to know the machine name and get all the related
> > > machine config.
> > > In native compilation, machine name is guessed from implementor id
> > > and pn (from config/arm/armv8_machine.py). We can directly output
> > > the machine name from this script and leave the naming logic in this script.
> > > In the cross-compilation config files (config/arm/*), we can just
> > > specify the machine name.
> > > Then every machine config (machine_args and dpdk_conf) would be
> > > specified in some arrays based on the machine name.
> > > Of course, we can keep some common default values.
> >
> > Thomas,
> >
> > This patch was around last three months. It reached upto v8.
> > I think, in that last minute for RC2, We cannot take major rework on
> > this as it needs to tested for Other arm64 platform too. It was pulled out from
> RC1 because other pcap issue from meson.
> > Now its not fair to say to rework the meson stuff now.
> > I suggest to take other rework in next release.
> 
> I was not confortable with this patch without being able to say why.
> Yesterday I spent more time to understand and see what may be improved.
> I agree it is late, so it won't block this patch for 19.05.
> Do you agree this file can be improved?

Moving to  the all to static config file is an option but we lose the flexibility
of runtime detecting the options and few of them are probing at runtime based
on gcc versions and mcpu combination etc.
I am not expert in meson area and not sure meson/python has better data strcture for this other than
list/array combo. If Bruce has any feedback on this, then we
will try to prototype it.






> Please would you like to look at reworking during next cycle?
> Thanks
> 

[dpdk-dev] [PATCH v9 1/4] mk: introduce helper to check valid compiler argument

[jerinj]

From: Jerin Jacob <jerinj@marvell.com>

Introduce rte_cc_has_argument() Makefile helper to
check a given argument is support by the compiler.

Example Usage:

include $(RTE_SDK)/mk/rte.helper.mk
MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)

This would allow adding -mcpu=octeontx2 in MACHINE_CFLAGS
if it is only supported by the compiler. The use case for such
scheme is to enable the mcpu optimization if the compiler
supports else it needs to compile the source code without
any errors.

This patch also moves inclusion of toolchain's rte.vars.mk
to before the machine's rte.vars.mk inclusion to make
correct CC available for the cross compile case.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
Change history of this series:

v9 Changes:
 - Remove compiler version check as it is now done using
   cc.has_argument().

v8 Changes:
 - Remove redudant lists (rebase aritfacts). (Yongseok Koh)
 
v7 Changes:
 - Updated cross compile config files align with 
 "build: improve pcap dependency handling" changeset to fix build issue with meson
 - Some compiler needs the following depended patch to compile with meson
   http://patches.dpdk.org/patch/52367/

v6 Changes:
 - Rework to change the config files to sync with "mk: use linux and freebsd in config names"
 - Fix the following error with latest gcc by fixing the mcpu type
   cc1: error: switch -mcpu=armv8.2-a conflicts with -march=armv8-a switch 

v5 Changes:
 - Fix incorrect meson flag parsing(Phil Yang)
 - Squash meson cross build patch(5/5) into configuration update patches for
 thunderx2(3/5) and octeontx2(4/5)(Thomas)
 - Changed octeontx2's march as armv8-a and added the extension required
   instead of armv8-2a(Phil Yang)
 - Improved rte_cc_has_argument() implementaion by removing the temp
   file(Thomas)

v4 Changes:
 - Fix incorrect signoff marrvell -> marvell.

v3 Changes:
 - Squash meson build support into config support for thunderx2/octeontx2.

v2 Changes:
 - Add meson build support.

 mk/rte.helper.mk              | 10 ++++++++++
 mk/target/generic/rte.vars.mk | 22 +++++++++++-----------
 2 files changed, 21 insertions(+), 11 deletions(-)
 create mode 100644 mk/rte.helper.mk

diff --git a/mk/rte.helper.mk b/mk/rte.helper.mk
new file mode 100644
index 000000000..6e7fd03d7
--- /dev/null
+++ b/mk/rte.helper.mk
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+
+# rte_cc_has_argument
+# Usage: MACHINE_CFLAGS += $(call rte_cc_has_argument, -mno-avx512f)
+# Return the argument if the argument is supported by the compiler.
+#
+define rte_cc_has_argument
+	$(shell $(CC) -E $(1) -xc /dev/null 1>/dev/null 2>/dev/null && echo $(1))
+endef
diff --git a/mk/target/generic/rte.vars.mk b/mk/target/generic/rte.vars.mk
index dd149acc9..25a578ad7 100644
--- a/mk/target/generic/rte.vars.mk
+++ b/mk/target/generic/rte.vars.mk
@@ -7,6 +7,17 @@
 # executive environment.
 #
 
+#
+# toolchain:
+#
+#   - define CC, LD, AR, AS, ...
+#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
+#   - may override any previously defined variable
+#
+include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
+
 #
 # machine:
 #
@@ -45,17 +56,6 @@ endif
 #
 include $(RTE_SDK)/mk/arch/$(RTE_ARCH)/rte.vars.mk
 
-#
-# toolchain:
-#
-#   - define CC, LD, AR, AS, ...
-#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
-#   - may override any previously defined variable
-#
-include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
-
 #
 # exec-env:
 #
-- 
2.21.0

[dpdk-dev] [PATCH v9 1/4] mk: introduce helper to check valid compiler argument

[jerinj]

From: Jerin Jacob <jerinj@marvell.com>

Introduce rte_cc_has_argument() Makefile helper to
check a given argument is support by the compiler.

Example Usage:

include $(RTE_SDK)/mk/rte.helper.mk
MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)

This would allow adding -mcpu=octeontx2 in MACHINE_CFLAGS
if it is only supported by the compiler. The use case for such
scheme is to enable the mcpu optimization if the compiler
supports else it needs to compile the source code without
any errors.

This patch also moves inclusion of toolchain's rte.vars.mk
to before the machine's rte.vars.mk inclusion to make
correct CC available for the cross compile case.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
Change history of this series:

v9 Changes:
 - Remove compiler version check as it is now done using
   cc.has_argument().

v8 Changes:
 - Remove redudant lists (rebase aritfacts). (Yongseok Koh)
 
v7 Changes:
 - Updated cross compile config files align with 
 "build: improve pcap dependency handling" changeset to fix build issue with meson
 - Some compiler needs the following depended patch to compile with meson
   http://patches.dpdk.org/patch/52367/

v6 Changes:
 - Rework to change the config files to sync with "mk: use linux and freebsd in config names"
 - Fix the following error with latest gcc by fixing the mcpu type
   cc1: error: switch -mcpu=armv8.2-a conflicts with -march=armv8-a switch 

v5 Changes:
 - Fix incorrect meson flag parsing(Phil Yang)
 - Squash meson cross build patch(5/5) into configuration update patches for
 thunderx2(3/5) and octeontx2(4/5)(Thomas)
 - Changed octeontx2's march as armv8-a and added the extension required
   instead of armv8-2a(Phil Yang)
 - Improved rte_cc_has_argument() implementaion by removing the temp
   file(Thomas)

v4 Changes:
 - Fix incorrect signoff marrvell -> marvell.

v3 Changes:
 - Squash meson build support into config support for thunderx2/octeontx2.

v2 Changes:
 - Add meson build support.

 mk/rte.helper.mk              | 10 ++++++++++
 mk/target/generic/rte.vars.mk | 22 +++++++++++-----------
 2 files changed, 21 insertions(+), 11 deletions(-)
 create mode 100644 mk/rte.helper.mk

diff --git a/mk/rte.helper.mk b/mk/rte.helper.mk
new file mode 100644
index 000000000..6e7fd03d7
--- /dev/null
+++ b/mk/rte.helper.mk
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+
+# rte_cc_has_argument
+# Usage: MACHINE_CFLAGS += $(call rte_cc_has_argument, -mno-avx512f)
+# Return the argument if the argument is supported by the compiler.
+#
+define rte_cc_has_argument
+	$(shell $(CC) -E $(1) -xc /dev/null 1>/dev/null 2>/dev/null && echo $(1))
+endef
diff --git a/mk/target/generic/rte.vars.mk b/mk/target/generic/rte.vars.mk
index dd149acc9..25a578ad7 100644
--- a/mk/target/generic/rte.vars.mk
+++ b/mk/target/generic/rte.vars.mk
@@ -7,6 +7,17 @@
 # executive environment.
 #
 
+#
+# toolchain:
+#
+#   - define CC, LD, AR, AS, ...
+#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
+#   - may override any previously defined variable
+#
+include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
+
 #
 # machine:
 #
@@ -45,17 +56,6 @@ endif
 #
 include $(RTE_SDK)/mk/arch/$(RTE_ARCH)/rte.vars.mk
 
-#
-# toolchain:
-#
-#   - define CC, LD, AR, AS, ...
-#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
-#   - may override any previously defined variable
-#
-include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
-
 #
 # exec-env:
 #
-- 
2.21.0

[dpdk-dev] [PATCH v9 2/4] meson: add infra to support machine specific flags

[jerinj]

From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Currently, RTE_* flags are set based on the implementer ID but there might
be some micro arch specific differences from the same vendor
eg. CACHE_LINESIZE. Add support to set micro arch specific flags.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
---
 config/arm/meson.build | 67 +++++++++++++++++++++---------------------
 1 file changed, 33 insertions(+), 34 deletions(-)

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 170a4981a..d30a17426 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -7,25 +7,6 @@ march_opt = '-march=@0@'.format(machine)
 
 arm_force_native_march = false
 
-machine_args_generic = [
-	['default', ['-march=armv8-a+crc+crypto']],
-	['native', ['-march=native']],
-	['0xd03', ['-mcpu=cortex-a53']],
-	['0xd04', ['-mcpu=cortex-a35']],
-	['0xd05', ['-mcpu=cortex-a55']],
-	['0xd07', ['-mcpu=cortex-a57']],
-	['0xd08', ['-mcpu=cortex-a72']],
-	['0xd09', ['-mcpu=cortex-a73']],
-	['0xd0a', ['-mcpu=cortex-a75']],
-	['0xd0b', ['-mcpu=cortex-a76']],
-]
-machine_args_cavium = [
-	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
-	['native', ['-march=native']],
-	['0xa1', ['-mcpu=thunderxt88']],
-	['0xa2', ['-mcpu=thunderxt81']],
-	['0xa3', ['-mcpu=thunderxt83']]]
-
 flags_common_default = [
 	# Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
 	# to determine the best threshold in code. Refer to notes in source file
@@ -52,12 +33,10 @@ flags_generic = [
 	['RTE_USE_C11_MEM_MODEL', true],
 	['RTE_CACHE_LINE_SIZE', 128]]
 flags_cavium = [
-	['RTE_MACHINE', '"thunderx"'],
 	['RTE_CACHE_LINE_SIZE', 128],
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 96],
-	['RTE_MAX_VFIO_GROUPS', 128],
-	['RTE_USE_C11_MEM_MODEL', false]]
+	['RTE_MAX_VFIO_GROUPS', 128]]
 flags_dpaa = [
 	['RTE_MACHINE', '"dpaa"'],
 	['RTE_USE_C11_MEM_MODEL', true],
@@ -71,6 +50,27 @@ flags_dpaa2 = [
 	['RTE_MAX_NUMA_NODES', 1],
 	['RTE_MAX_LCORE', 16],
 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
+flags_default_extra = []
+flags_thunderx_extra = [
+	['RTE_MACHINE', '"thunderx"'],
+	['RTE_USE_C11_MEM_MODEL', false]]
+
+machine_args_generic = [
+	['default', ['-march=armv8-a+crc+crypto']],
+	['native', ['-march=native']],
+	['0xd03', ['-mcpu=cortex-a53']],
+	['0xd04', ['-mcpu=cortex-a35']],
+	['0xd07', ['-mcpu=cortex-a57']],
+	['0xd08', ['-mcpu=cortex-a72']],
+	['0xd09', ['-mcpu=cortex-a73']],
+	['0xd0a', ['-mcpu=cortex-a75']]]
+
+machine_args_cavium = [
+	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
+	['native', ['-march=native']],
+	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
+	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
@@ -145,20 +145,19 @@ else
 			dpdk_conf.set(flag[0], flag[1])
 		endif
 	endforeach
-	# Primary part number based mcpu flags are supported
-	# for gcc versions > 7
-	if cc.version().version_compare(
-			'<7.0') or cmd_output.length() == 0
-		if not meson.is_cross_build() and arm_force_native_march == true
-			impl_pn = 'native'
-		else
-			impl_pn = 'default'
-		endif
-	endif
+	
 	foreach marg: machine[2]
 		if marg[0] == impl_pn
-			foreach f: marg[1]
-				machine_args += f
+			foreach flag: marg[1]
+				if cc.has_argument(flag)
+					machine_args += flag
+				endif
+			endforeach
+			# Apply any extra machine specific flags.
+			foreach flag: marg.get(2, flags_default_extra)
+				if flag.length() > 0
+					dpdk_conf.set(flag[0], flag[1])
+				endif
 			endforeach
 		endif
 	endforeach
-- 
2.21.0

[dpdk-dev] [PATCH v9 2/4] meson: add infra to support machine specific flags

[jerinj]

From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Currently, RTE_* flags are set based on the implementer ID but there might
be some micro arch specific differences from the same vendor
eg. CACHE_LINESIZE. Add support to set micro arch specific flags.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
---
 config/arm/meson.build | 67 +++++++++++++++++++++---------------------
 1 file changed, 33 insertions(+), 34 deletions(-)

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 170a4981a..d30a17426 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -7,25 +7,6 @@ march_opt = '-march=@0@'.format(machine)
 
 arm_force_native_march = false
 
-machine_args_generic = [
-	['default', ['-march=armv8-a+crc+crypto']],
-	['native', ['-march=native']],
-	['0xd03', ['-mcpu=cortex-a53']],
-	['0xd04', ['-mcpu=cortex-a35']],
-	['0xd05', ['-mcpu=cortex-a55']],
-	['0xd07', ['-mcpu=cortex-a57']],
-	['0xd08', ['-mcpu=cortex-a72']],
-	['0xd09', ['-mcpu=cortex-a73']],
-	['0xd0a', ['-mcpu=cortex-a75']],
-	['0xd0b', ['-mcpu=cortex-a76']],
-]
-machine_args_cavium = [
-	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
-	['native', ['-march=native']],
-	['0xa1', ['-mcpu=thunderxt88']],
-	['0xa2', ['-mcpu=thunderxt81']],
-	['0xa3', ['-mcpu=thunderxt83']]]
-
 flags_common_default = [
 	# Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
 	# to determine the best threshold in code. Refer to notes in source file
@@ -52,12 +33,10 @@ flags_generic = [
 	['RTE_USE_C11_MEM_MODEL', true],
 	['RTE_CACHE_LINE_SIZE', 128]]
 flags_cavium = [
-	['RTE_MACHINE', '"thunderx"'],
 	['RTE_CACHE_LINE_SIZE', 128],
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 96],
-	['RTE_MAX_VFIO_GROUPS', 128],
-	['RTE_USE_C11_MEM_MODEL', false]]
+	['RTE_MAX_VFIO_GROUPS', 128]]
 flags_dpaa = [
 	['RTE_MACHINE', '"dpaa"'],
 	['RTE_USE_C11_MEM_MODEL', true],
@@ -71,6 +50,27 @@ flags_dpaa2 = [
 	['RTE_MAX_NUMA_NODES', 1],
 	['RTE_MAX_LCORE', 16],
 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
+flags_default_extra = []
+flags_thunderx_extra = [
+	['RTE_MACHINE', '"thunderx"'],
+	['RTE_USE_C11_MEM_MODEL', false]]
+
+machine_args_generic = [
+	['default', ['-march=armv8-a+crc+crypto']],
+	['native', ['-march=native']],
+	['0xd03', ['-mcpu=cortex-a53']],
+	['0xd04', ['-mcpu=cortex-a35']],
+	['0xd07', ['-mcpu=cortex-a57']],
+	['0xd08', ['-mcpu=cortex-a72']],
+	['0xd09', ['-mcpu=cortex-a73']],
+	['0xd0a', ['-mcpu=cortex-a75']]]
+
+machine_args_cavium = [
+	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
+	['native', ['-march=native']],
+	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
+	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
@@ -145,20 +145,19 @@ else
 			dpdk_conf.set(flag[0], flag[1])
 		endif
 	endforeach
-	# Primary part number based mcpu flags are supported
-	# for gcc versions > 7
-	if cc.version().version_compare(
-			'<7.0') or cmd_output.length() == 0
-		if not meson.is_cross_build() and arm_force_native_march == true
-			impl_pn = 'native'
-		else
-			impl_pn = 'default'
-		endif
-	endif
+	
 	foreach marg: machine[2]
 		if marg[0] == impl_pn
-			foreach f: marg[1]
-				machine_args += f
+			foreach flag: marg[1]
+				if cc.has_argument(flag)
+					machine_args += flag
+				endif
+			endforeach
+			# Apply any extra machine specific flags.
+			foreach flag: marg.get(2, flags_default_extra)
+				if flag.length() > 0
+					dpdk_conf.set(flag[0], flag[1])
+				endif
 			endforeach
 		endif
 	endforeach
-- 
2.21.0

[dpdk-dev] [PATCH v9 3/4] config: add thunderx2 machine config

[jerinj]

From: Jerin Jacob <jerinj@marvell.com>

Optimized configuration for Marvell thunderx2 SoC.
Updated meson build to support Marvell thunderx2 SoC.
Added meson cross compile target.

Product details are here:

https://www.marvell.com/server-processors/thunderx2-arm-processors/

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
---
 config/arm/arm64_thunderx2_linux_gcc          | 16 +++++++++
 config/arm/meson.build                        |  9 ++++-
 config/defconfig_arm64-thunderx2-linux-gcc    |  1 +
 config/defconfig_arm64-thunderx2-linuxapp-gcc | 11 ++++++
 mk/machine/thunderx2/rte.vars.mk              | 34 +++++++++++++++++++
 5 files changed, 70 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/arm64_thunderx2_linux_gcc
 create mode 120000 config/defconfig_arm64-thunderx2-linux-gcc
 create mode 100644 config/defconfig_arm64-thunderx2-linuxapp-gcc
 create mode 100644 mk/machine/thunderx2/rte.vars.mk

diff --git a/config/arm/arm64_thunderx2_linux_gcc b/config/arm/arm64_thunderx2_linux_gcc
new file mode 100644
index 000000000..0dc275644
--- /dev/null
+++ b/config/arm/arm64_thunderx2_linux_gcc
@@ -0,0 +1,16 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x43'
+implementor_pn = '0xaf'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index d30a17426..a5fce7a59 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -54,6 +54,12 @@ flags_default_extra = []
 flags_thunderx_extra = [
 	['RTE_MACHINE', '"thunderx"'],
 	['RTE_USE_C11_MEM_MODEL', false]]
+flags_thunderx2_extra = [
+	['RTE_MACHINE', '"thunderx2"'],
+	['RTE_CACHE_LINE_SIZE', 64],
+	['RTE_MAX_NUMA_NODES', 2],
+	['RTE_MAX_LCORE', 256],
+	['RTE_USE_C11_MEM_MODEL', true]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -70,7 +76,8 @@ machine_args_cavium = [
 	['native', ['-march=native']],
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
-	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-thunderx2-linux-gcc b/config/defconfig_arm64-thunderx2-linux-gcc
new file mode 120000
index 000000000..b40a760b1
--- /dev/null
+++ b/config/defconfig_arm64-thunderx2-linux-gcc
@@ -0,0 +1 @@
+defconfig_arm64-thunderx2-linuxapp-gcc
\ No newline at end of file
diff --git a/config/defconfig_arm64-thunderx2-linuxapp-gcc b/config/defconfig_arm64-thunderx2-linuxapp-gcc
new file mode 100644
index 000000000..cc5c64ba0
--- /dev/null
+++ b/config/defconfig_arm64-thunderx2-linuxapp-gcc
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linux-gcc"
+
+CONFIG_RTE_MACHINE="thunderx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=64
+CONFIG_RTE_MAX_NUMA_NODES=2
+CONFIG_RTE_MAX_LCORE=256
diff --git a/mk/machine/thunderx2/rte.vars.mk b/mk/machine/thunderx2/rte.vars.mk
new file mode 100644
index 000000000..b80dc8680
--- /dev/null
+++ b/mk/machine/thunderx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.1-a+crc+crypto)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=thunderx2t99)
-- 
2.21.0

[dpdk-dev] [PATCH v9 3/4] config: add thunderx2 machine config

[jerinj]

From: Jerin Jacob <jerinj@marvell.com>

Optimized configuration for Marvell thunderx2 SoC.
Updated meson build to support Marvell thunderx2 SoC.
Added meson cross compile target.

Product details are here:

https://www.marvell.com/server-processors/thunderx2-arm-processors/

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
---
 config/arm/arm64_thunderx2_linux_gcc          | 16 +++++++++
 config/arm/meson.build                        |  9 ++++-
 config/defconfig_arm64-thunderx2-linux-gcc    |  1 +
 config/defconfig_arm64-thunderx2-linuxapp-gcc | 11 ++++++
 mk/machine/thunderx2/rte.vars.mk              | 34 +++++++++++++++++++
 5 files changed, 70 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/arm64_thunderx2_linux_gcc
 create mode 120000 config/defconfig_arm64-thunderx2-linux-gcc
 create mode 100644 config/defconfig_arm64-thunderx2-linuxapp-gcc
 create mode 100644 mk/machine/thunderx2/rte.vars.mk

diff --git a/config/arm/arm64_thunderx2_linux_gcc b/config/arm/arm64_thunderx2_linux_gcc
new file mode 100644
index 000000000..0dc275644
--- /dev/null
+++ b/config/arm/arm64_thunderx2_linux_gcc
@@ -0,0 +1,16 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x43'
+implementor_pn = '0xaf'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index d30a17426..a5fce7a59 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -54,6 +54,12 @@ flags_default_extra = []
 flags_thunderx_extra = [
 	['RTE_MACHINE', '"thunderx"'],
 	['RTE_USE_C11_MEM_MODEL', false]]
+flags_thunderx2_extra = [
+	['RTE_MACHINE', '"thunderx2"'],
+	['RTE_CACHE_LINE_SIZE', 64],
+	['RTE_MAX_NUMA_NODES', 2],
+	['RTE_MAX_LCORE', 256],
+	['RTE_USE_C11_MEM_MODEL', true]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -70,7 +76,8 @@ machine_args_cavium = [
 	['native', ['-march=native']],
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
-	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-thunderx2-linux-gcc b/config/defconfig_arm64-thunderx2-linux-gcc
new file mode 120000
index 000000000..b40a760b1
--- /dev/null
+++ b/config/defconfig_arm64-thunderx2-linux-gcc
@@ -0,0 +1 @@
+defconfig_arm64-thunderx2-linuxapp-gcc
\ No newline at end of file
diff --git a/config/defconfig_arm64-thunderx2-linuxapp-gcc b/config/defconfig_arm64-thunderx2-linuxapp-gcc
new file mode 100644
index 000000000..cc5c64ba0
--- /dev/null
+++ b/config/defconfig_arm64-thunderx2-linuxapp-gcc
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linux-gcc"
+
+CONFIG_RTE_MACHINE="thunderx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=64
+CONFIG_RTE_MAX_NUMA_NODES=2
+CONFIG_RTE_MAX_LCORE=256
diff --git a/mk/machine/thunderx2/rte.vars.mk b/mk/machine/thunderx2/rte.vars.mk
new file mode 100644
index 000000000..b80dc8680
--- /dev/null
+++ b/mk/machine/thunderx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.1-a+crc+crypto)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=thunderx2t99)
-- 
2.21.0

[dpdk-dev] [PATCH v9 4/4] config: add octeontx2 machine config

[jerinj]

From: Jerin Jacob <jerinj@marvell.com>

Optimized configuration for Marvell octeontx2 SoC.
Updated meson build to support Marvell octeontx2 SoC.
Added meson cross build target for octeontx2.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
---
 config/arm/arm64_octeontx2_linux_gcc          | 16 +++++++++
 config/arm/meson.build                        |  9 ++++-
 config/defconfig_arm64-octeontx2-linux-gcc    |  1 +
 config/defconfig_arm64-octeontx2-linuxapp-gcc | 18 ++++++++++
 mk/machine/octeontx2/rte.vars.mk              | 34 +++++++++++++++++++
 5 files changed, 77 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/arm64_octeontx2_linux_gcc
 create mode 120000 config/defconfig_arm64-octeontx2-linux-gcc
 create mode 100644 config/defconfig_arm64-octeontx2-linuxapp-gcc
 create mode 100644 mk/machine/octeontx2/rte.vars.mk

diff --git a/config/arm/arm64_octeontx2_linux_gcc b/config/arm/arm64_octeontx2_linux_gcc
new file mode 100644
index 000000000..e2c0b8f72
--- /dev/null
+++ b/config/arm/arm64_octeontx2_linux_gcc
@@ -0,0 +1,16 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x43'
+implementor_pn = '0xb2'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index a5fce7a59..bdb36ca69 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -60,6 +60,12 @@ flags_thunderx2_extra = [
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 256],
 	['RTE_USE_C11_MEM_MODEL', true]]
+flags_octeontx2_extra = [
+	['RTE_MACHINE', '"octeontx2"'],
+	['RTE_MAX_NUMA_NODES', 1],
+	['RTE_MAX_LCORE', 24],
+	['RTE_EAL_IGB_UIO', false],
+	['RTE_USE_C11_MEM_MODEL', true]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -77,7 +83,8 @@ machine_args_cavium = [
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
 	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
-	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra],
+	['0xb2', ['-mcpu=octeontx2'], flags_octeontx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-octeontx2-linux-gcc b/config/defconfig_arm64-octeontx2-linux-gcc
new file mode 120000
index 000000000..e25150531
--- /dev/null
+++ b/config/defconfig_arm64-octeontx2-linux-gcc
@@ -0,0 +1 @@
+defconfig_arm64-octeontx2-linuxapp-gcc
\ No newline at end of file
diff --git a/config/defconfig_arm64-octeontx2-linuxapp-gcc b/config/defconfig_arm64-octeontx2-linuxapp-gcc
new file mode 100644
index 000000000..9eae84538
--- /dev/null
+++ b/config/defconfig_arm64-octeontx2-linuxapp-gcc
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linux-gcc"
+
+CONFIG_RTE_MACHINE="octeontx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=128
+CONFIG_RTE_MAX_NUMA_NODES=1
+CONFIG_RTE_MAX_LCORE=24
+
+# Doesn't support NUMA
+CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
+CONFIG_RTE_LIBRTE_VHOST_NUMA=n
+
+# Recommend to use VFIO as co-processors needs SMMU/IOMMU
+CONFIG_RTE_EAL_IGB_UIO=n
diff --git a/mk/machine/octeontx2/rte.vars.mk b/mk/machine/octeontx2/rte.vars.mk
new file mode 100644
index 000000000..cbec7f14d
--- /dev/null
+++ b/mk/machine/octeontx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=-mcpu=armv8.2-a+crc+crypto+lse)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)
-- 
2.21.0

[dpdk-dev] [PATCH v9 4/4] config: add octeontx2 machine config

[jerinj]

From: Jerin Jacob <jerinj@marvell.com>

Optimized configuration for Marvell octeontx2 SoC.
Updated meson build to support Marvell octeontx2 SoC.
Added meson cross build target for octeontx2.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
---
 config/arm/arm64_octeontx2_linux_gcc          | 16 +++++++++
 config/arm/meson.build                        |  9 ++++-
 config/defconfig_arm64-octeontx2-linux-gcc    |  1 +
 config/defconfig_arm64-octeontx2-linuxapp-gcc | 18 ++++++++++
 mk/machine/octeontx2/rte.vars.mk              | 34 +++++++++++++++++++
 5 files changed, 77 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/arm64_octeontx2_linux_gcc
 create mode 120000 config/defconfig_arm64-octeontx2-linux-gcc
 create mode 100644 config/defconfig_arm64-octeontx2-linuxapp-gcc
 create mode 100644 mk/machine/octeontx2/rte.vars.mk

diff --git a/config/arm/arm64_octeontx2_linux_gcc b/config/arm/arm64_octeontx2_linux_gcc
new file mode 100644
index 000000000..e2c0b8f72
--- /dev/null
+++ b/config/arm/arm64_octeontx2_linux_gcc
@@ -0,0 +1,16 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x43'
+implementor_pn = '0xb2'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index a5fce7a59..bdb36ca69 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -60,6 +60,12 @@ flags_thunderx2_extra = [
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 256],
 	['RTE_USE_C11_MEM_MODEL', true]]
+flags_octeontx2_extra = [
+	['RTE_MACHINE', '"octeontx2"'],
+	['RTE_MAX_NUMA_NODES', 1],
+	['RTE_MAX_LCORE', 24],
+	['RTE_EAL_IGB_UIO', false],
+	['RTE_USE_C11_MEM_MODEL', true]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -77,7 +83,8 @@ machine_args_cavium = [
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
 	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
-	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra],
+	['0xb2', ['-mcpu=octeontx2'], flags_octeontx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-octeontx2-linux-gcc b/config/defconfig_arm64-octeontx2-linux-gcc
new file mode 120000
index 000000000..e25150531
--- /dev/null
+++ b/config/defconfig_arm64-octeontx2-linux-gcc
@@ -0,0 +1 @@
+defconfig_arm64-octeontx2-linuxapp-gcc
\ No newline at end of file
diff --git a/config/defconfig_arm64-octeontx2-linuxapp-gcc b/config/defconfig_arm64-octeontx2-linuxapp-gcc
new file mode 100644
index 000000000..9eae84538
--- /dev/null
+++ b/config/defconfig_arm64-octeontx2-linuxapp-gcc
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linux-gcc"
+
+CONFIG_RTE_MACHINE="octeontx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=128
+CONFIG_RTE_MAX_NUMA_NODES=1
+CONFIG_RTE_MAX_LCORE=24
+
+# Doesn't support NUMA
+CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
+CONFIG_RTE_LIBRTE_VHOST_NUMA=n
+
+# Recommend to use VFIO as co-processors needs SMMU/IOMMU
+CONFIG_RTE_EAL_IGB_UIO=n
diff --git a/mk/machine/octeontx2/rte.vars.mk b/mk/machine/octeontx2/rte.vars.mk
new file mode 100644
index 000000000..cbec7f14d
--- /dev/null
+++ b/mk/machine/octeontx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=-mcpu=armv8.2-a+crc+crypto+lse)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)
-- 
2.21.0

[dpdk-dev] [PATCH v10 1/4] mk: introduce helper to check valid compiler argument

[jerinj]

From: Jerin Jacob <jerinj@marvell.com>

Introduce rte_cc_has_argument() Makefile helper to
check a given argument is support by the compiler.

Example Usage:

include $(RTE_SDK)/mk/rte.helper.mk
MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)

This would allow adding -mcpu=octeontx2 in MACHINE_CFLAGS
if it is only supported by the compiler. The use case for such
scheme is to enable the mcpu optimization if the compiler
supports else it needs to compile the source code without
any errors.

This patch also moves inclusion of toolchain's rte.vars.mk
to before the machine's rte.vars.mk inclusion to make
correct CC available for the cross compile case.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---

Change history of this series:

v10 Changes:
- Fix the following checkpatch warning
http://mails.dpdk.org/archives/test-report/2019-April/080453.html

v9 Changes:
 - Remove compiler version check as it is now done using
   cc.has_argument().

v8 Changes:
 - Remove redudant lists (rebase aritfacts). (Yongseok Koh)
 
v7 Changes:
 - Updated cross compile config files align with 
 "build: improve pcap dependency handling" changeset to fix build issue with meson
 - Some compiler needs the following depended patch to compile with meson
   http://patches.dpdk.org/patch/52367/

v6 Changes:
 - Rework to change the config files to sync with "mk: use linux and freebsd in config names"
 - Fix the following error with latest gcc by fixing the mcpu type
   cc1: error: switch -mcpu=armv8.2-a conflicts with -march=armv8-a switch 

v5 Changes:
 - Fix incorrect meson flag parsing(Phil Yang)
 - Squash meson cross build patch(5/5) into configuration update patches for
 thunderx2(3/5) and octeontx2(4/5)(Thomas)
 - Changed octeontx2's march as armv8-a and added the extension required
   instead of armv8-2a(Phil Yang)
 - Improved rte_cc_has_argument() implementaion by removing the temp
   file(Thomas)

v4 Changes:
 - Fix incorrect signoff marrvell -> marvell.

v3 Changes:
 - Squash meson build support into config support for thunderx2/octeontx2.

v2 Changes:
 - Add meson build support.

---

 mk/rte.helper.mk              | 10 ++++++++++
 mk/target/generic/rte.vars.mk | 22 +++++++++++-----------
 2 files changed, 21 insertions(+), 11 deletions(-)
 create mode 100644 mk/rte.helper.mk

diff --git a/mk/rte.helper.mk b/mk/rte.helper.mk
new file mode 100644
index 000000000..6e7fd03d7
--- /dev/null
+++ b/mk/rte.helper.mk
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+
+# rte_cc_has_argument
+# Usage: MACHINE_CFLAGS += $(call rte_cc_has_argument, -mno-avx512f)
+# Return the argument if the argument is supported by the compiler.
+#
+define rte_cc_has_argument
+	$(shell $(CC) -E $(1) -xc /dev/null 1>/dev/null 2>/dev/null && echo $(1))
+endef
diff --git a/mk/target/generic/rte.vars.mk b/mk/target/generic/rte.vars.mk
index dd149acc9..25a578ad7 100644
--- a/mk/target/generic/rte.vars.mk
+++ b/mk/target/generic/rte.vars.mk
@@ -7,6 +7,17 @@
 # executive environment.
 #
 
+#
+# toolchain:
+#
+#   - define CC, LD, AR, AS, ...
+#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
+#   - may override any previously defined variable
+#
+include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
+
 #
 # machine:
 #
@@ -45,17 +56,6 @@ endif
 #
 include $(RTE_SDK)/mk/arch/$(RTE_ARCH)/rte.vars.mk
 
-#
-# toolchain:
-#
-#   - define CC, LD, AR, AS, ...
-#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
-#   - may override any previously defined variable
-#
-include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
-
 #
 # exec-env:
 #
-- 
2.21.0

[dpdk-dev] [PATCH v10 1/4] mk: introduce helper to check valid compiler argument

[jerinj]

From: Jerin Jacob <jerinj@marvell.com>

Introduce rte_cc_has_argument() Makefile helper to
check a given argument is support by the compiler.

Example Usage:

include $(RTE_SDK)/mk/rte.helper.mk
MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)

This would allow adding -mcpu=octeontx2 in MACHINE_CFLAGS
if it is only supported by the compiler. The use case for such
scheme is to enable the mcpu optimization if the compiler
supports else it needs to compile the source code without
any errors.

This patch also moves inclusion of toolchain's rte.vars.mk
to before the machine's rte.vars.mk inclusion to make
correct CC available for the cross compile case.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---

Change history of this series:

v10 Changes:
- Fix the following checkpatch warning
http://mails.dpdk.org/archives/test-report/2019-April/080453.html

v9 Changes:
 - Remove compiler version check as it is now done using
   cc.has_argument().

v8 Changes:
 - Remove redudant lists (rebase aritfacts). (Yongseok Koh)
 
v7 Changes:
 - Updated cross compile config files align with 
 "build: improve pcap dependency handling" changeset to fix build issue with meson
 - Some compiler needs the following depended patch to compile with meson
   http://patches.dpdk.org/patch/52367/

v6 Changes:
 - Rework to change the config files to sync with "mk: use linux and freebsd in config names"
 - Fix the following error with latest gcc by fixing the mcpu type
   cc1: error: switch -mcpu=armv8.2-a conflicts with -march=armv8-a switch 

v5 Changes:
 - Fix incorrect meson flag parsing(Phil Yang)
 - Squash meson cross build patch(5/5) into configuration update patches for
 thunderx2(3/5) and octeontx2(4/5)(Thomas)
 - Changed octeontx2's march as armv8-a and added the extension required
   instead of armv8-2a(Phil Yang)
 - Improved rte_cc_has_argument() implementaion by removing the temp
   file(Thomas)

v4 Changes:
 - Fix incorrect signoff marrvell -> marvell.

v3 Changes:
 - Squash meson build support into config support for thunderx2/octeontx2.

v2 Changes:
 - Add meson build support.

---

 mk/rte.helper.mk              | 10 ++++++++++
 mk/target/generic/rte.vars.mk | 22 +++++++++++-----------
 2 files changed, 21 insertions(+), 11 deletions(-)
 create mode 100644 mk/rte.helper.mk

diff --git a/mk/rte.helper.mk b/mk/rte.helper.mk
new file mode 100644
index 000000000..6e7fd03d7
--- /dev/null
+++ b/mk/rte.helper.mk
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+
+# rte_cc_has_argument
+# Usage: MACHINE_CFLAGS += $(call rte_cc_has_argument, -mno-avx512f)
+# Return the argument if the argument is supported by the compiler.
+#
+define rte_cc_has_argument
+	$(shell $(CC) -E $(1) -xc /dev/null 1>/dev/null 2>/dev/null && echo $(1))
+endef
diff --git a/mk/target/generic/rte.vars.mk b/mk/target/generic/rte.vars.mk
index dd149acc9..25a578ad7 100644
--- a/mk/target/generic/rte.vars.mk
+++ b/mk/target/generic/rte.vars.mk
@@ -7,6 +7,17 @@
 # executive environment.
 #
 
+#
+# toolchain:
+#
+#   - define CC, LD, AR, AS, ...
+#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
+#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
+#   - may override any previously defined variable
+#
+include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
+
 #
 # machine:
 #
@@ -45,17 +56,6 @@ endif
 #
 include $(RTE_SDK)/mk/arch/$(RTE_ARCH)/rte.vars.mk
 
-#
-# toolchain:
-#
-#   - define CC, LD, AR, AS, ...
-#   - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value)
-#   - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value)
-#   - may override any previously defined variable
-#
-include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk
-
 #
 # exec-env:
 #
-- 
2.21.0

[dpdk-dev] [PATCH v10 2/4] meson: add infra to support machine specific flags

[jerinj]

From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Currently, RTE_* flags are set based on the implementer ID but there might
be some micro arch specific differences from the same vendor
eg. CACHE_LINESIZE. Add support to set micro arch specific flags.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
---
 config/arm/meson.build | 67 +++++++++++++++++++++---------------------
 1 file changed, 33 insertions(+), 34 deletions(-)

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 170a4981a..104acd6d4 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -7,25 +7,6 @@ march_opt = '-march=@0@'.format(machine)
 
 arm_force_native_march = false
 
-machine_args_generic = [
-	['default', ['-march=armv8-a+crc+crypto']],
-	['native', ['-march=native']],
-	['0xd03', ['-mcpu=cortex-a53']],
-	['0xd04', ['-mcpu=cortex-a35']],
-	['0xd05', ['-mcpu=cortex-a55']],
-	['0xd07', ['-mcpu=cortex-a57']],
-	['0xd08', ['-mcpu=cortex-a72']],
-	['0xd09', ['-mcpu=cortex-a73']],
-	['0xd0a', ['-mcpu=cortex-a75']],
-	['0xd0b', ['-mcpu=cortex-a76']],
-]
-machine_args_cavium = [
-	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
-	['native', ['-march=native']],
-	['0xa1', ['-mcpu=thunderxt88']],
-	['0xa2', ['-mcpu=thunderxt81']],
-	['0xa3', ['-mcpu=thunderxt83']]]
-
 flags_common_default = [
 	# Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
 	# to determine the best threshold in code. Refer to notes in source file
@@ -52,12 +33,10 @@ flags_generic = [
 	['RTE_USE_C11_MEM_MODEL', true],
 	['RTE_CACHE_LINE_SIZE', 128]]
 flags_cavium = [
-	['RTE_MACHINE', '"thunderx"'],
 	['RTE_CACHE_LINE_SIZE', 128],
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 96],
-	['RTE_MAX_VFIO_GROUPS', 128],
-	['RTE_USE_C11_MEM_MODEL', false]]
+	['RTE_MAX_VFIO_GROUPS', 128]]
 flags_dpaa = [
 	['RTE_MACHINE', '"dpaa"'],
 	['RTE_USE_C11_MEM_MODEL', true],
@@ -71,6 +50,27 @@ flags_dpaa2 = [
 	['RTE_MAX_NUMA_NODES', 1],
 	['RTE_MAX_LCORE', 16],
 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
+flags_default_extra = []
+flags_thunderx_extra = [
+	['RTE_MACHINE', '"thunderx"'],
+	['RTE_USE_C11_MEM_MODEL', false]]
+
+machine_args_generic = [
+	['default', ['-march=armv8-a+crc+crypto']],
+	['native', ['-march=native']],
+	['0xd03', ['-mcpu=cortex-a53']],
+	['0xd04', ['-mcpu=cortex-a35']],
+	['0xd07', ['-mcpu=cortex-a57']],
+	['0xd08', ['-mcpu=cortex-a72']],
+	['0xd09', ['-mcpu=cortex-a73']],
+	['0xd0a', ['-mcpu=cortex-a75']]]
+
+machine_args_cavium = [
+	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
+	['native', ['-march=native']],
+	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
+	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
@@ -145,20 +145,19 @@ else
 			dpdk_conf.set(flag[0], flag[1])
 		endif
 	endforeach
-	# Primary part number based mcpu flags are supported
-	# for gcc versions > 7
-	if cc.version().version_compare(
-			'<7.0') or cmd_output.length() == 0
-		if not meson.is_cross_build() and arm_force_native_march == true
-			impl_pn = 'native'
-		else
-			impl_pn = 'default'
-		endif
-	endif
+
 	foreach marg: machine[2]
 		if marg[0] == impl_pn
-			foreach f: marg[1]
-				machine_args += f
+			foreach flag: marg[1]
+				if cc.has_argument(flag)
+					machine_args += flag
+				endif
+			endforeach
+			# Apply any extra machine specific flags.
+			foreach flag: marg.get(2, flags_default_extra)
+				if flag.length() > 0
+					dpdk_conf.set(flag[0], flag[1])
+				endif
 			endforeach
 		endif
 	endforeach
-- 
2.21.0

[dpdk-dev] [PATCH v10 2/4] meson: add infra to support machine specific flags

[jerinj]

From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Currently, RTE_* flags are set based on the implementer ID but there might
be some micro arch specific differences from the same vendor
eg. CACHE_LINESIZE. Add support to set micro arch specific flags.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
---
 config/arm/meson.build | 67 +++++++++++++++++++++---------------------
 1 file changed, 33 insertions(+), 34 deletions(-)

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 170a4981a..104acd6d4 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -7,25 +7,6 @@ march_opt = '-march=@0@'.format(machine)
 
 arm_force_native_march = false
 
-machine_args_generic = [
-	['default', ['-march=armv8-a+crc+crypto']],
-	['native', ['-march=native']],
-	['0xd03', ['-mcpu=cortex-a53']],
-	['0xd04', ['-mcpu=cortex-a35']],
-	['0xd05', ['-mcpu=cortex-a55']],
-	['0xd07', ['-mcpu=cortex-a57']],
-	['0xd08', ['-mcpu=cortex-a72']],
-	['0xd09', ['-mcpu=cortex-a73']],
-	['0xd0a', ['-mcpu=cortex-a75']],
-	['0xd0b', ['-mcpu=cortex-a76']],
-]
-machine_args_cavium = [
-	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
-	['native', ['-march=native']],
-	['0xa1', ['-mcpu=thunderxt88']],
-	['0xa2', ['-mcpu=thunderxt81']],
-	['0xa3', ['-mcpu=thunderxt83']]]
-
 flags_common_default = [
 	# Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
 	# to determine the best threshold in code. Refer to notes in source file
@@ -52,12 +33,10 @@ flags_generic = [
 	['RTE_USE_C11_MEM_MODEL', true],
 	['RTE_CACHE_LINE_SIZE', 128]]
 flags_cavium = [
-	['RTE_MACHINE', '"thunderx"'],
 	['RTE_CACHE_LINE_SIZE', 128],
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 96],
-	['RTE_MAX_VFIO_GROUPS', 128],
-	['RTE_USE_C11_MEM_MODEL', false]]
+	['RTE_MAX_VFIO_GROUPS', 128]]
 flags_dpaa = [
 	['RTE_MACHINE', '"dpaa"'],
 	['RTE_USE_C11_MEM_MODEL', true],
@@ -71,6 +50,27 @@ flags_dpaa2 = [
 	['RTE_MAX_NUMA_NODES', 1],
 	['RTE_MAX_LCORE', 16],
 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
+flags_default_extra = []
+flags_thunderx_extra = [
+	['RTE_MACHINE', '"thunderx"'],
+	['RTE_USE_C11_MEM_MODEL', false]]
+
+machine_args_generic = [
+	['default', ['-march=armv8-a+crc+crypto']],
+	['native', ['-march=native']],
+	['0xd03', ['-mcpu=cortex-a53']],
+	['0xd04', ['-mcpu=cortex-a35']],
+	['0xd07', ['-mcpu=cortex-a57']],
+	['0xd08', ['-mcpu=cortex-a72']],
+	['0xd09', ['-mcpu=cortex-a73']],
+	['0xd0a', ['-mcpu=cortex-a75']]]
+
+machine_args_cavium = [
+	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
+	['native', ['-march=native']],
+	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
+	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
@@ -145,20 +145,19 @@ else
 			dpdk_conf.set(flag[0], flag[1])
 		endif
 	endforeach
-	# Primary part number based mcpu flags are supported
-	# for gcc versions > 7
-	if cc.version().version_compare(
-			'<7.0') or cmd_output.length() == 0
-		if not meson.is_cross_build() and arm_force_native_march == true
-			impl_pn = 'native'
-		else
-			impl_pn = 'default'
-		endif
-	endif
+
 	foreach marg: machine[2]
 		if marg[0] == impl_pn
-			foreach f: marg[1]
-				machine_args += f
+			foreach flag: marg[1]
+				if cc.has_argument(flag)
+					machine_args += flag
+				endif
+			endforeach
+			# Apply any extra machine specific flags.
+			foreach flag: marg.get(2, flags_default_extra)
+				if flag.length() > 0
+					dpdk_conf.set(flag[0], flag[1])
+				endif
 			endforeach
 		endif
 	endforeach
-- 
2.21.0

[dpdk-dev] [PATCH v10 3/4] config: add thunderx2 machine config

[jerinj]

From: Jerin Jacob <jerinj@marvell.com>

Optimized configuration for Marvell thunderx2 SoC.
Updated meson build to support Marvell thunderx2 SoC.
Added meson cross compile target.

Product details are here:

https://www.marvell.com/server-processors/thunderx2-arm-processors/

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
---
 config/arm/arm64_thunderx2_linux_gcc          | 16 +++++++++
 config/arm/meson.build                        |  9 ++++-
 config/defconfig_arm64-thunderx2-linux-gcc    |  1 +
 config/defconfig_arm64-thunderx2-linuxapp-gcc | 11 ++++++
 mk/machine/thunderx2/rte.vars.mk              | 34 +++++++++++++++++++
 5 files changed, 70 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/arm64_thunderx2_linux_gcc
 create mode 120000 config/defconfig_arm64-thunderx2-linux-gcc
 create mode 100644 config/defconfig_arm64-thunderx2-linuxapp-gcc
 create mode 100644 mk/machine/thunderx2/rte.vars.mk

diff --git a/config/arm/arm64_thunderx2_linux_gcc b/config/arm/arm64_thunderx2_linux_gcc
new file mode 100644
index 000000000..0dc275644
--- /dev/null
+++ b/config/arm/arm64_thunderx2_linux_gcc
@@ -0,0 +1,16 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x43'
+implementor_pn = '0xaf'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 104acd6d4..ccf806e73 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -54,6 +54,12 @@ flags_default_extra = []
 flags_thunderx_extra = [
 	['RTE_MACHINE', '"thunderx"'],
 	['RTE_USE_C11_MEM_MODEL', false]]
+flags_thunderx2_extra = [
+	['RTE_MACHINE', '"thunderx2"'],
+	['RTE_CACHE_LINE_SIZE', 64],
+	['RTE_MAX_NUMA_NODES', 2],
+	['RTE_MAX_LCORE', 256],
+	['RTE_USE_C11_MEM_MODEL', true]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -70,7 +76,8 @@ machine_args_cavium = [
 	['native', ['-march=native']],
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
-	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-thunderx2-linux-gcc b/config/defconfig_arm64-thunderx2-linux-gcc
new file mode 120000
index 000000000..b40a760b1
--- /dev/null
+++ b/config/defconfig_arm64-thunderx2-linux-gcc
@@ -0,0 +1 @@
+defconfig_arm64-thunderx2-linuxapp-gcc
\ No newline at end of file
diff --git a/config/defconfig_arm64-thunderx2-linuxapp-gcc b/config/defconfig_arm64-thunderx2-linuxapp-gcc
new file mode 100644
index 000000000..cc5c64ba0
--- /dev/null
+++ b/config/defconfig_arm64-thunderx2-linuxapp-gcc
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linux-gcc"
+
+CONFIG_RTE_MACHINE="thunderx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=64
+CONFIG_RTE_MAX_NUMA_NODES=2
+CONFIG_RTE_MAX_LCORE=256
diff --git a/mk/machine/thunderx2/rte.vars.mk b/mk/machine/thunderx2/rte.vars.mk
new file mode 100644
index 000000000..b80dc8680
--- /dev/null
+++ b/mk/machine/thunderx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.1-a+crc+crypto)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=thunderx2t99)
-- 
2.21.0

[dpdk-dev] [PATCH v10 3/4] config: add thunderx2 machine config

[jerinj]

From: Jerin Jacob <jerinj@marvell.com>

Optimized configuration for Marvell thunderx2 SoC.
Updated meson build to support Marvell thunderx2 SoC.
Added meson cross compile target.

Product details are here:

https://www.marvell.com/server-processors/thunderx2-arm-processors/

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
---
 config/arm/arm64_thunderx2_linux_gcc          | 16 +++++++++
 config/arm/meson.build                        |  9 ++++-
 config/defconfig_arm64-thunderx2-linux-gcc    |  1 +
 config/defconfig_arm64-thunderx2-linuxapp-gcc | 11 ++++++
 mk/machine/thunderx2/rte.vars.mk              | 34 +++++++++++++++++++
 5 files changed, 70 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/arm64_thunderx2_linux_gcc
 create mode 120000 config/defconfig_arm64-thunderx2-linux-gcc
 create mode 100644 config/defconfig_arm64-thunderx2-linuxapp-gcc
 create mode 100644 mk/machine/thunderx2/rte.vars.mk

diff --git a/config/arm/arm64_thunderx2_linux_gcc b/config/arm/arm64_thunderx2_linux_gcc
new file mode 100644
index 000000000..0dc275644
--- /dev/null
+++ b/config/arm/arm64_thunderx2_linux_gcc
@@ -0,0 +1,16 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x43'
+implementor_pn = '0xaf'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 104acd6d4..ccf806e73 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -54,6 +54,12 @@ flags_default_extra = []
 flags_thunderx_extra = [
 	['RTE_MACHINE', '"thunderx"'],
 	['RTE_USE_C11_MEM_MODEL', false]]
+flags_thunderx2_extra = [
+	['RTE_MACHINE', '"thunderx2"'],
+	['RTE_CACHE_LINE_SIZE', 64],
+	['RTE_MAX_NUMA_NODES', 2],
+	['RTE_MAX_LCORE', 256],
+	['RTE_USE_C11_MEM_MODEL', true]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -70,7 +76,8 @@ machine_args_cavium = [
 	['native', ['-march=native']],
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
-	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-thunderx2-linux-gcc b/config/defconfig_arm64-thunderx2-linux-gcc
new file mode 120000
index 000000000..b40a760b1
--- /dev/null
+++ b/config/defconfig_arm64-thunderx2-linux-gcc
@@ -0,0 +1 @@
+defconfig_arm64-thunderx2-linuxapp-gcc
\ No newline at end of file
diff --git a/config/defconfig_arm64-thunderx2-linuxapp-gcc b/config/defconfig_arm64-thunderx2-linuxapp-gcc
new file mode 100644
index 000000000..cc5c64ba0
--- /dev/null
+++ b/config/defconfig_arm64-thunderx2-linuxapp-gcc
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linux-gcc"
+
+CONFIG_RTE_MACHINE="thunderx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=64
+CONFIG_RTE_MAX_NUMA_NODES=2
+CONFIG_RTE_MAX_LCORE=256
diff --git a/mk/machine/thunderx2/rte.vars.mk b/mk/machine/thunderx2/rte.vars.mk
new file mode 100644
index 000000000..b80dc8680
--- /dev/null
+++ b/mk/machine/thunderx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.1-a+crc+crypto)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=thunderx2t99)
-- 
2.21.0

[dpdk-dev] [PATCH v10 4/4] config: add octeontx2 machine config

[jerinj]

From: Jerin Jacob <jerinj@marvell.com>

Optimized configuration for Marvell octeontx2 SoC.
Updated meson build to support Marvell octeontx2 SoC.
Added meson cross build target for octeontx2.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
---
 config/arm/arm64_octeontx2_linux_gcc          | 16 +++++++++
 config/arm/meson.build                        |  9 ++++-
 config/defconfig_arm64-octeontx2-linux-gcc    |  1 +
 config/defconfig_arm64-octeontx2-linuxapp-gcc | 18 ++++++++++
 mk/machine/octeontx2/rte.vars.mk              | 34 +++++++++++++++++++
 5 files changed, 77 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/arm64_octeontx2_linux_gcc
 create mode 120000 config/defconfig_arm64-octeontx2-linux-gcc
 create mode 100644 config/defconfig_arm64-octeontx2-linuxapp-gcc
 create mode 100644 mk/machine/octeontx2/rte.vars.mk

diff --git a/config/arm/arm64_octeontx2_linux_gcc b/config/arm/arm64_octeontx2_linux_gcc
new file mode 100644
index 000000000..e2c0b8f72
--- /dev/null
+++ b/config/arm/arm64_octeontx2_linux_gcc
@@ -0,0 +1,16 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x43'
+implementor_pn = '0xb2'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index ccf806e73..22a062bad 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -60,6 +60,12 @@ flags_thunderx2_extra = [
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 256],
 	['RTE_USE_C11_MEM_MODEL', true]]
+flags_octeontx2_extra = [
+	['RTE_MACHINE', '"octeontx2"'],
+	['RTE_MAX_NUMA_NODES', 1],
+	['RTE_MAX_LCORE', 24],
+	['RTE_EAL_IGB_UIO', false],
+	['RTE_USE_C11_MEM_MODEL', true]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -77,7 +83,8 @@ machine_args_cavium = [
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
 	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
-	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra],
+	['0xb2', ['-mcpu=octeontx2'], flags_octeontx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-octeontx2-linux-gcc b/config/defconfig_arm64-octeontx2-linux-gcc
new file mode 120000
index 000000000..e25150531
--- /dev/null
+++ b/config/defconfig_arm64-octeontx2-linux-gcc
@@ -0,0 +1 @@
+defconfig_arm64-octeontx2-linuxapp-gcc
\ No newline at end of file
diff --git a/config/defconfig_arm64-octeontx2-linuxapp-gcc b/config/defconfig_arm64-octeontx2-linuxapp-gcc
new file mode 100644
index 000000000..9eae84538
--- /dev/null
+++ b/config/defconfig_arm64-octeontx2-linuxapp-gcc
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linux-gcc"
+
+CONFIG_RTE_MACHINE="octeontx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=128
+CONFIG_RTE_MAX_NUMA_NODES=1
+CONFIG_RTE_MAX_LCORE=24
+
+# Doesn't support NUMA
+CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
+CONFIG_RTE_LIBRTE_VHOST_NUMA=n
+
+# Recommend to use VFIO as co-processors needs SMMU/IOMMU
+CONFIG_RTE_EAL_IGB_UIO=n
diff --git a/mk/machine/octeontx2/rte.vars.mk b/mk/machine/octeontx2/rte.vars.mk
new file mode 100644
index 000000000..cbec7f14d
--- /dev/null
+++ b/mk/machine/octeontx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=-mcpu=armv8.2-a+crc+crypto+lse)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)
-- 
2.21.0

[dpdk-dev] [PATCH v10 4/4] config: add octeontx2 machine config

[jerinj]

From: Jerin Jacob <jerinj@marvell.com>

Optimized configuration for Marvell octeontx2 SoC.
Updated meson build to support Marvell octeontx2 SoC.
Added meson cross build target for octeontx2.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
---
 config/arm/arm64_octeontx2_linux_gcc          | 16 +++++++++
 config/arm/meson.build                        |  9 ++++-
 config/defconfig_arm64-octeontx2-linux-gcc    |  1 +
 config/defconfig_arm64-octeontx2-linuxapp-gcc | 18 ++++++++++
 mk/machine/octeontx2/rte.vars.mk              | 34 +++++++++++++++++++
 5 files changed, 77 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/arm64_octeontx2_linux_gcc
 create mode 120000 config/defconfig_arm64-octeontx2-linux-gcc
 create mode 100644 config/defconfig_arm64-octeontx2-linuxapp-gcc
 create mode 100644 mk/machine/octeontx2/rte.vars.mk

diff --git a/config/arm/arm64_octeontx2_linux_gcc b/config/arm/arm64_octeontx2_linux_gcc
new file mode 100644
index 000000000..e2c0b8f72
--- /dev/null
+++ b/config/arm/arm64_octeontx2_linux_gcc
@@ -0,0 +1,16 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x43'
+implementor_pn = '0xb2'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index ccf806e73..22a062bad 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -60,6 +60,12 @@ flags_thunderx2_extra = [
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 256],
 	['RTE_USE_C11_MEM_MODEL', true]]
+flags_octeontx2_extra = [
+	['RTE_MACHINE', '"octeontx2"'],
+	['RTE_MAX_NUMA_NODES', 1],
+	['RTE_MAX_LCORE', 24],
+	['RTE_EAL_IGB_UIO', false],
+	['RTE_USE_C11_MEM_MODEL', true]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc+crypto']],
@@ -77,7 +83,8 @@ machine_args_cavium = [
 	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
 	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
 	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
-	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]]
+	['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra],
+	['0xb2', ['-mcpu=octeontx2'], flags_octeontx2_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
diff --git a/config/defconfig_arm64-octeontx2-linux-gcc b/config/defconfig_arm64-octeontx2-linux-gcc
new file mode 120000
index 000000000..e25150531
--- /dev/null
+++ b/config/defconfig_arm64-octeontx2-linux-gcc
@@ -0,0 +1 @@
+defconfig_arm64-octeontx2-linuxapp-gcc
\ No newline at end of file
diff --git a/config/defconfig_arm64-octeontx2-linuxapp-gcc b/config/defconfig_arm64-octeontx2-linuxapp-gcc
new file mode 100644
index 000000000..9eae84538
--- /dev/null
+++ b/config/defconfig_arm64-octeontx2-linuxapp-gcc
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#include "defconfig_arm64-armv8a-linux-gcc"
+
+CONFIG_RTE_MACHINE="octeontx2"
+
+CONFIG_RTE_CACHE_LINE_SIZE=128
+CONFIG_RTE_MAX_NUMA_NODES=1
+CONFIG_RTE_MAX_LCORE=24
+
+# Doesn't support NUMA
+CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
+CONFIG_RTE_LIBRTE_VHOST_NUMA=n
+
+# Recommend to use VFIO as co-processors needs SMMU/IOMMU
+CONFIG_RTE_EAL_IGB_UIO=n
diff --git a/mk/machine/octeontx2/rte.vars.mk b/mk/machine/octeontx2/rte.vars.mk
new file mode 100644
index 000000000..cbec7f14d
--- /dev/null
+++ b/mk/machine/octeontx2/rte.vars.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Marvell International Ltd
+#
+
+#
+# machine:
+#
+#   - can define ARCH variable (overridden by cmdline value)
+#   - can define CROSS variable (overridden by cmdline value)
+#   - define MACHINE_CFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+#   - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+#   - can define CPU_CFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+#     overrides the one defined in arch.
+#   - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+include $(RTE_SDK)/mk/rte.helper.mk
+
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=-mcpu=armv8.2-a+crc+crypto+lse)
+MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)
-- 
2.21.0

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Thomas Monjalon]

13/04/2019 08:24, Jerin Jacob Kollanukkaran:
> > I was not confortable with this patch without being able to say why.
> > Yesterday I spent more time to understand and see what may be improved.
> > I agree it is late, so it won't block this patch for 19.05.
> > Do you agree this file can be improved?
> 
> Moving to  the all to static config file is an option but we lose the flexibility
> of runtime detecting the options and few of them are probing at runtime based
> on gcc versions and mcpu combination etc.

I think there is a misunderstanding.
I'm suggesting to symplify arrays by indexing only by machine name.
It should not change the behaviour.

> I am not expert in meson area and not sure meson/python has better data strcture for this other than
> list/array combo. If Bruce has any feedback on this, then we
> will try to prototype it.
> 
> > Please would you like to look at reworking during next cycle?
> > Thanks

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Thomas Monjalon]

13/04/2019 08:24, Jerin Jacob Kollanukkaran:
> > I was not confortable with this patch without being able to say why.
> > Yesterday I spent more time to understand and see what may be improved.
> > I agree it is late, so it won't block this patch for 19.05.
> > Do you agree this file can be improved?
> 
> Moving to  the all to static config file is an option but we lose the flexibility
> of runtime detecting the options and few of them are probing at runtime based
> on gcc versions and mcpu combination etc.

I think there is a misunderstanding.
I'm suggesting to symplify arrays by indexing only by machine name.
It should not change the behaviour.

> I am not expert in meson area and not sure meson/python has better data strcture for this other than
> list/array combo. If Bruce has any feedback on this, then we
> will try to prototype it.
> 
> > Please would you like to look at reworking during next cycle?
> > Thanks

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Pavan Nikhilesh Bhagavatula]

Hi Thomas, 

There is no guarantee of primary part number (machine names) uniqueness between implementors. 
If we limit lookups to only machine names through primary part number we would have a lot of repetitive defines.
Also, moving the arrays into the python script is not feasible as meson needs to reparse the standard out from the python script

Currently, config is split into three parts :
	1. Implementor specific defines.
	2. Micro-arch specific compiler flags.
	3. Micro-arch specific defines.

I think from a configurability point of view the above three are really important for fine grained control.

Thoughts?

Regards,
Pavan.

>-----Original Message-----
>From: Thomas Monjalon <thomas@monjalon.net>
>Sent: Sunday, April 14, 2019 2:13 AM
>To: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
>Cc: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>;
>dev@dpdk.org; jerinjacobk@gmail.com; yskoh@mellanox.com;
>bruce.richardson@intel.com
>Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine
>specific flags
>
>13/04/2019 08:24, Jerin Jacob Kollanukkaran:
>> > I was not confortable with this patch without being able to say why.
>> > Yesterday I spent more time to understand and see what may be improved.
>> > I agree it is late, so it won't block this patch for 19.05.
>> > Do you agree this file can be improved?
>>
>> Moving to  the all to static config file is an option but we lose the
>> flexibility of runtime detecting the options and few of them are
>> probing at runtime based on gcc versions and mcpu combination etc.
>
>I think there is a misunderstanding.
>I'm suggesting to symplify arrays by indexing only by machine name.
>It should not change the behaviour.
>
>> I am not expert in meson area and not sure meson/python has better
>> data strcture for this other than list/array combo. If Bruce has any
>> feedback on this, then we will try to prototype it.
>>
>> > Please would you like to look at reworking during next cycle?
>> > Thanks
>
>

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Pavan Nikhilesh Bhagavatula]

Hi Thomas, 

There is no guarantee of primary part number (machine names) uniqueness between implementors. 
If we limit lookups to only machine names through primary part number we would have a lot of repetitive defines.
Also, moving the arrays into the python script is not feasible as meson needs to reparse the standard out from the python script

Currently, config is split into three parts :
	1. Implementor specific defines.
	2. Micro-arch specific compiler flags.
	3. Micro-arch specific defines.

I think from a configurability point of view the above three are really important for fine grained control.

Thoughts?

Regards,
Pavan.

>-----Original Message-----
>From: Thomas Monjalon <thomas@monjalon.net>
>Sent: Sunday, April 14, 2019 2:13 AM
>To: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
>Cc: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>;
>dev@dpdk.org; jerinjacobk@gmail.com; yskoh@mellanox.com;
>bruce.richardson@intel.com
>Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine
>specific flags
>
>13/04/2019 08:24, Jerin Jacob Kollanukkaran:
>> > I was not confortable with this patch without being able to say why.
>> > Yesterday I spent more time to understand and see what may be improved.
>> > I agree it is late, so it won't block this patch for 19.05.
>> > Do you agree this file can be improved?
>>
>> Moving to  the all to static config file is an option but we lose the
>> flexibility of runtime detecting the options and few of them are
>> probing at runtime based on gcc versions and mcpu combination etc.
>
>I think there is a misunderstanding.
>I'm suggesting to symplify arrays by indexing only by machine name.
>It should not change the behaviour.
>
>> I am not expert in meson area and not sure meson/python has better
>> data strcture for this other than list/array combo. If Bruce has any
>> feedback on this, then we will try to prototype it.
>>
>> > Please would you like to look at reworking during next cycle?
>> > Thanks
>
>

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Thomas Monjalon]

14/04/2019 16:40, Pavan Nikhilesh Bhagavatula:
> Hi Thomas, 
> 
> There is no guarantee of primary part number (machine names) uniqueness between implementors.

I think we don't speak the same language :)
By machine name, I mean what we set in RTE_MACHINE, like octeontx2.

> If we limit lookups to only machine names through primary part number we would have a lot of repetitive defines.
> Also, moving the arrays into the python script is not feasible as meson needs to reparse the standard out from the python script

I will probably need to write a PoC.

> Currently, config is split into three parts :
> 	1. Implementor specific defines.
> 	2. Micro-arch specific compiler flags.
> 	3. Micro-arch specific defines.

This is currently unreadable in my opinion.

> I think from a configurability point of view the above three are really important for fine grained control.

I agree fine grain is required.


> Thoughts?
> 
> Regards,
> Pavan.
> 
> >-----Original Message-----
> >From: Thomas Monjalon <thomas@monjalon.net>
> >Sent: Sunday, April 14, 2019 2:13 AM
> >To: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
> >Cc: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>;
> >dev@dpdk.org; jerinjacobk@gmail.com; yskoh@mellanox.com;
> >bruce.richardson@intel.com
> >Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine
> >specific flags
> >
> >13/04/2019 08:24, Jerin Jacob Kollanukkaran:
> >> > I was not confortable with this patch without being able to say why.
> >> > Yesterday I spent more time to understand and see what may be improved.
> >> > I agree it is late, so it won't block this patch for 19.05.
> >> > Do you agree this file can be improved?
> >>
> >> Moving to  the all to static config file is an option but we lose the
> >> flexibility of runtime detecting the options and few of them are
> >> probing at runtime based on gcc versions and mcpu combination etc.
> >
> >I think there is a misunderstanding.
> >I'm suggesting to symplify arrays by indexing only by machine name.
> >It should not change the behaviour.
> >
> >> I am not expert in meson area and not sure meson/python has better
> >> data strcture for this other than list/array combo. If Bruce has any
> >> feedback on this, then we will try to prototype it.
> >>
> >> > Please would you like to look at reworking during next cycle?
> >> > Thanks
> >
> >
> 
> 

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Thomas Monjalon]

14/04/2019 16:40, Pavan Nikhilesh Bhagavatula:
> Hi Thomas, 
> 
> There is no guarantee of primary part number (machine names) uniqueness between implementors.

I think we don't speak the same language :)
By machine name, I mean what we set in RTE_MACHINE, like octeontx2.

> If we limit lookups to only machine names through primary part number we would have a lot of repetitive defines.
> Also, moving the arrays into the python script is not feasible as meson needs to reparse the standard out from the python script

I will probably need to write a PoC.

> Currently, config is split into three parts :
> 	1. Implementor specific defines.
> 	2. Micro-arch specific compiler flags.
> 	3. Micro-arch specific defines.

This is currently unreadable in my opinion.

> I think from a configurability point of view the above three are really important for fine grained control.

I agree fine grain is required.


> Thoughts?
> 
> Regards,
> Pavan.
> 
> >-----Original Message-----
> >From: Thomas Monjalon <thomas@monjalon.net>
> >Sent: Sunday, April 14, 2019 2:13 AM
> >To: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
> >Cc: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>;
> >dev@dpdk.org; jerinjacobk@gmail.com; yskoh@mellanox.com;
> >bruce.richardson@intel.com
> >Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine
> >specific flags
> >
> >13/04/2019 08:24, Jerin Jacob Kollanukkaran:
> >> > I was not confortable with this patch without being able to say why.
> >> > Yesterday I spent more time to understand and see what may be improved.
> >> > I agree it is late, so it won't block this patch for 19.05.
> >> > Do you agree this file can be improved?
> >>
> >> Moving to  the all to static config file is an option but we lose the
> >> flexibility of runtime detecting the options and few of them are
> >> probing at runtime based on gcc versions and mcpu combination etc.
> >
> >I think there is a misunderstanding.
> >I'm suggesting to symplify arrays by indexing only by machine name.
> >It should not change the behaviour.
> >
> >> I am not expert in meson area and not sure meson/python has better
> >> data strcture for this other than list/array combo. If Bruce has any
> >> feedback on this, then we will try to prototype it.
> >>
> >> > Please would you like to look at reworking during next cycle?
> >> > Thanks
> >
> >
> 
> 

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Jerin Jacob Kollanukkaran]

> -----Original Message-----
> From: Thomas Monjalon <thomas@monjalon.net>
> Sent: Sunday, April 14, 2019 11:14 PM
> To: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>
> Cc: Jerin Jacob Kollanukkaran <jerinj@marvell.com>; dev@dpdk.org;
> jerinjacobk@gmail.com; yskoh@mellanox.com; bruce.richardson@intel.com
> Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine
> specific flags
> 
> 14/04/2019 16:40, Pavan Nikhilesh Bhagavatula:
> > Hi Thomas,
> >
> > There is no guarantee of primary part number (machine names) uniqueness
> between implementors.
> 
> I think we don't speak the same language :) By machine name, I mean what we
> set in RTE_MACHINE, like octeontx2.

As you know, The system probes "implementor_id" and "implementor_pn"
Values. There is nothing like machine name in meson and in order to keep 
Synergy with native build, we need to just follow, "implementor_id"
and "implementor_pn". Now, it is possible to have "implemetor_id" to
"implementor_pn"  to machine name lookup but Unlike, "make"  based
Build system, meson supports supporting a lot of machines(like RTE_MACHINE),
with that structure. So converting to another intermediate called "machine string"
will have more overhead IMO.

['0xa1', ['-mcpu=thunderxt88']],
['0xa2', ['-mcpu=thunderxt81']],
['0xa3', ['-mcpu=thunderxt83']]]
['0xd03', ['-mcpu=cortex-a53']],
['0xd04', ['-mcpu=cortex-a35']],
['0xd05', ['-mcpu=cortex-a55']],
['0xd07', ['-mcpu=cortex-a57']],
['0xd08', ['-mcpu=cortex-a72']],
['0xd09', ['-mcpu=cortex-a73']],
['0xd0a', ['-mcpu=cortex-a75']],
['0xd0b', ['-mcpu=cortex-a76']]
impl_0x41 = ['Arm', flags_generic, machine_args_generic]
impl_0x42 = ['Broadcom', flags_generic, machine_args_generic]
impl_0x43 = ['Cavium', flags_cavium, machine_args_cavium]
impl_0x44 = ['DEC', flags_generic, machine_args_generic]
impl_0x49 = ['Infineon', flags_generic, machine_args_generic]
impl_0x4d = ['Motorola', flags_generic, machine_args_generic]
impl_0x4e = ['NVIDIA', flags_generic, machine_args_generic]
impl_0x50 = ['AppliedMicro', flags_generic, machine_args_generic]
impl_0x51 = ['Qualcomm', flags_generic, machine_args_generic]
impl_0x53 = ['Samsung', flags_generic, machine_args_generic]
impl_0x56 = ['Marvell', flags_generic, machine_args_generic]
impl_0x69 = ['Intel', flags_generic, machine_args_generic]
impl_dpaa = ['NXP DPAA', flags_dpaa, machine_args_generic]
impl_dpaa2 = ['NXP DPAA2', flags_dpaa2, machine_args_generic]



> 
> > If we limit lookups to only machine names through primary part number we
> would have a lot of repetitive defines.
> > Also, moving the arrays into the python script is not feasible as
> > meson needs to reparse the standard out from the python script
> 
> I will probably need to write a PoC.

Yes. Please


> 
> > Currently, config is split into three parts :
> > 	1. Implementor specific defines.
> > 	2. Micro-arch specific compiler flags.
> > 	3. Micro-arch specific defines.
> 
> This is currently unreadable in my opinion.

Bit  subjective.
If we want to keep all the fine grained control along with
"native" /"cross" build,  "distribution" build, cache line
differences etc, makes it bit difficult.

But if you think, it can be improved. Please share patch,
We are happy to review and test in  the platforms we have.

> > I think from a configurability point of view the above three are really
> important for fine grained control.
> 
> I agree fine grain is required.
> 
> 
> > Thoughts?
> >
> > Regards,
> > Pavan.
> >
> > >-----Original Message-----
> > >From: Thomas Monjalon <thomas@monjalon.net>
> > >Sent: Sunday, April 14, 2019 2:13 AM
> > >To: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
> > >Cc: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>;
> > >dev@dpdk.org; jerinjacobk@gmail.com; yskoh@mellanox.com;
> > >bruce.richardson@intel.com
> > >Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support
> > >machine specific flags
> > >
> > >13/04/2019 08:24, Jerin Jacob Kollanukkaran:
> > >> > I was not confortable with this patch without being able to say why.
> > >> > Yesterday I spent more time to understand and see what may be
> improved.
> > >> > I agree it is late, so it won't block this patch for 19.05.
> > >> > Do you agree this file can be improved?
> > >>
> > >> Moving to  the all to static config file is an option but we lose
> > >> the flexibility of runtime detecting the options and few of them
> > >> are probing at runtime based on gcc versions and mcpu combination etc.
> > >
> > >I think there is a misunderstanding.
> > >I'm suggesting to symplify arrays by indexing only by machine name.
> > >It should not change the behaviour.
> > >
> > >> I am not expert in meson area and not sure meson/python has better
> > >> data strcture for this other than list/array combo. If Bruce has
> > >> any feedback on this, then we will try to prototype it.
> > >>
> > >> > Please would you like to look at reworking during next cycle?
> > >> > Thanks
> > >
> > >
> >
> >
> 
> 
> 
> 

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Jerin Jacob Kollanukkaran]

> -----Original Message-----
> From: Thomas Monjalon <thomas@monjalon.net>
> Sent: Sunday, April 14, 2019 11:14 PM
> To: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>
> Cc: Jerin Jacob Kollanukkaran <jerinj@marvell.com>; dev@dpdk.org;
> jerinjacobk@gmail.com; yskoh@mellanox.com; bruce.richardson@intel.com
> Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine
> specific flags
> 
> 14/04/2019 16:40, Pavan Nikhilesh Bhagavatula:
> > Hi Thomas,
> >
> > There is no guarantee of primary part number (machine names) uniqueness
> between implementors.
> 
> I think we don't speak the same language :) By machine name, I mean what we
> set in RTE_MACHINE, like octeontx2.

As you know, The system probes "implementor_id" and "implementor_pn"
Values. There is nothing like machine name in meson and in order to keep 
Synergy with native build, we need to just follow, "implementor_id"
and "implementor_pn". Now, it is possible to have "implemetor_id" to
"implementor_pn"  to machine name lookup but Unlike, "make"  based
Build system, meson supports supporting a lot of machines(like RTE_MACHINE),
with that structure. So converting to another intermediate called "machine string"
will have more overhead IMO.

['0xa1', ['-mcpu=thunderxt88']],
['0xa2', ['-mcpu=thunderxt81']],
['0xa3', ['-mcpu=thunderxt83']]]
['0xd03', ['-mcpu=cortex-a53']],
['0xd04', ['-mcpu=cortex-a35']],
['0xd05', ['-mcpu=cortex-a55']],
['0xd07', ['-mcpu=cortex-a57']],
['0xd08', ['-mcpu=cortex-a72']],
['0xd09', ['-mcpu=cortex-a73']],
['0xd0a', ['-mcpu=cortex-a75']],
['0xd0b', ['-mcpu=cortex-a76']]
impl_0x41 = ['Arm', flags_generic, machine_args_generic]
impl_0x42 = ['Broadcom', flags_generic, machine_args_generic]
impl_0x43 = ['Cavium', flags_cavium, machine_args_cavium]
impl_0x44 = ['DEC', flags_generic, machine_args_generic]
impl_0x49 = ['Infineon', flags_generic, machine_args_generic]
impl_0x4d = ['Motorola', flags_generic, machine_args_generic]
impl_0x4e = ['NVIDIA', flags_generic, machine_args_generic]
impl_0x50 = ['AppliedMicro', flags_generic, machine_args_generic]
impl_0x51 = ['Qualcomm', flags_generic, machine_args_generic]
impl_0x53 = ['Samsung', flags_generic, machine_args_generic]
impl_0x56 = ['Marvell', flags_generic, machine_args_generic]
impl_0x69 = ['Intel', flags_generic, machine_args_generic]
impl_dpaa = ['NXP DPAA', flags_dpaa, machine_args_generic]
impl_dpaa2 = ['NXP DPAA2', flags_dpaa2, machine_args_generic]



> 
> > If we limit lookups to only machine names through primary part number we
> would have a lot of repetitive defines.
> > Also, moving the arrays into the python script is not feasible as
> > meson needs to reparse the standard out from the python script
> 
> I will probably need to write a PoC.

Yes. Please


> 
> > Currently, config is split into three parts :
> > 	1. Implementor specific defines.
> > 	2. Micro-arch specific compiler flags.
> > 	3. Micro-arch specific defines.
> 
> This is currently unreadable in my opinion.

Bit  subjective.
If we want to keep all the fine grained control along with
"native" /"cross" build,  "distribution" build, cache line
differences etc, makes it bit difficult.

But if you think, it can be improved. Please share patch,
We are happy to review and test in  the platforms we have.

> > I think from a configurability point of view the above three are really
> important for fine grained control.
> 
> I agree fine grain is required.
> 
> 
> > Thoughts?
> >
> > Regards,
> > Pavan.
> >
> > >-----Original Message-----
> > >From: Thomas Monjalon <thomas@monjalon.net>
> > >Sent: Sunday, April 14, 2019 2:13 AM
> > >To: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
> > >Cc: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>;
> > >dev@dpdk.org; jerinjacobk@gmail.com; yskoh@mellanox.com;
> > >bruce.richardson@intel.com
> > >Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support
> > >machine specific flags
> > >
> > >13/04/2019 08:24, Jerin Jacob Kollanukkaran:
> > >> > I was not confortable with this patch without being able to say why.
> > >> > Yesterday I spent more time to understand and see what may be
> improved.
> > >> > I agree it is late, so it won't block this patch for 19.05.
> > >> > Do you agree this file can be improved?
> > >>
> > >> Moving to  the all to static config file is an option but we lose
> > >> the flexibility of runtime detecting the options and few of them
> > >> are probing at runtime based on gcc versions and mcpu combination etc.
> > >
> > >I think there is a misunderstanding.
> > >I'm suggesting to symplify arrays by indexing only by machine name.
> > >It should not change the behaviour.
> > >
> > >> I am not expert in meson area and not sure meson/python has better
> > >> data strcture for this other than list/array combo. If Bruce has
> > >> any feedback on this, then we will try to prototype it.
> > >>
> > >> > Please would you like to look at reworking during next cycle?
> > >> > Thanks
> > >
> > >
> >
> >
> 
> 
> 
> 

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Thomas Monjalon]

14/04/2019 20:19, Jerin Jacob Kollanukkaran:
> From: Thomas Monjalon <thomas@monjalon.net>
> > 14/04/2019 16:40, Pavan Nikhilesh Bhagavatula:
> > > Hi Thomas,
> > >
> > > There is no guarantee of primary part number (machine names) uniqueness
> > between implementors.
> > 
> > I think we don't speak the same language :) By machine name, I mean what we
> > set in RTE_MACHINE, like octeontx2.
> 
> As you know, The system probes "implementor_id" and "implementor_pn"
> Values. There is nothing like machine name in meson and in order to keep 
> Synergy with native build, we need to just follow, "implementor_id"
> and "implementor_pn". Now, it is possible to have "implemetor_id" to
> "implementor_pn"  to machine name lookup but Unlike, "make"  based
> Build system, meson supports supporting a lot of machines(like RTE_MACHINE),
> with that structure. So converting to another intermediate called "machine string"
> will have more overhead IMO.

We already have this string with RTE_MACHINE.
You already set RTE_MACHINE based on id and pn.
I don't see any overhead.
Anyway, no need to discuss it more without any real code.

Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags

[Thomas Monjalon]

14/04/2019 20:19, Jerin Jacob Kollanukkaran:
> From: Thomas Monjalon <thomas@monjalon.net>
> > 14/04/2019 16:40, Pavan Nikhilesh Bhagavatula:
> > > Hi Thomas,
> > >
> > > There is no guarantee of primary part number (machine names) uniqueness
> > between implementors.
> > 
> > I think we don't speak the same language :) By machine name, I mean what we
> > set in RTE_MACHINE, like octeontx2.
> 
> As you know, The system probes "implementor_id" and "implementor_pn"
> Values. There is nothing like machine name in meson and in order to keep 
> Synergy with native build, we need to just follow, "implementor_id"
> and "implementor_pn". Now, it is possible to have "implemetor_id" to
> "implementor_pn"  to machine name lookup but Unlike, "make"  based
> Build system, meson supports supporting a lot of machines(like RTE_MACHINE),
> with that structure. So converting to another intermediate called "machine string"
> will have more overhead IMO.

We already have this string with RTE_MACHINE.
You already set RTE_MACHINE based on id and pn.
I don't see any overhead.
Anyway, no need to discuss it more without any real code.

Re: [dpdk-dev] [PATCH v10 1/4] mk: introduce helper to check valid compiler argument

[Thomas Monjalon]

13/04/2019 22:19, jerinj@marvell.com:
> Change history of this series:
> 
> v10 Changes:
> - Fix the following checkpatch warning
> http://mails.dpdk.org/archives/test-report/2019-April/080453.html
> 
> v9 Changes:
>  - Remove compiler version check as it is now done using
>    cc.has_argument().
> 
> v8 Changes:
>  - Remove redudant lists (rebase aritfacts). (Yongseok Koh)
>  
> v7 Changes:
>  - Updated cross compile config files align with 
>  "build: improve pcap dependency handling" changeset to fix build issue with meson
>  - Some compiler needs the following depended patch to compile with meson
>    http://patches.dpdk.org/patch/52367/

Applied, thanks

Re: [dpdk-dev] [PATCH v10 1/4] mk: introduce helper to check valid compiler argument

[Thomas Monjalon]

13/04/2019 22:19, jerinj@marvell.com:
> Change history of this series:
> 
> v10 Changes:
> - Fix the following checkpatch warning
> http://mails.dpdk.org/archives/test-report/2019-April/080453.html
> 
> v9 Changes:
>  - Remove compiler version check as it is now done using
>    cc.has_argument().
> 
> v8 Changes:
>  - Remove redudant lists (rebase aritfacts). (Yongseok Koh)
>  
> v7 Changes:
>  - Updated cross compile config files align with 
>  "build: improve pcap dependency handling" changeset to fix build issue with meson
>  - Some compiler needs the following depended patch to compile with meson
>    http://patches.dpdk.org/patch/52367/

Applied, thanks