From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id D436CA0096 for ; Thu, 11 Apr 2019 08:08:51 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 582825F0F; Thu, 11 Apr 2019 08:08:50 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 7AF815F0D for ; Thu, 11 Apr 2019 08:08:48 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x3B68gN6027116; Wed, 10 Apr 2019 23:08:47 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : references : in-reply-to : content-type : content-transfer-encoding : mime-version; s=pfpt0818; bh=YVqo/k2u+7epxcOAAlXf0+1PfekWk6aTCb9xftIv7XU=; b=QamwNUJZGOoOH5u6GQvMfQgajEdEQpXJJE7LG+LPR9WV05T+IQrtivXICplGRkm2O9g1 e36rfqK5ay8Kl69U0pt1NqZj13WBFkIclClnHvopleM5fy7qzXS0hbePRA+sUTe2pT4T 2rfcPgAGLQavSdfuH9vk8khlwsksmElHRw2fxZE9gV5Ea5R4QnkX1oXs2gkVCDKOTUNn EQhcTWlaqE/fQl6rNSALHyOFgL/lW3nxhS+Oe75ZWmVkGfU5gLXnfI6H/xnJMWzk3Nzi O//0IBpxgBcGigqDjUu4ITVsKulZqVoJLS/N+8AVmnjNJaazQoiPuVxra6TKFUIRSzRm Dw== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0b-0016f401.pphosted.com with ESMTP id 2rshba387k-7 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 10 Apr 2019 23:08:47 -0700 Received: from SC-EXCH04.marvell.com (10.93.176.84) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Wed, 10 Apr 2019 23:07:29 -0700 Received: from NAM01-BY2-obe.outbound.protection.outlook.com (104.47.34.53) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3 via Frontend Transport; Wed, 10 Apr 2019 23:07:29 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.onmicrosoft.com; s=selector1-marvell-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=YVqo/k2u+7epxcOAAlXf0+1PfekWk6aTCb9xftIv7XU=; b=iT97WTrS4WAFtUj6yu8sckHDeX47QOrFziFVyCvXSx6m2g+nv4A9T8F0ScV+ZdbrxsaWjBfdfIhp+kVkv6FEkwm2Wptf/wa2TAPlnl4UN/pSKXukz69RoQYybZMOlWrZ8FzknqbUjjOeftXtEjhDeMNfIgQtxC3XJii25CqorQk= Received: from CY4PR1801MB1863.namprd18.prod.outlook.com (10.171.255.14) by CY4PR1801MB1829.namprd18.prod.outlook.com (10.171.254.162) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1771.21; Thu, 11 Apr 2019 06:07:28 +0000 Received: from CY4PR1801MB1863.namprd18.prod.outlook.com ([fe80::e980:fa09:c83a:851d]) by CY4PR1801MB1863.namprd18.prod.outlook.com ([fe80::e980:fa09:c83a:851d%3]) with mapi id 15.20.1792.016; Thu, 11 Apr 2019 06:07:28 +0000 From: Pavan Nikhilesh Bhagavatula To: Yongseok Koh CC: Thomas Monjalon , dev , "Jerin Jacob Kollanukkaran" , "jerinjacobk@gmail.com" Thread-Topic: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags Thread-Index: AQHU78QiWKBsQk+ax0us2CHi4TSrFaY2dY2A Date: Thu, 11 Apr 2019 06:07:28 +0000 Message-ID: References: <20190406142737.20091-1-jerinj@marvell.com> <20190410161400.9361-1-jerinj@marvell.com> <20190410161400.9361-2-jerinj@marvell.com> <6CED2209-E8A8-4141-869E-4505DC42CC58@mellanox.com> In-Reply-To: <6CED2209-E8A8-4141-869E-4505DC42CC58@mellanox.com> Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [122.167.234.147] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: c5fcf035-87ce-4199-d0ac-08d6be43f9c8 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600139)(711020)(4605104)(2017052603328)(7193020); SRVR:CY4PR1801MB1829; x-ms-traffictypediagnostic: CY4PR1801MB1829: x-microsoft-antispam-prvs: x-forefront-prvs: 00046D390F x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(396003)(366004)(39860400002)(376002)(136003)(189003)(51914003)(199004)(13464003)(53936002)(74316002)(7696005)(7736002)(316002)(97736004)(54906003)(305945005)(78486014)(99286004)(3846002)(229853002)(6116002)(53546011)(186003)(93886005)(86362001)(446003)(76176011)(6506007)(476003)(11346002)(102836004)(26005)(478600001)(105586002)(66066001)(8936002)(106356001)(486006)(33656002)(5660300002)(71190400001)(6436002)(14454004)(2906002)(81166006)(6916009)(55016002)(25786009)(256004)(8676002)(68736007)(52536014)(4326008)(81156014)(6246003)(9686003)(71200400001); DIR:OUT; SFP:1101; SCL:1; SRVR:CY4PR1801MB1829; H:CY4PR1801MB1863.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: kfZ/Zhg9BZS7rEIx3iTTYakpZbC544y54cECc0i9/c71vs4rviwhPAFH2q7zp3dNMFi1Y9PlrwwjW87Me+DNyYKeZksqPfmu3kQnLDwbINrAxgdqsOzETSoptsVJSnTk6d6BtlZIJpSaZOTynNWdALzfI97Se2GPBeWoeLDefN2gi8qKn20KafV2rfOhApZ/Oumk9qCqbL05y+NrXlmHJThuekfJWRXRjgBy/ja2TituFqxx5dsvisVOmwGY7b6QtSiSGc5D0AQs/1Wkynn/doMLyOfdwr4iB3ZdInxMQ3xioBVNuNP9RkEOxbmzEmn2a8pNljQlhedC+Vy3P8Yg377/+znUoCiLVp1F2jVZeArbMf6suYQ501akZT2lILxQh0/FmwknOYCpuYQcx/m/DyiP7ASZKnXueihu41c7JJA= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: c5fcf035-87ce-4199-d0ac-08d6be43f9c8 X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Apr 2019 06:07:28.0996 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR1801MB1829 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-04-11_04:, , signatures=0 Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190411060728.FZUZzRbDW4cbyH5kPrkEEVXo1irhe9YOyPOo-YjuJso@z> Hi Yongseok, >-----Original Message----- >From: Yongseok Koh >Sent: Wednesday, April 10, 2019 11:08 PM >To: Pavan Nikhilesh Bhagavatula >Cc: Thomas Monjalon ; dev ; Jerin >Jacob Kollanukkaran ; jerinjacobk@gmail.com >Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support >machine specific flags > >External Email > >---------------------------------------------------------------------- > >> On Apr 10, 2019, at 9:13 AM, jerinjacobk@gmail.com wrote: >> >> From: Pavan Nikhilesh >> >> Currently, RTE_* flags are set based on the implementer ID but there >> might be some micro arch specific differences from the same vendor eg. >> CACHE_LINESIZE. Add support to set micro arch specific flags. >> >> Signed-off-by: Pavan Nikhilesh >> Signed-off-by: Jerin Jacob >> --- >> config/arm/meson.build | 56 ++++++++++++++++++++++++------------------ >> 1 file changed, 32 insertions(+), 24 deletions(-) >> >> diff --git a/config/arm/meson.build b/config/arm/meson.build index >> 170a4981a..24bce2b39 100644 >> --- a/config/arm/meson.build >> +++ b/config/arm/meson.build >> @@ -7,25 +7,6 @@ march_opt =3D '-march=3D@0@'.format(machine) >> >> arm_force_native_march =3D false >> >> -machine_args_generic =3D [ >> - ['default', ['-march=3Darmv8-a+crc+crypto']], >> - ['native', ['-march=3Dnative']], >> - ['0xd03', ['-mcpu=3Dcortex-a53']], >> - ['0xd04', ['-mcpu=3Dcortex-a35']], >> - ['0xd05', ['-mcpu=3Dcortex-a55']], >> - ['0xd07', ['-mcpu=3Dcortex-a57']], >> - ['0xd08', ['-mcpu=3Dcortex-a72']], >> - ['0xd09', ['-mcpu=3Dcortex-a73']], >> - ['0xd0a', ['-mcpu=3Dcortex-a75']], >> - ['0xd0b', ['-mcpu=3Dcortex-a76']], >> -] >> -machine_args_cavium =3D [ >> - ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], >> - ['native', ['-march=3Dnative']], >> - ['0xa1', ['-mcpu=3Dthunderxt88']], >> - ['0xa2', ['-mcpu=3Dthunderxt81']], >> - ['0xa3', ['-mcpu=3Dthunderxt83']]] >> - >> flags_common_default =3D [ >> # Accelarate rte_memcpy. Be sure to run unit test >(memcpy_perf_autotest) >> # to determine the best threshold in code. Refer to notes in source >> file @@ -52,12 +33,10 @@ flags_generic =3D [ >> ['RTE_USE_C11_MEM_MODEL', true], >> ['RTE_CACHE_LINE_SIZE', 128]] >> flags_cavium =3D [ >> - ['RTE_MACHINE', '"thunderx"'], >> ['RTE_CACHE_LINE_SIZE', 128], >> ['RTE_MAX_NUMA_NODES', 2], >> ['RTE_MAX_LCORE', 96], >> - ['RTE_MAX_VFIO_GROUPS', 128], >> - ['RTE_USE_C11_MEM_MODEL', false]] >> + ['RTE_MAX_VFIO_GROUPS', 128]] >> flags_dpaa =3D [ >> ['RTE_MACHINE', '"dpaa"'], >> ['RTE_USE_C11_MEM_MODEL', true], >> @@ -71,6 +50,27 @@ flags_dpaa2 =3D [ >> ['RTE_MAX_NUMA_NODES', 1], >> ['RTE_MAX_LCORE', 16], >> ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] >> +flags_default_extra =3D [] >> +flags_thunderx_extra =3D [ >> + ['RTE_MACHINE', '"thunderx"'], >> + ['RTE_USE_C11_MEM_MODEL', false]] >> + >> +machine_args_generic =3D [ >> + ['default', ['-march=3Darmv8-a+crc+crypto']], >> + ['native', ['-march=3Dnative']], >> + ['0xd03', ['-mcpu=3Dcortex-a53']], >> + ['0xd04', ['-mcpu=3Dcortex-a35']], >> + ['0xd07', ['-mcpu=3Dcortex-a57']], >> + ['0xd08', ['-mcpu=3Dcortex-a72']], >> + ['0xd09', ['-mcpu=3Dcortex-a73']], >> + ['0xd0a', ['-mcpu=3Dcortex-a75']]] >> + >> +machine_args_cavium =3D [ >> + ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], >> + ['native', ['-march=3Dnative']], >> + ['0xa1', ['-mcpu=3Dthunderxt88'], flags_thunderx_extra], >> + ['0xa2', ['-mcpu=3Dthunderxt81'], flags_thunderx_extra], >> + ['0xa3', ['-mcpu=3Dthunderxt83'], flags_thunderx_extra]] >> >> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page >> G7-5321) impl_generic =3D ['Generic armv8', flags_generic, >> machine_args_generic] @@ -157,8 +157,16 @@ else >> endif >> foreach marg: machine[2] >> if marg[0] =3D=3D impl_pn >> - foreach f: marg[1] >> - machine_args +=3D f >> + foreach flag: marg[1] >> + if cc.has_argument(flag) >> + machine_args +=3D flag >> + endif >> + endforeach >> + # Apply any extra machine specific flags. >> + foreach flag: marg.get(2, flags_default_extra) >> + if flag.length() > 0 >> + dpdk_conf.set(flag[0], flag[1]) >> + endif > >Let me continue the discussion from v7 here. >Seems I wan't clear enough. > >Let me take an example. If the host is thunderx2 (0xaf) and compiler is ol= der >than v7, flags_thunderx2_extra isn't set. This means, for example, >RTE_CACHE_LINE_SIZE will still be 128. Is that what you want? >RTE_CACHE_LINE_SIZE has nothing to do with compiler support and you might >want to set it regardless of gcc version. You could skip setting -mcpu wit= h setting >the extra flags. > Thanks for the detailed explanation. I think since we have the check to skip mcpu flag when cc doesn't support i= t (cc.has_argument(flag)) It will be safe to remove=20 ` # Primary part number based mcpu flags are supported # for gcc versions > 7 if cc.version().version_compare( '<7.0') or cmd_output.length() =3D=3D 0 if not meson.is_cross_build() and arm_force_native_march = =3D=3D true impl_pn =3D 'native' else impl_pn =3D 'default' endif endif ` The command output check can also be removed as it is handled when calling = the command script itself. Thoughts? PS. I think the safest way to set CACHELINE_SIZE is to read the cache type = register[1] but sadly only few latest kernels=20 have the support through sysfs (/sys/devices/system/cpu/cpu0/cache/index0/c= oherency_line_size)=20 >Thoughts? > >Thanks, >Yongseok > > > Regards, Pavan.