From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: <dev-bounces@dpdk.org> Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 9D1CBA0096 for <public@inbox.dpdk.org>; Sat, 13 Apr 2019 01:25:23 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2EED71B42B; Sat, 13 Apr 2019 01:25:13 +0200 (CEST) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 525041B13B for <dev@dpdk.org>; Sat, 13 Apr 2019 01:25:07 +0200 (CEST) Received: from Internal Mail-Server by MTLPINE1 (envelope-from yskoh@mellanox.com) with ESMTPS (AES256-SHA encrypted); 13 Apr 2019 02:25:02 +0300 Received: from mtibiz05-l.mti.labs.mlnx. (mtibiz05-l.mti.labs.mlnx [10.20.10.109]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id x3CNOrWH006596; Sat, 13 Apr 2019 02:24:59 +0300 From: Yongseok Koh <yskoh@mellanox.com> To: bruce.richardson@intel.com, jerinj@marvell.com, pbhagavatula@marvell.com, shahafs@mellanox.com Cc: dev@dpdk.org, thomas@monjalon.net, gavin.hu@arm.com, Honnappa.Nagarahalli@arm.com Date: Fri, 12 Apr 2019 16:24:47 -0700 Message-Id: <20190412232451.30197-3-yskoh@mellanox.com> X-Mailer: git-send-email 2.21.0.196.g041f5ea In-Reply-To: <20190412232451.30197-1-yskoh@mellanox.com> References: <20190412232451.30197-1-yskoh@mellanox.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH 2/6] meson: change default cache line size for cortex-a72 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org> Content-Type: text/plain; charset="UTF-8" Message-ID: <20190412232447.5EizYNzmEhvTK6L_MVzEi5CMSnSQ05OI9XWfL2VmUnc@z> Per the email discussion [1], the default cache line size of armv8 cortex-a72 is changed to 64 bytes. [1] https://mails.dpdk.org/archives/dev/2019-January/123218.html Signed-off-by: Yongseok Koh <yskoh@mellanox.com> --- config/arm/meson.build | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index e00b894523..73c581948c 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -51,6 +51,8 @@ flags_dpaa2 = [ ['RTE_MAX_LCORE', 16], ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] flags_default_extra = [] +flags_cortex_a72_extra = [ + ['RTE_CACHE_LINE_SIZE', 64]] flags_thunderx_extra = [ ['RTE_MACHINE', '"thunderx"'], ['RTE_USE_C11_MEM_MODEL', false]] @@ -73,7 +75,7 @@ machine_args_generic = [ ['0xd03', ['-mcpu=cortex-a53']], ['0xd04', ['-mcpu=cortex-a35']], ['0xd07', ['-mcpu=cortex-a57']], - ['0xd08', ['-mcpu=cortex-a72']], + ['0xd08', ['-mcpu=cortex-a72'], flags_cortex_a72_extra], ['0xd09', ['-mcpu=cortex-a73']], ['0xd0a', ['-mcpu=cortex-a75']]] -- 2.21.0.196.g041f5ea