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DIR:OUT; SFP:1101; SCL:1; SRVR:VE1PR08MB4861; H:VE1PR08MB5149.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: wsMzu559yjdORleaaOYy4Y2xnJjHhP/dnwSi9Q42B2knJ6/7WGxg+RJYk3Ymcu5MHhPk/PTeziwnAay7f78bcmhJ5LsCtqCfxLxHNZjtNcUyUVjusGKZUg1VAvqFABkWA8lJZJTXqD39lQWU5n0VNjojHQaXhwomHyLZLrnu2WXGwiqTkTBgXXQk7IdZpQe1fNtNISUckzTc+amiJIznBzJGLo1gEUpWtpbHASPVIejHNlE4ooBTPgIz5rRT38VNGUPsF55rn8B+dERUhfWo0LGosiR3QlbEe+Rze7eSG1unRRfgjoWlUX4KTXlRI8L/+qjgNwC1nf5GLnF5MKfnQSBFhHw2/asmRWQMee15jRVpPf8EEAPh3mtXKk/d25a3WRqEAfeBKiZTED4gvWvjPhe43COh/qRgvaC1Qu47Sjo= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 86d27d54-c1ff-46e3-b929-08d6c15bcfc6 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Apr 2019 04:35:39.0014 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR08MB4861 Subject: Re: [dpdk-dev] [EXT] [PATCH 2/6] meson: change default cache line size for cortex-a72 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190415043538.I5gYTItcUIkUPq9v8y1y_atlIbuXh2sS5B0kOGUpEaY@z> > > > > ---------------------------------------------------------------------- > > Per the email discussion [1], the default cache line size of armv8 > > cortex-a72 is changed to 64 bytes. >=20 > IMO, In git commit you remove the reference to specific discussion and > Update the reason correctly. >=20 >=20 > > > > [1] https://mails.dpdk.org/archives/dev/2019-January/123218.html > > > > Signed-off-by: Yongseok Koh > > --- > > config/arm/meson.build | 4 +++- > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > diff --git a/config/arm/meson.build b/config/arm/meson.build index > > e00b894523..73c581948c 100644 > > --- a/config/arm/meson.build > > +++ b/config/arm/meson.build > > @@ -51,6 +51,8 @@ flags_dpaa2 =3D [ > > ['RTE_MAX_LCORE', 16], > > ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] flags_default_extra > =3D [] > > +flags_cortex_a72_extra =3D [ > > + ['RTE_CACHE_LINE_SIZE', 64]] > > flags_thunderx_extra =3D [ Which tree does this patch apply to? I do not see the above line in master. > > ['RTE_MACHINE', '"thunderx"'], > > ['RTE_USE_C11_MEM_MODEL', false]] > > @@ -73,7 +75,7 @@ machine_args_generic =3D [ > > ['0xd03', ['-mcpu=3Dcortex-a53']], > > ['0xd04', ['-mcpu=3Dcortex-a35']], > > ['0xd07', ['-mcpu=3Dcortex-a57']], > > - ['0xd08', ['-mcpu=3Dcortex-a72']], > > + ['0xd08', ['-mcpu=3Dcortex-a72'], flags_cortex_a72_extra], > > ['0xd09', ['-mcpu=3Dcortex-a73']], > > ['0xd0a', ['-mcpu=3Dcortex-a75']]] >=20 > I think, flags_cortex_a72_extra() can be changed to > flags_vendor_arm_extra or something similar And update the following > CPUs also not just cortex-a72. >=20 Why not add 'flags_arm' similar to flags_dpaa2/flag_cavium etc? All the lis= ted Arm cores are 64B cache line size. > ['0xd03', ['-mcpu=3Dcortex-a53']], > ['0xd04', ['-mcpu=3Dcortex-a35']], > ['0xd05', ['-mcpu=3Dcortex-a55']], > ['0xd07', ['-mcpu=3Dcortex-a57']], > ['0xd08', ['-mcpu=3Dcortex-a72']], > ['0xd09', ['-mcpu=3Dcortex-a73']], > ['0xd0a', ['-mcpu=3Dcortex-a75']], > ['0xd0b', ['-mcpu=3Dcortex-a76']], >=20 >=20 > > > > -- > > 2.21.0.196.g041f5ea