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From: "Ruifeng Wang (Arm Technology China)" <Ruifeng.Wang@arm.com>
To: "Shreyansh.jain@nxp.com" <shreyansh.jain@nxp.com>,
	"Ananyev, Konstantin" <konstantin.ananyev@intel.com>,
	"dev@dpdk.org" <dev@dpdk.org>
Cc: nd <nd@arm.com>, nd <nd@arm.com>
Subject: Re: [dpdk-dev] [PATCH] examples/l3fwd: support separate buffer pool per	port
Date: Mon, 15 Apr 2019 07:58:15 +0000	[thread overview]
Message-ID: <AM6PR08MB37823191E9AC34CE2A865BAE9E2B0@AM6PR08MB3782.eurprd08.prod.outlook.com> (raw)
Message-ID: <20190415075815.xokk2xCjNCyP9438Y0BuNh3O7dbJlSzCQFvJ6SdftZg@z> (raw)
In-Reply-To: <VI1PR04MB46883416218659A038683249902B0@VI1PR04MB4688.eurprd04.prod.outlook.com>

Hi Shreyansh,

> -----Original Message-----
> From: Shreyansh Jain <shreyansh.jain@nxp.com>
> Sent: Monday, April 15, 2019 14:48
> To: Ruifeng Wang (Arm Technology China) <Ruifeng.Wang@arm.com>;
> Ananyev, Konstantin <konstantin.ananyev@intel.com>; dev@dpdk.org
> Cc: nd <nd@arm.com>; nd <nd@arm.com>
> Subject: RE: [dpdk-dev] [PATCH] examples/l3fwd: support separate buffer
> pool per port
> 
> Hi Ruifeng,
> 
> [...]
> 
> > >
> > > For hardware backed pools, hardware access and exclusion are
> > expensive. By
> > > segregating pool/port/lcores it is possible to attain a conflict free
> > path. This is
> > > the use-case this patch targets.
> > > And anyways, this is an optional feature.
> > >
> > > > Konstantin
> > > >
> > > > > In dual core test, both modes had nearly same performance.
> > >
> > > OK
> > >
> > > > >
> > > > > My setup only has two ports which is limited.
> > > > > Just want to know the per-port-pool mode has more performance
> gain
> > > > when many ports are bound to  different cores?
> > >
> > > Yes, though not necessarily *many* - in my case, I had 4 ports and
> > even then
> > > about ~10% improvement was directly visible. I increased the port
> > count and
> > > I was able to touch about ~15%. I did pin each port to a separate
> > core, though.
> > > But again, important point is that without this feature enabled, I
> > didn't see
> > > any drop in performance. Did you observe any drop?
> > >
> >
> > No, no drop without the feature enabled in my test.
> 
> So, in case this is an optional feature, it should be fine, right?
> (Obviously, assuming that my logical implementation is correct)
> 
> At my end also, I saw no drop in performance without this feature (Default)
> and a decent increase with this (with separate port-core combination) on
> NXP platform.
> 
> [...]

Tested on LS2088A and observed 12% performance gain when 4 ports were used.
I think sample_app_ug document should be updated to add the new option.
Acked-by: Ruifeng Wang <ruifeng.wang@arm.com>

Regards,
/Ruifeng

  parent reply	other threads:[~2019-04-15  7:58 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-15  6:48 Shreyansh Jain
2019-04-15  6:48 ` Shreyansh Jain
2019-04-15  7:58 ` Ruifeng Wang (Arm Technology China) [this message]
2019-04-15  7:58   ` Ruifeng Wang (Arm Technology China)
  -- strict thread matches above, loose matches on Subject: below --
2019-04-16 16:00 Shreyansh Jain
2019-04-16 16:00 ` Shreyansh Jain
2019-04-17 11:21 ` Ananyev, Konstantin
2019-04-17 11:21   ` Ananyev, Konstantin
2019-04-16 12:47 Shreyansh Jain
2019-04-16 12:47 ` Shreyansh Jain
2019-04-16 12:54 ` Ananyev, Konstantin
2019-04-16 12:54   ` Ananyev, Konstantin
2019-04-15 10:29 Shreyansh Jain
2019-04-15 10:29 ` Shreyansh Jain
2019-01-03 11:30 Shreyansh Jain
2019-04-04 11:54 ` Hemant Agrawal
2019-04-04 11:54   ` Hemant Agrawal
2019-04-08  6:10 ` Ruifeng Wang (Arm Technology China)
2019-04-08  6:10   ` Ruifeng Wang (Arm Technology China)
2019-04-08  9:29   ` Ananyev, Konstantin
2019-04-08  9:29     ` Ananyev, Konstantin
2019-04-12  9:24     ` Shreyansh Jain
2019-04-12  9:24       ` Shreyansh Jain
2019-04-14  9:13       ` Ruifeng Wang (Arm Technology China)
2019-04-14  9:13         ` Ruifeng Wang (Arm Technology China)
2019-04-15 12:05       ` Ananyev, Konstantin
2019-04-15 12:05         ` Ananyev, Konstantin

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