From: "Ananyev, Konstantin" <konstantin.ananyev@intel.com>
To: Shreyansh Jain <shreyansh.jain@nxp.com>,
"Ruifeng Wang (Arm Technology China)" <Ruifeng.Wang@arm.com>,
"dev@dpdk.org" <dev@dpdk.org>
Cc: nd <nd@arm.com>
Subject: Re: [dpdk-dev] [PATCH] examples/l3fwd: support separate buffer pool per port
Date: Mon, 15 Apr 2019 12:05:20 +0000 [thread overview]
Message-ID: <2601191342CEEE43887BDE71AB9772580148A97E0F@irsmsx105.ger.corp.intel.com> (raw)
Message-ID: <20190415120520.E5oOllRAdsnRFyKQ3nMVjuomuzlmjELX1gFZz3R4Lv8@z> (raw)
In-Reply-To: <VI1PR04MB4688AD1C0B617DEC35668C5E90280@VI1PR04MB4688.eurprd04.prod.outlook.com>
Hi Shreyansh,
> > > I tried this patch on MacchiatoBin + 82599 NIC.
> > > Compared with global-pool mode, per-port-pool mode showed slightly
> > lower performance in single core test.
> >
> > That was my thought too - for the case when queues from multiple ports
> > are handled by the same core
> > it probably would only slowdown things.
>
> Thanks for your comments.
>
> This is applicable for cases where separate cores can handle separate ports - each with their pools. (somehow I felt that message in commit
> was adequate - I can rephrase if that is misleading)
>
> In case there is enough number of cores available for datapath, such segregation can result in better performance - possibly because of
> drop in pool and cache conflicts.
> At least on some of NXP SoC, this resulted in over 15% improvement.
> And, in other cases it didn't lead to any drop/negative-impact.
If each core manages just one port, then yes definitely performance increase is expected.
If that's the case you'd like enable, then can I suggest to have mempool per lcore not per port?
I think it would be plausible for both cases:
- one port per core (your case).
- multiple ports per core.
Konstantin
>
> > Wonder what is the use case for the patch and what is the performance
> > gain you observed?
>
> For hardware backed pools, hardware access and exclusion are expensive. By segregating pool/port/lcores it is possible to attain a conflict
> free path. This is the use-case this patch targets.
> And anyways, this is an optional feature.
>
> > Konstantin
> >
> > > In dual core test, both modes had nearly same performance.
>
> OK
>
> > >
> > > My setup only has two ports which is limited.
> > > Just want to know the per-port-pool mode has more performance gain
> > when many ports are bound to different cores?
>
> Yes, though not necessarily *many* - in my case, I had 4 ports and even then about ~10% improvement was directly visible. I increased the
> port count and I was able to touch about ~15%. I did pin each port to a separate core, though.
> But again, important point is that without this feature enabled, I didn't see any drop in performance. Did you observe any drop?
>
> > >
> > > Used commands:
> > > sudo ./examples/l3fwd/build/l3fwd -c 0x4 -w 0000:01:00.0 -w
> > 0000:01:00.1 -- -P -p 3 --config='(0,0,2),(1,0,2)' --per-port-pool
> > > sudo ./examples/l3fwd/build/l3fwd -c 0xc -w 0000:01:00.0 -w
> > 0000:01:00.1 -- -P -p 3 --config='(0,0,2),(1,0,3)' --per-port-pool
> > >
> > > Regards,
> > > /Ruifeng
> > >
>
> [...]
next prev parent reply other threads:[~2019-04-15 12:05 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-03 11:30 Shreyansh Jain
2019-04-04 11:54 ` Hemant Agrawal
2019-04-04 11:54 ` Hemant Agrawal
2019-04-08 6:10 ` Ruifeng Wang (Arm Technology China)
2019-04-08 6:10 ` Ruifeng Wang (Arm Technology China)
2019-04-08 9:29 ` Ananyev, Konstantin
2019-04-08 9:29 ` Ananyev, Konstantin
2019-04-12 9:24 ` Shreyansh Jain
2019-04-12 9:24 ` Shreyansh Jain
2019-04-14 9:13 ` Ruifeng Wang (Arm Technology China)
2019-04-14 9:13 ` Ruifeng Wang (Arm Technology China)
2019-04-15 12:05 ` Ananyev, Konstantin [this message]
2019-04-15 12:05 ` Ananyev, Konstantin
2019-04-25 9:40 ` [dpdk-dev] [PATCH v2] " Shreyansh Jain
2019-04-25 9:40 ` Shreyansh Jain
2019-05-02 23:22 ` Thomas Monjalon
2019-05-02 23:22 ` Thomas Monjalon
2019-04-15 6:48 [dpdk-dev] [PATCH] " Shreyansh Jain
2019-04-15 6:48 ` Shreyansh Jain
2019-04-15 7:58 ` Ruifeng Wang (Arm Technology China)
2019-04-15 7:58 ` Ruifeng Wang (Arm Technology China)
2019-04-15 10:29 Shreyansh Jain
2019-04-15 10:29 ` Shreyansh Jain
2019-04-16 12:47 Shreyansh Jain
2019-04-16 12:47 ` Shreyansh Jain
2019-04-16 12:54 ` Ananyev, Konstantin
2019-04-16 12:54 ` Ananyev, Konstantin
2019-04-16 16:00 Shreyansh Jain
2019-04-16 16:00 ` Shreyansh Jain
2019-04-17 11:21 ` Ananyev, Konstantin
2019-04-17 11:21 ` Ananyev, Konstantin
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