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DIR:OUT; SFP:1101; SCL:1; SRVR:VE1PR08MB4800; H:VE1PR08MB5149.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: UJP8mCGnFkcuhuN7gaL3wWSG0dDdi/MeSn5PDQdvFaCn7GltOgr7KSp9Hbm0H2V/R6zPsv9PGmm6TMQwmE85xwdC5eilsmyHMT4kr5v5al6CjN9Qw7LH1gjGBH5Lb/IFy+mzZDijv1Ly8i6iTkJ+ZrCOGT/ByL7vwP/4moZz2vpDhdWzImhrsH0fAFnHawIoBL6pGkTMtd/iMlZNkKB24DcOQ2VBIlwNUic01N2y7a3ddyt1Z6Db7lccF00kC7S6Ajwq98zmGSiDWLDheJME2p0nOsnRXvZBxrIwpMuOky438N8ZIvNgZRf004Pmz0+0S2nx+ZyC4aMja1lTRgRS+QPwqmMyqF4rS1wN02wDq2tCo8xJaNmD86KDROrx12QmZgCgbpikIjPEbRIHsBavxvv0tLGz5izYYr7eARefk2E= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9f766f53-116a-4ca1-a0f9-08d6c1e32e71 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Apr 2019 20:44:39.9158 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR08MB4800 Subject: Re: [dpdk-dev] [EXT] [PATCH 2/6] meson: change default cache line size for cortex-a72 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190415204439.n42wDOC5OWbclGX5JrIaQD_w-S_LIxIoImpjT80-XSI@z> > > > >> > >>>> > >>>> ------------------------------------------------------------------- > >>>> - > >>>> -- Per the email discussion [1], the default cache line size of > >>>> armv8 > >>>> cortex-a72 is changed to 64 bytes. > >>> > >>> IMO, In git commit you remove the reference to specific discussion > >>> and Update the reason correctly. > >>> > >>> > >>>> > >>>> [1] > >>>> > https://eur03.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fm > >>>> ails.dpdk.org%2Farchives%2Fdev%2F2019- > January%2F123218.html&dat > >>>> > a=3D02%7C01%7Cyskoh%40mellanox.com%7C4c0cdd9535c84c8dd3c008d6c1a > 7f5eb > >>>> %7Ca652971c7d2e4d9ba6a4d149256f461b%7C0%7C0%7C6369093244 > 74698429&am > >>>> > p;sdata=3DUJO2lBtnYWSs5ud8CsAL7oGXH571f6zGjrVmP2SRChw%3D&re > served > >>>> =3D0 > >>>> > >>>> Signed-off-by: Yongseok Koh > >>>> --- > >>>> config/arm/meson.build | 4 +++- > >>>> 1 file changed, 3 insertions(+), 1 deletion(-) > >>>> > >>>> diff --git a/config/arm/meson.build b/config/arm/meson.build index > >>>> e00b894523..73c581948c 100644 > >>>> --- a/config/arm/meson.build > >>>> +++ b/config/arm/meson.build > >>>> @@ -51,6 +51,8 @@ flags_dpaa2 =3D [ > >>>> ['RTE_MAX_LCORE', 16], > >>>> ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] flags_default_extra > >>> =3D [] > >>>> +flags_cortex_a72_extra =3D [ > >>>> + ['RTE_CACHE_LINE_SIZE', 64]] > >>>> flags_thunderx_extra =3D [ > >> Which tree does this patch apply to? I do not see the above line in > master. > > Please ignore this comment, I missed the dependency provided in 0/6 > > > >> > >>>> ['RTE_MACHINE', '"thunderx"'], > >>>> ['RTE_USE_C11_MEM_MODEL', false]] > >>>> @@ -73,7 +75,7 @@ machine_args_generic =3D [ > >>>> ['0xd03', ['-mcpu=3Dcortex-a53']], > >>>> ['0xd04', ['-mcpu=3Dcortex-a35']], > >>>> ['0xd07', ['-mcpu=3Dcortex-a57']], > >>>> - ['0xd08', ['-mcpu=3Dcortex-a72']], > >>>> + ['0xd08', ['-mcpu=3Dcortex-a72'], flags_cortex_a72_extra], > >>>> ['0xd09', ['-mcpu=3Dcortex-a73']], > >>>> ['0xd0a', ['-mcpu=3Dcortex-a75']]] > >>> > >>> I think, flags_cortex_a72_extra() can be changed to > >>> flags_vendor_arm_extra or something similar And update the > following > >>> CPUs also not just cortex-a72. > >>> > >> Why not add 'flags_arm' similar to flags_dpaa2/flag_cavium etc? All > >> the listed Arm cores are 64B cache line size. >=20 > If so, I'd take your approach - flags_arm. > If we have an exception (CL size is 128 for some cpu) someday, then we > can add an extra flag for that. >=20 Agree. I see the likelihood to be slim given the list of CPUs with 64B > > Just to complete the thought, impl_0x41 can use 'flags_arm' instead of > 'flags_generic'. IMO, current use of 'flags_generic' in impl_0x41 is inco= rrect. > > > >> > >>> ['0xd03', ['-mcpu=3Dcortex-a53']], > >>> ['0xd04', ['-mcpu=3Dcortex-a35']], > >>> ['0xd05', ['-mcpu=3Dcortex-a55']], > >>> ['0xd07', ['-mcpu=3Dcortex-a57']], > >>> ['0xd08', ['-mcpu=3Dcortex-a72']], > >>> ['0xd09', ['-mcpu=3Dcortex-a73']], > >>> ['0xd0a', ['-mcpu=3Dcortex-a75']], > >>> ['0xd0b', ['-mcpu=3Dcortex-a76']], > >>> > >>> > >>>> > >>>> -- > >>>> 2.21.0.196.g041f5ea > >