From: "Ananyev, Konstantin" <konstantin.ananyev@intel.com>
To: Shreyansh Jain <shreyansh.jain@nxp.com>,
"Ruifeng Wang (Arm Technology China)" <Ruifeng.Wang@arm.com>,
"dev@dpdk.org" <dev@dpdk.org>
Cc: nd <nd@arm.com>
Subject: Re: [dpdk-dev] [PATCH] examples/l3fwd: support separate buffer pool per port
Date: Wed, 17 Apr 2019 11:21:59 +0000 [thread overview]
Message-ID: <2601191342CEEE43887BDE71AB9772580148A98E25@irsmsx105.ger.corp.intel.com> (raw)
Message-ID: <20190417112159.VTDwUNRfUzo2OS0ISoQqcXVHJJcUASpvH_iutwahDaw@z> (raw)
In-Reply-To: <VI1PR04MB46882E992789C61F624A8DCC90240@VI1PR04MB4688.eurprd04.prod.outlook.com>
Hi
> > > As you have stated below, it's just the same thing with two different
> > views.
> > >
> > > > I think it would be plausible for both cases:
> > > > - one port per core (your case).
> > > > - multiple ports per core.
> > >
> > > Indeed. For this particular patch, I just chose the first one.
> > Probably because that is the most general use-case I come across.
> > > I am sure the second too has equal number of possible use-cases - but
> > probably someone with access to that kind of scenario would be
> > > better suited for validating what is the performance increase.
> > > Do you think it would be OK to have that in and then sometime in
> > future enable the second option?
> >
> > What I am trying to say - if we'll have mempool per lcore (not per
> > port),
> > then it would cover both cases above.
> > So wouldn't need to make extra changes.
> > Konstantin
>
> What you are suggesting would end up as 1:N mapping of port:pool (when multiple queues are being used for a port, each affined to
> different core).
Yes.
Probably there is some misunderstanding from my part.
From your previous mail:
"This is applicable for cases where separate cores can handle separate
ports - each with their pools. (somehow I felt that message in commit
was adequate - I can rephrase if that is misleading)"
I made a conclusion (probably wrong)
that the only config you are interested (one that shows performance improvement):
when all queues of each port is managed by the same core and
each core manages only one port.
From that perspective - it doesn't matter would we have pool per core or per port -
we will still end-up with a separate pool per port (and core).
But probably that conclusion was wrong.
> In my observation, or rather the cases I generally see, that would end up reducing performance. Especially hardware pools
> work best when pool:port are co-located.
For generic pools (SW based) having one pool per core should definitely be faster than multiple ones.
For HW based pools - I can't say much, as I don't have such HW to try.
> At least for me this option of setting multiple buffer pools against lcores in l3fwd is NOT a preferred use-case. Which leads me to conclude
> that we would anyways need both way mapping: pool-per-port and pool-per-core, to cover larger number of use-cases (at least, yours and
> mine).
If my conclusion above was wrong, then yes.
Konstantin
next prev parent reply other threads:[~2019-04-17 11:22 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-16 16:00 Shreyansh Jain
2019-04-16 16:00 ` Shreyansh Jain
2019-04-17 11:21 ` Ananyev, Konstantin [this message]
2019-04-17 11:21 ` Ananyev, Konstantin
-- strict thread matches above, loose matches on Subject: below --
2019-04-16 12:47 Shreyansh Jain
2019-04-16 12:47 ` Shreyansh Jain
2019-04-16 12:54 ` Ananyev, Konstantin
2019-04-16 12:54 ` Ananyev, Konstantin
2019-04-15 10:29 Shreyansh Jain
2019-04-15 10:29 ` Shreyansh Jain
2019-04-15 6:48 Shreyansh Jain
2019-04-15 6:48 ` Shreyansh Jain
2019-04-15 7:58 ` Ruifeng Wang (Arm Technology China)
2019-04-15 7:58 ` Ruifeng Wang (Arm Technology China)
2019-01-03 11:30 Shreyansh Jain
2019-04-04 11:54 ` Hemant Agrawal
2019-04-04 11:54 ` Hemant Agrawal
2019-04-08 6:10 ` Ruifeng Wang (Arm Technology China)
2019-04-08 6:10 ` Ruifeng Wang (Arm Technology China)
2019-04-08 9:29 ` Ananyev, Konstantin
2019-04-08 9:29 ` Ananyev, Konstantin
2019-04-12 9:24 ` Shreyansh Jain
2019-04-12 9:24 ` Shreyansh Jain
2019-04-14 9:13 ` Ruifeng Wang (Arm Technology China)
2019-04-14 9:13 ` Ruifeng Wang (Arm Technology China)
2019-04-15 12:05 ` Ananyev, Konstantin
2019-04-15 12:05 ` Ananyev, Konstantin
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