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* [dpdk-dev] [PATCH] net/iavf: fix queue interrupt for ICE
@ 2019-04-18  4:58 Wei Zhao
  2019-04-18  4:58 ` Wei Zhao
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Wei Zhao @ 2019-04-18  4:58 UTC (permalink / raw)
  To: dev; +Cc: stable, qi.z.zhang, Wei Zhao

Enable CLEARPBA bit is required by ice NIC of A0/A1 version to
enable Tx and Rx queue interrupt.
Also enable CLEARPBA bit does no impact on IAVF behaviour when be
hosted by other devices, so we can make it as default.

Fixes: d6bde6b5eae9 ("net/avf: enable Rx interrupt")
Cc: stable@dpdk.org

Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
---
 drivers/net/iavf/iavf_ethdev.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c
index 846e604..57819dd 100644
--- a/drivers/net/iavf/iavf_ethdev.c
+++ b/drivers/net/iavf/iavf_ethdev.c
@@ -1015,11 +1015,13 @@ iavf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
 		PMD_DRV_LOG(INFO, "MISC is also enabled for control");
 		IAVF_WRITE_REG(hw, IAVFINT_DYN_CTL01,
 			      IAVFINT_DYN_CTL01_INTENA_MASK |
+			      IAVFINT_DYN_CTL01_CLEARPBA_MASK |
 			      IAVFINT_DYN_CTL01_ITR_INDX_MASK);
 	} else {
 		IAVF_WRITE_REG(hw,
 			      IAVFINT_DYN_CTLN1(msix_intr - IAVF_RX_VEC_START),
 			      IAVFINT_DYN_CTLN1_INTENA_MASK |
+			      IAVFINT_DYN_CTL01_CLEARPBA_MASK |
 			      IAVFINT_DYN_CTLN1_ITR_INDX_MASK);
 	}
 
-- 
2.7.5

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2019-05-08 10:37 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-04-18  4:58 [dpdk-dev] [PATCH] net/iavf: fix queue interrupt for ICE Wei Zhao
2019-04-18  4:58 ` Wei Zhao
2019-04-18  8:10 ` Zhang, Qi Z
2019-04-18  8:10   ` Zhang, Qi Z
2019-05-08 10:37 ` [dpdk-dev] [dpdk-stable] " Kevin Traynor
2019-05-08 10:37   ` Kevin Traynor

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