From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 743474CA6 for ; Thu, 18 Apr 2019 13:49:13 +0200 (CEST) Received: from Internal Mail-Server by MTLPINE1 (envelope-from yskoh@mellanox.com) with ESMTPS (AES256-SHA encrypted); 18 Apr 2019 14:49:12 +0300 Received: from scfae-sc-2.mti.labs.mlnx (scfae-sc-2.mti.labs.mlnx [10.101.0.96]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id x3IBn6jD003469; Thu, 18 Apr 2019 14:49:10 +0300 From: Yongseok Koh To: bruce.richardson@intel.com, jerinj@marvell.com, pbhagavatula@marvell.com, shahafs@mellanox.com Cc: dev@dpdk.org, thomas@monjalon.net, gavin.hu@arm.com, Honnappa.Nagarahalli@arm.com Date: Thu, 18 Apr 2019 04:49:01 -0700 Message-Id: <20190418114903.42231-2-yskoh@mellanox.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190418114903.42231-1-yskoh@mellanox.com> References: <20190412232451.30197-1-yskoh@mellanox.com> <20190418114903.42231-1-yskoh@mellanox.com> Subject: [dpdk-dev] [PATCH v3 2/4] meson: change default config for armv8 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 18 Apr 2019 11:49:13 -0000 Current default cache line size for armv8 CPUs having Implementor ID of 0x41 is 128 bytes, changing it to 64 bytes. Also, the max number of lcores is changed to 16 from 256. Signed-off-by: Yongseok Koh --- v3: * decrease RTE_MAX_LCORE to 16 from 256 * change title and commit log v2: * introduce flags_arm replacing flags_generic instead of using the extra flags config/arm/meson.build | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 22a062bad9..a5cce51707 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -32,6 +32,11 @@ flags_generic = [ ['RTE_MAX_LCORE', 256], ['RTE_USE_C11_MEM_MODEL', true], ['RTE_CACHE_LINE_SIZE', 128]] +flags_arm = [ + ['RTE_MACHINE', '"armv8a"'], + ['RTE_MAX_LCORE', 16], + ['RTE_USE_C11_MEM_MODEL', true], + ['RTE_CACHE_LINE_SIZE', 64]] flags_cavium = [ ['RTE_CACHE_LINE_SIZE', 128], ['RTE_MAX_NUMA_NODES', 2], @@ -88,7 +93,7 @@ machine_args_cavium = [ ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) impl_generic = ['Generic armv8', flags_generic, machine_args_generic] -impl_0x41 = ['Arm', flags_generic, machine_args_generic] +impl_0x41 = ['Arm', flags_arm, machine_args_generic] impl_0x42 = ['Broadcom', flags_generic, machine_args_generic] impl_0x43 = ['Cavium', flags_cavium, machine_args_cavium] impl_0x44 = ['DEC', flags_generic, machine_args_generic] -- 2.11.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 2D581A00E6 for ; Thu, 18 Apr 2019 13:49:15 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id DA6821B9AE; Thu, 18 Apr 2019 13:49:14 +0200 (CEST) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 743474CA6 for ; Thu, 18 Apr 2019 13:49:13 +0200 (CEST) Received: from Internal Mail-Server by MTLPINE1 (envelope-from yskoh@mellanox.com) with ESMTPS (AES256-SHA encrypted); 18 Apr 2019 14:49:12 +0300 Received: from scfae-sc-2.mti.labs.mlnx (scfae-sc-2.mti.labs.mlnx [10.101.0.96]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id x3IBn6jD003469; Thu, 18 Apr 2019 14:49:10 +0300 From: Yongseok Koh To: bruce.richardson@intel.com, jerinj@marvell.com, pbhagavatula@marvell.com, shahafs@mellanox.com Cc: dev@dpdk.org, thomas@monjalon.net, gavin.hu@arm.com, Honnappa.Nagarahalli@arm.com Date: Thu, 18 Apr 2019 04:49:01 -0700 Message-Id: <20190418114903.42231-2-yskoh@mellanox.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190418114903.42231-1-yskoh@mellanox.com> References: <20190412232451.30197-1-yskoh@mellanox.com> <20190418114903.42231-1-yskoh@mellanox.com> Subject: [dpdk-dev] [PATCH v3 2/4] meson: change default config for armv8 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Content-Type: text/plain; charset="UTF-8" Message-ID: <20190418114901.wbiQrodKcblMp6TvB2UScPIz5BQBHltCtOpbj1u2inY@z> Current default cache line size for armv8 CPUs having Implementor ID of 0x41 is 128 bytes, changing it to 64 bytes. Also, the max number of lcores is changed to 16 from 256. Signed-off-by: Yongseok Koh --- v3: * decrease RTE_MAX_LCORE to 16 from 256 * change title and commit log v2: * introduce flags_arm replacing flags_generic instead of using the extra flags config/arm/meson.build | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 22a062bad9..a5cce51707 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -32,6 +32,11 @@ flags_generic = [ ['RTE_MAX_LCORE', 256], ['RTE_USE_C11_MEM_MODEL', true], ['RTE_CACHE_LINE_SIZE', 128]] +flags_arm = [ + ['RTE_MACHINE', '"armv8a"'], + ['RTE_MAX_LCORE', 16], + ['RTE_USE_C11_MEM_MODEL', true], + ['RTE_CACHE_LINE_SIZE', 64]] flags_cavium = [ ['RTE_CACHE_LINE_SIZE', 128], ['RTE_MAX_NUMA_NODES', 2], @@ -88,7 +93,7 @@ machine_args_cavium = [ ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) impl_generic = ['Generic armv8', flags_generic, machine_args_generic] -impl_0x41 = ['Arm', flags_generic, machine_args_generic] +impl_0x41 = ['Arm', flags_arm, machine_args_generic] impl_0x42 = ['Broadcom', flags_generic, machine_args_generic] impl_0x43 = ['Cavium', flags_cavium, machine_args_cavium] impl_0x44 = ['DEC', flags_generic, machine_args_generic] -- 2.11.0