[dpdk-dev] [PATCH 4/4] test: fix memory barrier test failure on power CPUs

[David Christensen <drc@linux.vnet.ibm.com>]

The memory barrier test fails on IBM Power 9 systems.  Add additional
barriers to accommodate the weakly ordered model used on Power CPUs.

Signed-off-by: David Christensen <drc@linux.vnet.ibm.com>
---
 app/test/test_barrier.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/app/test/test_barrier.c b/app/test/test_barrier.c
index 58a3280..6136ee1 100644
--- a/app/test/test_barrier.c
+++ b/app/test/test_barrier.c
@@ -36,7 +36,7 @@
 #include "test.h"
 
 #define ADD_MAX		8
-#define ITER_MAX	0x100000000
+#define ITER_MAX	0x1000000
 
 enum plock_use_type {
 	USE_MB,
@@ -92,12 +92,19 @@ struct lcore_plock_test {
 	other = self ^ 1;
 
 	l->flag[self] = 1;
+#ifdef RTE_ARCH_PPC_64
+	rte_smp_wmb();
+#endif
 	l->victim = self;
 
 	store_load_barrier(l->utype);
 
 	while (l->flag[other] == 1 && l->victim == self)
 		rte_pause();
+
+#ifdef RTE_ARCH_PPC_64
+	rte_smp_rmb();
+#endif
 }
 
 static void
-- 
1.8.3.1