* [dpdk-dev] [PATCH 4/4] test: fix memory barrier test failure on power CPUs
@ 2019-04-30 22:33 David Christensen
2019-04-30 22:33 ` David Christensen
2019-05-02 21:45 ` Thomas Monjalon
0 siblings, 2 replies; 6+ messages in thread
From: David Christensen @ 2019-04-30 22:33 UTC (permalink / raw)
To: dev; +Cc: David Christensen
The memory barrier test fails on IBM Power 9 systems. Add additional
barriers to accommodate the weakly ordered model used on Power CPUs.
Signed-off-by: David Christensen <drc@linux.vnet.ibm.com>
---
app/test/test_barrier.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/app/test/test_barrier.c b/app/test/test_barrier.c
index 58a3280..6136ee1 100644
--- a/app/test/test_barrier.c
+++ b/app/test/test_barrier.c
@@ -36,7 +36,7 @@
#include "test.h"
#define ADD_MAX 8
-#define ITER_MAX 0x100000000
+#define ITER_MAX 0x1000000
enum plock_use_type {
USE_MB,
@@ -92,12 +92,19 @@ struct lcore_plock_test {
other = self ^ 1;
l->flag[self] = 1;
+#ifdef RTE_ARCH_PPC_64
+ rte_smp_wmb();
+#endif
l->victim = self;
store_load_barrier(l->utype);
while (l->flag[other] == 1 && l->victim == self)
rte_pause();
+
+#ifdef RTE_ARCH_PPC_64
+ rte_smp_rmb();
+#endif
}
static void
--
1.8.3.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [dpdk-dev] [PATCH 4/4] test: fix memory barrier test failure on power CPUs
2019-04-30 22:33 [dpdk-dev] [PATCH 4/4] test: fix memory barrier test failure on power CPUs David Christensen
@ 2019-04-30 22:33 ` David Christensen
2019-05-02 21:45 ` Thomas Monjalon
1 sibling, 0 replies; 6+ messages in thread
From: David Christensen @ 2019-04-30 22:33 UTC (permalink / raw)
To: dev; +Cc: David Christensen
The memory barrier test fails on IBM Power 9 systems. Add additional
barriers to accommodate the weakly ordered model used on Power CPUs.
Signed-off-by: David Christensen <drc@linux.vnet.ibm.com>
---
app/test/test_barrier.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/app/test/test_barrier.c b/app/test/test_barrier.c
index 58a3280..6136ee1 100644
--- a/app/test/test_barrier.c
+++ b/app/test/test_barrier.c
@@ -36,7 +36,7 @@
#include "test.h"
#define ADD_MAX 8
-#define ITER_MAX 0x100000000
+#define ITER_MAX 0x1000000
enum plock_use_type {
USE_MB,
@@ -92,12 +92,19 @@ struct lcore_plock_test {
other = self ^ 1;
l->flag[self] = 1;
+#ifdef RTE_ARCH_PPC_64
+ rte_smp_wmb();
+#endif
l->victim = self;
store_load_barrier(l->utype);
while (l->flag[other] == 1 && l->victim == self)
rte_pause();
+
+#ifdef RTE_ARCH_PPC_64
+ rte_smp_rmb();
+#endif
}
static void
--
1.8.3.1
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [dpdk-dev] [PATCH 4/4] test: fix memory barrier test failure on power CPUs
2019-04-30 22:33 [dpdk-dev] [PATCH 4/4] test: fix memory barrier test failure on power CPUs David Christensen
2019-04-30 22:33 ` David Christensen
@ 2019-05-02 21:45 ` Thomas Monjalon
2019-05-02 21:45 ` Thomas Monjalon
2019-05-06 18:26 ` David Christensen
1 sibling, 2 replies; 6+ messages in thread
From: Thomas Monjalon @ 2019-05-02 21:45 UTC (permalink / raw)
To: David Christensen; +Cc: dev
Hi,
01/05/2019 00:33, David Christensen:
> The memory barrier test fails on IBM Power 9 systems. Add additional
> barriers to accommodate the weakly ordered model used on Power CPUs.
>
> Signed-off-by: David Christensen <drc@linux.vnet.ibm.com>
[...]
> --- a/app/test/test_barrier.c
> +++ b/app/test/test_barrier.c
> @@ -36,7 +36,7 @@
> #include "test.h"
>
> #define ADD_MAX 8
> -#define ITER_MAX 0x100000000
> +#define ITER_MAX 0x1000000
This is a revert of a change done in patch 3.
> @@ -92,12 +92,19 @@ struct lcore_plock_test {
> other = self ^ 1;
>
> l->flag[self] = 1;
> +#ifdef RTE_ARCH_PPC_64
> + rte_smp_wmb();
> +#endif
You should not have such #ifdef in a test case
supposed to run on all architectures with the same code.
What can be fixed in EAL?
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [dpdk-dev] [PATCH 4/4] test: fix memory barrier test failure on power CPUs
2019-05-02 21:45 ` Thomas Monjalon
@ 2019-05-02 21:45 ` Thomas Monjalon
2019-05-06 18:26 ` David Christensen
1 sibling, 0 replies; 6+ messages in thread
From: Thomas Monjalon @ 2019-05-02 21:45 UTC (permalink / raw)
To: David Christensen; +Cc: dev
Hi,
01/05/2019 00:33, David Christensen:
> The memory barrier test fails on IBM Power 9 systems. Add additional
> barriers to accommodate the weakly ordered model used on Power CPUs.
>
> Signed-off-by: David Christensen <drc@linux.vnet.ibm.com>
[...]
> --- a/app/test/test_barrier.c
> +++ b/app/test/test_barrier.c
> @@ -36,7 +36,7 @@
> #include "test.h"
>
> #define ADD_MAX 8
> -#define ITER_MAX 0x100000000
> +#define ITER_MAX 0x1000000
This is a revert of a change done in patch 3.
> @@ -92,12 +92,19 @@ struct lcore_plock_test {
> other = self ^ 1;
>
> l->flag[self] = 1;
> +#ifdef RTE_ARCH_PPC_64
> + rte_smp_wmb();
> +#endif
You should not have such #ifdef in a test case
supposed to run on all architectures with the same code.
What can be fixed in EAL?
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [dpdk-dev] [PATCH 4/4] test: fix memory barrier test failure on power CPUs
2019-05-02 21:45 ` Thomas Monjalon
2019-05-02 21:45 ` Thomas Monjalon
@ 2019-05-06 18:26 ` David Christensen
2019-05-06 18:26 ` David Christensen
1 sibling, 1 reply; 6+ messages in thread
From: David Christensen @ 2019-05-06 18:26 UTC (permalink / raw)
To: Thomas Monjalon; +Cc: dev
>> -#define ITER_MAX 0x100000000
>> +#define ITER_MAX 0x1000000
>
> This is a revert of a change done in patch 3.
I'll fix and resubmit.
>> @@ -92,12 +92,19 @@ struct lcore_plock_test {
>> other = self ^ 1;
>>
>> l->flag[self] = 1;
>> +#ifdef RTE_ARCH_PPC_64
>> + rte_smp_wmb();
>> +#endif
>
> You should not have such #ifdef in a test case
> supposed to run on all architectures with the same code.
> What can be fixed in EAL?
I'll go ahead and remove the ifdefs since the code for rte_smp_wmb()
resolves to different architecture specific code (compiler memory
barriers in the x86 case).
Dave
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [dpdk-dev] [PATCH 4/4] test: fix memory barrier test failure on power CPUs
2019-05-06 18:26 ` David Christensen
@ 2019-05-06 18:26 ` David Christensen
0 siblings, 0 replies; 6+ messages in thread
From: David Christensen @ 2019-05-06 18:26 UTC (permalink / raw)
To: Thomas Monjalon; +Cc: dev
>> -#define ITER_MAX 0x100000000
>> +#define ITER_MAX 0x1000000
>
> This is a revert of a change done in patch 3.
I'll fix and resubmit.
>> @@ -92,12 +92,19 @@ struct lcore_plock_test {
>> other = self ^ 1;
>>
>> l->flag[self] = 1;
>> +#ifdef RTE_ARCH_PPC_64
>> + rte_smp_wmb();
>> +#endif
>
> You should not have such #ifdef in a test case
> supposed to run on all architectures with the same code.
> What can be fixed in EAL?
I'll go ahead and remove the ifdefs since the code for rte_smp_wmb()
resolves to different architecture specific code (compiler memory
barriers in the x86 case).
Dave
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-05-06 18:26 UTC | newest]
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2019-04-30 22:33 [dpdk-dev] [PATCH 4/4] test: fix memory barrier test failure on power CPUs David Christensen
2019-04-30 22:33 ` David Christensen
2019-05-02 21:45 ` Thomas Monjalon
2019-05-02 21:45 ` Thomas Monjalon
2019-05-06 18:26 ` David Christensen
2019-05-06 18:26 ` David Christensen
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