From: David Christensen <drc@linux.vnet.ibm.com>
To: Thomas Monjalon <thomas@monjalon.net>
Cc: dev@dpdk.org
Subject: Re: [dpdk-dev] [PATCH 4/4] test: fix memory barrier test failure on power CPUs
Date: Mon, 6 May 2019 11:26:26 -0700 [thread overview]
Message-ID: <e1e67b77-9733-dedd-41af-ba16e847b867@linux.vnet.ibm.com> (raw)
Message-ID: <20190506182626.GLZQfP8x12F11r7oy74WIPViFSQPe_3yl2-mTj9GzNw@z> (raw)
In-Reply-To: <6327337.9PMvuZf6XJ@xps>
>> -#define ITER_MAX 0x100000000
>> +#define ITER_MAX 0x1000000
>
> This is a revert of a change done in patch 3.
I'll fix and resubmit.
>> @@ -92,12 +92,19 @@ struct lcore_plock_test {
>> other = self ^ 1;
>>
>> l->flag[self] = 1;
>> +#ifdef RTE_ARCH_PPC_64
>> + rte_smp_wmb();
>> +#endif
>
> You should not have such #ifdef in a test case
> supposed to run on all architectures with the same code.
> What can be fixed in EAL?
I'll go ahead and remove the ifdefs since the code for rte_smp_wmb()
resolves to different architecture specific code (compiler memory
barriers in the x86 case).
Dave
next prev parent reply other threads:[~2019-05-06 18:26 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-30 22:33 David Christensen
2019-04-30 22:33 ` David Christensen
2019-05-02 21:45 ` Thomas Monjalon
2019-05-02 21:45 ` Thomas Monjalon
2019-05-06 18:26 ` David Christensen [this message]
2019-05-06 18:26 ` David Christensen
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