* [dpdk-dev] [PATCH v2 4/4] test: fix memory barrier test failure on power CPUs
@ 2019-05-06 19:24 David Christensen
2019-05-06 19:24 ` David Christensen
2019-05-07 10:40 ` Ananyev, Konstantin
0 siblings, 2 replies; 4+ messages in thread
From: David Christensen @ 2019-05-06 19:24 UTC (permalink / raw)
To: dev; +Cc: David Christensen
The memory barrier test fails on IBM Power 9 systems. Add additional
barriers to accommodate the weakly ordered model used on Power CPUs.
Signed-off-by: David Christensen <drc@linux.vnet.ibm.com>
---
v2:
* Removed ifdef's for PPC since the rte_smp_*mb() macros are already
customized for each CPU architecture
app/test/test_barrier.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/app/test/test_barrier.c b/app/test/test_barrier.c
index a022708..0bf82cf 100644
--- a/app/test/test_barrier.c
+++ b/app/test/test_barrier.c
@@ -92,12 +92,14 @@ struct lcore_plock_test {
other = self ^ 1;
l->flag[self] = 1;
+ rte_smp_wmb();
l->victim = self;
store_load_barrier(l->utype);
while (l->flag[other] == 1 && l->victim == self)
rte_pause();
+ rte_smp_rmb();
}
static void
--
1.8.3.1
^ permalink raw reply [flat|nested] 4+ messages in thread* [dpdk-dev] [PATCH v2 4/4] test: fix memory barrier test failure on power CPUs
2019-05-06 19:24 [dpdk-dev] [PATCH v2 4/4] test: fix memory barrier test failure on power CPUs David Christensen
@ 2019-05-06 19:24 ` David Christensen
2019-05-07 10:40 ` Ananyev, Konstantin
1 sibling, 0 replies; 4+ messages in thread
From: David Christensen @ 2019-05-06 19:24 UTC (permalink / raw)
To: dev; +Cc: David Christensen
The memory barrier test fails on IBM Power 9 systems. Add additional
barriers to accommodate the weakly ordered model used on Power CPUs.
Signed-off-by: David Christensen <drc@linux.vnet.ibm.com>
---
v2:
* Removed ifdef's for PPC since the rte_smp_*mb() macros are already
customized for each CPU architecture
app/test/test_barrier.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/app/test/test_barrier.c b/app/test/test_barrier.c
index a022708..0bf82cf 100644
--- a/app/test/test_barrier.c
+++ b/app/test/test_barrier.c
@@ -92,12 +92,14 @@ struct lcore_plock_test {
other = self ^ 1;
l->flag[self] = 1;
+ rte_smp_wmb();
l->victim = self;
store_load_barrier(l->utype);
while (l->flag[other] == 1 && l->victim == self)
rte_pause();
+ rte_smp_rmb();
}
static void
--
1.8.3.1
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [dpdk-dev] [PATCH v2 4/4] test: fix memory barrier test failure on power CPUs
2019-05-06 19:24 [dpdk-dev] [PATCH v2 4/4] test: fix memory barrier test failure on power CPUs David Christensen
2019-05-06 19:24 ` David Christensen
@ 2019-05-07 10:40 ` Ananyev, Konstantin
2019-05-07 10:40 ` Ananyev, Konstantin
1 sibling, 1 reply; 4+ messages in thread
From: Ananyev, Konstantin @ 2019-05-07 10:40 UTC (permalink / raw)
To: David Christensen, dev
>
> The memory barrier test fails on IBM Power 9 systems. Add additional
> barriers to accommodate the weakly ordered model used on Power CPUs.
>
> Signed-off-by: David Christensen <drc@linux.vnet.ibm.com>
> ---
> v2:
> * Removed ifdef's for PPC since the rte_smp_*mb() macros are already
> customized for each CPU architecture
>
> app/test/test_barrier.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/app/test/test_barrier.c b/app/test/test_barrier.c
> index a022708..0bf82cf 100644
> --- a/app/test/test_barrier.c
> +++ b/app/test/test_barrier.c
> @@ -92,12 +92,14 @@ struct lcore_plock_test {
> other = self ^ 1;
>
> l->flag[self] = 1;
> + rte_smp_wmb();
> l->victim = self;
>
> store_load_barrier(l->utype);
>
> while (l->flag[other] == 1 && l->victim == self)
> rte_pause();
> + rte_smp_rmb();
> }
>
> static void
> --
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
> 1.8.3.1
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [dpdk-dev] [PATCH v2 4/4] test: fix memory barrier test failure on power CPUs
2019-05-07 10:40 ` Ananyev, Konstantin
@ 2019-05-07 10:40 ` Ananyev, Konstantin
0 siblings, 0 replies; 4+ messages in thread
From: Ananyev, Konstantin @ 2019-05-07 10:40 UTC (permalink / raw)
To: David Christensen, dev
>
> The memory barrier test fails on IBM Power 9 systems. Add additional
> barriers to accommodate the weakly ordered model used on Power CPUs.
>
> Signed-off-by: David Christensen <drc@linux.vnet.ibm.com>
> ---
> v2:
> * Removed ifdef's for PPC since the rte_smp_*mb() macros are already
> customized for each CPU architecture
>
> app/test/test_barrier.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/app/test/test_barrier.c b/app/test/test_barrier.c
> index a022708..0bf82cf 100644
> --- a/app/test/test_barrier.c
> +++ b/app/test/test_barrier.c
> @@ -92,12 +92,14 @@ struct lcore_plock_test {
> other = self ^ 1;
>
> l->flag[self] = 1;
> + rte_smp_wmb();
> l->victim = self;
>
> store_load_barrier(l->utype);
>
> while (l->flag[other] == 1 && l->victim == self)
> rte_pause();
> + rte_smp_rmb();
> }
>
> static void
> --
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
> 1.8.3.1
^ permalink raw reply [flat|nested] 4+ messages in thread
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2019-05-06 19:24 [dpdk-dev] [PATCH v2 4/4] test: fix memory barrier test failure on power CPUs David Christensen
2019-05-06 19:24 ` David Christensen
2019-05-07 10:40 ` Ananyev, Konstantin
2019-05-07 10:40 ` Ananyev, Konstantin
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