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Mon, 13 May 2019 19:26:55 +0000 Received: from VE1PR08MB5149.eurprd08.prod.outlook.com ([fe80::f580:2129:8aa6:b534]) by VE1PR08MB5149.eurprd08.prod.outlook.com ([fe80::f580:2129:8aa6:b534%4]) with mapi id 15.20.1878.024; Mon, 13 May 2019 19:26:55 +0000 From: Honnappa Nagarahalli To: "yskoh@mellanox.com" , "jerinj@marvell.com" , "thomas@monjalon.net" CC: "dev@dpdk.org" , "bruce.richardson@intel.com" , "pbhagavatula@marvell.com" , "shahafs@mellanox.com" , "Gavin Hu (Arm Technology China)" , "stable@dpdk.org" , Dharmik Thakkar , Honnappa Nagarahalli , nd , nd Thread-Topic: [PATCH v3] build: disable armv8 crypto extension Thread-Index: AQHVBRl9ds4mIXxa20+1HjbMG4xT6aZpeTJA Date: Mon, 13 May 2019 19:26:55 +0000 Message-ID: References: <20190502015806.41497-1-yskoh@mellanox.com> <20190507211140.43569-1-yskoh@mellanox.com> In-Reply-To: <20190507211140.43569-1-yskoh@mellanox.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Honnappa.Nagarahalli@arm.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:VE1PR08MB5213; H:VE1PR08MB5149.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 3/czvOtYI/vccaaP937sErlqx6fsrFGseBYgApv6Nf8KA/vg5R8NI1voY5KCWcLBX2lvo1d65y8qGCJehB8meGreI3YkD9cOKiK9ygnd5tTxKFusiupiRn26S7xnfyJCh9Z3zaxzaV9VJIaMcvJgS4WuU3wibDomjDT8Z0j6LARqLpqHQWnl/rw3GwjpmfSHuzQdTjr+IMNAfBz2R/xSHeMGFkd3ZolZ0B1EGXvJPONoHHzNQpUayPR4bKbNOqFJE0MVnkaerXqR8+p2YnWOtyuSeTF07PrFuHabPl1+c8efHxxz1ldZSpXiDLiKWOzaMdxWnZXso1zjJbdrKDvu1i+mgp2NuSAzLNSSN7/INl2SwKXQs+JiZy9ptLMUpi7vgSTFMSJfFbUoEwHHRDWacBT9SpTVjNvG4EqGyTF0N00= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1748f3e3-c6b9-47be-643d-08d6d7d8f5b1 X-MS-Exchange-CrossTenant-originalarrivaltime: 13 May 2019 19:26:55.2903 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR08MB5213 Subject: Re: [dpdk-dev] [PATCH v3] build: disable armv8 crypto extension X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190513192655.HEi00ViubTvJDnNcE_YEnDwDi6YEYVcqmCwzMDxNics@z> >=20 > Per armv8 crypto extension support, make build always enable it by defaul= t as > long as compiler supports the feature while meson build only enables it f= or > 'default' machine of generic armv8 architecture. >=20 > It is known that not all the armv8 platforms have the crypto extension. F= or > example, Mellanox BlueField has a variant which doesn't have it. If crypt= o > enabled binary runs on such a platform, rte_eal_init() fails. >=20 > '+crypto' flag currently implies only '+aes' and '+sha2' and enabling it = will > generate the crypto instructions only when crypto intrinsics are used. > For the devices supporting 8.2 crypto or newer, compiler could generate s= uch > instructions beyond intrinsics or asm code. For example, compiler can gen= erate > 3-way exclusive OR instructions if sha3 is supported. However, it has to = be > enabled by adding '+sha3' as of today. >=20 > In DPDK, armv8 cryptodev is the only one which requires the crypto suppor= t. > As it even uses external library of Marvell which is compiled out of DPDK= with > crypto support and there's run-time check for required cpuflags, crypto > support can be disabled in DPDK. >=20 > Cc: stable@dpdk.org >=20 > Signed-off-by: Yongseok Koh > Acked-by: Jerin Jacob > Tested-by: Dharmik Thakkar > --- >=20 > v3: > * announce removal of the flag in release note >=20 > v2: > * disable crypto support instead of having a build config >=20 > config/arm/meson.build | 2 +- > doc/guides/rel_notes/release_19_05.rst | 2 ++ > mk/machine/armv8a/rte.vars.mk | 2 +- > 3 files changed, 4 insertions(+), 2 deletions(-) >=20 > diff --git a/config/arm/meson.build b/config/arm/meson.build index > 7fa6ed3105..abc8cf346c 100644 > --- a/config/arm/meson.build > +++ b/config/arm/meson.build > @@ -74,7 +74,7 @@ flags_octeontx2_extra =3D [ > ['RTE_USE_C11_MEM_MODEL', true]] >=20 > machine_args_generic =3D [ > - ['default', ['-march=3Darmv8-a+crc+crypto']], > + ['default', ['-march=3Darmv8-a+crc']], > ['native', ['-march=3Dnative']], > ['0xd03', ['-mcpu=3Dcortex-a53']], > ['0xd04', ['-mcpu=3Dcortex-a35']], > diff --git a/doc/guides/rel_notes/release_19_05.rst > b/doc/guides/rel_notes/release_19_05.rst > index 5044ac7df1..0d35f25094 100644 > --- a/doc/guides/rel_notes/release_19_05.rst > +++ b/doc/guides/rel_notes/release_19_05.rst > @@ -234,6 +234,8 @@ Removed Items > Also, make sure to start the actual text at the margin. > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D >=20 > +* build: armv8 crypto extension is disabled. > + >=20 > API Changes > ----------- > diff --git a/mk/machine/armv8a/rte.vars.mk > b/mk/machine/armv8a/rte.vars.mk index 8252efbb7b..5e3ffc3adf 100644 > --- a/mk/machine/armv8a/rte.vars.mk > +++ b/mk/machine/armv8a/rte.vars.mk > @@ -28,4 +28,4 @@ > # CPU_LDFLAGS =3D > # CPU_ASFLAGS =3D >=20 > -MACHINE_CFLAGS +=3D -march=3Darmv8-a+crc+crypto > +MACHINE_CFLAGS +=3D -march=3Darmv8-a+crc > -- > 2.21.0 Reviewed-by: Honnappa Nagarahalli