From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id DF567A05D3 for ; Thu, 23 May 2019 10:17:13 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D72C31B964; Thu, 23 May 2019 10:16:50 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id AD6141B9A7 for ; Thu, 23 May 2019 10:16:47 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x4N89eup019037; Thu, 23 May 2019 01:16:47 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=JLv/KXe3LtJcugrNssRFWV+z6prNoenTYmr9cbRxyfA=; b=fyVz4QrgyyTYQKzUjGFAM7AxUV2rAqJho8ZVqsB//mxk0fTQg75b4M9nxzdN7G7RGQHq StaYA6TukU+CLq9GFxvII4k2IdiNg/ip7+ttHx5TfVp0FUVmctqrvXtzGc6Nic2k6dno 9ZrpWpnpSrABmmt9SeualzIcMzgsdxLWbPegExbTnYY5WIy463Rx47jKss8tEJqVZD/2 DhYctXWPVSkHoldXAfXnCkgl7olmQdIv9XjgUYqraiYIWAvIXKCR1Ze9MWbqAWwLVGq3 CC8qvPiq/ZXAYJpQ4nfjAZLGZdhlNNE7nSS1S318rE1loFUi2M30HqPR0ijBTEZ5OIBK AA== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 2smnwk0s80-7 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 23 May 2019 01:16:45 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Thu, 23 May 2019 01:15:29 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Thu, 23 May 2019 01:15:29 -0700 Received: from jerin-lab.marvell.com (unknown [10.28.34.14]) by maili.marvell.com (Postfix) with ESMTP id 3C66A3F703F; Thu, 23 May 2019 01:15:28 -0700 (PDT) From: To: CC: , Jerin Jacob , Nithin Dabilpuram , Pavan Nikhilesh Date: Thu, 23 May 2019 13:43:21 +0530 Message-ID: <20190523081339.56348-10-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190523081339.56348-1-jerinj@marvell.com> References: <20190523081339.56348-1-jerinj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-23_08:, , signatures=0 Subject: [dpdk-dev] [PATCH v1 09/27] common/octeontx2: handle intra device operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jerin Jacob The mempool device(NPA) may be provisioned as a standalone device or it can be part of ethdev/eventdev device. In order to address mempool as standalone or integrated with ethdev/eventdev device, An intra device structure being introduced. When the _first_ ethdev/eventdev PCIe device or standalone mempool(NPA) devices get probed by the eal PCI subsystem, The NPA object(struct otx2_npa_lf) stored in otx2_dev base class. Once it is accomplished, the other consumer drivers like ethdev driver or eventdev driver use otx2_npa_* API to operate on shared NPA object. The similar concept followed for SSO object, Which needs to share between PCIe devices. Signed-off-by: Jerin Jacob Signed-off-by: Nithin Dabilpuram Signed-off-by: Pavan Nikhilesh --- drivers/common/octeontx2/otx2_common.c | 163 ++++++++++++++++++ drivers/common/octeontx2/otx2_common.h | 32 +++- drivers/common/octeontx2/otx2_dev.c | 6 + drivers/common/octeontx2/otx2_dev.h | 1 + .../rte_common_octeontx2_version.map | 9 + 5 files changed, 210 insertions(+), 1 deletion(-) diff --git a/drivers/common/octeontx2/otx2_common.c b/drivers/common/octeontx2/otx2_common.c index 544828825..18d28e82a 100644 --- a/drivers/common/octeontx2/otx2_common.c +++ b/drivers/common/octeontx2/otx2_common.c @@ -2,9 +2,172 @@ * Copyright(C) 2019 Marvell International Ltd. */ +#include +#include #include #include "otx2_common.h" +#include "otx2_dev.h" +#include "otx2_mbox.h" + +/** + * @internal + * Set default NPA configuration. + */ +void +otx2_npa_set_defaults(struct otx2_idev_cfg *idev) +{ + idev->npa_pf_func = 0; + rte_atomic16_set(&idev->npa_refcnt, 0); +} + +/** + * @internal + * Get intra device config structure. + */ +struct otx2_idev_cfg * +otx2_intra_dev_get_cfg(void) +{ + const char name[] = "octeontx2_intra_device_conf"; + const struct rte_memzone *mz; + struct otx2_idev_cfg *idev; + + mz = rte_memzone_lookup(name); + if (mz != NULL) + return mz->addr; + + /* Request for the first time */ + mz = rte_memzone_reserve_aligned(name, sizeof(struct otx2_idev_cfg), + SOCKET_ID_ANY, 0, OTX2_ALIGN); + if (mz != NULL) { + idev = mz->addr; + idev->sso_pf_func = 0; + idev->npa_lf = NULL; + otx2_npa_set_defaults(idev); + return idev; + } + return NULL; +} + +/** + * @internal + * Get SSO PF_FUNC. + */ +uint16_t +otx2_sso_pf_func_get(void) +{ + struct otx2_idev_cfg *idev; + uint16_t sso_pf_func; + + sso_pf_func = 0; + idev = otx2_intra_dev_get_cfg(); + + if (idev != NULL) + sso_pf_func = idev->sso_pf_func; + + return sso_pf_func; +} + +/** + * @internal + * Set SSO PF_FUNC. + */ +void +otx2_sso_pf_func_set(uint16_t sso_pf_func) +{ + struct otx2_idev_cfg *idev; + + idev = otx2_intra_dev_get_cfg(); + + if (idev != NULL) { + idev->sso_pf_func = sso_pf_func; + rte_smp_wmb(); + } +} + +/** + * @internal + * Get NPA PF_FUNC. + */ +uint16_t +otx2_npa_pf_func_get(void) +{ + struct otx2_idev_cfg *idev; + uint16_t npa_pf_func; + + npa_pf_func = 0; + idev = otx2_intra_dev_get_cfg(); + + if (idev != NULL) + npa_pf_func = idev->npa_pf_func; + + return npa_pf_func; +} + +/** + * @internal + * Get NPA lf object. + */ +struct otx2_npa_lf * +otx2_npa_lf_obj_get(void) +{ + struct otx2_idev_cfg *idev; + + idev = otx2_intra_dev_get_cfg(); + + if (idev != NULL && rte_atomic16_read(&idev->npa_refcnt)) + return idev->npa_lf; + + return NULL; +} + +/** + * @internal + * Is NPA lf active for the given device?. + */ +int +otx2_npa_lf_active(void *otx2_dev) +{ + struct otx2_dev *dev = otx2_dev; + struct otx2_idev_cfg *idev; + + /* Check if npalf is actively used on this dev */ + idev = otx2_intra_dev_get_cfg(); + if (!idev || !idev->npa_lf || idev->npa_lf->mbox != dev->mbox) + return 0; + + return rte_atomic16_read(&idev->npa_refcnt); +} + +/* + * @internal + * Gets reference only to existing NPA LF object. + */ +int otx2_npa_lf_obj_ref(void) +{ + struct otx2_idev_cfg *idev; + uint16_t cnt; + int rc; + + idev = otx2_intra_dev_get_cfg(); + + /* Check if ref not possible */ + if (idev == NULL) + return -EINVAL; + + + /* Get ref only if > 0 */ + cnt = rte_atomic16_read(&idev->npa_refcnt); + while (cnt != 0) { + rc = rte_atomic16_cmpset(&idev->npa_refcnt_u16, cnt, cnt + 1); + if (rc) + break; + + cnt = rte_atomic16_read(&idev->npa_refcnt); + } + + return cnt ? 0 : -EINVAL; +} /** * @internal diff --git a/drivers/common/octeontx2/otx2_common.h b/drivers/common/octeontx2/otx2_common.h index 0750cdd14..d4bc2f59c 100644 --- a/drivers/common/octeontx2/otx2_common.h +++ b/drivers/common/octeontx2/otx2_common.h @@ -5,9 +5,12 @@ #ifndef _OTX2_COMMON_H_ #define _OTX2_COMMON_H_ +#include #include -#include +#include #include +#include +#include #include "hw/otx2_rvu.h" #include "hw/otx2_nix.h" @@ -33,6 +36,33 @@ #define __hot __attribute__((hot)) #endif +/* Intra device related functions */ +struct otx2_npa_lf { + struct otx2_mbox *mbox; + struct rte_pci_device *pci_dev; + struct rte_intr_handle *intr_handle; +}; + +struct otx2_idev_cfg { + uint16_t sso_pf_func; + uint16_t npa_pf_func; + struct otx2_npa_lf *npa_lf; + RTE_STD_C11 + union { + rte_atomic16_t npa_refcnt; + uint16_t npa_refcnt_u16; + }; +}; + +struct otx2_idev_cfg *otx2_intra_dev_get_cfg(void); +void otx2_sso_pf_func_set(uint16_t sso_pf_func); +uint16_t otx2_sso_pf_func_get(void); +uint16_t otx2_npa_pf_func_get(void); +struct otx2_npa_lf *otx2_npa_lf_obj_get(void); +void otx2_npa_set_defaults(struct otx2_idev_cfg *idev); +int otx2_npa_lf_active(void *dev); +int otx2_npa_lf_obj_ref(void); + /* Log */ extern int otx2_logtype_base; extern int otx2_logtype_mbox; diff --git a/drivers/common/octeontx2/otx2_dev.c b/drivers/common/octeontx2/otx2_dev.c index ccdb2df78..59bd988d1 100644 --- a/drivers/common/octeontx2/otx2_dev.c +++ b/drivers/common/octeontx2/otx2_dev.c @@ -177,8 +177,14 @@ void otx2_dev_fini(struct rte_pci_device *pci_dev, void *otx2_dev) { struct otx2_dev *dev = otx2_dev; + struct otx2_idev_cfg *idev; struct otx2_mbox *mbox; + /* Clear references to this pci dev */ + idev = otx2_intra_dev_get_cfg(); + if (idev->npa_lf && idev->npa_lf->pci_dev == pci_dev) + idev->npa_lf = NULL; + /* Release PF - VF */ mbox = &dev->mbox_vfpf; if (mbox->hwbase && mbox->dev) diff --git a/drivers/common/octeontx2/otx2_dev.h b/drivers/common/octeontx2/otx2_dev.h index a89570b62..70104dfa2 100644 --- a/drivers/common/octeontx2/otx2_dev.h +++ b/drivers/common/octeontx2/otx2_dev.h @@ -40,6 +40,7 @@ struct otx2_dev; otx2_intr_t intr; \ int timer_set; /* ~0 : no alarm handling */ \ uint64_t hwcap; \ + struct otx2_npa_lf npalf; \ struct otx2_mbox *mbox; \ uint16_t maxvf; \ const struct otx2_dev_ops *ops diff --git a/drivers/common/octeontx2/rte_common_octeontx2_version.map b/drivers/common/octeontx2/rte_common_octeontx2_version.map index 2fda35aad..b151ce6e2 100644 --- a/drivers/common/octeontx2/rte_common_octeontx2_version.map +++ b/drivers/common/octeontx2/rte_common_octeontx2_version.map @@ -20,6 +20,15 @@ DPDK_19.05 { otx2_mbox_msg_send; otx2_mbox_wait_for_rsp; + otx2_intra_dev_get_cfg; + otx2_npa_lf_active; + otx2_npa_lf_obj_get; + otx2_npa_lf_obj_ref; + otx2_npa_pf_func_get; + otx2_npa_set_defaults; + otx2_sso_pf_func_get; + otx2_sso_pf_func_set; + otx2_disable_irqs; otx2_unregister_irq; otx2_register_irq; -- 2.21.0