From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 33279A05D3 for ; Thu, 23 May 2019 10:16:17 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 116B81B96B; Thu, 23 May 2019 10:16:12 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 79FF61B949 for ; Thu, 23 May 2019 10:16:08 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x4N89bZs018693; Thu, 23 May 2019 01:16:08 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=G4nlfOxso1ngdfC0SLJcrdhE4szTn8su5va4DJPtkVo=; b=kTU2BnXOj9SCM5wnQrCh3lbIp15wb2wcaTO27+9mtxwYxO4dkmMQP4PfDKhqmJ1sdu4m w769Nybl900TClUFkyiYt2U2ktZVHJRcgM3ZWa8F0mPqkFBwPVnhQx9ZNdjac5A0B9gy F8gwsdh+J1YR+1NFqowAAbG2ih2y8IeaLKh1sjEMdR4GMN+wDfIOUSPIIdigNtCFk5TZ lV4sqz0p8P+TLF2VB9pQkKR76wi3RejFUSe9ilaCgsuIVd6X5iYR7XzP1h1O8Hcu81+q GJQN6CsF0J3tZZuSssdLUPiAvu5Xcf9zvm2GbMBwkxgjYTSm2jF8s9upOeSEJYsaRlfW 1Q== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 2smnwk0sc1-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 23 May 2019 01:16:07 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Thu, 23 May 2019 01:16:03 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Thu, 23 May 2019 01:16:03 -0700 Received: from jerin-lab.marvell.com (unknown [10.28.34.14]) by maili.marvell.com (Postfix) with ESMTP id 6AFB83F704E; Thu, 23 May 2019 01:16:02 -0700 (PDT) From: To: CC: , Jerin Jacob , Vivek Sharma Date: Thu, 23 May 2019 13:43:32 +0530 Message-ID: <20190523081339.56348-21-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190523081339.56348-1-jerinj@marvell.com> References: <20190523081339.56348-1-jerinj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-23_08:, , signatures=0 Subject: [dpdk-dev] [PATCH v1 20/27] mempool/octeontx2: add context dump support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jerin Jacob Add a helper function to dump aura and pool context for NPA debugging. Signed-off-by: Jerin Jacob Signed-off-by: Vivek Sharma --- drivers/mempool/octeontx2/Makefile | 3 +- drivers/mempool/octeontx2/meson.build | 1 + drivers/mempool/octeontx2/otx2_mempool.h | 3 + .../mempool/octeontx2/otx2_mempool_debug.c | 135 ++++++++++++++++++ drivers/mempool/octeontx2/otx2_mempool_irq.c | 1 + 5 files changed, 142 insertions(+), 1 deletion(-) create mode 100644 drivers/mempool/octeontx2/otx2_mempool_debug.c diff --git a/drivers/mempool/octeontx2/Makefile b/drivers/mempool/octeontx2/Makefile index 86950b270..b86d469f4 100644 --- a/drivers/mempool/octeontx2/Makefile +++ b/drivers/mempool/octeontx2/Makefile @@ -29,7 +29,8 @@ LIBABIVER := 1 # SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL) += \ otx2_mempool.c \ - otx2_mempool_irq.c + otx2_mempool_irq.c \ + otx2_mempool_debug.c LDLIBS += -lrte_eal -lrte_mempool -lrte_mbuf LDLIBS += -lrte_common_octeontx2 -lrte_kvargs -lrte_bus_pci diff --git a/drivers/mempool/octeontx2/meson.build b/drivers/mempool/octeontx2/meson.build index 3f93b509d..ab306b729 100644 --- a/drivers/mempool/octeontx2/meson.build +++ b/drivers/mempool/octeontx2/meson.build @@ -4,6 +4,7 @@ sources = files('otx2_mempool.c', 'otx2_mempool_irq.c', + 'otx2_mempool_debug.c' ) extra_flags = [] diff --git a/drivers/mempool/octeontx2/otx2_mempool.h b/drivers/mempool/octeontx2/otx2_mempool.h index 41542cf89..efaa308b3 100644 --- a/drivers/mempool/octeontx2/otx2_mempool.h +++ b/drivers/mempool/octeontx2/otx2_mempool.h @@ -202,4 +202,7 @@ int otx2_npa_lf_fini(void); int otx2_npa_register_irqs(struct otx2_npa_lf *lf); void otx2_npa_unregister_irqs(struct otx2_npa_lf *lf); +/* Debug */ +int otx2_mempool_ctx_dump(struct otx2_npa_lf *lf); + #endif /* __OTX2_MEMPOOL_H__ */ diff --git a/drivers/mempool/octeontx2/otx2_mempool_debug.c b/drivers/mempool/octeontx2/otx2_mempool_debug.c new file mode 100644 index 000000000..eef61ef07 --- /dev/null +++ b/drivers/mempool/octeontx2/otx2_mempool_debug.c @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#include "otx2_mempool.h" + +#define npa_dump(fmt, ...) fprintf(stderr, fmt "\n", ##__VA_ARGS__) + +static inline void +npa_lf_pool_dump(struct npa_pool_s *pool) +{ + npa_dump("W0: Stack base\t\t0x%"PRIx64"", pool->stack_base); + npa_dump("W1: ena \t\t%d\nW1: nat_align \t\t%d\nW1: stack_caching \t%d", + pool->ena, pool->nat_align, pool->stack_caching); + npa_dump("W1: stack_way_mask\t%d\nW1: buf_offset\t\t%d", + pool->stack_way_mask, pool->buf_offset); + npa_dump("W1: buf_size \t\t%d", pool->buf_size); + + npa_dump("W2: stack_max_pages \t%d\nW2: stack_pages\t\t%d", + pool->stack_max_pages, pool->stack_pages); + + npa_dump("W3: op_pc \t\t0x%"PRIx64"", (uint64_t)pool->op_pc); + + npa_dump("W4: stack_offset\t%d\nW4: shift\t\t%d\nW4: avg_level\t\t%d", + pool->stack_offset, pool->shift, pool->avg_level); + npa_dump("W4: avg_con \t\t%d\nW4: fc_ena\t\t%d\nW4: fc_stype\t\t%d", + pool->avg_con, pool->fc_ena, pool->fc_stype); + npa_dump("W4: fc_hyst_bits\t%d\nW4: fc_up_crossing\t%d", + pool->fc_hyst_bits, pool->fc_up_crossing); + npa_dump("W4: update_time\t\t%d\n", pool->update_time); + + npa_dump("W5: fc_addr\t\t0x%"PRIx64"\n", pool->fc_addr); + + npa_dump("W6: ptr_start\t\t0x%"PRIx64"\n", pool->ptr_start); + + npa_dump("W7: ptr_end\t\t0x%"PRIx64"\n", pool->ptr_end); + npa_dump("W8: err_int\t\t%d\nW8: err_int_ena\t\t%d", + pool->err_int, pool->err_int_ena); + npa_dump("W8: thresh_int\t\t%d", pool->thresh_int); + + npa_dump("W8: thresh_int_ena\t%d\nW8: thresh_up\t\t%d", + pool->thresh_int_ena, pool->thresh_up); + npa_dump("W8: thresh_qint_idx\t%d\nW8: err_qint_idx\t%d", + pool->thresh_qint_idx, pool->err_qint_idx); +} + +static inline void +npa_lf_aura_dump(struct npa_aura_s *aura) +{ + npa_dump("W0: Pool addr\t\t0x%"PRIx64"\n", aura->pool_addr); + + npa_dump("W1: ena\t\t\t%d\nW1: pool caching\t%d\nW1: pool way mask\t%d", + aura->ena, aura->pool_caching, aura->pool_way_mask); + npa_dump("W1: avg con\t\t%d\nW1: pool drop ena\t%d", + aura->avg_con, aura->pool_drop_ena); + npa_dump("W1: aura drop ena\t%d", aura->aura_drop_ena); + npa_dump("W1: bp_ena\t\t%d\nW1: aura drop\t\t%d\nW1: aura shift\t\t%d", + aura->bp_ena, aura->aura_drop, aura->shift); + npa_dump("W1: avg_level\t\t%d\n", aura->avg_level); + + npa_dump("W2: count\t\t%"PRIx64"\nW2: nix0_bpid\t\t%d", + (uint64_t)aura->count, aura->nix0_bpid); + npa_dump("W2: nix1_bpid\t\t%d", aura->nix1_bpid); + + npa_dump("W3: limit\t\t%"PRIx64"\nW3: bp\t\t\t%d\nW3: fc_ena\t\t%d\n", + (uint64_t)aura->limit, aura->bp, aura->fc_ena); + npa_dump("W3: fc_up_crossing\t%d\nW3: fc_stype\t\t%d", + aura->fc_up_crossing, aura->fc_stype); + + npa_dump("W3: fc_hyst_bits\t%d", aura->fc_hyst_bits); + + npa_dump("W4: fc_addr\t\t0x%"PRIx64"\n", aura->fc_addr); + + npa_dump("W5: pool_drop\t\t%d\nW5: update_time\t\t%d", + aura->pool_drop, aura->update_time); + npa_dump("W5: err_int\t\t%d", aura->err_int); + npa_dump("W5: err_int_ena\t\t%d\nW5: thresh_int\t\t%d", + aura->err_int_ena, aura->thresh_int); + npa_dump("W5: thresh_int_ena\t%d", aura->thresh_int_ena); + + npa_dump("W5: thresh_up\t\t%d\nW5: thresh_qint_idx\t%d", + aura->thresh_up, aura->thresh_qint_idx); + npa_dump("W5: err_qint_idx\t%d", aura->err_qint_idx); + + npa_dump("W6: thresh\t\t%"PRIx64"\n", (uint64_t)aura->thresh); +} + +int +otx2_mempool_ctx_dump(struct otx2_npa_lf *lf) +{ + struct npa_aq_enq_req *aq; + struct npa_aq_enq_rsp *rsp; + uint32_t q; + int rc; + + for (q = 0; q < lf->nr_pools; q++) { + /* Skip disabled POOL */ + if (rte_bitmap_get(lf->npa_bmp, q)) + continue; + + aq = otx2_mbox_alloc_msg_npa_aq_enq(lf->mbox); + aq->aura_id = q; + aq->ctype = NPA_AQ_CTYPE_POOL; + aq->op = NPA_AQ_INSTOP_READ; + + rc = otx2_mbox_process_msg(lf->mbox, (void *)&rsp); + if (rc) { + otx2_err("Failed to get pool(%d) context", q); + return rc; + } + npa_dump("============== pool=%d ===============\n", q); + npa_lf_pool_dump(&rsp->pool); + } + + for (q = 0; q < lf->nr_pools; q++) { + /* Skip disabled AURA */ + if (rte_bitmap_get(lf->npa_bmp, q)) + continue; + + aq = otx2_mbox_alloc_msg_npa_aq_enq(lf->mbox); + aq->aura_id = q; + aq->ctype = NPA_AQ_CTYPE_AURA; + aq->op = NPA_AQ_INSTOP_READ; + + rc = otx2_mbox_process_msg(lf->mbox, (void *)&rsp); + if (rc) { + otx2_err("Failed to get aura(%d) context", q); + return rc; + } + npa_dump("============== aura=%d ===============\n", q); + npa_lf_aura_dump(&rsp->aura); + } + + return rc; +} diff --git a/drivers/mempool/octeontx2/otx2_mempool_irq.c b/drivers/mempool/octeontx2/otx2_mempool_irq.c index 510d3e994..f8a01a696 100644 --- a/drivers/mempool/octeontx2/otx2_mempool_irq.c +++ b/drivers/mempool/octeontx2/otx2_mempool_irq.c @@ -203,6 +203,7 @@ npa_lf_q_irq(void *param) /* Clear interrupt */ otx2_write64(intr, lf->base + NPA_LF_QINTX_INT(qintx)); + otx2_mempool_ctx_dump(lf); rte_panic("npa_lf_q_interrupt\n"); } -- 2.21.0