From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id E96C4A045E for ; Sat, 1 Jun 2019 03:52:35 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 714C81B9DF; Sat, 1 Jun 2019 03:50:14 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id DCE981B9D4 for ; Sat, 1 Jun 2019 03:50:08 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x511jb5W000471 for ; Fri, 31 May 2019 18:50:08 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=n//xOsoCq7QWzfqAT50Hxj+CLCwJmhcdLcYHfysEmmI=; b=uvmUJWB+olORb4dTdV0aRAgV4o0loMmMSnf8rwn2OlX86WpbYstFfa7USnGCiFByE8/+ rLIE1cZ9rrLIu2vT6M372sqnuzX0Y8twGqtl13MjIxD+VHPWh2HaYud0xZ29bTZBQW2Q 2TeJ8fAhQWG1RWnj2ItwEpCjBhfa6qUScuLmPoy0ZgQ5oTDvl9MZM8+aCuTAs7lzcZk1 egXoZhXlmfndIZK+MQzp7eylJWVuoe8F44QMBuWxATyiJw9h5uSXN/gIIO8U7o/bAPlP +uNzzX4ggq/sxaEBm4Mxp2aCRGYGqgoaAivwGWqxEegsqaroRm3JVeFIsnGZ0z1N9iGA qg== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0a-0016f401.pphosted.com with ESMTP id 2sufgn82yh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 31 May 2019 18:50:08 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Fri, 31 May 2019 18:50:07 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Fri, 31 May 2019 18:50:07 -0700 Received: from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14]) by maili.marvell.com (Postfix) with ESMTP id 074903F704B; Fri, 31 May 2019 18:50:05 -0700 (PDT) From: To: , Jerin Jacob , Nithin Dabilpuram , Vamsi Attunuru CC: Kiran Kumar K Date: Sat, 1 Jun 2019 07:18:56 +0530 Message-ID: <20190601014905.45531-19-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190601014905.45531-1-jerinj@marvell.com> References: <20190523081339.56348-1-jerinj@marvell.com> <20190601014905.45531-1-jerinj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-01_02:, , signatures=0 Subject: [dpdk-dev] [PATCH v2 18/27] mempool/octeontx2: add NPA HW operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jerin Jacob Implement the low-level NPA HW operations such as alloc, free memory, etc. Signed-off-by: Jerin Jacob Signed-off-by: Kiran Kumar K --- drivers/mempool/octeontx2/otx2_mempool.h | 146 +++++++++++++++++++++++ 1 file changed, 146 insertions(+) diff --git a/drivers/mempool/octeontx2/otx2_mempool.h b/drivers/mempool/octeontx2/otx2_mempool.h index e1c255c60..871b45870 100644 --- a/drivers/mempool/octeontx2/otx2_mempool.h +++ b/drivers/mempool/octeontx2/otx2_mempool.h @@ -48,6 +48,152 @@ struct otx2_npa_lf { #define AURA_ID_MASK (BIT_ULL(16) - 1) +/* + * Generate 64bit handle to have optimized alloc and free aura operation. + * 0 - AURA_ID_MASK for storing the aura_id. + * AURA_ID_MASK+1 - (2^64 - 1) for storing the lf base address. + * This scheme is valid when OS can give AURA_ID_MASK + * aligned address for lf base address. + */ +static inline uint64_t +npa_lf_aura_handle_gen(uint32_t aura_id, uintptr_t addr) +{ + uint64_t val; + + val = aura_id & AURA_ID_MASK; + return (uint64_t)addr | val; +} + +static inline uint64_t +npa_lf_aura_handle_to_aura(uint64_t aura_handle) +{ + return aura_handle & AURA_ID_MASK; +} + +static inline uintptr_t +npa_lf_aura_handle_to_base(uint64_t aura_handle) +{ + return (uintptr_t)(aura_handle & ~AURA_ID_MASK); +} + +static inline uint64_t +npa_lf_aura_op_alloc(uint64_t aura_handle, const int drop) +{ + uint64_t wdata = npa_lf_aura_handle_to_aura(aura_handle); + + if (drop) + wdata |= BIT_ULL(63); /* DROP */ + + return otx2_atomic64_add_nosync(wdata, + (int64_t *)(npa_lf_aura_handle_to_base(aura_handle) + + NPA_LF_AURA_OP_ALLOCX(0))); +} + +static inline void +npa_lf_aura_op_free(uint64_t aura_handle, const int fabs, uint64_t iova) +{ + uint64_t reg = npa_lf_aura_handle_to_aura(aura_handle); + + if (fabs) + reg |= BIT_ULL(63); /* FABS */ + + otx2_store_pair(iova, reg, + npa_lf_aura_handle_to_base(aura_handle) + NPA_LF_AURA_OP_FREE0); +} + +static inline uint64_t +npa_lf_aura_op_cnt_get(uint64_t aura_handle) +{ + uint64_t wdata; + uint64_t reg; + + wdata = npa_lf_aura_handle_to_aura(aura_handle) << 44; + + reg = otx2_atomic64_add_nosync(wdata, + (int64_t *)(npa_lf_aura_handle_to_base(aura_handle) + + NPA_LF_AURA_OP_CNT)); + + if (reg & BIT_ULL(42) /* OP_ERR */) + return 0; + else + return reg & 0xFFFFFFFFF; +} + +static inline void +npa_lf_aura_op_cnt_set(uint64_t aura_handle, const int sign, uint64_t count) +{ + uint64_t reg = count & (BIT_ULL(36) - 1); + + if (sign) + reg |= BIT_ULL(43); /* CNT_ADD */ + + reg |= (npa_lf_aura_handle_to_aura(aura_handle) << 44); + + otx2_write64(reg, + npa_lf_aura_handle_to_base(aura_handle) + NPA_LF_AURA_OP_CNT); +} + +static inline uint64_t +npa_lf_aura_op_limit_get(uint64_t aura_handle) +{ + uint64_t wdata; + uint64_t reg; + + wdata = npa_lf_aura_handle_to_aura(aura_handle) << 44; + + reg = otx2_atomic64_add_nosync(wdata, + (int64_t *)(npa_lf_aura_handle_to_base(aura_handle) + + NPA_LF_AURA_OP_LIMIT)); + + if (reg & BIT_ULL(42) /* OP_ERR */) + return 0; + else + return reg & 0xFFFFFFFFF; +} + +static inline void +npa_lf_aura_op_limit_set(uint64_t aura_handle, uint64_t limit) +{ + uint64_t reg = limit & (BIT_ULL(36) - 1); + + reg |= (npa_lf_aura_handle_to_aura(aura_handle) << 44); + + otx2_write64(reg, + npa_lf_aura_handle_to_base(aura_handle) + NPA_LF_AURA_OP_LIMIT); +} + +static inline uint64_t +npa_lf_aura_op_available(uint64_t aura_handle) +{ + uint64_t wdata; + uint64_t reg; + + wdata = npa_lf_aura_handle_to_aura(aura_handle) << 44; + + reg = otx2_atomic64_add_nosync(wdata, + (int64_t *)(npa_lf_aura_handle_to_base( + aura_handle) + NPA_LF_POOL_OP_AVAILABLE)); + + if (reg & BIT_ULL(42) /* OP_ERR */) + return 0; + else + return reg & 0xFFFFFFFFF; +} + +static inline void +npa_lf_aura_op_range_set(uint64_t aura_handle, uint64_t start_iova, + uint64_t end_iova) +{ + uint64_t reg = npa_lf_aura_handle_to_aura(aura_handle); + + otx2_store_pair(start_iova, reg, + npa_lf_aura_handle_to_base(aura_handle) + + NPA_LF_POOL_OP_PTR_START0); + otx2_store_pair(end_iova, reg, + npa_lf_aura_handle_to_base(aura_handle) + + NPA_LF_POOL_OP_PTR_END0); +} + /* NPA LF */ int otx2_npa_lf_init(struct rte_pci_device *pci_dev, void *otx2_dev); int otx2_npa_lf_fini(void); -- 2.21.0