From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id E8A85A046B for ; Sat, 1 Jun 2019 20:57:43 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 94C961B9B6; Sat, 1 Jun 2019 20:56:11 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 20ECE1B947 for ; Sat, 1 Jun 2019 20:55:41 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x51Itbrd030054 for ; Sat, 1 Jun 2019 11:55:40 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=ahpRi9fGIWyJ190rzyTCbayQvi4ncvlAKDrizzwvnb8=; b=fX3gLEtKIx1G1JEL/3RQvdVCeJgimsYymyM8wxVmYTAu1WV/zeAcYMfjPAzrmmldYSmm /Grdiw5eVEcYC3/LAtsLtqyDGCgwMxtJj4x8IfW7vPK2ikwV3eEDergPLwanwUNbXtlN UfI4Nq6dak/PYtOpPX8rR1WE9QG1iHWfDsHm7Si3a+za5AkMC058Su9xdRxazCdTHUXl 0KL9O62+HKphDc1tx3DMK/+Q6X+j/xUo6Afcf9w7p3hbV/HexE+oeUaQnDGE2KwTxdL1 QGRnQ72U6bxolyM1d4PP3d7hR7sEdKQoByb5cwEcC1crp4RFKAOluZz+/wf0i6y2jK2n +w== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0b-0016f401.pphosted.com with ESMTP id 2survk12dg-6 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 01 Jun 2019 11:55:40 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 1 Jun 2019 11:55:37 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 1 Jun 2019 11:55:37 -0700 Received: from BG-LT7430.marvell.com (unknown [10.28.17.28]) by maili.marvell.com (Postfix) with ESMTP id 6E4BC3F7129; Sat, 1 Jun 2019 11:55:17 -0700 (PDT) From: To: , Pavan Nikhilesh CC: Date: Sun, 2 Jun 2019 00:23:19 +0530 Message-ID: <20190601185355.370-10-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190601185355.370-1-pbhagavatula@marvell.com> References: <20190601185355.370-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-01_13:, , signatures=0 Subject: [dpdk-dev] [PATCH 09/44] event/octeontx2: support linking queues to ports X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Links between queues and ports are controlled by setting/clearing GGRP membership in SSOW_LF_GWS_GRPMSK_CHG. Signed-off-by: Pavan Nikhilesh --- drivers/event/octeontx2/otx2_evdev.c | 73 ++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c index baae47054..7875a9ac5 100644 --- a/drivers/event/octeontx2/otx2_evdev.c +++ b/drivers/event/octeontx2/otx2_evdev.c @@ -39,6 +39,60 @@ otx2_sso_info_get(struct rte_eventdev *event_dev, RTE_EVENT_DEV_CAP_NONSEQ_MODE; } +static void +sso_port_link_modify(struct otx2_ssogws *ws, uint8_t queue, uint8_t enable) +{ + uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op); + uint64_t val; + + val = queue; + val |= 0ULL << 12; /* SET 0 */ + val |= 0x8000800080000000; /* Dont modify rest of the masks */ + val |= (uint64_t)enable << 14; /* Enable/Disable Membership. */ + + otx2_write64(val, base + SSOW_LF_GWS_GRPMSK_CHG); +} + +static int +otx2_sso_port_link(struct rte_eventdev *event_dev, void *port, + const uint8_t queues[], const uint8_t priorities[], + uint16_t nb_links) +{ + uint8_t port_id = 0; + uint16_t link; + + RTE_SET_USED(event_dev); + RTE_SET_USED(priorities); + for (link = 0; link < nb_links; link++) { + struct otx2_ssogws *ws = port; + + port_id = ws->port; + sso_port_link_modify(ws, queues[link], true); + } + sso_func_trace("port=%d nb_links=%d", port_id, nb_links); + + return (int)nb_links; +} + +static int +otx2_sso_port_unlink(struct rte_eventdev *event_dev, void *port, + uint8_t queues[], uint16_t nb_unlinks) +{ + uint8_t port_id = 0; + uint16_t unlink; + + RTE_SET_USED(event_dev); + for (unlink = 0; unlink < nb_unlinks; unlink++) { + struct otx2_ssogws *ws = port; + + port_id = ws->port; + sso_port_link_modify(ws, queues[unlink], false); + } + sso_func_trace("port=%d nb_unlinks=%d", port_id, nb_unlinks); + + return (int)nb_unlinks; +} + static int sso_hw_lf_cfg(struct otx2_mbox *mbox, enum otx2_sso_lf_type type, uint16_t nb_lf, uint8_t attach) @@ -157,6 +211,21 @@ otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id) RTE_SET_USED(queue_id); } +static void +sso_clr_links(const struct rte_eventdev *event_dev) +{ + struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev); + int i, j; + + for (i = 0; i < dev->nb_event_ports; i++) { + struct otx2_ssogws *ws; + + ws = event_dev->data->ports[i]; + for (j = 0; j < dev->nb_event_queues; j++) + sso_port_link_modify(ws, j, false); + } +} + static void sso_set_port_ops(struct otx2_ssogws *ws, uintptr_t base) { @@ -445,6 +514,8 @@ otx2_sso_configure(const struct rte_eventdev *event_dev) goto teardown_hwggrp; } + /* Clear any prior port-queue mapping. */ + sso_clr_links(event_dev); rc = sso_ggrp_alloc_xaq(dev); if (rc < 0) { otx2_err("failed to alloc xaq to ggrp %d", rc); @@ -569,6 +640,8 @@ static struct rte_eventdev_ops otx2_sso_ops = { .port_def_conf = otx2_sso_port_def_conf, .port_setup = otx2_sso_port_setup, .port_release = otx2_sso_port_release, + .port_link = otx2_sso_port_link, + .port_unlink = otx2_sso_port_unlink, }; #define OTX2_SSO_XAE_CNT "xae_cnt" -- 2.21.0