From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id F0993A046B for ; Sat, 1 Jun 2019 20:57:17 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7EC301B9A8; Sat, 1 Jun 2019 20:56:06 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id DDA7F2F4F for ; Sat, 1 Jun 2019 20:55:40 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x51Itbrc030054 for ; Sat, 1 Jun 2019 11:55:40 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=bgpRd0PLzXhsRrtQGWq3mlLAh4J7VkTWa3YkLG6+nbo=; b=FDrNaBbZxs6S0PMTmg6MN/QNFMJANRp1hklT7mC2xlsNeL+Nfa9hMK9jYAx/Z8Am0etE bKdc5PVVHJcUc9qgMz643L/k3AvrUUG0qPUSIK+Aexwizqs0uXt/L/+enwCgS22R2TWF y0ov6nROxDCvMb7Zlre0GzZMRlH70eGgCP6Fmr2PizfwrIBhcVe8PyNy17BS2G+q9OYh avYzxfAgex1nFIpFClMIqLNDQd7DcbpPJZ4jPi8sYTRX4Hek37ZIKMKZDOXy+YbkanLL fyQoMxsKH+MD1AkYRgyQcVlHBOn9tFjqvpBTHqGwbZEaqhtyUMfboy74pS8XHjVWHvj1 VQ== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0b-0016f401.pphosted.com with ESMTP id 2survk12dh-5 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 01 Jun 2019 11:55:40 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 1 Jun 2019 11:55:37 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 1 Jun 2019 11:55:37 -0700 Received: from BG-LT7430.marvell.com (unknown [10.28.17.28]) by maili.marvell.com (Postfix) with ESMTP id A47E23F7132; Sat, 1 Jun 2019 11:55:22 -0700 (PDT) From: To: , Pavan Nikhilesh CC: Date: Sun, 2 Jun 2019 00:23:21 +0530 Message-ID: <20190601185355.370-12-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190601185355.370-1-pbhagavatula@marvell.com> References: <20190601185355.370-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-01_13:, , signatures=0 Subject: [dpdk-dev] [PATCH 11/44] event/octeontx2: add SSO GWS and GGRP IRQ handlers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Register and implement SSO GWS and GGRP IRQ handlers for error interrupts. Signed-off-by: Pavan Nikhilesh Signed-off-by: Jerin Jacob --- drivers/event/octeontx2/Makefile | 1 + drivers/event/octeontx2/meson.build | 4 +- drivers/event/octeontx2/otx2_evdev.c | 38 +++++ drivers/event/octeontx2/otx2_evdev.h | 6 + drivers/event/octeontx2/otx2_evdev_irq.c | 179 +++++++++++++++++++++++ 5 files changed, 227 insertions(+), 1 deletion(-) create mode 100644 drivers/event/octeontx2/otx2_evdev_irq.c diff --git a/drivers/event/octeontx2/Makefile b/drivers/event/octeontx2/Makefile index 58853e1b9..4f09c1fc8 100644 --- a/drivers/event/octeontx2/Makefile +++ b/drivers/event/octeontx2/Makefile @@ -31,6 +31,7 @@ LIBABIVER := 1 # SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_evdev.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_evdev_irq.c LDLIBS += -lrte_eal -lrte_bus_pci -lrte_pci -lrte_kvargs LDLIBS += -lrte_mempool -lrte_eventdev -lrte_mbuf diff --git a/drivers/event/octeontx2/meson.build b/drivers/event/octeontx2/meson.build index 3fc96421d..5aa8113bd 100644 --- a/drivers/event/octeontx2/meson.build +++ b/drivers/event/octeontx2/meson.build @@ -2,7 +2,9 @@ # Copyright(C) 2019 Marvell International Ltd. # -sources = files('otx2_evdev.c') +sources = files('otx2_evdev.c', + 'otx2_evdev_irq.c', + ) allow_experimental_apis = true diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c index 485552c44..c8623b502 100644 --- a/drivers/event/octeontx2/otx2_evdev.c +++ b/drivers/event/octeontx2/otx2_evdev.c @@ -13,6 +13,29 @@ #include #include "otx2_evdev.h" +#include "otx2_irq.h" + +static inline int +sso_get_msix_offsets(const struct rte_eventdev *event_dev) +{ + struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev); + uint8_t nb_ports = dev->nb_event_ports; + struct otx2_mbox *mbox = dev->mbox; + struct msix_offset_rsp *msix_rsp; + int i, rc; + + /* Get SSO and SSOW MSIX vector offsets */ + otx2_mbox_alloc_msg_msix_offset(mbox); + rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp); + + for (i = 0; i < nb_ports; i++) + dev->ssow_msixoff[i] = msix_rsp->ssow_msixoff[i]; + + for (i = 0; i < dev->nb_event_queues; i++) + dev->sso_msixoff[i] = msix_rsp->sso_msixoff[i]; + + return rc; +} static void otx2_sso_info_get(struct rte_eventdev *event_dev, @@ -486,6 +509,9 @@ otx2_sso_configure(const struct rte_eventdev *event_dev) return -EINVAL; } + if (dev->configured) + sso_unregister_irqs(event_dev); + if (dev->nb_event_queues) { /* Finit any previous queues. */ sso_lf_teardown(dev, SSO_LF_GGRP); @@ -522,6 +548,18 @@ otx2_sso_configure(const struct rte_eventdev *event_dev) goto teardown_hwggrp; } + rc = sso_get_msix_offsets(event_dev); + if (rc < 0) { + otx2_err("failed to get msix offsets %d", rc); + goto teardown_hwggrp; + } + + rc = sso_register_irqs(event_dev); + if (rc < 0) { + otx2_err("failed to register irq %d", rc); + goto teardown_hwggrp; + } + dev->configured = 1; rte_mb(); diff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h index 1a9de1b86..e1d2dcc69 100644 --- a/drivers/event/octeontx2/otx2_evdev.h +++ b/drivers/event/octeontx2/otx2_evdev.h @@ -105,6 +105,9 @@ struct otx2_sso_evdev { uint32_t xae_waes; uint32_t xaq_buf_size; uint32_t iue; + /* MSIX offsets */ + uint16_t sso_msixoff[OTX2_SSO_MAX_VHGRP]; + uint16_t ssow_msixoff[OTX2_SSO_MAX_VHWS]; } __rte_cache_aligned; #define OTX2_SSOGWS_OPS \ @@ -148,5 +151,8 @@ parse_kvargs_value(const char *key, const char *value, void *opaque) /* Init and Fini API's */ int otx2_sso_init(struct rte_eventdev *event_dev); int otx2_sso_fini(struct rte_eventdev *event_dev); +/* IRQ handlers */ +int sso_register_irqs(const struct rte_eventdev *event_dev); +void sso_unregister_irqs(const struct rte_eventdev *event_dev); #endif /* __OTX2_EVDEV_H__ */ diff --git a/drivers/event/octeontx2/otx2_evdev_irq.c b/drivers/event/octeontx2/otx2_evdev_irq.c new file mode 100644 index 000000000..ecc8ae775 --- /dev/null +++ b/drivers/event/octeontx2/otx2_evdev_irq.c @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#include "otx2_evdev.h" + +static void +sso_lf_irq(void *param) +{ + uintptr_t base = (uintptr_t)param; + uint64_t intr; + uint8_t ggrp; + + ggrp = (base >> 12) & 0xFF; + + intr = otx2_read64(base + SSO_LF_GGRP_INT); + if (intr == 0) + return; + + otx2_err("GGRP %d GGRP_INT=0x%" PRIx64 "", ggrp, intr); + + /* Clear interrupt */ + otx2_write64(intr, base + SSO_LF_GGRP_INT); + + abort(); +} + +static int +sso_lf_register_irq(const struct rte_eventdev *event_dev, uint16_t ggrp_msixoff, + uintptr_t base) +{ + struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev); + struct rte_intr_handle *handle = &pci_dev->intr_handle; + int rc, vec; + + vec = ggrp_msixoff + SSO_LF_INT_VEC_GRP; + + /* Clear err interrupt */ + otx2_write64(~0ull, base + SSO_LF_GGRP_INT_ENA_W1C); + /* Set used interrupt vectors */ + rc = otx2_register_irq(handle, sso_lf_irq, (void *)base, vec); + /* Enable hw interrupt */ + otx2_write64(~0ull, base + SSO_LF_GGRP_INT_ENA_W1S); + + return rc; +} + +static void +ssow_lf_irq(void *param) +{ + uintptr_t base = (uintptr_t)param; + uint8_t gws = (base >> 12) & 0xFF; + uint64_t intr; + + intr = otx2_read64(base + SSOW_LF_GWS_INT); + if (intr == 0) + return; + + otx2_err("GWS %d GWS_INT=0x%" PRIx64 "", gws, intr); + + /* Clear interrupt */ + otx2_write64(intr, base + SSOW_LF_GWS_INT); + + abort(); +} + +static int +ssow_lf_register_irq(const struct rte_eventdev *event_dev, uint16_t gws_msixoff, + uintptr_t base) +{ + struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev); + struct rte_intr_handle *handle = &pci_dev->intr_handle; + int rc, vec; + + vec = gws_msixoff + SSOW_LF_INT_VEC_IOP; + + /* Clear err interrupt */ + otx2_write64(~0ull, base + SSOW_LF_GWS_INT_ENA_W1C); + /* Set used interrupt vectors */ + rc = otx2_register_irq(handle, ssow_lf_irq, (void *)base, vec); + /* Enable hw interrupt */ + otx2_write64(~0ull, base + SSOW_LF_GWS_INT_ENA_W1S); + + return rc; +} + +static void +sso_lf_unregister_irq(const struct rte_eventdev *event_dev, + uint16_t ggrp_msixoff, uintptr_t base) +{ + struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev); + struct rte_intr_handle *handle = &pci_dev->intr_handle; + int vec; + + vec = ggrp_msixoff + SSO_LF_INT_VEC_GRP; + + /* Clear err interrupt */ + otx2_write64(~0ull, base + SSO_LF_GGRP_INT_ENA_W1C); + otx2_unregister_irq(handle, sso_lf_irq, (void *)base, vec); +} + +static void +ssow_lf_unregister_irq(const struct rte_eventdev *event_dev, + uint16_t gws_msixoff, uintptr_t base) +{ + struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev); + struct rte_intr_handle *handle = &pci_dev->intr_handle; + int vec; + + vec = gws_msixoff + SSOW_LF_INT_VEC_IOP; + + /* Clear err interrupt */ + otx2_write64(~0ull, base + SSOW_LF_GWS_INT_ENA_W1C); + otx2_unregister_irq(handle, ssow_lf_irq, (void *)base, vec); +} + +int +sso_register_irqs(const struct rte_eventdev *event_dev) +{ + struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev); + int i, rc = -EINVAL; + uint8_t nb_ports; + + nb_ports = dev->nb_event_ports; + + for (i = 0; i < dev->nb_event_queues; i++) { + if (dev->sso_msixoff[i] == MSIX_VECTOR_INVALID) { + otx2_err("Invalid SSOLF MSIX offset[%d] vector: 0x%x", + i, dev->sso_msixoff[i]); + goto fail; + } + } + + for (i = 0; i < nb_ports; i++) { + if (dev->ssow_msixoff[i] == MSIX_VECTOR_INVALID) { + otx2_err("Invalid SSOWLF MSIX offset[%d] vector: 0x%x", + i, dev->ssow_msixoff[i]); + goto fail; + } + } + + for (i = 0; i < dev->nb_event_queues; i++) { + uintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | + i << 12); + rc = sso_lf_register_irq(event_dev, dev->sso_msixoff[i], base); + } + + for (i = 0; i < nb_ports; i++) { + uintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | + i << 12); + rc = ssow_lf_register_irq(event_dev, dev->ssow_msixoff[i], + base); + } + +fail: + return rc; +} + +void +sso_unregister_irqs(const struct rte_eventdev *event_dev) +{ + struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev); + uint8_t nb_ports; + int i; + + nb_ports = dev->nb_event_ports; + + for (i = 0; i < dev->nb_event_queues; i++) { + uintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | + i << 12); + sso_lf_unregister_irq(event_dev, dev->sso_msixoff[i], base); + } + + for (i = 0; i < nb_ports; i++) { + uintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | + i << 12); + ssow_lf_unregister_irq(event_dev, dev->ssow_msixoff[i], base); + } +} -- 2.21.0