From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 1537CA046B for ; Sat, 1 Jun 2019 21:00:44 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 262B61BAB6; Sat, 1 Jun 2019 20:57:05 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id BC6621B9DC for ; Sat, 1 Jun 2019 20:56:22 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x51ItbNT029526 for ; Sat, 1 Jun 2019 11:56:22 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=36oElAralxVt9dQk+X6JT+x8UQQ1v9WR+Pdukful8Ik=; b=N9wND+czyt5pA6apWnNqjkuANaFu5f8HNlzS9QtlcYQG7kE9TYLFgxnrj8HhZlAUmJt6 9OAuD+8yE3exjk+CggdbvRs9nYaczZREnjU5zrj54/wctMJFAESj5CITGk8/k/xBtD4q fn/TJJFVQjQmxSBzMrEC+OgisVfAhRULSoPJdFZuRaoTgstpQEp3c4DqSzM6GgTmJ6oh nZxnkqC6ICkO7uo8B5Dx1G2p7wrWYrERS2FJErIOfKUai1jZiiwT4s7nDar/3T1e5Aii EnX1hIgoH+Q3Faza0yYWR/knHjG/iAfYXGndT5ZYD9j117IrIKWXCrAgmKwzkcMt+1EJ Kg== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0a-0016f401.pphosted.com with ESMTP id 2supqksg05-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 01 Jun 2019 11:56:21 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 1 Jun 2019 11:56:20 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 1 Jun 2019 11:56:20 -0700 Received: from BG-LT7430.marvell.com (unknown [10.28.17.28]) by maili.marvell.com (Postfix) with ESMTP id AD45C3F7040; Sat, 1 Jun 2019 11:56:19 -0700 (PDT) From: To: , Pavan Nikhilesh CC: Date: Sun, 2 Jun 2019 00:23:42 +0530 Message-ID: <20190601185355.370-33-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190601185355.370-1-pbhagavatula@marvell.com> References: <20190601185355.370-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-01_13:, , signatures=0 Subject: [dpdk-dev] [PATCH 32/44] event/octeontx2: add devargs to modify chunk slots X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add devargs support to modify number of chunk slots. Chunks are used to store event timers, a chunk can be visualised as an array where the last element points to the next chunk and rest of them are used to store events. TIM traverses the list of chunks and enqueues the event timers to SSO. If no argument is passed then a default value of 255 is taken. Example: --dev "0002:0e:00.0,tim_chnk_slots=511" Signed-off-by: Pavan Nikhilesh --- drivers/event/octeontx2/otx2_tim_evdev.c | 11 ++++++++++- drivers/event/octeontx2/otx2_tim_evdev.h | 2 ++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c index 9cceafd77..bba6cc609 100644 --- a/drivers/event/octeontx2/otx2_tim_evdev.c +++ b/drivers/event/octeontx2/otx2_tim_evdev.c @@ -240,7 +240,7 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr) tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10); tim_ring->max_tout = rcfg->max_tmo_ns; tim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec); - tim_ring->chunk_sz = OTX2_TIM_RING_DEF_CHNK_SZ; + tim_ring->chunk_sz = dev->chunk_sz; nb_timers = rcfg->nb_timers; tim_ring->disable_npa = dev->disable_npa; @@ -355,6 +355,7 @@ otx2_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, } #define OTX2_TIM_DISABLE_NPA "tim_disable_npa" +#define OTX2_TIM_CHNK_SLOTS "tim_chnk_slots" static void tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev) @@ -370,6 +371,8 @@ tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev) rte_kvargs_process(kvlist, OTX2_TIM_DISABLE_NPA, &parse_kvargs_flag, &dev->disable_npa); + rte_kvargs_process(kvlist, OTX2_TIM_CHNK_SLOTS, + &parse_kvargs_value, &dev->chunk_slots); } void @@ -423,6 +426,12 @@ otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev) goto mz_free; } + if (!dev->chunk_slots) + dev->chunk_sz = OTX2_TIM_RING_DEF_CHNK_SZ; + else + dev->chunk_sz = (dev->chunk_slots + 1) * + OTX2_TIM_CHUNK_ALIGNMENT; + return; mz_free: diff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h index e4b8cd4ce..617902a0b 100644 --- a/drivers/event/octeontx2/otx2_tim_evdev.h +++ b/drivers/event/octeontx2/otx2_tim_evdev.h @@ -54,9 +54,11 @@ struct otx2_tim_evdev { struct rte_eventdev *event_dev; struct otx2_mbox *mbox; uint16_t nb_rings; + uint32_t chunk_sz; uintptr_t bar2; /* Dev args */ uint8_t disable_npa; + uint16_t chunk_slots; }; struct otx2_tim_ring { -- 2.21.0