From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 95E21A046B for ; Sat, 1 Jun 2019 20:56:58 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id DBFB21B99F; Sat, 1 Jun 2019 20:56:02 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id B66854F91 for ; Sat, 1 Jun 2019 20:55:40 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x51Itbrb030054 for ; Sat, 1 Jun 2019 11:55:40 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=egDoLneDj9iUNK6jBinN9RopHF2nVKRvGWL3/pu2Tkc=; b=fEkicmmGSbLrTMn+2B/3dClTpIbfYHYvldKzEwMvHetGFQzQDUoizIdrRM3CVSGFAL70 LgK+EBmUT22R+0rsBLcE2kCk9hZO09nMw1G+dlm5IkqNnBEA+2MtLChRK7KtLLgmmuZL Gk0a1Ae+Rw6OmQgsTJirzTqXB3MvIH315Z1GEcJF6jkdBUvm8TmnXBheDw1ML/tGXAht U7sGFScmZnEQeSI5YHKiE2Zr2XzfNlZ/c2p6MLxuKKwGbfxgloQStfwAyD8Si0W7xQiM iLUG3tFbCKInfc9c6P8GewV9bGsFqLwRaooehNuS+c4PiYb1fIiW/fQLS2/lgC1WDwOx IQ== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0b-0016f401.pphosted.com with ESMTP id 2survk12dg-5 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 01 Jun 2019 11:55:39 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 1 Jun 2019 11:55:35 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 1 Jun 2019 11:55:35 -0700 Received: from BG-LT7430.marvell.com (unknown [10.28.17.28]) by maili.marvell.com (Postfix) with ESMTP id C11583F70E5; Sat, 1 Jun 2019 11:55:01 -0700 (PDT) From: To: , Pavan Nikhilesh CC: Date: Sun, 2 Jun 2019 00:23:13 +0530 Message-ID: <20190601185355.370-4-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190601185355.370-1-pbhagavatula@marvell.com> References: <20190601185355.370-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-01_13:, , signatures=0 Subject: [dpdk-dev] [PATCH 03/44] event/octeontx2: add device capabilities function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add the info_get function to return details on the queues, flow, prioritization capabilities, etc. which this device has. Signed-off-by: Pavan Nikhilesh --- drivers/event/octeontx2/otx2_evdev.c | 31 ++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c index 15190af9e..7c46906e8 100644 --- a/drivers/event/octeontx2/otx2_evdev.c +++ b/drivers/event/octeontx2/otx2_evdev.c @@ -12,6 +12,36 @@ #include "otx2_evdev.h" +static void +otx2_sso_info_get(struct rte_eventdev *event_dev, + struct rte_event_dev_info *dev_info) +{ + struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev); + + dev_info->driver_name = RTE_STR(EVENTDEV_NAME_OCTEONTX2_PMD); + dev_info->min_dequeue_timeout_ns = dev->min_dequeue_timeout_ns; + dev_info->max_dequeue_timeout_ns = dev->max_dequeue_timeout_ns; + dev_info->max_event_queues = dev->max_event_queues; + dev_info->max_event_queue_flows = (1ULL << 20); + dev_info->max_event_queue_priority_levels = 8; + dev_info->max_event_priority_levels = 1; + dev_info->max_event_ports = dev->max_event_ports; + dev_info->max_event_port_dequeue_depth = 1; + dev_info->max_event_port_enqueue_depth = 1; + dev_info->max_num_events = dev->max_num_events; + dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_QUEUE_QOS | + RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED | + RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES | + RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK | + RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT | + RTE_EVENT_DEV_CAP_NONSEQ_MODE; +} + +/* Initialize and register event driver with DPDK Application */ +static struct rte_eventdev_ops otx2_sso_ops = { + .dev_infos_get = otx2_sso_info_get, +}; + static int otx2_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) { @@ -51,6 +81,7 @@ otx2_sso_init(struct rte_eventdev *event_dev) struct otx2_sso_evdev *dev; int rc; + event_dev->dev_ops = &otx2_sso_ops; /* For secondary processes, the primary has done all the work */ if (rte_eal_process_type() != RTE_PROC_PRIMARY) return 0; -- 2.21.0