From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id C0081A046B for ; Sat, 1 Jun 2019 21:02:18 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C48041BBD6; Sat, 1 Jun 2019 20:57:20 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id E83D91B94B for ; Sat, 1 Jun 2019 20:56:51 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x51IsdL8029443 for ; Sat, 1 Jun 2019 11:56:51 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=dY3oqenZB92TN5m0ab29398sf0NL87pXGHveAphbphk=; b=jDGmxexM+eLEga46OMk5b+vCSGYIbDkAGdNOlMlPKY+CD9OWaoDQLgQy1uWp5eyz5h1/ ZNWdxHkKamNHwl+VGEFf82PJaIf2kAP6ForkAEqOoYLJHIoTbqBqesNEW4NZMuz/nMyZ yQYe+uXCphhYhOSCHub2dyjxhw1IrK6RpajWBx+R/2aJpfEFt4WYaqoeIP4pe4qQjXfJ csQPa9ASLsaf1FCdN1FbZNA2NxtkQwckcdqSLQyepA8sR8Qo9PQYBEMD82k0faQhtZWb uAgXKBklZEGstfEP3E9EGwpkoVgbG3PpHvCJq2FECo4uzNlVWFL72V20woA6REu2BuTv vA== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 2survk12k7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 01 Jun 2019 11:56:51 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 1 Jun 2019 11:56:49 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 1 Jun 2019 11:56:49 -0700 Received: from BG-LT7430.marvell.com (unknown [10.28.17.28]) by maili.marvell.com (Postfix) with ESMTP id 7B8073F7040; Sat, 1 Jun 2019 11:56:48 -0700 (PDT) From: To: , Pavan Nikhilesh CC: Date: Sun, 2 Jun 2019 00:23:53 +0530 Message-ID: <20190601185355.370-44-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190601185355.370-1-pbhagavatula@marvell.com> References: <20190601185355.370-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-01_13:, , signatures=0 Subject: [dpdk-dev] [PATCH 43/44] event/octeontx2: add devargs to control adapter parameters X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add devargs to control each event timer adapter i.e. TIM rings internal parameters uniquely. The following dict format is expected [ring-chnk_slots-disable_npa-stats_ena]. 0 represents default values. Example: --dev "0002:0e:00.0,tim_ring_ctl=[2-1023-1-0]" Signed-off-by: Pavan Nikhilesh --- drivers/event/octeontx2/otx2_tim_evdev.c | 87 +++++++++++++++++++++++- drivers/event/octeontx2/otx2_tim_evdev.h | 10 +++ 2 files changed, 96 insertions(+), 1 deletion(-) diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c index c4fd2271e..2f9b7acc4 100644 --- a/drivers/event/octeontx2/otx2_tim_evdev.c +++ b/drivers/event/octeontx2/otx2_tim_evdev.c @@ -255,7 +255,7 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr) struct tim_lf_alloc_req *req; struct tim_lf_alloc_rsp *rsp; uint64_t nb_timers; - int rc; + int i, rc; if (dev == NULL) return -ENODEV; @@ -304,6 +304,18 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr) tim_ring->disable_npa = dev->disable_npa; tim_ring->enable_stats = dev->enable_stats; + for (i = 0; i < dev->ring_ctl_cnt ; i++) { + struct otx2_tim_ctl *ring_ctl = &dev->ring_ctl_data[i]; + + if (ring_ctl->ring == tim_ring->ring_id) { + tim_ring->chunk_sz = ring_ctl->chunk_slots ? + ((uint32_t)(ring_ctl->chunk_slots + 1) * + OTX2_TIM_CHUNK_ALIGNMENT) : tim_ring->chunk_sz; + tim_ring->enable_stats = ring_ctl->enable_stats; + tim_ring->disable_npa = ring_ctl->disable_npa; + } + } + tim_ring->nb_chunks = nb_timers / OTX2_TIM_NB_CNK_SLOTS( tim_ring->chunk_sz); tim_ring->nb_chunk_slots = OTX2_TIM_NB_CNK_SLOTS(tim_ring->chunk_sz); @@ -528,6 +540,77 @@ otx2_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, #define OTX2_TIM_CHNK_SLOTS "tim_chnk_slots" #define OTX2_TIM_STATS_ENA "tim_stats_ena" #define OTX2_TIM_RINGS_LMT "tim_rings_lmt" +#define OTX2_TIM_RING_CTL "tim_ring_ctl" + +static void +tim_parse_ring_param(char *value, void *opaque) +{ + struct otx2_tim_evdev *dev = opaque; + struct otx2_tim_ctl ring_ctl = {0}; + char *tok = strtok(value, "-"); + uint16_t *val; + + val = (uint16_t *)&ring_ctl; + + if (!strlen(value)) + return; + + while (tok != NULL) { + *val = atoi(tok); + tok = strtok(NULL, "-"); + val++; + } + + if (val != (&ring_ctl.enable_stats + 1)) { + otx2_err( + "Invalid ring param expected [ring-chunk_sz-disable_npa-enable_stats]"); + return; + } + + dev->ring_ctl_cnt++; + dev->ring_ctl_data = rte_realloc(dev->ring_ctl_data, + sizeof(struct otx2_tim_ctl), 0); + dev->ring_ctl_data[dev->ring_ctl_cnt - 1] = ring_ctl; +} + +static void +tim_parse_ring_ctl_list(const char *value, void *opaque) +{ + char *s = strdup(value); + char *start = NULL; + char *end = NULL; + char *f = s; + + while (*s) { + if (*s == '[') + start = s; + else if (*s == ']') + end = s; + + if (start < end && *start) { + *end = 0; + tim_parse_ring_param(start + 1, opaque); + start = end; + s = end; + } + s++; + } + + free(f); +} + +static int +tim_parse_kvargs_dict(const char *key, const char *value, void *opaque) +{ + RTE_SET_USED(key); + + /* Dict format [ring-chunk_sz-disable_npa-enable_stats] use '-' as ',' + * isn't allowed. 0 represents default. + */ + tim_parse_ring_ctl_list(value, opaque); + + return 0; +} static void tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev) @@ -549,6 +632,8 @@ tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev) &dev->enable_stats); rte_kvargs_process(kvlist, OTX2_TIM_RINGS_LMT, &parse_kvargs_value, &dev->min_ring_cnt); + rte_kvargs_process(kvlist, OTX2_TIM_RING_CTL, + &tim_parse_kvargs_dict, &dev); } void diff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h index ef3c8b50e..731b266a3 100644 --- a/drivers/event/octeontx2/otx2_tim_evdev.h +++ b/drivers/event/octeontx2/otx2_tim_evdev.h @@ -101,6 +101,13 @@ struct otx2_tim_ent { uint64_t wqe; } __rte_packed; +struct otx2_tim_ctl { + uint16_t ring; + uint16_t chunk_slots; + uint16_t disable_npa; + uint16_t enable_stats; +}; + struct otx2_tim_evdev { struct rte_pci_device *pci_dev; struct rte_eventdev *event_dev; @@ -113,6 +120,9 @@ struct otx2_tim_evdev { uint16_t chunk_slots; uint16_t min_ring_cnt; uint8_t enable_stats; + uint16_t ring_ctl_cnt; + struct otx2_tim_ctl *ring_ctl_data; + /* HW const */ /* MSIX offsets */ uint16_t tim_msixoff[OTX2_MAX_TIM_RINGS]; }; -- 2.21.0