From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 879F7A046B for ; Sat, 1 Jun 2019 20:56:27 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id EA8031B96E; Sat, 1 Jun 2019 20:55:56 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 4A2AD378B for ; Sat, 1 Jun 2019 20:55:40 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x51ItbrY030054 for ; Sat, 1 Jun 2019 11:55:39 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=94LLsJ9sfCPfnQ44hb3S1knTsSmveGsdbG21k7ejumo=; b=R3tsbOqWizmGKDSRFypjR2rZK4SZwCeNpj1bHmtbvLGg4PVAkJEJHYM/2G6spA4NorQl V6H51qSPOIYIqJB98Qya1Cqv2Mm7g/9if6kMKDG0Bk5UAn+rJyDlho6+nteNNUvKgMEE CzpPpwSd63igLe3CG56SlLbK6sC1TFI5CrFx8HPheOdRLQXPi6lrWZHjAwqTvWzQhyVI xJy9rcc9EMp20mvs+2hGu95r4TTYT37u0ajbJQ/bG7pLmfXjrlV1LdmypGOxC2SW2eG4 dJp22zQ13f+UhRYyfeEw0mJSjiMXYSt4t4h5gDWSYUgQ5ymwP8REnEFXmDxNh/ags95R Tw== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0b-0016f401.pphosted.com with ESMTP id 2survk12dh-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 01 Jun 2019 11:55:39 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 1 Jun 2019 11:55:37 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 1 Jun 2019 11:55:37 -0700 Received: from BG-LT7430.marvell.com (unknown [10.28.17.28]) by maili.marvell.com (Postfix) with ESMTP id 25C443F711E; Sat, 1 Jun 2019 11:55:11 -0700 (PDT) From: To: , Pavan Nikhilesh CC: Date: Sun, 2 Jun 2019 00:23:17 +0530 Message-ID: <20190601185355.370-8-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190601185355.370-1-pbhagavatula@marvell.com> References: <20190601185355.370-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-01_13:, , signatures=0 Subject: [dpdk-dev] [PATCH 07/44] event/octeontx2: add devargs for inflight buffer count X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh The number of events for a *open system* event device is specified as -1 as per the eventdev specification. Since, Octeontx2 SSO inflight events are only limited by DRAM size, the xae_cnt devargs parameter is introduced to provide upper limit for in-flight events. Example: --dev "0002:0e:00.0,xae_cnt=8192" Signed-off-by: Pavan Nikhilesh --- drivers/event/octeontx2/Makefile | 2 +- drivers/event/octeontx2/otx2_evdev.c | 28 +++++++++++++++++++++++++++- drivers/event/octeontx2/otx2_evdev.h | 11 +++++++++++ 3 files changed, 39 insertions(+), 2 deletions(-) diff --git a/drivers/event/octeontx2/Makefile b/drivers/event/octeontx2/Makefile index b3c3beccb..58853e1b9 100644 --- a/drivers/event/octeontx2/Makefile +++ b/drivers/event/octeontx2/Makefile @@ -32,7 +32,7 @@ LIBABIVER := 1 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_evdev.c -LDLIBS += -lrte_eal -lrte_bus_pci -lrte_pci +LDLIBS += -lrte_eal -lrte_bus_pci -lrte_pci -lrte_kvargs LDLIBS += -lrte_mempool -lrte_eventdev -lrte_mbuf LDLIBS += -lrte_common_octeontx2 -lrte_mempool_octeontx2 diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c index 325e61426..54afb0ee5 100644 --- a/drivers/event/octeontx2/otx2_evdev.c +++ b/drivers/event/octeontx2/otx2_evdev.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -245,7 +246,10 @@ sso_xaq_allocate(struct otx2_sso_evdev *dev) /* Taken from HRM 14.3.3(4) */ xaq_cnt = dev->nb_event_queues * OTX2_SSO_XAQ_CACHE_CNT; - xaq_cnt += (dev->iue / dev->xae_waes) + + if (dev->xae_cnt) + xaq_cnt += dev->xae_cnt / dev->xae_waes; + else + xaq_cnt += (dev->iue / dev->xae_waes) + (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues); otx2_sso_dbg("configuring %d xaq buffers", xaq_cnt); @@ -459,6 +463,25 @@ static struct rte_eventdev_ops otx2_sso_ops = { .queue_release = otx2_sso_queue_release, }; +#define OTX2_SSO_XAE_CNT "xae_cnt" + +static void +sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs) +{ + struct rte_kvargs *kvlist; + + if (devargs == NULL) + return; + kvlist = rte_kvargs_parse(devargs->args, NULL); + if (kvlist == NULL) + return; + + rte_kvargs_process(kvlist, OTX2_SSO_XAE_CNT, &parse_kvargs_value, + &dev->xae_cnt); + + rte_kvargs_free(kvlist); +} + static int otx2_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) { @@ -548,6 +571,8 @@ otx2_sso_init(struct rte_eventdev *event_dev) goto otx2_npa_lf_uninit; } + sso_parse_devargs(dev, pci_dev->device.devargs); + otx2_sso_pf_func_set(dev->pf_func); otx2_sso_dbg("initializing %s max_queues=%d max_ports=%d", event_dev->data->name, dev->max_event_queues, @@ -597,3 +622,4 @@ otx2_sso_fini(struct rte_eventdev *event_dev) RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso); RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map); RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, "vfio-pci"); +RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT "="); diff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h index 375640bca..acc8b6b3e 100644 --- a/drivers/event/octeontx2/otx2_evdev.h +++ b/drivers/event/octeontx2/otx2_evdev.h @@ -62,6 +62,8 @@ struct otx2_sso_evdev { uint64_t nb_xaq_cfg; rte_iova_t fc_iova; struct rte_mempool *xaq_pool; + /* Dev args */ + uint32_t xae_cnt; /* HW const */ uint32_t xae_waes; uint32_t xaq_buf_size; @@ -74,6 +76,15 @@ sso_pmd_priv(const struct rte_eventdev *event_dev) return event_dev->data->dev_private; } +static inline int +parse_kvargs_value(const char *key, const char *value, void *opaque) +{ + RTE_SET_USED(key); + + *(uint32_t *)opaque = (uint32_t)atoi(value); + return 0; +} + /* Init and Fini API's */ int otx2_sso_init(struct rte_eventdev *event_dev); int otx2_sso_fini(struct rte_eventdev *event_dev); -- 2.21.0