From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id C1D80A0096 for ; Sun, 2 Jun 2019 17:25:27 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A33521B95A; Sun, 2 Jun 2019 17:24:54 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 196BD1B964 for ; Sun, 2 Jun 2019 17:24:53 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x52FK4Yc020248; Sun, 2 Jun 2019 08:24:52 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=BwLUGcyJQijgn6oO43rjpGDJqEAJjgcDtPiQJVHf2x4=; b=YIj4XYCfWRFQlnbID+0oKrZiBbs+s4n2QTR4a+rORpLIqJFP1g7GrukzNvrI5lg955Ru 3KSsLLx/kMF4woFvl+f2YCzxOuZyyrmVMzqEo5aWSI7aKU2y8f1W+U6zhJ+/QuwsNIjR Z8hjJeJoUrncDMwkQgpcjxY536Cforx3bQRbiA6d/+uyelUhIkPwRWj/PEW1SXCsyY1Y TT4iUPFV/7jKKbf5HCoTJwxQ+nTw9EZV31IJ1DS0BfSDvc8Sk8eeeFQ63XO7xlCMuXPj LV0Iaxqq6AuRvonu/DAqq7mGUOrQA9PKMerChFUB6045FI+t/Rddr8U2iI9i9tQ0adH9 Cg== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 2survk4912-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 02 Jun 2019 08:24:52 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sun, 2 Jun 2019 08:24:50 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sun, 2 Jun 2019 08:24:50 -0700 Received: from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14]) by maili.marvell.com (Postfix) with ESMTP id 20D123F7040; Sun, 2 Jun 2019 08:24:48 -0700 (PDT) From: To: , Jerin Jacob , Nithin Dabilpuram , Kiran Kumar K CC: , Harman Kalra Date: Sun, 2 Jun 2019 20:53:41 +0530 Message-ID: <20190602152434.23996-6-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190602152434.23996-1-jerinj@marvell.com> References: <20190602152434.23996-1-jerinj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-02_09:, , signatures=0 Subject: [dpdk-dev] [PATCH v1 05/58] net/octeontx2: handle device error interrupts X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jerin Jacob Handle device specific error and ras interrupts. Signed-off-by: Jerin Jacob Signed-off-by: Nithin Dabilpuram Signed-off-by: Harman Kalra --- drivers/net/octeontx2/Makefile | 1 + drivers/net/octeontx2/meson.build | 1 + drivers/net/octeontx2/otx2_ethdev.c | 12 +- drivers/net/octeontx2/otx2_ethdev.h | 4 + drivers/net/octeontx2/otx2_ethdev_irq.c | 140 ++++++++++++++++++++++++ 5 files changed, 156 insertions(+), 2 deletions(-) create mode 100644 drivers/net/octeontx2/otx2_ethdev_irq.c diff --git a/drivers/net/octeontx2/Makefile b/drivers/net/octeontx2/Makefile index dbcfec5b4..a56143dcd 100644 --- a/drivers/net/octeontx2/Makefile +++ b/drivers/net/octeontx2/Makefile @@ -32,6 +32,7 @@ LIBABIVER := 1 SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD) += \ otx2_mac.c \ otx2_ethdev.c \ + otx2_ethdev_irq.c \ otx2_ethdev_devargs.c LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_common_octeontx2 -lm diff --git a/drivers/net/octeontx2/meson.build b/drivers/net/octeontx2/meson.build index 57657de3d..c49e1cb80 100644 --- a/drivers/net/octeontx2/meson.build +++ b/drivers/net/octeontx2/meson.build @@ -5,6 +5,7 @@ sources = files( 'otx2_mac.c', 'otx2_ethdev.c', + 'otx2_ethdev_irq.c', 'otx2_ethdev_devargs.c' ) diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c index eeba0c2c6..67a7ebb36 100644 --- a/drivers/net/octeontx2/otx2_ethdev.c +++ b/drivers/net/octeontx2/otx2_ethdev.c @@ -175,12 +175,17 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev) if (rc) goto otx2_npa_uninit; + /* Register LF irq handlers */ + rc = otx2_nix_register_irqs(eth_dev); + if (rc) + goto mbox_detach; + /* Get maximum number of supported MAC entries */ max_entries = otx2_cgx_mac_max_entries_get(dev); if (max_entries < 0) { otx2_err("Failed to get max entries for mac addr"); rc = -ENOTSUP; - goto mbox_detach; + goto unregister_irq; } /* For VFs, returned max_entries will be 0. But to keep default MAC @@ -194,7 +199,7 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev) if (eth_dev->data->mac_addrs == NULL) { otx2_err("Failed to allocate memory for mac addr"); rc = -ENOMEM; - goto mbox_detach; + goto unregister_irq; } dev->max_mac_entries = max_entries; @@ -226,6 +231,8 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev) free_mac_addrs: rte_free(eth_dev->data->mac_addrs); +unregister_irq: + otx2_nix_unregister_irqs(eth_dev); mbox_detach: otx2_eth_dev_lf_detach(dev->mbox); otx2_npa_uninit: @@ -261,6 +268,7 @@ otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close) dev->drv_inited = false; pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + otx2_nix_unregister_irqs(eth_dev); rc = otx2_eth_dev_lf_detach(dev->mbox); if (rc) diff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h index f91e5fcac..670d1ff0b 100644 --- a/drivers/net/octeontx2/otx2_ethdev.h +++ b/drivers/net/octeontx2/otx2_ethdev.h @@ -102,6 +102,10 @@ otx2_eth_pmd_priv(struct rte_eth_dev *eth_dev) return eth_dev->data->dev_private; } +/* IRQ */ +int otx2_nix_register_irqs(struct rte_eth_dev *eth_dev); +void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev); + /* CGX */ int otx2_cgx_rxtx_start(struct otx2_eth_dev *dev); int otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev); diff --git a/drivers/net/octeontx2/otx2_ethdev_irq.c b/drivers/net/octeontx2/otx2_ethdev_irq.c new file mode 100644 index 000000000..33fed93c4 --- /dev/null +++ b/drivers/net/octeontx2/otx2_ethdev_irq.c @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#include + +#include + +#include "otx2_ethdev.h" + +static void +nix_lf_err_irq(void *param) +{ + struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; + struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev); + uint64_t intr; + + intr = otx2_read64(dev->base + NIX_LF_ERR_INT); + if (intr == 0) + return; + + otx2_err("Err_intr=0x%" PRIx64 " pf=%d, vf=%d", intr, dev->pf, dev->vf); + + /* Clear interrupt */ + otx2_write64(intr, dev->base + NIX_LF_ERR_INT); +} + +static int +nix_lf_register_err_irq(struct rte_eth_dev *eth_dev) +{ + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + struct rte_intr_handle *handle = &pci_dev->intr_handle; + struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev); + int rc, vec; + + vec = dev->nix_msixoff + NIX_LF_INT_VEC_ERR_INT; + + /* Clear err interrupt */ + otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C); + /* Set used interrupt vectors */ + rc = otx2_register_irq(handle, nix_lf_err_irq, eth_dev, vec); + /* Enable all dev interrupt except for RQ_DISABLED */ + otx2_write64(~BIT_ULL(11), dev->base + NIX_LF_ERR_INT_ENA_W1S); + + return rc; +} + +static void +nix_lf_unregister_err_irq(struct rte_eth_dev *eth_dev) +{ + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + struct rte_intr_handle *handle = &pci_dev->intr_handle; + struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev); + int vec; + + vec = dev->nix_msixoff + NIX_LF_INT_VEC_ERR_INT; + + /* Clear err interrupt */ + otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C); + otx2_unregister_irq(handle, nix_lf_err_irq, eth_dev, vec); +} + +static void +nix_lf_ras_irq(void *param) +{ + struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; + struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev); + uint64_t intr; + + intr = otx2_read64(dev->base + NIX_LF_RAS); + if (intr == 0) + return; + + otx2_err("Ras_intr=0x%" PRIx64 " pf=%d, vf=%d", intr, dev->pf, dev->vf); + + /* Clear interrupt */ + otx2_write64(intr, dev->base + NIX_LF_RAS); +} + +static int +nix_lf_register_ras_irq(struct rte_eth_dev *eth_dev) +{ + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + struct rte_intr_handle *handle = &pci_dev->intr_handle; + struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev); + int rc, vec; + + vec = dev->nix_msixoff + NIX_LF_INT_VEC_POISON; + + /* Clear err interrupt */ + otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C); + /* Set used interrupt vectors */ + rc = otx2_register_irq(handle, nix_lf_ras_irq, eth_dev, vec); + /* Enable dev interrupt */ + otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1S); + + return rc; +} + +static void +nix_lf_unregister_ras_irq(struct rte_eth_dev *eth_dev) +{ + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + struct rte_intr_handle *handle = &pci_dev->intr_handle; + struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev); + int vec; + + vec = dev->nix_msixoff + NIX_LF_INT_VEC_POISON; + + /* Clear err interrupt */ + otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C); + otx2_unregister_irq(handle, nix_lf_ras_irq, eth_dev, vec); +} + +int +otx2_nix_register_irqs(struct rte_eth_dev *eth_dev) +{ + struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev); + int rc; + + if (dev->nix_msixoff == MSIX_VECTOR_INVALID) { + otx2_err("Invalid NIXLF MSIX vector offset vector: 0x%x", + dev->nix_msixoff); + return -EINVAL; + } + + /* Register lf err interrupt */ + rc = nix_lf_register_err_irq(eth_dev); + /* Register RAS interrupt */ + rc |= nix_lf_register_ras_irq(eth_dev); + + return rc; +} + +void +otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev) +{ + nix_lf_unregister_err_irq(eth_dev); + nix_lf_unregister_ras_irq(eth_dev); +} -- 2.21.0