From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id A217BA0096 for ; Thu, 6 Jun 2019 17:27:35 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7EEB81B9A1; Thu, 6 Jun 2019 17:27:35 +0200 (CEST) Received: from rcdn-iport-4.cisco.com (rcdn-iport-4.cisco.com [173.37.86.75]) by dpdk.org (Postfix) with ESMTP id C7EA31B99E for ; Thu, 6 Jun 2019 17:27:33 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=cisco.com; i=@cisco.com; l=3903; q=dns/txt; s=iport; t=1559834853; x=1561044453; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=II7QwwL2GLdT5tF09utxaFvh3JRowqhWdmegcx27SU0=; b=kXlDU0DOIXt7HZ8JieCYbwDqdAaV19xQFn/f8jrcrZtNsxz2KREBnVOl bsODjdvLdd+KfY4PiUpa1ihi8a/oGg0fMuAT11BIk/qbXTO0nWNsUC0PB IDmYjYFRm6rvfeG5TkbejuCnFcxLdcGuhiAcODUxgD6H9jhoPbu/QbT74 0=; X-IronPort-AV: E=Sophos;i="5.63,559,1557187200"; d="scan'208";a="570562923" Received: from rcdn-core-10.cisco.com ([173.37.93.146]) by rcdn-iport-4.cisco.com with ESMTP/TLS/DHE-RSA-SEED-SHA; 06 Jun 2019 15:27:31 +0000 Received: from cisco.com (savbu-usnic-a.cisco.com [10.193.184.48]) by rcdn-core-10.cisco.com (8.15.2/8.15.2) with ESMTP id x56FRVQq032385; Thu, 6 Jun 2019 15:27:31 GMT Received: by cisco.com (Postfix, from userid 508933) id 5E77A20F2001; Thu, 6 Jun 2019 08:27:31 -0700 (PDT) From: Hyong Youb Kim To: Ferruh Yigit Cc: dev@dpdk.org, John Daley , Hyong Youb Kim Date: Thu, 6 Jun 2019 08:26:56 -0700 Message-Id: <20190606152658.17311-3-hyonkim@cisco.com> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20190606152658.17311-1-hyonkim@cisco.com> References: <20190606152658.17311-1-hyonkim@cisco.com> X-Outbound-SMTP-Client: 10.193.184.48, savbu-usnic-a.cisco.com X-Outbound-Node: rcdn-core-10.cisco.com Subject: [dpdk-dev] [PATCH 2/4] net/enic: report speed capabilities X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Available link speeds are based on VIC adapter model, which is encoded in PCI subsystem device ID. Signed-off-by: Hyong Youb Kim Reviewed-by: John Daley --- doc/guides/nics/features/enic.ini | 1 + drivers/net/enic/enic_ethdev.c | 51 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/doc/guides/nics/features/enic.ini b/doc/guides/nics/features/enic.ini index c6d374984..d0f3ae23f 100644 --- a/doc/guides/nics/features/enic.ini +++ b/doc/guides/nics/features/enic.ini @@ -4,6 +4,7 @@ ; Refer to default.ini for the full list of available PMD features. ; [Features] +Speed capabilities = Y Link status = Y Link status event = Y Rx interrupt = Y diff --git a/drivers/net/enic/enic_ethdev.c b/drivers/net/enic/enic_ethdev.c index 1bf2ecca8..5cfbd31a2 100644 --- a/drivers/net/enic/enic_ethdev.c +++ b/drivers/net/enic/enic_ethdev.c @@ -36,6 +36,38 @@ static const struct rte_pci_id pci_id_enic_map[] = { {.vendor_id = 0, /* sentinel */}, }; +/* Supported link speeds of production VIC models */ +static const struct vic_speed_capa { + uint16_t sub_devid; + uint32_t capa; +} vic_speed_capa_map[] = { + { 0x0043, ETH_LINK_SPEED_10G }, /* VIC */ + { 0x0047, ETH_LINK_SPEED_10G }, /* P81E PCIe */ + { 0x0048, ETH_LINK_SPEED_10G }, /* M81KR Mezz */ + { 0x004f, ETH_LINK_SPEED_10G }, /* 1280 Mezz */ + { 0x0084, ETH_LINK_SPEED_10G }, /* 1240 MLOM */ + { 0x0085, ETH_LINK_SPEED_10G }, /* 1225 PCIe */ + { 0x00cd, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1285 PCIe */ + { 0x00ce, ETH_LINK_SPEED_10G }, /* 1225T PCIe */ + { 0x012a, ETH_LINK_SPEED_40G }, /* M4308 */ + { 0x012c, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1340 MLOM */ + { 0x012e, ETH_LINK_SPEED_10G }, /* 1227 PCIe */ + { 0x0137, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1380 Mezz */ + { 0x014d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1385 PCIe */ + { 0x015d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1387 MLOM */ + { 0x0215, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G | + ETH_LINK_SPEED_40G }, /* 1440 Mezz */ + { 0x0216, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G | + ETH_LINK_SPEED_40G }, /* 1480 MLOM */ + { 0x0217, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1455 PCIe */ + { 0x0218, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1457 MLOM */ + { 0x0219, ETH_LINK_SPEED_40G }, /* 1485 PCIe */ + { 0x021a, ETH_LINK_SPEED_40G }, /* 1487 MLOM */ + { 0x024a, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1495 PCIe */ + { 0x024b, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1497 MLOM */ + { 0, 0 }, /* End marker */ +}; + #define ENIC_DEVARG_DISABLE_OVERLAY "disable-overlay" #define ENIC_DEVARG_ENABLE_AVX2_RX "enable-avx2-rx" #define ENIC_DEVARG_IG_VLAN_REWRITE "ig-vlan-rewrite" @@ -456,6 +488,24 @@ static void enicpmd_dev_stats_reset(struct rte_eth_dev *eth_dev) enic_dev_stats_clear(enic); } +static uint32_t speed_capa_from_pci_id(struct rte_eth_dev *eth_dev) +{ + const struct vic_speed_capa *m; + struct rte_pci_device *pdev; + uint16_t id; + + pdev = RTE_ETH_DEV_TO_PCI(eth_dev); + id = pdev->id.subsystem_device_id; + for (m = vic_speed_capa_map; m->sub_devid != 0; m++) { + if (m->sub_devid == id) + return m->capa; + } + /* 1300 and later models are at least 40G */ + if (id >= 0x0100) + return ETH_LINK_SPEED_40G; + return ETH_LINK_SPEED_10G; +} + static void enicpmd_dev_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *device_info) { @@ -510,6 +560,7 @@ static void enicpmd_dev_info_get(struct rte_eth_dev *eth_dev, ENIC_DEFAULT_TX_RING_SIZE), .nb_queues = ENIC_DEFAULT_TX_RINGS, }; + device_info->speed_capa = speed_capa_from_pci_id(eth_dev); } static const uint32_t *enicpmd_dev_supported_ptypes_get(struct rte_eth_dev *dev) -- 2.16.2