From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 56981A0471 for ; Wed, 19 Jun 2019 17:47:27 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9B6E51C56C; Wed, 19 Jun 2019 17:21:51 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id 0F8981C4E9 for ; Wed, 19 Jun 2019 17:20:54 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Jun 2019 08:20:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,392,1557212400"; d="scan'208";a="165050393" Received: from lrong-srv-03.sh.intel.com ([10.67.119.177]) by orsmga006.jf.intel.com with ESMTP; 19 Jun 2019 08:20:54 -0700 From: Leyi Rong To: qi.z.zhang@intel.com Cc: dev@dpdk.org, Leyi Rong Date: Wed, 19 Jun 2019 23:18:10 +0800 Message-Id: <20190619151846.113820-34-leyi.rong@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190619151846.113820-1-leyi.rong@intel.com> References: <20190611155221.2703-1-leyi.rong@intel.com> <20190619151846.113820-1-leyi.rong@intel.com> Subject: [dpdk-dev] [PATCH v3 33/69] net/ice/base: add rd64 support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add API support for rd64. Signed-off-by: Qi Zhang Signed-off-by: Leyi Rong --- drivers/net/ice/base/ice_osdep.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/net/ice/base/ice_osdep.h b/drivers/net/ice/base/ice_osdep.h index ede893fc9..35a17b941 100644 --- a/drivers/net/ice/base/ice_osdep.h +++ b/drivers/net/ice/base/ice_osdep.h @@ -126,11 +126,19 @@ do { \ #define ICE_PCI_REG(reg) rte_read32(reg) #define ICE_PCI_REG_ADDR(a, reg) \ ((volatile uint32_t *)((char *)(a)->hw_addr + (reg))) +#define ICE_PCI_REG64(reg) rte_read64(reg) +#define ICE_PCI_REG_ADDR64(a, reg) \ + ((volatile uint64_t *)((char *)(a)->hw_addr + (reg))) static inline uint32_t ice_read_addr(volatile void *addr) { return rte_le_to_cpu_32(ICE_PCI_REG(addr)); } +static inline uint64_t ice_read_addr64(volatile void *addr) +{ + return rte_le_to_cpu_64(ICE_PCI_REG64(addr)); +} + #define ICE_PCI_REG_WRITE(reg, value) \ rte_write32((rte_cpu_to_le_32(value)), reg) @@ -145,6 +153,7 @@ static inline uint32_t ice_read_addr(volatile void *addr) ICE_PCI_REG_WRITE(ICE_PCI_REG_ADDR((a), (reg)), (value)) #define flush(a) ice_read_addr(ICE_PCI_REG_ADDR((a), (GLGEN_STAT))) #define div64_long(n, d) ((n) / (d)) +#define rd64(a, reg) ice_read_addr64(ICE_PCI_REG_ADDR64((a), (reg))) #define BITS_PER_BYTE 8 -- 2.17.1