From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 4FE86A0471 for ; Wed, 19 Jun 2019 18:17:14 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 55D501D123; Wed, 19 Jun 2019 17:56:22 +0200 (CEST) Received: from huawei.com (szxga04-in.huawei.com [45.249.212.190]) by dpdk.org (Postfix) with ESMTP id C2AE91C588 for ; Wed, 19 Jun 2019 17:56:08 +0200 (CEST) Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 4459DB2243453F880738 for ; Wed, 19 Jun 2019 23:35:09 +0800 (CST) Received: from tester_149.localdomain (10.175.119.39) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.439.0; Wed, 19 Jun 2019 23:35:00 +0800 From: Ziyang Xuan To: CC: , , , , , Ziyang Xuan Date: Wed, 19 Jun 2019 23:47:04 +0800 Message-ID: X-Mailer: git-send-email 2.18.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" X-Originating-IP: [10.175.119.39] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH v5 02/15] net/hinic/base: add HW interfaces of bar operation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190619154704.UPbM2eTlqZYoAVknDVlveaZxVQx8SR0N1SD-DSJ3IqY@z> This patch adds some HW interfaces for bar operatioin interfaces, including: mapped bar address geeting, HW attributes getting, msi-x reg operation, function type getting and so on. Signed-off-by: Ziyang Xuan --- drivers/net/hinic/base/hinic_pmd_hwif.c | 474 ++++++++++++++++++++++++ drivers/net/hinic/base/hinic_pmd_hwif.h | 119 ++++++ 2 files changed, 593 insertions(+) create mode 100644 drivers/net/hinic/base/hinic_pmd_hwif.c create mode 100644 drivers/net/hinic/base/hinic_pmd_hwif.h diff --git a/drivers/net/hinic/base/hinic_pmd_hwif.c b/drivers/net/hinic/base/hinic_pmd_hwif.c new file mode 100644 index 000000000..a5e223b21 --- /dev/null +++ b/drivers/net/hinic/base/hinic_pmd_hwif.c @@ -0,0 +1,474 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Huawei Technologies Co., Ltd + */ + +#include + +#include "hinic_compat.h" +#include "hinic_csr.h" +#include "hinic_pmd_hwdev.h" +#include "hinic_pmd_hwif.h" + +#define HINIC_CFG_REGS_BAR 0 +#define HINIC_INTR_MSI_BAR 2 +#define HINIC_DB_MEM_BAR 4 + +#define HINIC_MSIX_CNT_RESEND_TIMER_SHIFT 29 +#define HINIC_MSIX_CNT_RESEND_TIMER_MASK 0x7U + +#define HINIC_MSIX_CNT_SET(val, member) \ + (((val) & HINIC_MSIX_CNT_##member##_MASK) << \ + HINIC_MSIX_CNT_##member##_SHIFT) + +/** + * hwif_ready - test if the HW initialization passed + * @hwdev: the pointer to the private hardware device object + * Return: 0 - success, negative - failure + **/ +static int hwif_ready(struct hinic_hwdev *hwdev) +{ + u32 addr, attr1; + + addr = HINIC_CSR_FUNC_ATTR1_ADDR; + attr1 = hinic_hwif_read_reg(hwdev->hwif, addr); + + if (!HINIC_AF1_GET(attr1, MGMT_INIT_STATUS)) + return -EBUSY; + + return 0; +} + +/** + * set_hwif_attr - set the attributes as members in hwif + * @hwif: the hardware interface of a pci function device + * @attr0: the first attribute that was read from the hw + * @attr1: the second attribute that was read from the hw + * @attr2: the third attribute that was read from the hw + **/ +static void set_hwif_attr(struct hinic_hwif *hwif, u32 attr0, u32 attr1, + u32 attr2) +{ + hwif->attr.func_global_idx = HINIC_AF0_GET(attr0, FUNC_GLOBAL_IDX); + hwif->attr.port_to_port_idx = HINIC_AF0_GET(attr0, P2P_IDX); + hwif->attr.pci_intf_idx = HINIC_AF0_GET(attr0, PCI_INTF_IDX); + hwif->attr.vf_in_pf = HINIC_AF0_GET(attr0, VF_IN_PF); + hwif->attr.func_type = HINIC_AF0_GET(attr0, FUNC_TYPE); + + hwif->attr.ppf_idx = HINIC_AF1_GET(attr1, PPF_IDX); + + hwif->attr.num_aeqs = BIT(HINIC_AF1_GET(attr1, AEQS_PER_FUNC)); + hwif->attr.num_ceqs = BIT(HINIC_AF1_GET(attr1, CEQS_PER_FUNC)); + hwif->attr.num_irqs = BIT(HINIC_AF1_GET(attr1, IRQS_PER_FUNC)); + hwif->attr.num_dma_attr = BIT(HINIC_AF1_GET(attr1, DMA_ATTR_PER_FUNC)); + + hwif->attr.global_vf_id_of_pf = HINIC_AF2_GET(attr2, + GLOBAL_VF_ID_OF_PF); +} + +/** + * get_hwif_attr - read and set the attributes as members in hwif + * @hwif: the hardware interface of a pci function device + **/ +static void get_hwif_attr(struct hinic_hwif *hwif) +{ + u32 addr, attr0, attr1, attr2; + + addr = HINIC_CSR_FUNC_ATTR0_ADDR; + attr0 = hinic_hwif_read_reg(hwif, addr); + + addr = HINIC_CSR_FUNC_ATTR1_ADDR; + attr1 = hinic_hwif_read_reg(hwif, addr); + + addr = HINIC_CSR_FUNC_ATTR2_ADDR; + attr2 = hinic_hwif_read_reg(hwif, addr); + + set_hwif_attr(hwif, attr0, attr1, attr2); +} + +void hinic_set_pf_status(struct hinic_hwif *hwif, enum hinic_pf_status status) +{ + u32 attr5 = HINIC_AF5_SET(status, PF_STATUS); + u32 addr = HINIC_CSR_FUNC_ATTR5_ADDR; + + hinic_hwif_write_reg(hwif, addr, attr5); +} + +enum hinic_pf_status hinic_get_pf_status(struct hinic_hwif *hwif) +{ + u32 attr5 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR5_ADDR); + + return HINIC_AF5_GET(attr5, PF_STATUS); +} + +static enum hinic_doorbell_ctrl +hinic_get_doorbell_ctrl_status(struct hinic_hwif *hwif) +{ + u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); + + return HINIC_AF4_GET(attr4, DOORBELL_CTRL); +} + +static enum hinic_outbound_ctrl +hinic_get_outbound_ctrl_status(struct hinic_hwif *hwif) +{ + u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); + + return HINIC_AF4_GET(attr4, OUTBOUND_CTRL); +} + +void hinic_enable_doorbell(struct hinic_hwif *hwif) +{ + u32 addr, attr4; + + addr = HINIC_CSR_FUNC_ATTR4_ADDR; + attr4 = hinic_hwif_read_reg(hwif, addr); + + attr4 = HINIC_AF4_CLEAR(attr4, DOORBELL_CTRL); + attr4 |= HINIC_AF4_SET(ENABLE_DOORBELL, DOORBELL_CTRL); + + hinic_hwif_write_reg(hwif, addr, attr4); +} + +void hinic_disable_doorbell(struct hinic_hwif *hwif) +{ + u32 addr, attr4; + + addr = HINIC_CSR_FUNC_ATTR4_ADDR; + attr4 = hinic_hwif_read_reg(hwif, addr); + + attr4 = HINIC_AF4_CLEAR(attr4, DOORBELL_CTRL); + attr4 |= HINIC_AF4_SET(DISABLE_DOORBELL, DOORBELL_CTRL); + + hinic_hwif_write_reg(hwif, addr, attr4); +} + +/** + * set_ppf - try to set hwif as ppf and set the type of hwif in this case + * @hwif: the hardware interface of a pci function device + **/ +static void set_ppf(struct hinic_hwif *hwif) +{ + struct hinic_func_attr *attr = &hwif->attr; + u32 addr, val, ppf_election; + + /* Read Modify Write */ + addr = HINIC_CSR_PPF_ELECTION_ADDR; + + val = hinic_hwif_read_reg(hwif, addr); + val = HINIC_PPF_ELECTION_CLEAR(val, IDX); + + ppf_election = HINIC_PPF_ELECTION_SET(attr->func_global_idx, IDX); + val |= ppf_election; + + hinic_hwif_write_reg(hwif, addr, val); + + /* Check PPF */ + val = hinic_hwif_read_reg(hwif, addr); + + attr->ppf_idx = HINIC_PPF_ELECTION_GET(val, IDX); + if (attr->ppf_idx == attr->func_global_idx) + attr->func_type = TYPE_PPF; +} + +static void init_db_area_idx(struct hinic_free_db_area *free_db_area) +{ + u32 i; + + for (i = 0; i < HINIC_DB_MAX_AREAS; i++) + free_db_area->db_idx[i] = i; + + free_db_area->alloc_pos = 0; + free_db_area->return_pos = 0; + + free_db_area->num_free = HINIC_DB_MAX_AREAS; + + spin_lock_init(&free_db_area->idx_lock); +} + +static int get_db_idx(struct hinic_hwif *hwif, u32 *idx) +{ + struct hinic_free_db_area *free_db_area = &hwif->free_db_area; + u32 pos; + u32 pg_idx; + + spin_lock(&free_db_area->idx_lock); + + if (free_db_area->num_free == 0) { + spin_unlock(&free_db_area->idx_lock); + return -ENOMEM; + } + + free_db_area->num_free--; + + pos = free_db_area->alloc_pos++; + pos &= HINIC_DB_MAX_AREAS - 1; + + pg_idx = free_db_area->db_idx[pos]; + + free_db_area->db_idx[pos] = 0xFFFFFFFF; + + spin_unlock(&free_db_area->idx_lock); + + *idx = pg_idx; + + return 0; +} + +static void free_db_idx(struct hinic_hwif *hwif, u32 idx) +{ + struct hinic_free_db_area *free_db_area = &hwif->free_db_area; + u32 pos; + + spin_lock(&free_db_area->idx_lock); + + pos = free_db_area->return_pos++; + pos &= HINIC_DB_MAX_AREAS - 1; + + free_db_area->db_idx[pos] = idx; + + free_db_area->num_free++; + + spin_unlock(&free_db_area->idx_lock); +} + +void hinic_free_db_addr(void *hwdev, void __iomem *db_base) +{ + struct hinic_hwif *hwif = ((struct hinic_hwdev *)hwdev)->hwif; + u32 idx = DB_IDX(db_base, hwif->db_base); + + free_db_idx(hwif, idx); +} + +int hinic_alloc_db_addr(void *hwdev, void __iomem **db_base) +{ + struct hinic_hwif *hwif = ((struct hinic_hwdev *)hwdev)->hwif; + u32 idx; + int err; + + err = get_db_idx(hwif, &idx); + if (err) + return -EFAULT; + + *db_base = hwif->db_base + idx * HINIC_DB_PAGE_SIZE; + + return 0; +} + +void hinic_set_msix_state(void *hwdev, u16 msix_idx, enum hinic_msix_state flag) +{ + struct hinic_hwdev *hw = hwdev; + struct hinic_hwif *hwif = hw->hwif; + u32 offset = msix_idx * HINIC_PCI_MSIX_ENTRY_SIZE + + HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL; + u32 mask_bits; + + /* vfio-pci does not mmap msi-x vector table to user space, + * we can not access the space when kernel driver is vfio-pci + */ + if (hw->pcidev_hdl->kdrv == RTE_KDRV_VFIO) + return; + + mask_bits = readl(hwif->intr_regs_base + offset); + mask_bits &= ~HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT; + if (flag) + mask_bits |= HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT; + + writel(mask_bits, hwif->intr_regs_base + offset); +} + +static void disable_all_msix(struct hinic_hwdev *hwdev) +{ + u16 num_irqs = hwdev->hwif->attr.num_irqs; + u16 i; + + for (i = 0; i < num_irqs; i++) + hinic_set_msix_state(hwdev, i, HINIC_MSIX_DISABLE); +} + +static int wait_until_doorbell_and_outbound_enabled(struct hinic_hwif *hwif) +{ + unsigned long end; + enum hinic_doorbell_ctrl db_ctrl; + enum hinic_outbound_ctrl outbound_ctrl; + + end = jiffies + + msecs_to_jiffies(HINIC_WAIT_DOORBELL_AND_OUTBOUND_TIMEOUT); + do { + db_ctrl = hinic_get_doorbell_ctrl_status(hwif); + outbound_ctrl = hinic_get_outbound_ctrl_status(hwif); + + if (outbound_ctrl == ENABLE_OUTBOUND && + db_ctrl == ENABLE_DOORBELL) + return 0; + + rte_delay_ms(1); + } while (time_before(jiffies, end)); + + return -EFAULT; +} + +u16 hinic_global_func_id(void *hwdev) +{ + struct hinic_hwif *hwif = ((struct hinic_hwdev *)hwdev)->hwif; + + return hwif->attr.func_global_idx; +} + +enum func_type hinic_func_type(void *hwdev) +{ + struct hinic_hwif *hwif = ((struct hinic_hwdev *)hwdev)->hwif; + + return hwif->attr.func_type; +} + +u8 hinic_ppf_idx(void *hwdev) +{ + struct hinic_hwif *hwif = ((struct hinic_hwdev *)hwdev)->hwif; + + return hwif->attr.ppf_idx; +} + +/** + * hinic_init_hwif - initialize the hw interface + * @hwdev: the pointer to the private hardware device object + * @cfg_reg_base: base physical address of configuration registers + * @intr_reg_base: base physical address of msi-x vector table + * @db_base_phy: base physical address of doorbell registers + * @db_base: base virtual address of doorbell registers + * @dwqe_mapping: direct wqe io mapping address + * Return: 0 - success, negative - failure + **/ +static int hinic_init_hwif(struct hinic_hwdev *hwdev, void *cfg_reg_base, + void *intr_reg_base, u64 db_base_phy, + void *db_base, __rte_unused void *dwqe_mapping) +{ + struct hinic_hwif *hwif; + int err; + + hwif = hwdev->hwif; + + hwif->cfg_regs_base = (u8 __iomem *)cfg_reg_base; + hwif->intr_regs_base = (u8 __iomem *)intr_reg_base; + + hwif->db_base_phy = db_base_phy; + hwif->db_base = (u8 __iomem *)db_base; + init_db_area_idx(&hwif->free_db_area); + + get_hwif_attr(hwif); + + err = hwif_ready(hwdev); + if (err) { + PMD_DRV_LOG(ERR, "Hwif is not ready"); + goto hwif_ready_err; + } + + err = wait_until_doorbell_and_outbound_enabled(hwif); + if (err) { + PMD_DRV_LOG(ERR, "Hw doorbell/outbound is disabled"); + goto hwif_ready_err; + } + + if (!HINIC_IS_VF(hwdev)) + set_ppf(hwif); + + return 0; + +hwif_ready_err: + spin_lock_deinit(&hwif->free_db_area.idx_lock); + + return err; +} + +#define HINIC_HWIF_ATTR_REG_PRINT_NUM (6) +#define HINIC_HWIF_APICMD_REG_PRINT_NUM (2) +#define HINIC_HWIF_EQ_REG_PRINT_NUM (2) + +static void hinic_parse_hwif_attr(struct hinic_hwdev *hwdev) +{ + struct hinic_hwif *hwif = hwdev->hwif; + + PMD_DRV_LOG(INFO, "Device %s hwif attribute:", hwdev->pcidev_hdl->name); + PMD_DRV_LOG(INFO, "func_idx:%u, p2p_idx:%u, pciintf_idx:%u, " + "vf_in_pf:%u, ppf_idx:%u, global_vf_id:%u, func_type:%u", + hwif->attr.func_global_idx, + hwif->attr.port_to_port_idx, hwif->attr.pci_intf_idx, + hwif->attr.vf_in_pf, hwif->attr.ppf_idx, + hwif->attr.global_vf_id_of_pf, hwif->attr.func_type); + PMD_DRV_LOG(INFO, "num_aeqs:%u, num_ceqs:%u, num_irqs:%u, dma_attr:%u", + hwif->attr.num_aeqs, hwif->attr.num_ceqs, + hwif->attr.num_irqs, hwif->attr.num_dma_attr); +} + +static void hinic_get_mmio(struct hinic_hwdev *hwdev, void **cfg_regs_base, + void **intr_base, void **db_base) +{ + struct rte_pci_device *pci_dev = hwdev->pcidev_hdl; + + *cfg_regs_base = pci_dev->mem_resource[HINIC_CFG_REGS_BAR].addr; + *intr_base = pci_dev->mem_resource[HINIC_INTR_MSI_BAR].addr; + *db_base = pci_dev->mem_resource[HINIC_DB_MEM_BAR].addr; +} + +void hinic_hwif_res_free(struct hinic_hwdev *hwdev) +{ + rte_free(hwdev->hwif); + hwdev->hwif = NULL; +} + +int hinic_hwif_res_init(struct hinic_hwdev *hwdev) +{ + int err = HINIC_ERROR; + void *cfg_regs_base, *db_base, *intr_base = NULL; + + /* hinic related init */ + hwdev->hwif = rte_zmalloc("hinic_hwif", sizeof(*hwdev->hwif), + RTE_CACHE_LINE_SIZE); + if (!hwdev->hwif) { + PMD_DRV_LOG(ERR, "Allocate hwif failed, dev_name: %s", + hwdev->pcidev_hdl->name); + return -ENOMEM; + } + + hinic_get_mmio(hwdev, &cfg_regs_base, &intr_base, &db_base); + + err = hinic_init_hwif(hwdev, cfg_regs_base, + intr_base, 0, db_base, NULL); + if (err) { + PMD_DRV_LOG(ERR, "Initialize hwif failed, dev_name: %s", + hwdev->pcidev_hdl->name); + goto init_hwif_err; + } + + /* disable msix interrupt in hw device */ + disable_all_msix(hwdev); + + /* print hwif attributes */ + hinic_parse_hwif_attr(hwdev); + + return HINIC_OK; + +init_hwif_err: + rte_free(hwdev->hwif); + hwdev->hwif = NULL; + + return err; +} + +/** + * hinic_misx_intr_clear_resend_bit - clear interrupt resend configuration + * @hwdev: the hardware interface of a nic device + * @msix_idx: Index of msix interrupt + * @clear_resend_en: enable flag of clear resend configuration + **/ +void hinic_misx_intr_clear_resend_bit(void *hwdev, u16 msix_idx, + u8 clear_resend_en) +{ + struct hinic_hwif *hwif = ((struct hinic_hwdev *)hwdev)->hwif; + u32 msix_ctrl = 0, addr; + + msix_ctrl = HINIC_MSIX_CNT_SET(clear_resend_en, RESEND_TIMER); + + addr = HINIC_CSR_MSIX_CNT_ADDR(msix_idx); + + hinic_hwif_write_reg(hwif, addr, msix_ctrl); +} diff --git a/drivers/net/hinic/base/hinic_pmd_hwif.h b/drivers/net/hinic/base/hinic_pmd_hwif.h new file mode 100644 index 000000000..c1289b57f --- /dev/null +++ b/drivers/net/hinic/base/hinic_pmd_hwif.h @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Huawei Technologies Co., Ltd + */ + +#ifndef _HINIC_PMD_HWIF_H_ +#define _HINIC_PMD_HWIF_H_ + +#define HINIC_WAIT_DOORBELL_AND_OUTBOUND_TIMEOUT 30000 + +#define HINIC_HWIF_NUM_AEQS(hwif) ((hwif)->attr.num_aeqs) +#define HINIC_HWIF_NUM_CEQS(hwif) ((hwif)->attr.num_ceqs) +#define HINIC_HWIF_NUM_IRQS(hwif) ((hwif)->attr.num_irqs) +#define HINIC_HWIF_GLOBAL_IDX(hwif) ((hwif)->attr.func_global_idx) +#define HINIC_HWIF_GLOBAL_VF_OFFSET(hwif) ((hwif)->attr.global_vf_id_of_pf) +#define HINIC_HWIF_PPF_IDX(hwif) ((hwif)->attr.ppf_idx) +#define HINIC_PCI_INTF_IDX(hwif) ((hwif)->attr.pci_intf_idx) + +#define HINIC_FUNC_TYPE(dev) ((dev)->hwif->attr.func_type) +#define HINIC_IS_PF(dev) (HINIC_FUNC_TYPE(dev) == TYPE_PF) +#define HINIC_IS_VF(dev) (HINIC_FUNC_TYPE(dev) == TYPE_VF) +#define HINIC_IS_PPF(dev) (HINIC_FUNC_TYPE(dev) == TYPE_PPF) + +enum func_type { + TYPE_PF, + TYPE_VF, + TYPE_PPF, +}; + +enum hinic_msix_state { + HINIC_MSIX_ENABLE, + HINIC_MSIX_DISABLE, +}; + +/* Defines the IRQ information structure*/ +struct irq_info { + u16 msix_entry_idx; /* IRQ corresponding index number */ + u32 irq_id; /* the IRQ number from OS */ +}; + +struct hinic_free_db_area { + u32 db_idx[HINIC_DB_MAX_AREAS]; + + u32 num_free; + + u32 alloc_pos; + u32 return_pos; + /* spinlock for idx */ + spinlock_t idx_lock; +}; + +struct hinic_func_attr { + u16 func_global_idx; + u8 port_to_port_idx; + u8 pci_intf_idx; + u8 vf_in_pf; + enum func_type func_type; + + u8 mpf_idx; + + u8 ppf_idx; + + u16 num_irqs; /* max: 2 ^ 15 */ + u8 num_aeqs; /* max: 2 ^ 3 */ + u8 num_ceqs; /* max: 2 ^ 7 */ + + u8 num_dma_attr; /* max: 2 ^ 6 */ + + u16 global_vf_id_of_pf; +}; + +struct hinic_hwif { + u8 __iomem *cfg_regs_base; + u8 __iomem *intr_regs_base; + u64 db_base_phy; + u8 __iomem *db_base; + struct hinic_free_db_area free_db_area; + struct hinic_func_attr attr; +}; + +static inline u32 hinic_hwif_read_reg(struct hinic_hwif *hwif, u32 reg) +{ + return be32_to_cpu(readl(hwif->cfg_regs_base + reg)); +} + +static inline void +hinic_hwif_write_reg(struct hinic_hwif *hwif, u32 reg, u32 val) +{ + writel(cpu_to_be32(val), hwif->cfg_regs_base + reg); +} + +u16 hinic_global_func_id(void *hwdev); /* func_attr.glb_func_idx */ + +enum func_type hinic_func_type(void *hwdev); + +void hinic_set_pf_status(struct hinic_hwif *hwif, enum hinic_pf_status status); + +enum hinic_pf_status hinic_get_pf_status(struct hinic_hwif *hwif); + +void hinic_enable_doorbell(struct hinic_hwif *hwif); + +void hinic_disable_doorbell(struct hinic_hwif *hwif); + +int hinic_alloc_db_addr(void *hwdev, void __iomem **db_base); + +void hinic_free_db_addr(void *hwdev, void __iomem *db_base); + +void hinic_set_msix_state(void *hwdev, u16 msix_idx, + enum hinic_msix_state flag); + +void hinic_misx_intr_clear_resend_bit(void *hwdev, u16 msix_idx, + u8 clear_resend_en); + +u8 hinic_ppf_idx(void *hwdev); + +int hinic_hwif_res_init(struct hinic_hwdev *hwdev); + +void hinic_hwif_res_free(struct hinic_hwdev *hwdev); + +#endif /* _HINIC_PMD_HWIF_H_ */ -- 2.18.0