From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 081ECA0471 for ; Sat, 22 Jun 2019 15:28:49 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C227E1D010; Sat, 22 Jun 2019 15:26:51 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id ADECB1CDF7 for ; Sat, 22 Jun 2019 15:25:48 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x5MDOd2m028283 for ; Sat, 22 Jun 2019 06:25:48 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=gzs4puvF1mB6n+riegbq62g6dxMGU95hgvNcoxG0XQg=; b=cs4yAMJn9W79Xkqvq8CEu+KQXKMkp3tT/xb4lDJw/ieeRyWN3hVb/vvgiCYiMWF12S9Q ghy2jK3RpMYj3KilTaXRfpfs5yKWYHvSIgA7wUmGv8lSO7KxauDjX8n8zCKJoAi/7dWB WriDpGOg+XEIDS1/Yg1ihplPSuGHl2Waxyzmin76Ny4gVelQjGAOWwIzkcOSvr6eLXnC w26tGnHCnh2U4mx+eBJEyZeOy18Z//MmBMN5apnxHx2o9iOVT8+brQ/6rvNhpFmY2PI+ v5d/NJ0wPrLJqdnC3xH3+oHf51eT9USJCHP8vnayv40O+tplhFcJl7i8d/YP1IKrH6PN gg== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0a-0016f401.pphosted.com with ESMTP id 2t9hpnrghg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 22 Jun 2019 06:25:47 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 22 Jun 2019 06:25:46 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 22 Jun 2019 06:25:46 -0700 Received: from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14]) by maili.marvell.com (Postfix) with ESMTP id E39C93F703F; Sat, 22 Jun 2019 06:25:44 -0700 (PDT) From: To: Jerin Jacob , Nithin Dabilpuram , Vamsi Attunuru CC: , Harman Kalra Date: Sat, 22 Jun 2019 18:54:16 +0530 Message-ID: <20190622132417.32694-27-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190622132417.32694-1-jerinj@marvell.com> References: <20190617155537.36144-1-jerinj@marvell.com> <20190622132417.32694-1-jerinj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-22_09:, , signatures=0 Subject: [dpdk-dev] [PATCH v4 26/27] mempool/octeontx2: add devargs for max pool selection X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jerin Jacob The maximum number of mempools per application needs to be configured on HW during mempool driver initialization. HW can support up to 1M mempools, Since each mempool costs set of HW resources, the max_pools devargs parameter is being introduced to configure the number of mempools required for the application. For example: -w 0002:02:00.0,max_pools=512 With the above configuration, the driver will set up only 512 mempools for the given application to save HW resources. Signed-off-by: Jerin Jacob Signed-off-by: Harman Kalra --- drivers/mempool/octeontx2/otx2_mempool.c | 41 +++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/drivers/mempool/octeontx2/otx2_mempool.c b/drivers/mempool/octeontx2/otx2_mempool.c index c47f95fb0..9a5f11cf4 100644 --- a/drivers/mempool/octeontx2/otx2_mempool.c +++ b/drivers/mempool/octeontx2/otx2_mempool.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -159,6 +160,42 @@ otx2_aura_size_to_u32(uint8_t val) return 1 << (val + 6); } +static int +parse_max_pools(const char *key, const char *value, void *extra_args) +{ + RTE_SET_USED(key); + uint32_t val; + + val = atoi(value); + if (val < otx2_aura_size_to_u32(NPA_AURA_SZ_128)) + val = 128; + if (val > otx2_aura_size_to_u32(NPA_AURA_SZ_1M)) + val = BIT_ULL(20); + + *(uint8_t *)extra_args = rte_log2_u32(val) - 6; + return 0; +} + +#define OTX2_MAX_POOLS "max_pools" + +static uint8_t +otx2_parse_aura_size(struct rte_devargs *devargs) +{ + uint8_t aura_sz = NPA_AURA_SZ_128; + struct rte_kvargs *kvlist; + + if (devargs == NULL) + goto exit; + kvlist = rte_kvargs_parse(devargs->args, NULL); + if (kvlist == NULL) + goto exit; + + rte_kvargs_process(kvlist, OTX2_MAX_POOLS, &parse_max_pools, &aura_sz); + rte_kvargs_free(kvlist); +exit: + return aura_sz; +} + static inline int npa_lf_attach(struct otx2_mbox *mbox) { @@ -251,7 +288,7 @@ otx2_npa_lf_init(struct rte_pci_device *pci_dev, void *otx2_dev) if (rc) goto npa_detach; - aura_sz = NPA_AURA_SZ_128; + aura_sz = otx2_parse_aura_size(pci_dev->device.devargs); nr_pools = otx2_aura_size_to_u32(aura_sz); lf = &dev->npalf; @@ -414,3 +451,5 @@ static struct rte_pci_driver pci_npa = { RTE_PMD_REGISTER_PCI(mempool_octeontx2, pci_npa); RTE_PMD_REGISTER_PCI_TABLE(mempool_octeontx2, pci_npa_map); RTE_PMD_REGISTER_KMOD_DEP(mempool_octeontx2, "vfio-pci"); +RTE_PMD_REGISTER_PARAM_STRING(mempool_octeontx2, + OTX2_MAX_POOLS "=<128-1048576>"); -- 2.21.0