From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id D940FA046B for ; Fri, 28 Jun 2019 09:54:14 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 555FE1B9E9; Fri, 28 Jun 2019 09:51:39 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id ADD5D1B9B3 for ; Fri, 28 Jun 2019 09:51:12 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x5S7o7bt001145 for ; Fri, 28 Jun 2019 00:51:12 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=cH7lXRTmMQD2DavsumXgJCryOksO0W3VM2Zg4SC+wu0=; b=gAv4ceOlV38IauGj+SnR27VXiRVaBo/9AvkoC/alGqhhciAzghnBMg6PdyaGjo3VdiYx 7GnAgUOeZuOFCUsIhwNgHJ6cq1/rijHF2Zw1XCFJbnXqdE+cprZ/b5Fa0wz1/eSbzAkU 0/AyzzjnV7EDqQES6hOjqBPOuwA57FbRqZNDPnsjLBjm+Q4umrLL/DhttxXWFjd3yL7v 5NqXb9m7LNoKElNjHX0U4P27uLDoVYUAUR1bh1ORY2sJSfOMtnxrpzuJBnmkLal2QeY6 sMb5btUKZUpQiRIvrp19WpVmzHl7OXwCi0BaC2vHtlMXamqnrqkG1111jmwYreuU25xG lA== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0a-0016f401.pphosted.com with ESMTP id 2tdd778as5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 28 Jun 2019 00:51:11 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Fri, 28 Jun 2019 00:51:10 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Fri, 28 Jun 2019 00:51:10 -0700 Received: from BG-LT7430.marvell.com (bg-lt7430.marvell.com [10.28.10.255]) by maili.marvell.com (Postfix) with ESMTP id 998C03F7040; Fri, 28 Jun 2019 00:51:09 -0700 (PDT) From: To: CC: , Pavan Nikhilesh Date: Fri, 28 Jun 2019 13:20:00 +0530 Message-ID: <20190628075024.404-22-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190628075024.404-1-pbhagavatula@marvell.com> References: <20190628075024.404-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-28_02:, , signatures=0 Subject: [dpdk-dev] [PATCH v2 21/44] event/octeontx2: add devargs to force legacy mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Octeontx2 SSO by default is set to use dual workslot mode. Add devargs option to force legacy mode i.e. single workslot mode. Example: --dev "0002:0e:00.0,single_ws=1" Signed-off-by: Pavan Nikhilesh --- drivers/event/octeontx2/otx2_evdev.c | 8 +++++++- drivers/event/octeontx2/otx2_evdev.h | 11 ++++++++++- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c index 16d5e7dfa..5dc39f029 100644 --- a/drivers/event/octeontx2/otx2_evdev.c +++ b/drivers/event/octeontx2/otx2_evdev.c @@ -911,11 +911,13 @@ static struct rte_eventdev_ops otx2_sso_ops = { }; #define OTX2_SSO_XAE_CNT "xae_cnt" +#define OTX2_SSO_SINGLE_WS "single_ws" static void sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs) { struct rte_kvargs *kvlist; + uint8_t single_ws = 0; if (devargs == NULL) return; @@ -925,7 +927,10 @@ sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs) rte_kvargs_process(kvlist, OTX2_SSO_XAE_CNT, &parse_kvargs_value, &dev->xae_cnt); + rte_kvargs_process(kvlist, OTX2_SSO_SINGLE_WS, &parse_kvargs_flag, + &single_ws); + dev->dual_ws = !single_ws; rte_kvargs_free(kvlist); } @@ -1075,4 +1080,5 @@ otx2_sso_fini(struct rte_eventdev *event_dev) RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso); RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map); RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, "vfio-pci"); -RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT "="); +RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT "=" + OTX2_SSO_SINGLE_WS "=1"); diff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h index 30b5d2c32..8e614b109 100644 --- a/drivers/event/octeontx2/otx2_evdev.h +++ b/drivers/event/octeontx2/otx2_evdev.h @@ -121,8 +121,8 @@ struct otx2_sso_evdev { uint64_t nb_xaq_cfg; rte_iova_t fc_iova; struct rte_mempool *xaq_pool; - uint8_t dual_ws; /* Dev args */ + uint8_t dual_ws; uint32_t xae_cnt; /* HW const */ uint32_t xae_waes; @@ -178,6 +178,15 @@ sso_pmd_priv(const struct rte_eventdev *event_dev) return event_dev->data->dev_private; } +static inline int +parse_kvargs_flag(const char *key, const char *value, void *opaque) +{ + RTE_SET_USED(key); + + *(uint8_t *)opaque = !!atoi(value); + return 0; +} + static inline int parse_kvargs_value(const char *key, const char *value, void *opaque) { -- 2.22.0