From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 99399A046B for ; Fri, 28 Jun 2019 09:55:13 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 08A471BA59; Fri, 28 Jun 2019 09:52:14 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id C9ED81B9F3 for ; Fri, 28 Jun 2019 09:51:24 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x5S7oS6I025270; Fri, 28 Jun 2019 00:51:24 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=tY2ReDuxzDXESAKk0VU++ZqoTSOK2WaYKHekPTX2R5c=; b=BUw4UbBODQyiM6sn6SzZnXbUETsybwOhmrK30RgaCuBYlcjFEAET6EViKtbQCcdKgxDt P4jJrM4khGIMj0dYhTbE4U2fbpxjv+Y/tRXpU7PfRu1FTr3VOOlWo4t9jsDHWLS9FGir wTZlSz4SzJ6wmaSJrd2WNFOmCifKBIQdNv/wgYZ2IQq4gMMvWq4xsOByqdkDmOAUrblb Y7V/PQVtJ/XUOcn5hZxQnwlrgxqY1rs9oKY8hwZhE9s3hZ/dNmm4Wl2fAi+OsdUi9A6Q jdjtJUcrPpWk5fKPKjRfm2ua8sos/SaJjZ0Y2nB16ygDoMJczOgmoTw3Eiml0Lhm6ApZ Pw== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 2tcvnhc6kb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 28 Jun 2019 00:51:24 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Fri, 28 Jun 2019 00:51:22 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Fri, 28 Jun 2019 00:51:22 -0700 Received: from BG-LT7430.marvell.com (bg-lt7430.marvell.com [10.28.10.255]) by maili.marvell.com (Postfix) with ESMTP id 55E473F7041; Fri, 28 Jun 2019 00:51:20 -0700 (PDT) From: To: , John McNamara , "Marko Kovacevic" , Nithin Dabilpuram , Vamsi Attunuru CC: , Pavan Nikhilesh , "Thomas Monjalon" Date: Fri, 28 Jun 2019 13:20:05 +0530 Message-ID: <20190628075024.404-27-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190628075024.404-1-pbhagavatula@marvell.com> References: <20190628075024.404-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-28_02:, , signatures=0 Subject: [dpdk-dev] [PATCH v2 26/44] doc: add Marvell OCTEON TX2 event device documentation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add Marvell OCTEON TX2 event device documentation. This patch also updates the MAINTAINERS file and updates shared library versions in release_19_08.rst. Cc: John McNamara Cc: Thomas Monjalon Signed-off-by: Pavan Nikhilesh --- doc/guides/eventdevs/index.rst | 1 + doc/guides/eventdevs/octeontx2.rst | 104 +++++++++++++++++++++++++++++ doc/guides/platform/octeontx2.rst | 3 + 3 files changed, 108 insertions(+) create mode 100644 doc/guides/eventdevs/octeontx2.rst diff --git a/doc/guides/eventdevs/index.rst b/doc/guides/eventdevs/index.rst index f7382dc8a..570905b81 100644 --- a/doc/guides/eventdevs/index.rst +++ b/doc/guides/eventdevs/index.rst @@ -16,4 +16,5 @@ application trough the eventdev API. dsw sw octeontx + octeontx2 opdl diff --git a/doc/guides/eventdevs/octeontx2.rst b/doc/guides/eventdevs/octeontx2.rst new file mode 100644 index 000000000..928251aa6 --- /dev/null +++ b/doc/guides/eventdevs/octeontx2.rst @@ -0,0 +1,104 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2019 Marvell International Ltd. + +OCTEON TX2 SSO Eventdev Driver +=============================== + +The OCTEON TX2 SSO PMD (**librte_pmd_octeontx2_event**) provides poll mode +eventdev driver support for the inbuilt event device found in the **Marvell OCTEON TX2** +SoC family. + +More information about OCTEON TX2 SoC can be found at `Marvell Official Website +`_. + +Features +-------- + +Features of the OCTEON TX2 SSO PMD are: + +- 256 Event queues +- 26 (dual) and 52 (single) Event ports +- HW event scheduler +- Supports 1M flows per event queue +- Flow based event pipelining +- Flow pinning support in flow based event pipelining +- Queue based event pipelining +- Supports ATOMIC, ORDERED, PARALLEL schedule types per flow +- Event scheduling QoS based on event queue priority +- Open system with configurable amount of outstanding events limited only by + DRAM +- HW accelerated dequeue timeout support to enable power management + +Prerequisites and Compilation procedure +--------------------------------------- + + See :doc:`../platform/octeontx2` for setup information. + +Pre-Installation Configuration +------------------------------ + +Compile time Config Options +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The following option can be modified in the ``config`` file. + +- ``CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV`` (default ``y``) + + Toggle compilation of the ``librte_pmd_octeontx2_event`` driver. + +Runtime Config Options +~~~~~~~~~~~~~~~~~~~~~~ + +- ``Maximum number of in-flight events`` (default ``8192``) + + In **Marvell OCTEON TX2** the max number of in-flight events are only limited + by DRAM size, the ``xae_cnt`` devargs parameter is introduced to provide + upper limit for in-flight events. + For example:: + + --dev "0002:0e:00.0,xae_cnt=16384" + +- ``Force legacy mode`` + + The ``single_ws`` devargs parameter is introduced to force legacy mode i.e + single workslot mode in SSO and disable the default dual workslot mode. + For example:: + + --dev "0002:0e:00.0,single_ws=1" + +- ``Event Group QoS support`` + + SSO GGRPs i.e. queue uses DRAM & SRAM buffers to hold in-flight + events. By default the buffers are assigned to the SSO GGRPs to + satisfy minimum HW requirements. SSO is free to assign the remaining + buffers to GGRPs based on a preconfigured threshold. + We can control the QoS of SSO GGRP by modifying the above mentioned + thresholds. GGRPs that have higher importance can be assigned higher + thresholds than the rest. The dictionary format is as follows + [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] expressed in percentages, 0 represents + default. + For example:: + + --dev "0002:0e:00.0,qos=[1-50-50-50]" + +- ``Selftest`` + + The functionality of OCTEON TX2 eventdev can be verified using this option, + various unit and functional tests are run to verify the sanity. + The tests are run once the vdev creation is successfully complete. + For example:: + + --dev "0002:0e:00.0,selftest=1" + +Debugging Options +~~~~~~~~~~~~~~~~~ + +.. _table_octeontx2_event_debug_options: + +.. table:: OCTEON TX2 event device debug options + + +---+------------+-------------------------------------------------------+ + | # | Component | EAL log command | + +===+============+=======================================================+ + | 1 | SSO | --log-level='pmd\.event\.octeontx2,8' | + +---+------------+-------------------------------------------------------+ diff --git a/doc/guides/platform/octeontx2.rst b/doc/guides/platform/octeontx2.rst index c9ea45647..fbf1193e7 100644 --- a/doc/guides/platform/octeontx2.rst +++ b/doc/guides/platform/octeontx2.rst @@ -101,6 +101,9 @@ This section lists dataplane H/W block(s) available in OCTEON TX2 SoC. #. **Mempool Driver** See :doc:`../mempool/octeontx2` for NPA mempool driver information. +#. **Event Device Driver** + See :doc:`../eventdevs/octeontx2` for SSO event device driver information. + Procedure to Setup Platform --------------------------- -- 2.22.0