From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 05680A046B for ; Fri, 28 Jun 2019 09:55:58 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7C4741BA83; Fri, 28 Jun 2019 09:52:30 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 1D63C1B9FC for ; Fri, 28 Jun 2019 09:51:33 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x5S7oS6M025270 for ; Fri, 28 Jun 2019 00:51:32 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=mBekD5UTrCG27xzjYG0c9H8OeLt0NiHOB3FbOKcTARY=; b=k1iEGplqAHP7ttl1oBYNx01RfcTArvuVVXMF1/S2HV9zaQOP5Ufa1TGnbvIIcmYuwtki Ok9h9AUUfTkjHYmIZoBc9ZO0SFwEi9JsMBdZGb6p46xnFwadYGQledo0Lndwsz7AhsWk CnN2ZrJYJ5u/c780YZSKRRwSAF2zsXMH9AU7Ex3h5tRmqgZjzOD3lVz8Wk6JAo6VaRDU QXTVLBePPMpFfT9lCybAYkU0DanBrcb0AZKLrI1KYa4B7GOonSstMGn2NADJVdkQTbye 3a2XXUB/G1HiRy3RssGCe4RDo7VEmbCTCD+5jEW9BU0xDG4AjOxa9OzrWUfNC4P22xKk aw== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 2tcvnhc6kt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 28 Jun 2019 00:51:32 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Fri, 28 Jun 2019 00:51:30 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Fri, 28 Jun 2019 00:51:30 -0700 Received: from BG-LT7430.marvell.com (bg-lt7430.marvell.com [10.28.10.255]) by maili.marvell.com (Postfix) with ESMTP id BF1C03F7040; Fri, 28 Jun 2019 00:51:29 -0700 (PDT) From: To: CC: , Pavan Nikhilesh Date: Fri, 28 Jun 2019 13:20:09 +0530 Message-ID: <20190628075024.404-31-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190628075024.404-1-pbhagavatula@marvell.com> References: <20190628075024.404-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-28_02:, , signatures=0 Subject: [dpdk-dev] [PATCH v2 30/44] event/octeontx2: allow TIM to optimize config X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Allow TIM to optimize user supplied configuration based on RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES flag. Signed-off-by: Pavan Nikhilesh --- drivers/event/octeontx2/otx2_evdev.h | 1 + drivers/event/octeontx2/otx2_tim_evdev.c | 62 +++++++++++++++++++++++- drivers/event/octeontx2/otx2_tim_evdev.h | 3 ++ 3 files changed, 64 insertions(+), 2 deletions(-) diff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h index fc8dde416..1e15b7e1c 100644 --- a/drivers/event/octeontx2/otx2_evdev.h +++ b/drivers/event/octeontx2/otx2_evdev.h @@ -76,6 +76,7 @@ #define NSEC2USEC(__ns) ((__ns) / 1E3) #define USEC2NSEC(__us) ((__us) * 1E3) #define NSEC2TICK(__ns, __freq) (((__ns) * (__freq)) / 1E9) +#define TICK2NSEC(__tck, __freq) (((__tck) * 1E9) / (__freq)) enum otx2_sso_lf_type { SSO_LF_GGRP, diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c index e24f7ce9e..a0953bb49 100644 --- a/drivers/event/octeontx2/otx2_tim_evdev.c +++ b/drivers/event/octeontx2/otx2_tim_evdev.c @@ -10,6 +10,51 @@ static struct rte_event_timer_adapter_ops otx2_tim_ops; +static void +tim_optimze_bkt_param(struct otx2_tim_ring *tim_ring) +{ + uint64_t tck_nsec; + uint32_t hbkts; + uint32_t lbkts; + + hbkts = rte_align32pow2(tim_ring->nb_bkts); + tck_nsec = RTE_ALIGN_MUL_CEIL(tim_ring->max_tout / (hbkts - 1), 10); + + if ((tck_nsec < TICK2NSEC(OTX2_TIM_MIN_TMO_TKS, + tim_ring->tenns_clk_freq) || + hbkts > OTX2_TIM_MAX_BUCKETS)) + hbkts = 0; + + lbkts = rte_align32prevpow2(tim_ring->nb_bkts); + tck_nsec = RTE_ALIGN_MUL_CEIL((tim_ring->max_tout / (lbkts - 1)), 10); + + if ((tck_nsec < TICK2NSEC(OTX2_TIM_MIN_TMO_TKS, + tim_ring->tenns_clk_freq) || + lbkts > OTX2_TIM_MAX_BUCKETS)) + lbkts = 0; + + if (!hbkts && !lbkts) + return; + + if (!hbkts) { + tim_ring->nb_bkts = lbkts; + goto end; + } else if (!lbkts) { + tim_ring->nb_bkts = hbkts; + goto end; + } + + tim_ring->nb_bkts = (hbkts - tim_ring->nb_bkts) < + (tim_ring->nb_bkts - lbkts) ? hbkts : lbkts; +end: + tim_ring->optimized = true; + tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL((tim_ring->max_tout / + (tim_ring->nb_bkts - 1)), 10); + otx2_tim_dbg("Optimized configured values"); + otx2_tim_dbg("Nb_bkts : %" PRIu32 "", tim_ring->nb_bkts); + otx2_tim_dbg("Tck_nsec : %" PRIu64 "", tim_ring->tck_nsec); +} + static int tim_chnk_pool_create(struct otx2_tim_ring *tim_ring, struct rte_event_timer_adapter_conf *rcfg) @@ -159,8 +204,13 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr) if (NSEC2TICK(RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10), rsp->tenns_clk) < OTX2_TIM_MIN_TMO_TKS) { - rc = -ERANGE; - goto rng_mem_err; + if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES) + rcfg->timer_tick_ns = TICK2NSEC(OTX2_TIM_MIN_TMO_TKS, + rsp->tenns_clk); + else { + rc = -ERANGE; + goto rng_mem_err; + } } tim_ring = rte_zmalloc("otx2_tim_prv", sizeof(struct otx2_tim_ring), 0); @@ -183,6 +233,14 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr) tim_ring->chunk_sz); tim_ring->nb_chunk_slots = OTX2_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz); + /* Try to optimize the bucket parameters. */ + if ((rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES)) { + if (rte_is_power_of_2(tim_ring->nb_bkts)) + tim_ring->optimized = true; + else + tim_optimze_bkt_param(tim_ring); + } + /* Create buckets. */ tim_ring->bkt = rte_zmalloc("otx2_tim_bucket", (tim_ring->nb_bkts) * sizeof(struct otx2_tim_bkt), diff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h index aaa4d93f5..fdd076ebd 100644 --- a/drivers/event/octeontx2/otx2_tim_evdev.h +++ b/drivers/event/octeontx2/otx2_tim_evdev.h @@ -17,6 +17,8 @@ #define TIM_LF_RING_AURA (0x0) #define TIM_LF_RING_BASE (0x130) +#define OTX2_MAX_TIM_RINGS (256) +#define OTX2_TIM_MAX_BUCKETS (0xFFFFF) #define OTX2_TIM_RING_DEF_CHUNK_SZ (4096) #define OTX2_TIM_CHUNK_ALIGNMENT (16) #define OTX2_TIM_NB_CHUNK_SLOTS(sz) (((sz) / OTX2_TIM_CHUNK_ALIGNMENT) - 1) @@ -63,6 +65,7 @@ struct otx2_tim_ring { struct rte_mempool *chunk_pool; uint64_t tck_int; uint8_t prod_type_sp; + uint8_t optimized; uint8_t ena_dfb; uint16_t ring_id; uint32_t aura; -- 2.22.0