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[204.195.22.127]) by smtp.gmail.com with ESMTPSA id 1sm8868977pfe.102.2019.06.30.13.27.59 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sun, 30 Jun 2019 13:28:00 -0700 (PDT) Date: Sun, 30 Jun 2019 13:27:53 -0700 From: Stephen Hemminger To: Gavin Hu Cc: dev@dpdk.org, thomas@monjalon.net, jerinj@marvell.com, hemant.agrawal@nxp.com, bruce.richardson@intel.com, chaozhu@linux.vnet.ibm.com, Honnappa.Nagarahalli@arm.com, nd@arm.com Message-ID: <20190630132753.3f8139f0@hermes.lan> In-Reply-To: <1561911676-37718-2-git-send-email-gavin.hu@arm.com> References: <1561911676-37718-1-git-send-email-gavin.hu@arm.com> <1561911676-37718-2-git-send-email-gavin.hu@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: [dpdk-dev] [RFC 1/5] eal: add the APIs to wait until equal X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Mon, 1 Jul 2019 00:21:12 +0800 Gavin Hu wrote: > +#ifdef RTE_USE_WFE > +#define rte_wait_until_equal_relaxed(addr, expected) do {\ > + typeof(*addr) tmp; \ > + if (__builtin_constant_p((expected))) \ > + do { \ > + if (sizeof(*(addr)) == 16)\ > + asm volatile( \ > + "sevl\n" \ > + "1: wfe\n" \ > + "ldxrh %w0, %1\n" \ > + "cmp %w0, %w2\n" \ > + "bne 1b\n" \ > + : "=&r"(tmp) \ > + : "Q"(*addr), "i"(expected) \ > + : "cc", "memory"); \ > + else if (sizeof(*(addr)) == 32)\ > + asm volatile( \ > + "sevl\n" \ > + "1: wfe\n" \ > + "ldxr %w0, %1\n" \ > + "cmp %w0, %w2\n" \ > + "bne 1b\n" \ > + : "=&r"(tmp) \ > + : "Q"(*addr), "i"(expected) \ > + : "cc", "memory"); \ > + else if (sizeof(*(addr)) == 64)\ > + asm volatile( \ > + "sevl\n" \ > + "1: wfe\n" \ > + "ldxr %x0, %1\n" \ > + "cmp %x0, %x2\n" \ > + "bne 1b\n" \ > + : "=&r" (tmp) \ > + : "Q"(*addr), "i"(expected) \ > + : "cc", "memory"); \ > + } while (0); \ > + else \ > + do { \ > + if (sizeof(*(addr)) == 16)\ > + asm volatile( \ > + "sevl\n" \ > + "1: wfe\n" \ > + "ldxrh %w0, %1\n" \ > + "cmp %w0, %w2\n" \ > + "bne 1b\n" \ > + : "=&r"(tmp) \ > + : "Q"(*addr), "r"(expected) \ > + : "cc", "memory"); \ > + else if (sizeof(*(addr)) == 32)\ > + asm volatile( \ > + "sevl\n" \ > + "1: wfe\n" \ > + "ldxr %w0, %1\n" \ > + "cmp %w0, %w2\n" \ > + "bne 1b\n" \ > + : "=&r"(tmp) \ > + : "Q"(*addr), "r"(expected) \ > + : "cc", "memory"); \ > + else if (sizeof(*(addr)) == 64)\ > + asm volatile( \ > + "sevl\n" \ > + "1: wfe\n" \ > + "ldxr %x0, %1\n" \ > + "cmp %x0, %x2\n" \ > + "bne 1b\n" \ > + : "=&r" (tmp) \ > + : "Q"(*addr), "r"(expected) \ > + : "cc", "memory"); \ > + } while (0); \ > +} while (0) That is a hot mess. Macro's are harder to maintain and offer no benefit over inline functions.