From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8DD37A0487 for ; Fri, 5 Jul 2019 10:38:35 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id F066B1BDF2; Fri, 5 Jul 2019 10:38:13 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 9B2991BDE6 for ; Fri, 5 Jul 2019 10:38:09 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x658ZSoX028886; Fri, 5 Jul 2019 01:38:08 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=Y3zCj6Z8Cn1850EqI4fwAB6ISPxfNIgqdzpClu0cJpA=; b=CuPdeKL0xi7v+8SxY6WRscwQ6zquhGstUeaoSrPpfjA50WqFpAPm+z5946vTqz6LiRcA YEarOz/r1h6tP/zehkdkuRXYY/fDchraSZT7rMwMgVR1VFhizvWaKPzeYh8WF19bafqh 0GEx/2n0miM9zS6RGXS/RT6CA+Z/HZrh3IWmdG45aoBgsYSQcYhUFRREMd2s9NU6R7Ip hcX8OIWoMpOHciABvFgwkKqjk/DIV7KdlUbr2N56EsG4DpxHe1bSO/GU6FtzyXbDFgWn l7mOrSb6RBC46t7X6/W0/PIbllE7aw53IqaRdVdj4Z10A2D2+sX8BOtFwLT5FXP+Ve+1 pg== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0a-0016f401.pphosted.com with ESMTP id 2thv9p1cr4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 05 Jul 2019 01:38:08 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Fri, 5 Jul 2019 01:38:07 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Fri, 5 Jul 2019 01:38:07 -0700 Received: from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14]) by maili.marvell.com (Postfix) with ESMTP id 453B43F703F; Fri, 5 Jul 2019 01:38:06 -0700 (PDT) From: To: , Satha Rao , Vamsi Attunuru CC: Date: Fri, 5 Jul 2019 14:08:01 +0530 Message-ID: <20190705083805.29519-5-jerinj@marvell.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190705083805.29519-1-jerinj@marvell.com> References: <20190601182030.8282-1-jerinj@marvell.com> <20190705083805.29519-1-jerinj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-07-05_03:, , signatures=0 Subject: [dpdk-dev] [PATCH v2 4/8] raw/octeontx2_dma: add device close operation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satha Rao Send message to PF to stop DMA queue when device close is called from application. Defined the required data structures to support enqueue and dequeue APIs. Signed-off-by: Satha Rao Signed-off-by: Vamsi Attunuru --- drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c | 33 +++++ drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h | 133 ++++++++++++++++++++ 2 files changed, 166 insertions(+) diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c index 224c5e5c3..f9c330d69 100644 --- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c +++ b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c @@ -41,6 +41,34 @@ dma_engine_enb_dis(struct dpi_vf_s *dpivf, const bool enb) return DPI_DMA_QUEUE_SUCCESS; } +/* Free DMA Queue instruction buffers, and send close notification to PF */ +static inline int +dma_queue_finish(struct dpi_vf_s *dpivf) +{ + uint32_t timeout = 0, sleep = 1; + uint64_t reg = 0ULL; + + /* Wait for SADDR to become idle */ + reg = otx2_read64(dpivf->vf_bar0 + DPI_VDMA_SADDR); + while (!(reg & BIT_ULL(DPI_VDMA_SADDR_REQ_IDLE))) { + rte_delay_ms(sleep); + timeout++; + if (timeout >= DPI_QFINISH_TIMEOUT) { + otx2_dpi_dbg("Timeout!!! Closing Forcibly"); + break; + } + reg = otx2_read64(dpivf->vf_bar0 + DPI_VDMA_SADDR); + } + + if (otx2_dpi_queue_close(dpivf->vf_id) < 0) + return -EACCES; + + rte_mempool_put(dpivf->chunk_pool, dpivf->base_ptr); + dpivf->vf_bar0 = (uintptr_t)NULL; + + return DPI_DMA_QUEUE_SUCCESS; +} + static int otx2_dpi_rawdev_configure(const struct rte_rawdev *dev, rte_rawdev_obj_t config) { @@ -140,6 +168,7 @@ otx2_dpi_rawdev_remove(struct rte_pci_device *pci_dev) { char name[RTE_RAWDEV_NAME_MAX_LEN]; struct rte_rawdev *rawdev; + struct dpi_vf_s *dpivf; if (pci_dev == NULL) { otx2_dpi_dbg("Invalid pci_dev of the device!"); @@ -157,6 +186,10 @@ otx2_dpi_rawdev_remove(struct rte_pci_device *pci_dev) return -EINVAL; } + dpivf = (struct dpi_vf_s *)rawdev->dev_private; + dma_engine_enb_dis(dpivf, false); + dma_queue_finish(dpivf); + /* rte_rawdev_close is called by pmd_release */ return rte_rawdev_pmd_release(rawdev); } diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h index 918ae725a..f59bab97f 100644 --- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h +++ b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h @@ -31,6 +31,32 @@ #define DPI_QUEUE_STOP 0x0 #define DPI_QUEUE_START 0x1 +#define DPI_VDMA_SADDR_REQ_IDLE 63 +#define DPI_MAX_POINTER 15 +#define STRM_INC(s) ((s)->tail = ((s)->tail + 1) % (s)->max_cnt) +#define DPI_QFINISH_TIMEOUT (10 * 1000) + +/* DPI Transfer Type, pointer type in DPI_DMA_INSTR_HDR_S[XTYPE] */ +#define DPI_XTYPE_OUTBOUND (0) +#define DPI_XTYPE_INBOUND (1) +#define DPI_XTYPE_INTERNAL_ONLY (2) +#define DPI_XTYPE_EXTERNAL_ONLY (3) +#define DPI_XTYPE_MASK 0x3 +#define DPI_HDR_PT_ZBW_CA 0x0 +#define DPI_HDR_PT_ZBW_NC 0x1 +#define DPI_HDR_PT_WQP 0x2 +#define DPI_HDR_PT_WQP_NOSTATUS 0x0 +#define DPI_HDR_PT_WQP_STATUSCA 0x1 +#define DPI_HDR_PT_WQP_STATUSNC 0x3 +#define DPI_HDR_PT_CNT 0x3 +#define DPI_HDR_PT_MASK 0x3 +#define DPI_W0_TT_MASK 0x3 +#define DPI_W0_GRP_MASK 0x3FF +/* Set Completion data to 0xFF when request submitted, + * upon successful request completion engine reset to completion status + */ +#define DPI_REQ_CDATA 0xFF + struct dpi_vf_s { struct rte_pci_device *dev; uint8_t state; @@ -56,6 +82,113 @@ enum dpi_dma_queue_result_e { DPI_DMA_QUEUE_INVALID_PARAM = -2, }; +struct dpi_dma_req_compl_s { + uint64_t cdata; + void (*compl_cb)(void *dev, void *arg); + void *cb_data; +}; + +union dpi_dma_ptr_u { + uint64_t u[2]; + struct dpi_dma_s { + uint64_t length:16; + uint64_t reserved:44; + uint64_t bed:1; /* Big-Endian */ + uint64_t alloc_l2:1; + uint64_t full_write:1; + uint64_t invert:1; + uint64_t ptr; + } s; +}; + +struct dpi_dma_buf_ptr_s { + union dpi_dma_ptr_u *rptr[DPI_MAX_POINTER]; /* Read From pointer list */ + union dpi_dma_ptr_u *wptr[DPI_MAX_POINTER]; /* Write to pointer list */ + uint8_t rptr_cnt; + uint8_t wptr_cnt; + struct dpi_dma_req_compl_s *comp_ptr; +}; + +struct dpi_cring_data_s { + struct dpi_dma_req_compl_s **compl_data; + uint16_t max_cnt; + uint16_t head; + uint16_t tail; +}; + +struct dpi_dma_queue_ctx_s { + uint16_t xtype:2; + + /* Completion pointer type */ + uint16_t pt:2; + + /* Completion updated using WQE */ + uint16_t tt:2; + uint16_t grp:10; + uint32_t tag; + + /* Valid only for Outbound only mode */ + uint16_t aura:12; + uint16_t csel:1; + uint16_t ca:1; + uint16_t fi:1; + uint16_t ii:1; + uint16_t fl:1; + + uint16_t pvfe:1; + uint16_t dealloce:1; + uint16_t req_type:2; + uint16_t use_lock:1; + uint16_t deallocv; + + struct dpi_cring_data_s *c_ring; +}; + +/* DPI DMA Instruction Header Format */ +union dpi_dma_instr_hdr_u { + uint64_t u[4]; + + struct dpi_dma_instr_hdr_s_s { + uint64_t tag:32; + uint64_t tt:2; + uint64_t grp:10; + uint64_t reserved_44_47:4; + uint64_t nfst:4; + uint64_t reserved_52_53:2; + uint64_t nlst:4; + uint64_t reserved_58_63:6; + /* Word 0 - End */ + + uint64_t aura:12; + uint64_t reserved_76_79:4; + uint64_t deallocv:16; + uint64_t dealloce:1; + uint64_t pvfe:1; + uint64_t reserved_98_99:2; + uint64_t pt:2; + uint64_t reserved_102_103:2; + uint64_t fl:1; + uint64_t ii:1; + uint64_t fi:1; + uint64_t ca:1; + uint64_t csel:1; + uint64_t reserved_109_111:3; + uint64_t xtype:2; + uint64_t reserved_114_119:6; + uint64_t fport:2; + uint64_t reserved_122_123:2; + uint64_t lport:2; + uint64_t reserved_126_127:2; + /* Word 1 - End */ + + uint64_t ptr:64; + /* Word 2 - End */ + + uint64_t reserved_192_255:64; + /* Word 3 - End */ + } s; +}; + int otx2_dpi_queue_open(uint16_t vf_id, uint32_t size, uint32_t gaura); int otx2_dpi_queue_close(uint16_t vf_id); -- 2.22.0