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Mon, 22 Jul 2019 09:30:59 +0000 Received: from AM6PR05MB6567.eurprd05.prod.outlook.com ([fe80::496b:bd1c:863a:ed47]) by AM6PR05MB6567.eurprd05.prod.outlook.com ([fe80::496b:bd1c:863a:ed47%3]) with mapi id 15.20.2094.017; Mon, 22 Jul 2019 09:30:59 +0000 From: Jack Min To: Dekel Peled CC: Yongseok Koh , Slava Ovsiienko , Shahaf Shuler , Ori Kam , "dev@dpdk.org" Thread-Topic: [PATCH] net/mlx5: fix NVGRE matching Thread-Index: AQHVPaEEMr3JZ6qWCUqOpqJnqLntg6bWZQmA Date: Mon, 22 Jul 2019 09:30:59 +0000 Message-ID: <20190722093049.chqtifxh3gdrq77e@mellanox.com> References: <3cd91c82dfa7f0feb325c0ed866659c07230c9fb.1563478228.git.dekelp@mellanox.com> In-Reply-To: <3cd91c82dfa7f0feb325c0ed866659c07230c9fb.1563478228.git.dekelp@mellanox.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK0P153CA0006.APCP153.PROD.OUTLOOK.COM (2603:1096:203:18::18) To AM6PR05MB6567.eurprd05.prod.outlook.com (2603:10a6:20b:bc::23) authentication-results: spf=none (sender IP is ) smtp.mailfrom=jackmin@mellanox.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR05MB6229; H:AM6PR05MB6567.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: cnNrVmeTAcoBMYlGK+9v08sTf9EqVWW69Dd9A9FA/duNA4qeYXvuFGcgPtdrJQt79flwmn2Oubl3ygYf3rzIO6NQEMjsvzlSRXN4cCw2AuwzrOmHK3JzRZzR3nBxKtmuJjMJJfvNjWRLQ6ceu2Sa3nFD9mN7BAzziWiUFfFUxNCxKR2hoE8LngU57VrKdYCBWK4x01iIH3rXFE/x7L38CHKsGAvixS/Zds6X/5O0r0sdT34P3eCOggpKXpa48/GWfMIgSwf8+ICbUYMQWEhMlcMx1O0UhYEp4EbU0txaWVsPHQQXwZTknOCalqaj2rzWDDY86AimKjsb1ysBeJX4X76wyh7jrb+3u1qrNygqmvKsJiJmW/5kG0eYwVLfzQbmMkUrKRaavIb7HqI+Sgpg2wui0KF9sqqWo1GQiRjwg5k= Content-Type: text/plain; charset="us-ascii" Content-ID: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 263a29ae-d7b3-4f5b-d88b-08d70e874de6 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Jul 2019 09:30:59.0660 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jackmin@mellanox.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR05MB6229 Subject: Re: [dpdk-dev] [PATCH] net/mlx5: fix NVGRE matching X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Thu, 19-07-18, 22:42, Dekel Peled wrote: > NVGRE has a GRE header with c_rsvd0_ver value 0x2000 and protocol > value 0x6558. > These should be matched when item_nvgre is provided. >=20 > This patch adds validation function of NVGRE item, to validate that > the input values, if exist, are as required. > It also updates the translate function of NVGRE item, to add the > required values, if they were not specified. >=20 > Original work by Xiaoyu Min >=20 > Fixes: fc2c498ccb94 ("net/mlx5: add Direct Verbs translate items") > Signed-off-by: Dekel Peled > --- > drivers/net/mlx5/mlx5_flow.c | 69 +++++++++++++++++++++++++++++++++++= ++++++ > drivers/net/mlx5/mlx5_flow.h | 10 ++++-- > drivers/net/mlx5/mlx5_flow_dv.c | 25 +++++++++++++-- > drivers/net/mlx5/mlx5_rxtx.h | 2 +- > 4 files changed, 101 insertions(+), 5 deletions(-) >=20 > diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c > index e082cbb..6aca4d6 100644 > --- a/drivers/net/mlx5/mlx5_flow.c > +++ b/drivers/net/mlx5/mlx5_flow.c > @@ -298,6 +298,10 @@ struct mlx5_flow_tunnel_info { > .tunnel =3D MLX5_FLOW_LAYER_MPLS, > .ptype =3D RTE_PTYPE_TUNNEL_MPLS_IN_GRE, > }, > + { > + .tunnel =3D MLX5_FLOW_LAYER_NVGRE, > + .ptype =3D RTE_PTYPE_TUNNEL_NVGRE, > + }, > }; > =20 > /** > @@ -1323,6 +1327,11 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_= dev *dev, int32_t priority, > return rte_flow_error_set(error, EINVAL, > RTE_FLOW_ERROR_TYPE_ITEM, item, > "L3 cannot follow an L4 layer."); > + else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && > + !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) > + return rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, item, > + "L3 cannot follow an NVGRE layer."); > if (!mask) > mask =3D &rte_flow_item_ipv4_mask; > else if (mask->hdr.next_proto_id !=3D 0 && > @@ -1409,6 +1418,11 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_= dev *dev, int32_t priority, > return rte_flow_error_set(error, EINVAL, > RTE_FLOW_ERROR_TYPE_ITEM, item, > "L3 cannot follow an L4 layer."); > + else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && > + !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) > + return rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, item, > + "L3 cannot follow an NVGRE layer."); > if (!mask) > mask =3D &rte_flow_item_ipv6_mask; > ret =3D mlx5_flow_item_acceptable(item, (const uint8_t *)mask, > @@ -1887,6 +1901,61 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_= dev *dev, int32_t priority, > " update."); > } > =20 > +/** > + * Validate NVGRE item. > + * > + * @param[in] item > + * Item specification. > + * @param[in] item_flags > + * Bit flags to mark detected items. > + * @param[in] target_protocol > + * The next protocol in the previous item. > + * @param[out] error > + * Pointer to error structure. > + * > + * @return > + * 0 on success, a negative errno value otherwise and rte_errno is set= . > + */ > +int > +mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, > + uint64_t item_flags, > + uint8_t target_protocol, > + struct rte_flow_error *error) > +{ > + const struct rte_flow_item_nvgre *mask =3D item->mask; > + const struct rte_flow_item_nvgre *spec =3D item->spec; > + int ret; > + > + if (target_protocol !=3D 0xff && target_protocol !=3D IPPROTO_GRE) > + return rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, item, > + "protocol filtering not compatible" > + " with this GRE layer"); > + if (item_flags & MLX5_FLOW_LAYER_TUNNEL) > + return rte_flow_error_set(error, ENOTSUP, > + RTE_FLOW_ERROR_TYPE_ITEM, item, > + "multiple tunnel layers not" > + " supported"); > + if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) > + return rte_flow_error_set(error, ENOTSUP, > + RTE_FLOW_ERROR_TYPE_ITEM, item, > + "L3 Layer is missing"); > + if (spec && (spec->protocol !=3D RTE_BE16(RTE_ETHER_TYPE_TEB) || > + spec->c_k_s_rsvd0_ver !=3D RTE_BE16(0x2000))) > + return rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, item, > + "wrong values for NVGRE"); Not necessary to check the spec because the following mlx5_flow_item_acceptable only accept matching on .tni field. Since there is no meaning allowing the user to match on .protocol and .c_k_s_rsvd0_ver. What do you think? > + if (!mask) > + mask =3D &rte_flow_item_nvgre_mask; > + ret =3D mlx5_flow_item_acceptable > + (item, (const uint8_t *)mask, > + (const uint8_t *)&rte_flow_item_nvgre_mask, > + sizeof(struct rte_flow_item_nvgre), error); > + if (ret < 0) > + return ret; > + return 0; > +} > + > static int > flow_null_validate(struct rte_eth_dev *dev __rte_unused, > const struct rte_flow_attr *attr __rte_unused, > diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h > index 3f96bec..24da74b 100644 > --- a/drivers/net/mlx5/mlx5_flow.h > +++ b/drivers/net/mlx5/mlx5_flow.h > @@ -48,6 +48,7 @@ > #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13) > #define MLX5_FLOW_LAYER_GRE (1u << 14) > #define MLX5_FLOW_LAYER_MPLS (1u << 15) > +/* List of tunnel Layer bits continued below. */ > =20 > /* General pattern items bits. */ > #define MLX5_FLOW_ITEM_METADATA (1u << 16) > @@ -58,8 +59,10 @@ > #define MLX5_FLOW_LAYER_ICMP6 (1u << 19) > #define MLX5_FLOW_LAYER_GRE_KEY (1u << 20) > =20 > +/* Pattern tunnel Layer bits (continued). */ > #define MLX5_FLOW_LAYER_IPIP (1u << 21) > #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 22) > +#define MLX5_FLOW_LAYER_NVGRE (1u << 23) > =20 > /* Outer Masks. */ > #define MLX5_FLOW_LAYER_OUTER_L3 \ > @@ -79,7 +82,7 @@ > /* Tunnel Masks. */ > #define MLX5_FLOW_LAYER_TUNNEL \ > (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \ > - MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_MPLS | \ > + MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \ > MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP) > =20 > /* Inner Masks. */ > @@ -518,5 +521,8 @@ int mlx5_flow_validate_item_icmp6(const struct rte_fl= ow_item *item, > uint64_t item_flags, > uint8_t target_protocol, > struct rte_flow_error *error); > - > +int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, > + uint64_t item_flags, > + uint8_t target_protocol, > + struct rte_flow_error *error); > #endif /* RTE_PMD_MLX5_FLOW_H_ */ > diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow= _dv.c > index 7240d3b..ab758d4 100644 > --- a/drivers/net/mlx5/mlx5_flow_dv.c > +++ b/drivers/net/mlx5/mlx5_flow_dv.c > @@ -2966,7 +2966,6 @@ struct field_modify_info modify_tcp[] =3D { > MLX5_FLOW_LAYER_OUTER_L4_UDP; > break; > case RTE_FLOW_ITEM_TYPE_GRE: > - case RTE_FLOW_ITEM_TYPE_NVGRE: > ret =3D mlx5_flow_validate_item_gre(items, item_flags, > next_protocol, error); > if (ret < 0) > @@ -2974,6 +2973,14 @@ struct field_modify_info modify_tcp[] =3D { > gre_item =3D items; > last_item =3D MLX5_FLOW_LAYER_GRE; > break; > + case RTE_FLOW_ITEM_TYPE_NVGRE: > + ret =3D mlx5_flow_validate_item_nvgre(items, item_flags, > + next_protocol, > + error); > + if (ret < 0) > + return ret; > + last_item =3D MLX5_FLOW_LAYER_NVGRE; > + break; > case RTE_FLOW_ITEM_TYPE_GRE_KEY: > ret =3D mlx5_flow_validate_item_gre_key > (items, item_flags, gre_item, error); > @@ -3919,7 +3926,21 @@ struct field_modify_info modify_tcp[] =3D { > int size; > int i; > =20 > - flow_dv_translate_item_gre(matcher, key, item, inner); > + /* For NVGRE, GRE header fields must be set with defined values. */ > + const struct rte_flow_item_gre gre_spec =3D { > + .c_rsvd0_ver =3D RTE_BE16(0x2000), > + .protocol =3D RTE_BE16(RTE_ETHER_TYPE_TEB) > + }; > + const struct rte_flow_item_gre gre_mask =3D { > + .c_rsvd0_ver =3D RTE_BE16(UINT16_MAX), Well, it should be `RTE_BE16(0xB000)`, which, I think, is more explicit. Because our NIC only support matching on C,K,S bits, not else bits in c_rsvd0_ver. Our PMD just ignore the other bits.=20 > + .protocol =3D RTE_BE16(UINT16_MAX), > + }; > + const struct rte_flow_item gre_item =3D { > + .spec =3D &gre_spec, > + .mask =3D &gre_mask, > + .last =3D NULL, > + }; > + flow_dv_translate_item_gre(matcher, key, &gre_item, inner); > if (!nvgre_v) > return; > if (!nvgre_m) > diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h > index dfa79e2..d732757 100644 > --- a/drivers/net/mlx5/mlx5_rxtx.h > +++ b/drivers/net/mlx5/mlx5_rxtx.h > @@ -40,7 +40,7 @@ > #include "mlx5_glue.h" > =20 > /* Support tunnel matching. */ > -#define MLX5_FLOW_TUNNEL 5 > +#define MLX5_FLOW_TUNNEL 6 > =20 > struct mlx5_rxq_stats { > #ifdef MLX5_PMD_SOFT_COUNTERS > --=20 > 1.8.3.1 >=20