From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 010A7A046B for ; Fri, 26 Jul 2019 07:24:53 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4BDE01C3C2; Fri, 26 Jul 2019 07:24:52 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 7593C1C3C0 for ; Fri, 26 Jul 2019 07:24:50 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x6Q5Oi1s020169; Thu, 25 Jul 2019 22:24:49 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=t5/nHBtQjs0cMv966vDL/KKjeOcfXQv1UDiFE1IAy3w=; b=l+kQ8wTuvgZa3d3DxQT+djsqr5n3B2SgSvPCB1UHzAtCuQyjmcwm8eW1Nq32u3gQmI3M MFIAr6E0qLx9mSp4Kb+XcMZ/RzgRi61kv1DuhzCewyJ9JJ3eywmg2VHuvOK3/ocrVFL9 WvBDaF202U5DWspZrahy7ruekFwiGhnn6bHyX5Jd07MDa8lIEbpCJVUNKYsS2uEJApKe hhW4O458EuHVkMJydjjUdoKb31JLTFynZa15PVYNQkJ45/CP+THYN7lbdJsS8v4NfanK 3dpOSl3sTcMqI1OGcIuPF52wE+c4FpQv8PsVxwbBcfqaZlDxGHkgU1AOhJD2vFT93Mcg Ig== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 2tx6254s7j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 25 Jul 2019 22:24:49 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Thu, 25 Jul 2019 22:24:47 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Thu, 25 Jul 2019 22:24:47 -0700 Received: from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14]) by maili.marvell.com (Postfix) with ESMTP id 451C03F703F; Thu, 25 Jul 2019 22:24:46 -0700 (PDT) From: To: , Jerin Jacob , Nithin Dabilpuram , Vamsi Attunuru CC: Date: Fri, 26 Jul 2019 10:54:43 +0530 Message-ID: <20190726052443.21302-1-jerinj@marvell.com> X-Mailer: git-send-email 2.22.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:5.22.84,1.0.8 definitions=2019-07-26_03:2019-07-26,2019-07-26 signatures=0 Subject: [dpdk-dev] [PATCH] common/octeontx2: fix to prevent STP instruction fissure X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jerin Jacob OTX2 AP core can sometimes fissure STP instructions when it is more optimal to send such writes into the pipeline as 2 separate instructions. However registers should be excluded from such optimization. This commit ensures that no CSR write is ever fissured by introducing zero cost workaround by setting STP pre-index by zero to make sure OTX2 AP core prevent fissure. Fixes: 8a4f835971f5 ("common/octeontx2: add IO handling APIs") Signed-off-by: Jerin Jacob --- drivers/common/octeontx2/otx2_io_arm64.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/common/octeontx2/otx2_io_arm64.h b/drivers/common/octeontx2/otx2_io_arm64.h index 468243c04..7e45329b3 100644 --- a/drivers/common/octeontx2/otx2_io_arm64.h +++ b/drivers/common/octeontx2/otx2_io_arm64.h @@ -14,7 +14,7 @@ #define otx2_store_pair(val0, val1, addr) ({ \ asm volatile( \ - "stp %x[x0], %x[x1], [%x[p1]]" \ + "stp %x[x0], %x[x1], [%x[p1],#0]!" \ ::[x0]"r"(val0), [x1]"r"(val1), [p1]"r"(addr) \ ); }) -- 2.22.0