From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id AF053A0613 for ; Tue, 30 Jul 2019 15:26:48 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E4EFF1C120; Tue, 30 Jul 2019 15:26:47 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id C18031B953; Tue, 30 Jul 2019 15:26:45 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Jul 2019 06:26:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,326,1559545200"; d="scan'208";a="174234734" Received: from silpixa00389816.ir.intel.com ([10.237.222.12]) by orsmga003.jf.intel.com with ESMTP; 30 Jul 2019 06:26:41 -0700 From: Hariprasad Govindharajan To: Marko Kovacevic , Ori Kam , Bruce Richardson , Pablo de Lara , Radu Nicolau , Akhil Goyal , Tomasz Kantecki Cc: dev@dpdk.org, Hariprasad Govindharajan , maciej.czekaj@caviumnetworks.com, stable@dpdk.org, Jerin Jacob Date: Tue, 30 Jul 2019 14:26:38 +0100 Message-Id: <20190730132639.84137-1-hariprasad.govindharajan@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190726135858.55792-1-hariprasad.govindharajan@intel.com> References: <20190726135858.55792-1-hariprasad.govindharajan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v5] Examples/l3fwd: fix unaligned memory access X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Fix unaligned memory access when reading IPv6 header which leads to segmentation fault by changing aligned memory read to unaligned memory read. Bugzilla ID: 279 Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build") Cc: maciej.czekaj@caviumnetworks.com Cc: stable@dpdk.org Signed-off-by: Hariprasad Govindharajan Reviewed-by: Bruce Richardson Reviewed-by: Jerin Jacob --- V2: Added functions which will do unaligned load based on the underlying architecture V3: Removed functions added in V2 and replaced them with if macros which will branch based on the underlying architecture. As per my understanding since the unaligned load affects only Intel arch, I added that function branch and left the original code for other arc. Can someone with ARM and PowerPC arch, could you please validate this patch and let me know? V5: Fixed coding style issues. --- examples/l3fwd/l3fwd_em.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c index 5f499e005..74a7c8fa4 100644 --- a/examples/l3fwd/l3fwd_em.c +++ b/examples/l3fwd/l3fwd_em.c @@ -287,7 +287,11 @@ em_get_ipv6_dst_port(void *ipv6_hdr, uint16_t portid, void *lookup_struct) * Get part of 5 tuple: dst IP address lower 96 bits * and src IP address higher 32 bits. */ +#if defined RTE_ARCH_X86 + key.xmm[1] = _mm_loadu_si128(data1); +#else key.xmm[1] = *(xmm_t *)data1; +#endif /* * Get part of 5 tuple: dst port and src port -- 2.22.0