* [dpdk-dev] [PATCH 01/63] net/ice/base: enhance NVM read
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 02/63] net/ice/base: add function to get FW mode Qi Zhang
` (62 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang; +Cc: dev, xiaolong.ye, Qi Zhang, Paul M Stillwell Jr
Add an option to read NVM from flash directly.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_adminq_cmd.h | 22 ++++++++++++++++++++++
drivers/net/ice/base/ice_dcb.h | 1 +
drivers/net/ice/base/ice_nvm.c | 12 +++++++++---
3 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index 7afdb6578..b5faa5bf6 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1684,6 +1684,28 @@ struct ice_aqc_nvm {
__le32 addr_low;
};
+/* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */
+#define ICE_AQC_NVM_SECTOR_UNIT 4096 /* In Bytes */
+#define ICE_AQC_NVM_WORD_UNIT 2 /* In Bytes */
+
+#define ICE_AQC_NVM_START_POINT 0
+#define ICE_AQC_NVM_EMP_SR_PTR_OFFSET 0x90
+#define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN 2 /* In Bytes */
+#define ICE_AQC_NVM_EMP_SR_PTR_M MAKEMASK(0x7FFF, 0)
+#define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S 15
+#define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M BIT(15)
+#define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR 1
+
+#define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET 0x46
+#define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN 2 /* In Bytes */
+#define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */
+
+#define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129
+#define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */
+#define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0)
+#define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */
+#define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */
+
/* Used for 0x0704 as well as for 0x0705 commands */
struct ice_aqc_nvm_cfg {
diff --git a/drivers/net/ice/base/ice_dcb.h b/drivers/net/ice/base/ice_dcb.h
index 47127096b..9a0968f5b 100644
--- a/drivers/net/ice/base/ice_dcb.h
+++ b/drivers/net/ice/base/ice_dcb.h
@@ -6,6 +6,7 @@
#define _ICE_DCB_H_
#include "ice_type.h"
+#include "ice_common.h"
#define ICE_DCBX_OFFLOAD_DIS 0
#define ICE_DCBX_OFFLOAD_ENABLED 1
diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c
index 6178cd4ac..f4567ca8f 100644
--- a/drivers/net/ice/base/ice_nvm.c
+++ b/drivers/net/ice/base/ice_nvm.c
@@ -13,13 +13,15 @@
* @length: length of the section to be read (in bytes from the offset)
* @data: command buffer (size [bytes] = length)
* @last_command: tells if this is the last command in a series
+ * @read_shadow_ram: tell if this is a shadow RAM read
* @cd: pointer to command details structure or NULL
*
* Read the NVM using the admin queue commands (0x0701)
*/
static enum ice_status
ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,
- void *data, bool last_command, struct ice_sq_cd *cd)
+ void *data, bool last_command, bool read_shadow_ram,
+ struct ice_sq_cd *cd)
{
struct ice_aq_desc desc;
struct ice_aqc_nvm *cmd;
@@ -34,6 +36,9 @@ ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);
+ if (!read_shadow_ram && module_typeid == ICE_AQC_NVM_START_POINT)
+ cmd->cmd_flags |= ICE_AQC_NVM_FLASH_ONLY;
+
/* If this is the last command in a series, set the proper flag. */
if (last_command)
cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
@@ -104,8 +109,9 @@ ice_read_sr_aq(struct ice_hw *hw, u32 offset, u16 words, u16 *data,
* So do this conversion while calling ice_aq_read_nvm.
*/
if (!status)
- status = ice_aq_read_nvm(hw, 0, 2 * offset, 2 * words, data,
- last_command, NULL);
+ status = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT,
+ 2 * offset, 2 * words, data,
+ last_command, true, NULL);
return status;
}
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 02/63] net/ice/base: add function to get FW mode
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 01/63] net/ice/base: enhance NVM read Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 03/63] net/ice/base: add support for NVM rollback detection Qi Zhang
` (61 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Anirudh Venkataramanan, Paul M Stillwell Jr
Add a helper function to get FW mode. The FW mode can be normal,
debug, recovery or rollback.
This makes ice_is_fw_in_rec_mode redundant, so remove it.
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 23 ++++++++++++++++-------
drivers/net/ice/base/ice_common.h | 4 ++--
2 files changed, 18 insertions(+), 9 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 52fd8c897..681740cee 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -4102,16 +4102,25 @@ ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
}
/**
- * ice_is_fw_in_rec_mode
+ * ice_get_fw_mode - returns FW mode
* @hw: pointer to the HW struct
- *
- * This function returns true if fw is in recovery mode
*/
-bool ice_is_fw_in_rec_mode(struct ice_hw *hw)
+enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)
{
- u32 reg;
+#define ICE_FW_MODE_DBG_M BIT(0)
+#define ICE_FW_MODE_REC_M BIT(1)
+#define ICE_FW_MODE_ROLLBACK_M BIT(2)
+ u32 fw_mode;
/* check the current FW mode */
- reg = rd32(hw, GL_MNG_FWSM);
- return (reg & GL_MNG_FWSM_FW_MODES_M) > ICE_FW_MODE_DBG;
+ fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M;
+
+ if (fw_mode & ICE_FW_MODE_DBG_M)
+ return ICE_FW_MODE_DBG;
+ else if (fw_mode & ICE_FW_MODE_REC_M)
+ return ICE_FW_MODE_REC;
+ else if (fw_mode & ICE_FW_MODE_ROLLBACK_M)
+ return ICE_FW_MODE_ROLLBACK;
+ else
+ return ICE_FW_MODE_NORMAL;
}
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index 2063295ce..1d8701d64 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -14,7 +14,7 @@ enum ice_fw_modes {
ICE_FW_MODE_NORMAL,
ICE_FW_MODE_DBG,
ICE_FW_MODE_REC,
- ICE_FW_MODE_DBG_REC
+ ICE_FW_MODE_ROLLBACK
};
enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw);
@@ -198,8 +198,8 @@ ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
void
ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
u64 *prev_stat, u64 *cur_stat);
+enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw);
enum ice_status
ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
struct ice_aqc_get_elem *buf);
-bool ice_is_fw_in_rec_mode(struct ice_hw *hw);
#endif /* _ICE_COMMON_H_ */
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 03/63] net/ice/base: add support for NVM rollback detection
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 01/63] net/ice/base: enhance NVM read Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 02/63] net/ice/base: add function to get FW mode Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 04/63] net/ice/base: add support to init RXDID descs fields Qi Zhang
` (60 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Anirudh Venkataramanan, Paul M Stillwell Jr
This patch adds code to detect NVM rollback. The rollback detection
is done as part of the HW init flow. When NVM rollback is detected,
a warning message is printed along with the FW/NVM version data.
To do this, this patch adds a helper function ice_get_nvm_version.
Also, a pointer to hw->nvm is already available in ice_init_nvm. Just use
this instead of &hw->nvm.
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 46 +++++++++++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_common.h | 4 ++++
drivers/net/ice/base/ice_nvm.c | 6 ++---
drivers/net/ice/base/ice_type.h | 4 +++-
4 files changed, 56 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 681740cee..4968808fa 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -814,6 +814,49 @@ static void ice_get_itr_intrl_gran(struct ice_hw *hw)
}
/**
+ * ice_get_nvm_version - get cached NVM version data
+ * @hw: pointer to the hardware structure
+ * @oem_ver: 8 bit NVM version
+ * @oem_build: 16 bit NVM build number
+ * @oem_patch: 8 NVM patch number
+ * @ver_hi: high 16 bits of the NVM version
+ * @ver_lo: low 16 bits of the NVM version
+ */
+void
+ice_get_nvm_version(struct ice_hw *hw, u8 *oem_ver, u16 *oem_build,
+ u8 *oem_patch, u8 *ver_hi, u8 *ver_lo)
+{
+ struct ice_nvm_info *nvm = &hw->nvm;
+
+ *oem_ver = (u8)((nvm->oem_ver & ICE_OEM_VER_MASK) >> ICE_OEM_VER_SHIFT);
+ *oem_patch = (u8)(nvm->oem_ver & ICE_OEM_VER_PATCH_MASK);
+ *oem_build = (u16)((nvm->oem_ver & ICE_OEM_VER_BUILD_MASK) >>
+ ICE_OEM_VER_BUILD_SHIFT);
+ *ver_hi = (nvm->ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
+ *ver_lo = (nvm->ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT;
+}
+
+/**
+ * ice_print_rollback_msg - print FW rollback message
+ * @hw: pointer to the hardware structure
+ */
+void ice_print_rollback_msg(struct ice_hw *hw)
+{
+ char nvm_str[ICE_NVM_VER_LEN] = { 0 };
+ u8 oem_ver, oem_patch, ver_hi, ver_lo;
+ u16 oem_build;
+
+ ice_get_nvm_version(hw, &oem_ver, &oem_build, &oem_patch, &ver_hi,
+ &ver_lo);
+ SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d", ver_hi,
+ ver_lo, hw->nvm.eetrack, oem_ver, oem_build, oem_patch);
+
+ ice_warn(hw,
+ "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode",
+ nvm_str, hw->fw_maj_ver, hw->fw_min_ver);
+}
+
+/**
* ice_init_hw - main hardware initialization routine
* @hw: pointer to the hardware structure
*/
@@ -848,6 +891,9 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
if (status)
goto err_unroll_cqinit;
+ if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
+ ice_print_rollback_msg(hw);
+
/* Enable FW logging. Not fatal if this fails. */
status = ice_cfg_fw_log(hw, true);
if (status)
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index 1d8701d64..009c052ca 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -198,7 +198,11 @@ ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
void
ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
u64 *prev_stat, u64 *cur_stat);
+void
+ice_get_nvm_version(struct ice_hw *hw, u8 *oem_ver, u16 *oem_build,
+ u8 *oem_patch, u8 *ver_hi, u8 *ver_lo);
enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw);
+void ice_print_rollback_msg(struct ice_hw *hw);
enum ice_status
ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
struct ice_aqc_get_elem *buf);
diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c
index f4567ca8f..c0f9e353e 100644
--- a/drivers/net/ice/base/ice_nvm.c
+++ b/drivers/net/ice/base/ice_nvm.c
@@ -292,7 +292,7 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)
return status;
}
- status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &hw->nvm.ver);
+ status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &nvm->ver);
if (status) {
ice_debug(hw, ICE_DBG_INIT,
"Failed to read DEV starter version.\n");
@@ -310,7 +310,7 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)
return status;
}
- hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo;
+ nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
status = ice_read_sr_word(hw, ICE_SR_BOOT_CFG_PTR, &cfg_ptr);
if (status) {
@@ -331,7 +331,7 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)
return status;
}
- hw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo;
+ nvm->oem_ver = ((u32)oem_hi << 16) | oem_lo;
return status;
}
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index b03f18d16..2d010e643 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -436,10 +436,12 @@ struct ice_nvm_info {
u32 eetrack; /* NVM data version */
u32 oem_ver; /* OEM version info */
u16 sr_words; /* Shadow RAM size in words */
- u16 ver; /* NVM package version */
+ u16 ver; /* dev starter version */
u8 blank_nvm_mode; /* is NVM empty (no FW present)*/
};
+#define ICE_NVM_VER_LEN 32
+
/* Max number of port to queue branches w.r.t topology */
#define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 04/63] net/ice/base: add support to init RXDID descs fields
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (2 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 03/63] net/ice/base: add support for NVM rollback detection Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 05/63] net/ice/base: store number of functions for the device Qi Zhang
` (59 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Junfeng Guo, Haiyue Wang,
Paul M Stillwell Jr
Add new switch cases to init RXDID descs MD fields.
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 91 ++++++++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_lan_tx_rx.h | 6 +++
2 files changed, 97 insertions(+)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 4968808fa..58dd01ea1 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -19,6 +19,16 @@
(((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M))
+#define ICE_PROG_FLEX_ENTRY_EXTRACT(hw, rxdid, protid, off, idx) \
+ wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \
+ ((ICE_RX_OPC_EXTRACT << \
+ GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
+ GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
+ (((protid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
+ GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M) | \
+ (((off) << GLFLXP_RXDID_FLX_WRD_##idx##_EXTRACTION_OFFSET_S) & \
+ GLFLXP_RXDID_FLX_WRD_##idx##_EXTRACTION_OFFSET_M))
+
#define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \
wr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \
(((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \
@@ -412,6 +422,8 @@ static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)
*/
static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)
{
+ enum ice_prot_id protid_0, protid_1;
+ u16 offset_0, offset_1;
enum ice_flex_mdid mdid;
switch (prof_id) {
@@ -428,7 +440,80 @@ static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)
ice_init_flex_flags(hw, prof_id);
break;
+ case ICE_RXDID_COMMS_GENERIC:
+ case ICE_RXDID_COMMS_AUX_VLAN:
+ case ICE_RXDID_COMMS_AUX_IPV4:
+ case ICE_RXDID_COMMS_AUX_IPV6:
+ case ICE_RXDID_COMMS_AUX_IPV6_FLOW:
+ case ICE_RXDID_COMMS_AUX_TCP:
+ ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_LOW, 0);
+ ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_HIGH, 1);
+ ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_LOWER, 2);
+ ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_HIGH, 3);
+
+ if (prof_id == ICE_RXDID_COMMS_AUX_VLAN) {
+ /* FlexiMD.4: VLAN1 - single or EVLAN (first for QinQ).
+ * FlexiMD.5: VLAN2 - C-VLAN (second for QinQ).
+ */
+ protid_0 = ICE_PROT_EVLAN_O;
+ offset_0 = 0;
+ protid_1 = ICE_PROT_VLAN_O;
+ offset_1 = 0;
+ } else if (prof_id == ICE_RXDID_COMMS_AUX_IPV4) {
+ /* FlexiMD.4: IPHDR1 - IPv4 header word 4, "TTL" and
+ * "Protocol" fields.
+ * FlexiMD.5: IPHDR0 - IPv4 header word 0, "Ver",
+ * "Hdr Len" and "Type of Service" fields.
+ */
+ protid_0 = ICE_PROT_IPV4_OF_OR_S;
+ offset_0 = 8;
+ protid_1 = ICE_PROT_IPV4_OF_OR_S;
+ offset_1 = 0;
+ } else if (prof_id == ICE_RXDID_COMMS_AUX_IPV6) {
+ /* FlexiMD.4: IPHDR1 - IPv6 header word 3,
+ * "Next Header" and "Hop Limit" fields.
+ * FlexiMD.5: IPHDR0 - IPv6 header word 0,
+ * "Ver", "Traffic class" and high 4 bits of
+ * "Flow Label" fields.
+ */
+ protid_0 = ICE_PROT_IPV6_OF_OR_S;
+ offset_0 = 6;
+ protid_1 = ICE_PROT_IPV6_OF_OR_S;
+ offset_1 = 0;
+ } else if (prof_id == ICE_RXDID_COMMS_AUX_IPV6_FLOW) {
+ /* FlexiMD.4: IPHDR1 - IPv6 header word 1,
+ * 16 low bits of the "Flow Label" field.
+ * FlexiMD.5: IPHDR0 - IPv6 header word 0,
+ * "Ver", "Traffic class" and high 4 bits
+ * of "Flow Label" fields.
+ */
+ protid_0 = ICE_PROT_IPV6_OF_OR_S;
+ offset_0 = 2;
+ protid_1 = ICE_PROT_IPV6_OF_OR_S;
+ offset_1 = 0;
+ } else if (prof_id == ICE_RXDID_COMMS_AUX_TCP) {
+ /* FlexiMD.4: TCPHDR - TCP header word 6,
+ * "Data Offset" and "Flags" fields.
+ * FlexiMD.5: Reserved
+ */
+ protid_0 = ICE_PROT_TCP_IL;
+ offset_0 = 12;
+ protid_1 = ICE_PROT_ID_INVAL;
+ offset_1 = 0;
+ } else {
+ protid_0 = ICE_PROT_ID_INVAL;
+ offset_0 = 0;
+ protid_1 = ICE_PROT_ID_INVAL;
+ offset_1 = 0;
+ }
+ ICE_PROG_FLEX_ENTRY_EXTRACT(hw, prof_id,
+ protid_0, offset_0, 4);
+ ICE_PROG_FLEX_ENTRY_EXTRACT(hw, prof_id,
+ protid_1, offset_1, 5);
+
+ ice_init_flex_flags(hw, prof_id);
+ break;
default:
ice_debug(hw, ICE_DBG_INIT,
"Field init for profile ID %d not supported\n",
@@ -1001,6 +1086,12 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC);
ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC_2);
+ ice_init_flex_flds(hw, ICE_RXDID_COMMS_GENERIC);
+ ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_VLAN);
+ ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_IPV4);
+ ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_IPV6);
+ ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_IPV6_FLOW);
+ ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_TCP);
/* Obtain counter base index which would be used by flow director */
status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
if (status)
diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h
index 02c54e818..2cba6bc1e 100644
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -606,6 +606,12 @@ enum ice_rxdid {
ICE_RXDID_FLEX_NIC = 2,
ICE_RXDID_FLEX_NIC_2 = 6,
ICE_RXDID_HW = 7,
+ ICE_RXDID_COMMS_GENERIC = 16,
+ ICE_RXDID_COMMS_AUX_VLAN = 17,
+ ICE_RXDID_COMMS_AUX_IPV4 = 18,
+ ICE_RXDID_COMMS_AUX_IPV6 = 19,
+ ICE_RXDID_COMMS_AUX_IPV6_FLOW = 20,
+ ICE_RXDID_COMMS_AUX_TCP = 21,
ICE_RXDID_LAST = 63,
};
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 05/63] net/ice/base: store number of functions for the device
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (3 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 04/63] net/ice/base: add support to init RXDID descs fields Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 06/63] net/ice/base: add read PBA module function Qi Zhang
` (58 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Kevin Scott, Paul M Stillwell Jr
Store the number of functions the device has. This value can be
very useful when calculating how to best allocate global resources.
Signed-off-by: Kevin Scott <kevin.c.scott@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 6 +++++-
drivers/net/ice/base/ice_type.h | 1 +
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 58dd01ea1..fa97b792e 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -2114,6 +2114,10 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
ice_debug(hw, ICE_DBG_INIT,
"%s: valid functions = %d\n", prefix,
caps->valid_functions);
+
+ /* store func count for resource management purposes */
+ if (dev_p)
+ dev_p->num_funcs = ice_hweight32(number);
break;
case ICE_AQC_CAPS_VSI:
if (dev_p) {
@@ -2230,7 +2234,7 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
* physical ports; i.e. some features are not supported or function
* differently on devices with more than 4 ports.
*/
- if (caps && (ice_hweight32(caps->valid_functions) > 4)) {
+ if (hw->dev_caps.num_funcs > 4) {
/* Max 4 TCs per port */
caps->maxtc = 4;
ice_debug(hw, ICE_DBG_INIT,
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 2d010e643..88846e042 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -359,6 +359,7 @@ struct ice_hw_dev_caps {
struct ice_hw_common_caps common_cap;
u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
u32 num_flow_director_fltr; /* Number of FD filters available */
+ u32 num_funcs;
};
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 06/63] net/ice/base: add read PBA module function
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (4 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 05/63] net/ice/base: store number of functions for the device Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 07/63] net/ice/base: correct argument port info Qi Zhang
` (57 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Tarun Singh, Paul M Stillwell Jr
New support function added - ice_get_pfa_module_tlv(), the driver or
other modules can make use of this function to read the pfa area.
Signed-off-by: Tarun Singh <tarun.k.singh@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 66 +++++++++++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_common.h | 3 ++
2 files changed, 69 insertions(+)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index fa97b792e..0356537a4 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -1283,6 +1283,72 @@ enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
return ice_check_reset(hw);
}
+/**
+ * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA
+ * @hw: pointer to hardware structure
+ * @module_tlv: pointer to module TLV to return
+ * @module_tlv_len: pointer to module TLV length to return
+ * @module_type: module type requested
+ *
+ * Finds the requested sub module TLV type from the Preserved Field
+ * Area (PFA) and returns the TLV pointer and length. The caller can
+ * use these to read the variable length TLV value.
+ */
+enum ice_status
+ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
+ u16 module_type)
+{
+ enum ice_status status;
+ u16 pfa_len, pfa_ptr;
+ u16 next_tlv;
+
+ status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr);
+ if (status != ICE_SUCCESS) {
+ ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n");
+ return status;
+ }
+ status = ice_read_sr_word(hw, pfa_ptr, &pfa_len);
+ if (status != ICE_SUCCESS) {
+ ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n");
+ return status;
+ }
+ /* Starting with first TLV after PFA length, iterate through the list
+ * of TLVs to find the requested one.
+ */
+ next_tlv = pfa_ptr + 1;
+ while (next_tlv < pfa_ptr + pfa_len) {
+ u16 tlv_sub_module_type;
+ u16 tlv_len;
+
+ /* Read TLV type */
+ status = ice_read_sr_word(hw, next_tlv, &tlv_sub_module_type);
+ if (status != ICE_SUCCESS) {
+ ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV type.\n");
+ break;
+ }
+ /* Read TLV length */
+ status = ice_read_sr_word(hw, next_tlv + 1, &tlv_len);
+ if (status != ICE_SUCCESS) {
+ ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n");
+ break;
+ }
+ if (tlv_sub_module_type == module_type) {
+ if (tlv_len) {
+ *module_tlv = next_tlv;
+ *module_tlv_len = tlv_len;
+ return ICE_SUCCESS;
+ }
+ return ICE_ERR_INVAL_SIZE;
+ }
+ /* Check next TLV, i.e. current TLV pointer + length + 2 words
+ * (for current TLV's type and length)
+ */
+ next_tlv = next_tlv + tlv_len + 2;
+ }
+ /* Module does not exist */
+ return ICE_ERR_DOES_NOT_EXIST;
+}
+
/**
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index 009c052ca..c5170f705 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -21,6 +21,9 @@ enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw);
enum ice_status ice_init_hw(struct ice_hw *hw);
void ice_deinit_hw(struct ice_hw *hw);
+enum ice_status
+ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
+ u16 module_type);
enum ice_status ice_check_reset(struct ice_hw *hw);
enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req);
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 07/63] net/ice/base: correct argument port info
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (5 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 06/63] net/ice/base: add read PBA module function Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 08/63] net/ice/base: remove debug code Qi Zhang
` (56 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Tarun Singh, Paul M Stillwell Jr
correct argument pi(port_info) passed in function
ice_sched_get_first_node(), otherwise it will return the incorrect
node.
functions ice_sched_get_agg_node and ice_sched_cfg_sibl_node_prio:
change argument from hw to pi for it to align to correct port.
Moved saving tc node bw info from hardware structure(hw) to port info
structure(pi). This change allows multiple ports to save and replay
the information correctly.
Signed-off-by: Tarun Singh <tarun.k.singh@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 2 +-
drivers/net/ice/base/ice_common.h | 2 +-
drivers/net/ice/base/ice_sched.c | 70 ++++++++++++++++++++-------------------
drivers/net/ice/base/ice_sched.h | 4 +--
drivers/net/ice/base/ice_type.h | 2 +-
5 files changed, 41 insertions(+), 39 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 0356537a4..b4f0b964d 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -4158,7 +4158,7 @@ static enum ice_status ice_replay_pre_init(struct ice_hw *hw)
&sw->recp_list[i].filt_replay_rules);
ice_sched_replay_agg_vsi_preinit(hw);
- return ice_sched_replay_tc_node_bw(hw);
+ return ice_sched_replay_tc_node_bw(hw->port_info);
}
/**
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index c5170f705..4ecfa6b9b 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -184,7 +184,7 @@ enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle);
void ice_replay_post(struct ice_hw *hw);
void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw);
void ice_sched_replay_agg(struct ice_hw *hw);
-enum ice_status ice_sched_replay_tc_node_bw(struct ice_hw *hw);
+enum ice_status ice_sched_replay_tc_node_bw(struct ice_port_info *pi);
enum ice_status ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle);
enum ice_status
ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx);
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index 2d80af731..d16f256c9 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -1480,7 +1480,7 @@ ice_sched_get_vsi_node(struct ice_port_info *pi, struct ice_sched_node *tc_node,
/**
* ice_sched_get_agg_node - Get an aggregator node based on aggregator ID
- * @hw: pointer to the HW struct
+ * @pi: pointer to the port information structure
* @tc_node: pointer to the TC node
* @agg_id: aggregator ID
*
@@ -1488,14 +1488,17 @@ ice_sched_get_vsi_node(struct ice_port_info *pi, struct ice_sched_node *tc_node,
* a given TC branch
*/
static struct ice_sched_node *
-ice_sched_get_agg_node(struct ice_hw *hw, struct ice_sched_node *tc_node,
+ice_sched_get_agg_node(struct ice_port_info *pi, struct ice_sched_node *tc_node,
u32 agg_id)
{
struct ice_sched_node *node;
+ struct ice_hw *hw = pi->hw;
u8 agg_layer;
+ if (!hw)
+ return NULL;
agg_layer = ice_sched_get_agg_layer(hw);
- node = ice_sched_get_first_node(hw->port_info, tc_node, agg_layer);
+ node = ice_sched_get_first_node(pi, tc_node, agg_layer);
/* Check whether it already exists */
while (node) {
@@ -2251,7 +2254,7 @@ ice_sched_move_vsi_to_agg(struct ice_port_info *pi, u16 vsi_handle, u32 agg_id,
if (!tc_node)
return ICE_ERR_CFG;
- agg_node = ice_sched_get_agg_node(pi->hw, tc_node, agg_id);
+ agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id);
if (!agg_node)
return ICE_ERR_DOES_NOT_EXIST;
@@ -2388,7 +2391,7 @@ ice_sched_rm_agg_cfg(struct ice_port_info *pi, u32 agg_id, u8 tc)
if (!tc_node)
return ICE_ERR_CFG;
- agg_node = ice_sched_get_agg_node(hw, tc_node, agg_id);
+ agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id);
if (!agg_node)
return ICE_ERR_DOES_NOT_EXIST;
@@ -2497,7 +2500,7 @@ ice_sched_add_agg_cfg(struct ice_port_info *pi, u32 agg_id, u8 tc)
if (!tc_node)
return ICE_ERR_CFG;
- agg_node = ice_sched_get_agg_node(hw, tc_node, agg_id);
+ agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id);
/* Does Agg node already exist ? */
if (agg_node)
return status;
@@ -3445,7 +3448,6 @@ ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 num_qs, u32 *q_ids,
u8 *q_prio)
{
enum ice_status status = ICE_ERR_PARAM;
- struct ice_hw *hw = pi->hw;
u16 i;
ice_acquire_lock(&pi->sched_lock);
@@ -3460,7 +3462,7 @@ ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 num_qs, u32 *q_ids,
break;
}
/* Configure Priority */
- status = ice_sched_cfg_sibl_node_prio(hw, node, q_prio[i]);
+ status = ice_sched_cfg_sibl_node_prio(pi, node, q_prio[i]);
if (status)
break;
}
@@ -3508,7 +3510,7 @@ ice_cfg_agg_vsi_priority_per_tc(struct ice_port_info *pi, u32 agg_id,
if (!tc_node)
goto exit_agg_priority_per_tc;
- agg_node = ice_sched_get_agg_node(hw, tc_node, agg_id);
+ agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id);
if (!agg_node)
goto exit_agg_priority_per_tc;
@@ -3542,7 +3544,7 @@ ice_cfg_agg_vsi_priority_per_tc(struct ice_port_info *pi, u32 agg_id,
if (ice_sched_find_node_in_subtree(hw, agg_node, vsi_node)) {
/* Configure Priority */
- status = ice_sched_cfg_sibl_node_prio(hw, vsi_node,
+ status = ice_sched_cfg_sibl_node_prio(pi, vsi_node,
node_prio[i]);
if (status)
break;
@@ -3654,7 +3656,7 @@ ice_cfg_agg_bw_alloc(struct ice_port_info *pi, u32 agg_id, u8 ena_tcmap,
if (!tc_node)
continue;
- agg_node = ice_sched_get_agg_node(hw, tc_node, agg_id);
+ agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id);
if (!agg_node)
continue;
@@ -4453,19 +4455,17 @@ static enum ice_status
ice_sched_save_tc_node_bw(struct ice_port_info *pi, u8 tc,
enum ice_rl_type rl_type, u32 bw)
{
- struct ice_hw *hw = pi->hw;
-
if (tc >= ICE_MAX_TRAFFIC_CLASS)
return ICE_ERR_PARAM;
switch (rl_type) {
case ICE_MIN_BW:
- ice_set_clear_cir_bw(&hw->tc_node_bw_t_info[tc], bw);
+ ice_set_clear_cir_bw(&pi->tc_node_bw_t_info[tc], bw);
break;
case ICE_MAX_BW:
- ice_set_clear_eir_bw(&hw->tc_node_bw_t_info[tc], bw);
+ ice_set_clear_eir_bw(&pi->tc_node_bw_t_info[tc], bw);
break;
case ICE_SHARED_BW:
- ice_set_clear_shared_bw(&hw->tc_node_bw_t_info[tc], bw);
+ ice_set_clear_shared_bw(&pi->tc_node_bw_t_info[tc], bw);
break;
default:
return ICE_ERR_PARAM;
@@ -4552,17 +4552,15 @@ static enum ice_status
ice_sched_save_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc,
enum ice_rl_type rl_type, u16 bw_alloc)
{
- struct ice_hw *hw = pi->hw;
-
if (tc >= ICE_MAX_TRAFFIC_CLASS)
return ICE_ERR_PARAM;
switch (rl_type) {
case ICE_MIN_BW:
- ice_set_clear_cir_bw_alloc(&hw->tc_node_bw_t_info[tc],
+ ice_set_clear_cir_bw_alloc(&pi->tc_node_bw_t_info[tc],
bw_alloc);
break;
case ICE_MAX_BW:
- ice_set_clear_eir_bw_alloc(&hw->tc_node_bw_t_info[tc],
+ ice_set_clear_eir_bw_alloc(&pi->tc_node_bw_t_info[tc],
bw_alloc);
break;
default:
@@ -4710,7 +4708,7 @@ ice_sched_get_node_by_id_type(struct ice_port_info *pi, u32 id,
tc_node = ice_sched_get_tc_node(pi, tc);
if (tc_node)
- node = ice_sched_get_agg_node(pi->hw, tc_node, id);
+ node = ice_sched_get_agg_node(pi, tc_node, id);
break;
}
@@ -4921,7 +4919,7 @@ ice_sched_validate_agg_srl_node(struct ice_port_info *pi, u32 agg_id)
if (!tc_node)
continue;
- agg_node = ice_sched_get_agg_node(pi->hw, tc_node, agg_id);
+ agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id);
if (!agg_node)
continue;
/* SRL bandwidth layer selection */
@@ -4992,7 +4990,7 @@ ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw)
if (!tc_node)
continue;
- agg_node = ice_sched_get_agg_node(pi->hw, tc_node, agg_id);
+ agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id);
if (!agg_node)
continue;
@@ -5017,7 +5015,7 @@ ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw)
/**
* ice_sched_cfg_sibl_node_prio - configure node sibling priority
- * @hw: pointer to the HW struct
+ * @pi: port information structure
* @node: sched node to configure
* @priority: sibling priority
*
@@ -5025,13 +5023,16 @@ ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw)
* function needs to be called with scheduler lock held.
*/
enum ice_status
-ice_sched_cfg_sibl_node_prio(struct ice_hw *hw, struct ice_sched_node *node,
- u8 priority)
+ice_sched_cfg_sibl_node_prio(struct ice_port_info *pi,
+ struct ice_sched_node *node, u8 priority)
{
struct ice_aqc_txsched_elem_data buf;
struct ice_aqc_txsched_elem *data;
+ struct ice_hw *hw = pi->hw;
enum ice_status status;
+ if (!hw)
+ return ICE_ERR_PARAM;
buf = node->info;
data = &buf.data;
data->valid_sections |= ICE_AQC_ELEM_VALID_GENERIC;
@@ -5198,7 +5199,7 @@ ice_sched_replay_agg_bw(struct ice_hw *hw, struct ice_sched_agg_info *agg_info)
status = ICE_ERR_PARAM;
break;
}
- agg_node = ice_sched_get_agg_node(hw, tc_node,
+ agg_node = ice_sched_get_agg_node(hw->port_info, tc_node,
agg_info->agg_id);
if (!agg_node) {
status = ICE_ERR_PARAM;
@@ -5310,26 +5311,27 @@ void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw)
/**
* ice_sched_replay_tc_node_bw - replay TC node(s) BW
- * @hw: pointer to the HW struct
+ * @pi: port information structure
*
- * This function replay TC nodes. The caller needs to hold the scheduler lock.
+ * This function replay TC nodes.
*/
enum ice_status
-ice_sched_replay_tc_node_bw(struct ice_hw *hw)
+ice_sched_replay_tc_node_bw(struct ice_port_info *pi)
{
- struct ice_port_info *pi = hw->port_info;
enum ice_status status = ICE_SUCCESS;
u8 tc;
+ if (!pi->hw)
+ return ICE_ERR_PARAM;
ice_acquire_lock(&pi->sched_lock);
ice_for_each_traffic_class(tc) {
struct ice_sched_node *tc_node;
- tc_node = ice_sched_get_tc_node(hw->port_info, tc);
+ tc_node = ice_sched_get_tc_node(pi, tc);
if (!tc_node)
continue; /* TC not present */
- status = ice_sched_replay_node_bw(hw, tc_node,
- &hw->tc_node_bw_t_info[tc]);
+ status = ice_sched_replay_node_bw(pi->hw, tc_node,
+ &pi->tc_node_bw_t_info[tc]);
if (status)
break;
}
diff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h
index 38f8f93d2..932ae075f 100644
--- a/drivers/net/ice/base/ice_sched.h
+++ b/drivers/net/ice/base/ice_sched.h
@@ -183,6 +183,6 @@ ice_sched_set_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle,
enum ice_status
ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw);
enum ice_status
-ice_sched_cfg_sibl_node_prio(struct ice_hw *hw, struct ice_sched_node *node,
- u8 priority);
+ice_sched_cfg_sibl_node_prio(struct ice_port_info *pi,
+ struct ice_sched_node *node, u8 priority);
#endif /* _ICE_SCHED_H_ */
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 88846e042..d8cb8eecd 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -674,6 +674,7 @@ struct ice_port_info {
sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
/* List contain profile ID(s) and other params per layer */
struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
+ struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
/* DCBX info */
struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
@@ -742,7 +743,6 @@ struct ice_hw {
u8 sw_entry_point_layer;
u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */
- struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
u8 evb_veb; /* true for VEB, false for VEPA */
u8 reset_ongoing; /* true if HW is in reset, false otherwise */
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 08/63] net/ice/base: remove debug code
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (6 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 07/63] net/ice/base: correct argument port info Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 09/63] net/ice/base: add SFF EEPROM AQ Command Qi Zhang
` (55 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang; +Cc: dev, xiaolong.ye, Qi Zhang, Paul M Stillwell Jr
Remove firmware logging debug code.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_adminq_cmd.h | 88 --------------
drivers/net/ice/base/ice_common.c | 223 ----------------------------------
drivers/net/ice/base/ice_common.h | 1 -
drivers/net/ice/base/ice_type.h | 20 ---
4 files changed, 332 deletions(-)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index b5faa5bf6..9e5853cca 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -2176,87 +2176,6 @@ struct ice_aqc_event_lan_overflow {
-/* Configure Firmware Logging Command (indirect 0xFF09)
- * Logging Information Read Response (indirect 0xFF10)
- * Note: The 0xFF10 command has no input parameters.
- */
-struct ice_aqc_fw_logging {
- u8 log_ctrl;
-#define ICE_AQC_FW_LOG_AQ_EN BIT(0)
-#define ICE_AQC_FW_LOG_UART_EN BIT(1)
- u8 rsvd0;
- u8 log_ctrl_valid; /* Not used by 0xFF10 Response */
-#define ICE_AQC_FW_LOG_AQ_VALID BIT(0)
-#define ICE_AQC_FW_LOG_UART_VALID BIT(1)
- u8 rsvd1[5];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-
-enum ice_aqc_fw_logging_mod {
- ICE_AQC_FW_LOG_ID_GENERAL = 0,
- ICE_AQC_FW_LOG_ID_CTRL,
- ICE_AQC_FW_LOG_ID_LINK,
- ICE_AQC_FW_LOG_ID_LINK_TOPO,
- ICE_AQC_FW_LOG_ID_DNL,
- ICE_AQC_FW_LOG_ID_I2C,
- ICE_AQC_FW_LOG_ID_SDP,
- ICE_AQC_FW_LOG_ID_MDIO,
- ICE_AQC_FW_LOG_ID_ADMINQ,
- ICE_AQC_FW_LOG_ID_HDMA,
- ICE_AQC_FW_LOG_ID_LLDP,
- ICE_AQC_FW_LOG_ID_DCBX,
- ICE_AQC_FW_LOG_ID_DCB,
- ICE_AQC_FW_LOG_ID_NETPROXY,
- ICE_AQC_FW_LOG_ID_NVM,
- ICE_AQC_FW_LOG_ID_AUTH,
- ICE_AQC_FW_LOG_ID_VPD,
- ICE_AQC_FW_LOG_ID_IOSF,
- ICE_AQC_FW_LOG_ID_PARSER,
- ICE_AQC_FW_LOG_ID_SW,
- ICE_AQC_FW_LOG_ID_SCHEDULER,
- ICE_AQC_FW_LOG_ID_TXQ,
- ICE_AQC_FW_LOG_ID_RSVD,
- ICE_AQC_FW_LOG_ID_POST,
- ICE_AQC_FW_LOG_ID_WATCHDOG,
- ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
- ICE_AQC_FW_LOG_ID_MNG,
- ICE_AQC_FW_LOG_ID_SYNCE,
- ICE_AQC_FW_LOG_ID_MAX,
-};
-
-/* This is the buffer for both of the logging commands.
- * The entry array size depends on the datalen parameter in the descriptor.
- * There will be a total of datalen / 2 entries.
- */
-struct ice_aqc_fw_logging_data {
- __le16 entry[1];
-#define ICE_AQC_FW_LOG_ID_S 0
-#define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S)
-
-#define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */
-#define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */
-
-#define ICE_AQC_FW_LOG_EN_S 12
-#define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S)
-#define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */
-#define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */
-#define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */
-#define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */
-};
-
-
-/* Get/Clear FW Log (indirect 0xFF11) */
-struct ice_aqc_get_clear_fw_log {
- u8 flags;
-#define ICE_AQC_FW_LOG_CLEAR BIT(0)
-#define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1)
- u8 rsvd1[7];
- __le32 addr_high;
- __le32 addr_low;
-};
-
/**
* struct ice_aq_desc - Admin Queue (AQ) descriptor
@@ -2337,8 +2256,6 @@ struct ice_aq_desc {
struct ice_aqc_get_vsi_resp get_vsi_resp;
struct ice_aqc_download_pkg download_pkg;
struct ice_aqc_get_pkg_info_list get_pkg_info_list;
- struct ice_aqc_fw_logging fw_logging;
- struct ice_aqc_get_clear_fw_log get_clear_fw_log;
struct ice_aqc_set_mac_lb set_mac_lb;
struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
struct ice_aqc_get_res_alloc get_res;
@@ -2558,11 +2475,6 @@ enum ice_adminq_opc {
/* Standalone Commands/Events */
ice_aqc_opc_event_lan_overflow = 0x1001,
-
- /* debug commands */
- ice_aqc_opc_fw_logging = 0xFF09,
- ice_aqc_opc_fw_logging_info = 0xFF10,
- ice_aqc_opc_get_clear_fw_log = 0xFF11
};
#endif /* _ICE_ADMINQ_CMD_H_ */
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index b4f0b964d..43c06948f 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -653,223 +653,6 @@ static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
ice_free(hw, sw);
}
-#define ICE_FW_LOG_DESC_SIZE(n) (sizeof(struct ice_aqc_fw_logging_data) + \
- (((n) - 1) * sizeof(((struct ice_aqc_fw_logging_data *)0)->entry)))
-#define ICE_FW_LOG_DESC_SIZE_MAX \
- ICE_FW_LOG_DESC_SIZE(ICE_AQC_FW_LOG_ID_MAX)
-
-/**
- * ice_get_fw_log_cfg - get FW logging configuration
- * @hw: pointer to the HW struct
- */
-static enum ice_status ice_get_fw_log_cfg(struct ice_hw *hw)
-{
- struct ice_aqc_fw_logging_data *config;
- struct ice_aq_desc desc;
- enum ice_status status;
- u16 size;
-
- size = ICE_FW_LOG_DESC_SIZE_MAX;
- config = (struct ice_aqc_fw_logging_data *)ice_malloc(hw, size);
- if (!config)
- return ICE_ERR_NO_MEMORY;
-
- ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info);
-
- desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_BUF);
- desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
-
- status = ice_aq_send_cmd(hw, &desc, config, size, NULL);
- if (!status) {
- u16 i;
-
- /* Save fw logging information into the HW structure */
- for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
- u16 v, m, flgs;
-
- v = LE16_TO_CPU(config->entry[i]);
- m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
- flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S;
-
- if (m < ICE_AQC_FW_LOG_ID_MAX)
- hw->fw_log.evnts[m].cur = flgs;
- }
- }
-
- ice_free(hw, config);
-
- return status;
-}
-
-/**
- * ice_cfg_fw_log - configure FW logging
- * @hw: pointer to the HW struct
- * @enable: enable certain FW logging events if true, disable all if false
- *
- * This function enables/disables the FW logging via Rx CQ events and a UART
- * port based on predetermined configurations. FW logging via the Rx CQ can be
- * enabled/disabled for individual PF's. However, FW logging via the UART can
- * only be enabled/disabled for all PFs on the same device.
- *
- * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in
- * hw->fw_log need to be set accordingly, e.g. based on user-provided input,
- * before initializing the device.
- *
- * When re/configuring FW logging, callers need to update the "cfg" elements of
- * the hw->fw_log.evnts array with the desired logging event configurations for
- * modules of interest. When disabling FW logging completely, the callers can
- * just pass false in the "enable" parameter. On completion, the function will
- * update the "cur" element of the hw->fw_log.evnts array with the resulting
- * logging event configurations of the modules that are being re/configured. FW
- * logging modules that are not part of a reconfiguration operation retain their
- * previous states.
- *
- * Before resetting the device, it is recommended that the driver disables FW
- * logging before shutting down the control queue. When disabling FW logging
- * ("enable" = false), the latest configurations of FW logging events stored in
- * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after
- * a device reset.
- *
- * When enabling FW logging to emit log messages via the Rx CQ during the
- * device's initialization phase, a mechanism alternative to interrupt handlers
- * needs to be used to extract FW log messages from the Rx CQ periodically and
- * to prevent the Rx CQ from being full and stalling other types of control
- * messages from FW to SW. Interrupts are typically disabled during the device's
- * initialization phase.
- */
-static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable)
-{
- struct ice_aqc_fw_logging_data *data = NULL;
- struct ice_aqc_fw_logging *cmd;
- enum ice_status status = ICE_SUCCESS;
- u16 i, chgs = 0, len = 0;
- struct ice_aq_desc desc;
- u8 actv_evnts = 0;
- void *buf = NULL;
-
- if (!hw->fw_log.cq_en && !hw->fw_log.uart_en)
- return ICE_SUCCESS;
-
- /* Disable FW logging only when the control queue is still responsive */
- if (!enable &&
- (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq)))
- return ICE_SUCCESS;
-
- /* Get current FW log settings */
- status = ice_get_fw_log_cfg(hw);
- if (status)
- return status;
-
- ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging);
- cmd = &desc.params.fw_logging;
-
- /* Indicate which controls are valid */
- if (hw->fw_log.cq_en)
- cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID;
-
- if (hw->fw_log.uart_en)
- cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID;
-
- if (enable) {
- /* Fill in an array of entries with FW logging modules and
- * logging events being reconfigured.
- */
- for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
- u16 val;
-
- /* Keep track of enabled event types */
- actv_evnts |= hw->fw_log.evnts[i].cfg;
-
- if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur)
- continue;
-
- if (!data) {
- data = (struct ice_aqc_fw_logging_data *)
- ice_malloc(hw,
- ICE_FW_LOG_DESC_SIZE_MAX);
- if (!data)
- return ICE_ERR_NO_MEMORY;
- }
-
- val = i << ICE_AQC_FW_LOG_ID_S;
- val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S;
- data->entry[chgs++] = CPU_TO_LE16(val);
- }
-
- /* Only enable FW logging if at least one module is specified.
- * If FW logging is currently enabled but all modules are not
- * enabled to emit log messages, disable FW logging altogether.
- */
- if (actv_evnts) {
- /* Leave if there is effectively no change */
- if (!chgs)
- goto out;
-
- if (hw->fw_log.cq_en)
- cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN;
-
- if (hw->fw_log.uart_en)
- cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN;
-
- buf = data;
- len = ICE_FW_LOG_DESC_SIZE(chgs);
- desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
- }
- }
-
- status = ice_aq_send_cmd(hw, &desc, buf, len, NULL);
- if (!status) {
- /* Update the current configuration to reflect events enabled.
- * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW
- * logging mode is enabled for the device. They do not reflect
- * actual modules being enabled to emit log messages. So, their
- * values remain unchanged even when all modules are disabled.
- */
- u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX;
-
- hw->fw_log.actv_evnts = actv_evnts;
- for (i = 0; i < cnt; i++) {
- u16 v, m;
-
- if (!enable) {
- /* When disabling all FW logging events as part
- * of device's de-initialization, the original
- * configurations are retained, and can be used
- * to reconfigure FW logging later if the device
- * is re-initialized.
- */
- hw->fw_log.evnts[i].cur = 0;
- continue;
- }
-
- v = LE16_TO_CPU(data->entry[i]);
- m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
- hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg;
- }
- }
-
-out:
- if (data)
- ice_free(hw, data);
-
- return status;
-}
-
-/**
- * ice_output_fw_log
- * @hw: pointer to the HW struct
- * @desc: pointer to the AQ message descriptor
- * @buf: pointer to the buffer accompanying the AQ message
- *
- * Formats a FW Log message and outputs it via the standard driver logs.
- */
-void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf)
-{
- ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n");
- ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf,
- LE16_TO_CPU(desc->datalen));
- ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n");
-}
/**
* ice_get_itr_intrl_gran - determine int/intrl granularity
@@ -979,10 +762,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
ice_print_rollback_msg(hw);
- /* Enable FW logging. Not fatal if this fails. */
- status = ice_cfg_fw_log(hw, true);
- if (status)
- ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n");
status = ice_clear_pf_cfg(hw);
if (status)
@@ -1136,8 +915,6 @@ void ice_deinit_hw(struct ice_hw *hw)
hw->port_info = NULL;
}
- /* Attempt to disable FW logging before shutting down control queues */
- ice_cfg_fw_log(hw, false);
ice_destroy_all_ctrlq(hw);
/* Clear VSI contexts if not already cleared */
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index 4ecfa6b9b..4e44c2f13 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -194,7 +194,6 @@ enum ice_status
ice_cfg_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc,
enum ice_rl_type rl_type, u8 bw_alloc);
enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes);
-void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf);
void
ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
u64 *prev_stat, u64 *cur_stat);
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index d8cb8eecd..7194cb9ec 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -690,25 +690,6 @@ struct ice_switch_info {
struct ice_sw_recipe *recp_list;
};
-/* FW logging configuration */
-struct ice_fw_log_evnt {
- u8 cfg : 4; /* New event enables to configure */
- u8 cur : 4; /* Current/active event enables */
-};
-
-struct ice_fw_log_cfg {
- u8 cq_en : 1; /* FW logging is enabled via the control queue */
- u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */
- u8 actv_evnts; /* Cumulation of currently enabled log events */
-
-#define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S)
-#define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S)
-#define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S)
-#define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S)
-#define ICE_FW_LOG_EVNT_ALL (ICE_FW_LOG_EVNT_INFO | ICE_FW_LOG_EVNT_INIT | \
- ICE_FW_LOG_EVNT_FLOW | ICE_FW_LOG_EVNT_ERR)
- struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX];
-};
/* Port hardware description */
struct ice_hw {
@@ -767,7 +748,6 @@ struct ice_hw {
u8 fw_patch; /* firmware patch version */
u32 fw_build; /* firmware build number */
- struct ice_fw_log_cfg fw_log;
/* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
* register. Used for determining the itr/intrl granularity during
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 09/63] net/ice/base: add SFF EEPROM AQ Command
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (7 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 08/63] net/ice/base: remove debug code Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 10/63] net/ice/base: improve debug print message Qi Zhang
` (54 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Scott W Taylor, Paul M Stillwell Jr
read/write module eeprom on i2c bus.
Signed-off-by: Scott W Taylor <scott.w.taylor@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_adminq_cmd.h | 29 ++++++++++++++++++++++
drivers/net/ice/base/ice_common.c | 46 +++++++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_common.h | 5 +++-
3 files changed, 79 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index 9e5853cca..4de69dd7a 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1660,6 +1660,33 @@ struct ice_aqc_set_port_id_led {
+/* Read/Write SFF EEPROM command (indirect 0x06EE) */
+struct ice_aqc_sff_eeprom {
+ u8 lport_num;
+ u8 lport_num_valid;
+#define ICE_AQC_SFF_PORT_NUM_VALID BIT(0)
+ __le16 i2c_bus_addr;
+#define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F
+#define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF
+#define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10)
+#define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0
+#define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M
+#define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11
+#define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S)
+#define ICE_AQC_SFF_NO_PAGE_CHANGE 0
+#define ICE_AQC_SFF_SET_23_ON_MISMATCH 1
+#define ICE_AQC_SFF_SET_22_ON_MISMATCH 2
+#define ICE_AQC_SFF_IS_WRITE BIT(15)
+ __le16 i2c_mem_addr;
+ __le16 eeprom_page;
+#define ICE_AQC_SFF_EEPROM_BANK_S 0
+#define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)
+#define ICE_AQC_SFF_EEPROM_PAGE_S 8
+#define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)
+ __le32 addr_high;
+ __le32 addr_low;
+};
+
/* NVM Read command (indirect 0x0701)
* NVM Erase commands (direct 0x0702)
* NVM Update commands (indirect 0x0703)
@@ -2218,6 +2245,7 @@ struct ice_aq_desc {
struct ice_aqc_get_phy_caps get_phy;
struct ice_aqc_set_phy_cfg set_phy;
struct ice_aqc_restart_an restart_an;
+ struct ice_aqc_sff_eeprom read_write_sff_param;
struct ice_aqc_set_port_id_led set_port_id_led;
struct ice_aqc_get_sw_cfg get_sw_conf;
struct ice_aqc_sw_rules sw_rules;
@@ -2431,6 +2459,7 @@ enum ice_adminq_opc {
ice_aqc_opc_set_port_option = 0x06EB,
ice_aqc_opc_set_gpio = 0x06EC,
ice_aqc_opc_get_gpio = 0x06ED,
+ ice_aqc_opc_sff_eeprom = 0x06EE,
/* NVM commands */
ice_aqc_opc_nvm_read = 0x0701,
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 43c06948f..cd94995f4 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -2860,6 +2860,52 @@ ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
}
/**
+ * ice_aq_sff_eeprom
+ * @hw: pointer to the HW struct
+ * @lport: bits [7:0] = logical port, bit [8] = logical port valid
+ * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
+ * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
+ * @page: QSFP page
+ * @set_page: set or ignore the page
+ * @data: pointer to data buffer to be read/written to the I2C device.
+ * @length: 1-16 for read, 1 for write.
+ * @write: 0 read, 1 for write.
+ * @cd: pointer to command details structure or NULL
+ *
+ * Read/Write SFF EEPROM (0x06EE)
+ */
+enum ice_status
+ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
+ u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
+ bool write, struct ice_sq_cd *cd)
+{
+ struct ice_aqc_sff_eeprom *cmd;
+ struct ice_aq_desc desc;
+ enum ice_status status;
+
+ if (!data || (mem_addr & 0xff00))
+ return ICE_ERR_PARAM;
+
+ ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
+ cmd = &desc.params.read_write_sff_param;
+ desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF);
+ cmd->lport_num = (u8)(lport & 0xff);
+ cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
+ cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) &
+ ICE_AQC_SFF_I2CBUS_7BIT_M) |
+ ((set_page <<
+ ICE_AQC_SFF_SET_EEPROM_PAGE_S) &
+ ICE_AQC_SFF_SET_EEPROM_PAGE_M));
+ cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff);
+ cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);
+ if (write)
+ cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE);
+
+ status = ice_aq_send_cmd(hw, &desc, data, length, cd);
+ return status;
+}
+
+/**
* __ice_aq_get_set_rss_lut
* @hw: pointer to the hardware structure
* @vsi_id: VSI FW index
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index 4e44c2f13..d865021bf 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -163,7 +163,10 @@ ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd);
enum ice_status
ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
struct ice_sq_cd *cd);
-
+enum ice_status
+ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
+ u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
+ bool write, struct ice_sq_cd *cd);
enum ice_status
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 10/63] net/ice/base: improve debug print message
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (8 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 09/63] net/ice/base: add SFF EEPROM AQ Command Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 11/63] net/ice/base: add capabilities when in safe mode Qi Zhang
` (53 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang; +Cc: dev, xiaolong.ye, Qi Zhang, Paul M Stillwell Jr
Improve debug print message.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 41 +++++++++++++++++++------------------
drivers/net/ice/base/ice_controlq.c | 10 +++++----
2 files changed, 27 insertions(+), 24 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index cd94995f4..ae7837149 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -1955,7 +1955,7 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
case ICE_AQC_CAPS_VALID_FUNCTIONS:
caps->valid_functions = number;
ice_debug(hw, ICE_DBG_INIT,
- "%s: valid functions = %d\n", prefix,
+ "%s: valid_functions (bitmap) = %d\n", prefix,
caps->valid_functions);
/* store func count for resource management purposes */
@@ -1966,17 +1966,17 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
if (dev_p) {
dev_p->num_vsi_allocd_to_host = number;
ice_debug(hw, ICE_DBG_INIT,
- "%s: num VSI alloc to host = %d\n",
+ "%s: num_vsi_allocd_to_host = %d\n",
prefix,
dev_p->num_vsi_allocd_to_host);
} else if (func_p) {
func_p->guar_num_vsi =
ice_get_num_per_func(hw, ICE_MAX_VSI);
ice_debug(hw, ICE_DBG_INIT,
- "%s: num guaranteed VSI (fw) = %d\n",
+ "%s: guar_num_vsi (fw) = %d\n",
prefix, number);
ice_debug(hw, ICE_DBG_INIT,
- "%s: num guaranteed VSI = %d\n",
+ "%s: guar_num_vsi = %d\n",
prefix, func_p->guar_num_vsi);
}
break;
@@ -1985,51 +1985,51 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
caps->active_tc_bitmap = logical_id;
caps->maxtc = phys_id;
ice_debug(hw, ICE_DBG_INIT,
- "%s: DCB = %d\n", prefix, caps->dcb);
+ "%s: dcb = %d\n", prefix, caps->dcb);
ice_debug(hw, ICE_DBG_INIT,
- "%s: active TC bitmap = %d\n", prefix,
+ "%s: active_tc_bitmap = %d\n", prefix,
caps->active_tc_bitmap);
ice_debug(hw, ICE_DBG_INIT,
- "%s: TC max = %d\n", prefix, caps->maxtc);
+ "%s: maxtc = %d\n", prefix, caps->maxtc);
break;
case ICE_AQC_CAPS_RSS:
caps->rss_table_size = number;
caps->rss_table_entry_width = logical_id;
ice_debug(hw, ICE_DBG_INIT,
- "%s: RSS table size = %d\n", prefix,
+ "%s: rss_table_size = %d\n", prefix,
caps->rss_table_size);
ice_debug(hw, ICE_DBG_INIT,
- "%s: RSS table width = %d\n", prefix,
+ "%s: rss_table_entry_width = %d\n", prefix,
caps->rss_table_entry_width);
break;
case ICE_AQC_CAPS_RXQS:
caps->num_rxq = number;
caps->rxq_first_id = phys_id;
ice_debug(hw, ICE_DBG_INIT,
- "%s: num Rx queues = %d\n", prefix,
+ "%s: num_rxq = %d\n", prefix,
caps->num_rxq);
ice_debug(hw, ICE_DBG_INIT,
- "%s: Rx first queue ID = %d\n", prefix,
+ "%s: rxq_first_id = %d\n", prefix,
caps->rxq_first_id);
break;
case ICE_AQC_CAPS_TXQS:
caps->num_txq = number;
caps->txq_first_id = phys_id;
ice_debug(hw, ICE_DBG_INIT,
- "%s: num Tx queues = %d\n", prefix,
+ "%s: num_txq = %d\n", prefix,
caps->num_txq);
ice_debug(hw, ICE_DBG_INIT,
- "%s: Tx first queue ID = %d\n", prefix,
+ "%s: txq_first_id = %d\n", prefix,
caps->txq_first_id);
break;
case ICE_AQC_CAPS_MSIX:
caps->num_msix_vectors = number;
caps->msix_vector_first_id = phys_id;
ice_debug(hw, ICE_DBG_INIT,
- "%s: MSIX vector count = %d\n", prefix,
+ "%s: num_msix_vectors = %d\n", prefix,
caps->num_msix_vectors);
ice_debug(hw, ICE_DBG_INIT,
- "%s: MSIX first vector index = %d\n", prefix,
+ "%s: msix_vector_first_id = %d\n", prefix,
caps->msix_vector_first_id);
break;
case ICE_AQC_CAPS_FD:
@@ -2039,7 +2039,8 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
if (dev_p) {
dev_p->num_flow_director_fltr = number;
ice_debug(hw, ICE_DBG_INIT,
- "%s: num FD filters = %d\n", prefix,
+ "%s: num_flow_director_fltr = %d\n",
+ prefix,
dev_p->num_flow_director_fltr);
}
if (func_p) {
@@ -2052,17 +2053,17 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
GLQF_FD_SIZE_FD_BSIZE_S;
func_p->fd_fltr_best_effort = val;
ice_debug(hw, ICE_DBG_INIT,
- "%s: num guaranteed FD filters = %d\n",
+ "%s: fd_fltr_guar = %d\n",
prefix, func_p->fd_fltr_guar);
ice_debug(hw, ICE_DBG_INIT,
- "%s: num best effort FD filters = %d\n",
+ "%s: fd_fltr_best_effort = %d\n",
prefix, func_p->fd_fltr_best_effort);
}
break;
}
case ICE_AQC_CAPS_MAX_MTU:
caps->max_mtu = number;
- ice_debug(hw, ICE_DBG_INIT, "%s: max MTU = %d\n",
+ ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
prefix, caps->max_mtu);
break;
default:
@@ -2081,7 +2082,7 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
/* Max 4 TCs per port */
caps->maxtc = 4;
ice_debug(hw, ICE_DBG_INIT,
- "%s: TC max = %d (based on #ports)\n", prefix,
+ "%s: maxtc = %d (based on #ports)\n", prefix,
caps->maxtc);
}
}
diff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c
index 80322e70d..8070bb9a7 100644
--- a/drivers/net/ice/base/ice_controlq.c
+++ b/drivers/net/ice/base/ice_controlq.c
@@ -968,7 +968,7 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
}
/* Debug desc and buffer */
- ice_debug(hw, ICE_DBG_AQ_MSG,
+ ice_debug(hw, ICE_DBG_AQ_DESC,
"ATQ: Control Send queue desc and buffer:\n");
ice_debug_cq(hw, (void *)desc_on_ring, buf, buf_size);
@@ -1008,7 +1008,8 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
retval = LE16_TO_CPU(desc->retval);
if (retval) {
ice_debug(hw, ICE_DBG_AQ_MSG,
- "Control Send Queue command completed with error 0x%x\n",
+ "Control Send Queue command 0x%04X completed with error 0x%X\n",
+ LE16_TO_CPU(desc->opcode),
retval);
/* strip off FW internal code */
@@ -1113,7 +1114,8 @@ ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
if (flags & ICE_AQ_FLAG_ERR) {
ret_code = ICE_ERR_AQ_ERROR;
ice_debug(hw, ICE_DBG_AQ_MSG,
- "Control Receive Queue Event received with error 0x%x\n",
+ "Control Receive Queue Event 0x%04X received with error 0x%X\n",
+ LE16_TO_CPU(desc->opcode),
cq->rq_last_status);
}
ice_memcpy(&e->desc, desc, sizeof(e->desc), ICE_DMA_TO_NONDMA);
@@ -1123,7 +1125,7 @@ ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
ice_memcpy(e->msg_buf, cq->rq.r.rq_bi[desc_idx].va,
e->msg_len, ICE_DMA_TO_NONDMA);
- ice_debug(hw, ICE_DBG_AQ_MSG, "ARQ: desc and buffer:\n");
+ ice_debug(hw, ICE_DBG_AQ_DESC, "ARQ: desc and buffer:\n");
ice_debug_cq(hw, (void *)desc, e->msg_buf,
cq->rq_buf_size);
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 11/63] net/ice/base: add capabilities when in safe mode
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (9 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 10/63] net/ice/base: improve debug print message Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 12/63] net/ice/base: add helper functions for PHY caching Qi Zhang
` (52 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Anirudh Venkataramanan, Paul M Stillwell Jr
The dynamic device personalization (DDP) file download onto the device
can fail, and when this happens the driver has to transition to "safe
mode" where only basic functionality is possible.
The device though doesn't understand safe mode, and so the opcodes to
discover device/function capabilities (0x000A and 0x000B) return all
the capabilities of the device, which includes capabilities that the
driver cannot support when in safe mode.
The initialization flows in the driver are based on the capabilities
information (obtained by the driver with the above mentioned opcodes).
To reuse the same initialization flows in safe mode, it becomes
necessary for the driver to override the currently stored capabilities
information with safe mode capabilities. This is done by a new function
introduced in this patch - ice_set_safe_mode_caps.
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 64 +++++++++++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_common.h | 2 ++
2 files changed, 66 insertions(+)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index ae7837149..9907d9dae 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -2172,6 +2172,70 @@ ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
}
/**
+ * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
+ * @hw: pointer to the hardware structure
+ */
+void ice_set_safe_mode_caps(struct ice_hw *hw)
+{
+ struct ice_hw_func_caps *func_caps = &hw->func_caps;
+ struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
+ u32 valid_func, rxq_first_id, txq_first_id;
+ u32 msix_vector_first_id, max_mtu;
+ u32 num_funcs;
+
+ /* cache some func_caps values that should be restored after memset */
+ valid_func = func_caps->common_cap.valid_functions;
+ txq_first_id = func_caps->common_cap.txq_first_id;
+ rxq_first_id = func_caps->common_cap.rxq_first_id;
+ msix_vector_first_id = func_caps->common_cap.msix_vector_first_id;
+ max_mtu = func_caps->common_cap.max_mtu;
+
+ /* unset func capabilities */
+ memset(func_caps, 0, sizeof(*func_caps));
+
+ /* restore cached values */
+ func_caps->common_cap.valid_functions = valid_func;
+ func_caps->common_cap.txq_first_id = txq_first_id;
+ func_caps->common_cap.rxq_first_id = rxq_first_id;
+ func_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
+ func_caps->common_cap.max_mtu = max_mtu;
+
+ /* one Tx and one Rx queue in safe mode */
+ func_caps->common_cap.num_rxq = 1;
+ func_caps->common_cap.num_txq = 1;
+
+ /* two MSIX vectors, one for traffic and one for misc causes */
+ func_caps->common_cap.num_msix_vectors = 2;
+ func_caps->guar_num_vsi = 1;
+
+ /* cache some dev_caps values that should be restored after memset */
+ valid_func = dev_caps->common_cap.valid_functions;
+ txq_first_id = dev_caps->common_cap.txq_first_id;
+ rxq_first_id = dev_caps->common_cap.rxq_first_id;
+ msix_vector_first_id = dev_caps->common_cap.msix_vector_first_id;
+ max_mtu = dev_caps->common_cap.max_mtu;
+ num_funcs = dev_caps->num_funcs;
+
+ /* unset dev capabilities */
+ memset(dev_caps, 0, sizeof(*dev_caps));
+
+ /* restore cached values */
+ dev_caps->common_cap.valid_functions = valid_func;
+ dev_caps->common_cap.txq_first_id = txq_first_id;
+ dev_caps->common_cap.rxq_first_id = rxq_first_id;
+ dev_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
+ dev_caps->common_cap.max_mtu = max_mtu;
+ dev_caps->num_funcs = num_funcs;
+
+ /* one Tx and one Rx queue per function in safe mode */
+ dev_caps->common_cap.num_rxq = num_funcs;
+ dev_caps->common_cap.num_txq = num_funcs;
+
+ /* two MSIX vectors per function */
+ dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
+}
+
+/**
* ice_get_caps - get info about the HW
* @hw: pointer to the hardware structure
*/
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index d865021bf..df1fecec5 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -61,6 +61,8 @@ void ice_clear_pxe_mode(struct ice_hw *hw);
enum ice_status ice_get_caps(struct ice_hw *hw);
+void ice_set_safe_mode_caps(struct ice_hw *hw);
+
/* Define a macro that will align a pointer to point to the next memory address
* that falls on the given power of 2 (i.e., 2, 4, 8, 16, 32, 64...). For
* example, given the variable pointer = 0x1006, then after the following call:
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 12/63] net/ice/base: add helper functions for PHY caching
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (10 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 11/63] net/ice/base: add capabilities when in safe mode Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 13/63] net/ice/base: add support for reading REPC statistics Qi Zhang
` (51 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Tony Nguyen, Paul M Stillwell Jr
Add additional functions to aide in caching PHY
configuration. In order to cache the initial modes,
we need to determine the operating mode based on
capabilities. Add helper functions for flow control
and FEC to take a set of capabilities and return the
operating mode matching those capabilities. Also add
a helper function to determine whether a PHY capability
matches a PHY configuration.
Introduce a mask for valid link speeds and unwrap
ice_copy_caps_to_cfg() for more builds so that we can utilize
it in more places.
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_adminq_cmd.h | 1 +
drivers/net/ice/base/ice_common.c | 83 +++++++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_common.h | 9 +++-
3 files changed, 91 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index 4de69dd7a..cc42180ea 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1598,6 +1598,7 @@ struct ice_aqc_get_link_status_data {
#define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
#define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
__le16 link_speed;
+#define ICE_AQ_LINK_SPEED_M 0x7FF
#define ICE_AQ_LINK_SPEED_10MB BIT(0)
#define ICE_AQ_LINK_SPEED_100MB BIT(1)
#define ICE_AQ_LINK_SPEED_1000MB BIT(2)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 9907d9dae..6b28f6230 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -2613,6 +2613,53 @@ ice_cache_phy_user_req(struct ice_port_info *pi,
}
/**
+ * ice_caps_to_fc_mode
+ * @caps: PHY capabilities
+ *
+ * Convert PHY FC capabilities to ice FC mode
+ */
+enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
+{
+ if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
+ caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
+ return ICE_FC_FULL;
+
+ if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
+ return ICE_FC_TX_PAUSE;
+
+ if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
+ return ICE_FC_RX_PAUSE;
+
+ return ICE_FC_NONE;
+}
+
+/**
+ * ice_caps_to_fec_mode
+ * @caps: PHY capabilities
+ * @fec_options: Link FEC options
+ *
+ * Convert PHY FEC capabilities to ice FEC mode
+ */
+enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
+{
+ if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
+ return ICE_FEC_AUTO;
+
+ if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
+ ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
+ ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
+ ICE_AQC_PHY_FEC_25G_KR_REQ))
+ return ICE_FEC_BASER;
+
+ if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
+ ICE_AQC_PHY_FEC_25G_RS_544_REQ |
+ ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
+ return ICE_FEC_RS;
+
+ return ICE_FEC_NONE;
+}
+
+/**
* ice_set_fc
* @pi: port information structure
* @aq_failures: pointer to status code, specific to ice_set_fc routine
@@ -2719,6 +2766,42 @@ ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
}
/**
+ * ice_phy_caps_equals_cfg
+ * @phy_caps: PHY capabilities
+ * @phy_cfg: PHY configuration
+ *
+ * Helper function to determine if PHY capabilities matches PHY
+ * configuration
+ */
+bool
+ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
+ struct ice_aqc_set_phy_cfg_data *phy_cfg)
+{
+ u8 caps_mask, cfg_mask;
+
+ if (!phy_caps || !phy_cfg)
+ return false;
+
+ /* These bits are not common between capabilities and configuration.
+ * Do not use them to determine equality.
+ */
+ caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
+ ICE_AQC_PHY_EN_MOD_QUAL);
+ cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
+
+ if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
+ phy_caps->phy_type_high != phy_cfg->phy_type_high ||
+ ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
+ phy_caps->low_power_ctrl != phy_cfg->low_power_ctrl ||
+ phy_caps->eee_cap != phy_cfg->eee_cap ||
+ phy_caps->eeer_value != phy_cfg->eeer_value ||
+ phy_caps->link_fec_options != phy_cfg->link_fec_opt)
+ return false;
+
+ return true;
+}
+
+/**
* ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
* @caps: PHY ability structure to copy date from
* @cfg: PHY configuration structure to copy data to
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index df1fecec5..a8104dfa2 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -139,14 +139,19 @@ enum ice_status ice_clear_pf_cfg(struct ice_hw *hw);
enum ice_status
ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd);
+enum ice_fc_mode ice_caps_to_fc_mode(u8 caps);
+enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options);
enum ice_status
ice_set_fc(struct ice_port_info *pi, u8 *aq_failures,
bool ena_auto_link_update);
-void
-ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec);
+bool
+ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps,
+ struct ice_aqc_set_phy_cfg_data *cfg);
void
ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,
struct ice_aqc_set_phy_cfg_data *cfg);
+void
+ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec);
enum ice_status
ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
struct ice_sq_cd *cd);
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 13/63] net/ice/base: add support for reading REPC statistics
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (11 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 12/63] net/ice/base: add helper functions for PHY caching Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 14/63] net/ice/base: adjust DCB INIT for SW mode Qi Zhang
` (50 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Jacob Keller, Paul M Stillwell Jr
The GLV_REPC register contains statistics for tracking received packets
that are discarded due to certain errors.
This register behaves differently from some of the other related
statistics registers in two ways. First, it contains two 16bit
statistics, and thus cannot be read as a 32bit or 40bit statistic.
Second, the two stats do not roll over, but instead cap at 0xFFFF.
Add a new ice_stat_update_repc function which will read the register and
increment the appropriate statistics in the ice_eth_stats structure.
Since the register does not roll over, make use of the "Write Clear"
behavior, and write to the register to reset it every time we read it.
Add extra space for the two statistics that are counted by this
register, rx_errors, and rx_no_desc.
For now, wrap the new function and stats counters in !LINUX_SUPPORT.
This can later be removed if and when the Linux driver implements
support for reading the statistics.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 51 +++++++++++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_common.h | 3 +++
drivers/net/ice/base/ice_type.h | 2 ++
3 files changed, 56 insertions(+)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 6b28f6230..36434ee42 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -4253,6 +4253,57 @@ ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
*prev_stat = new_data;
}
+/**
+ * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values
+ * @hw: ptr to the hardware info
+ * @vsi_handle: VSI handle
+ * @prev_stat_loaded: bool to specify if the previous stat values are loaded
+ * @cur_stats: ptr to current stats structure
+ *
+ * The GLV_REPC statistic register actually tracks two 16bit statistics, and
+ * thus cannot be read using the normal ice_stat_update32 function.
+ *
+ * Read the GLV_REPC register associated with the given VSI, and update the
+ * rx_no_desc and rx_error values in the ice_eth_stats structure.
+ *
+ * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be
+ * cleared each time it's read.
+ *
+ * Note that the GLV_RDPC register also counts the causes that would trigger
+ * GLV_REPC. However, it does not give the finer grained detail about why the
+ * packets are being dropped. The GLV_REPC values can be used to distinguish
+ * whether Rx packets are dropped due to errors or due to no available
+ * descriptors.
+ */
+void
+ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
+ struct ice_eth_stats *cur_stats)
+{
+ u16 vsi_num, no_desc, error_cnt;
+ u32 repc;
+
+ if (!ice_is_vsi_valid(hw, vsi_handle))
+ return;
+
+ vsi_num = ice_get_hw_vsi_num(hw, vsi_handle);
+
+ /* If we haven't loaded stats yet, just clear the current value */
+ if (!prev_stat_loaded) {
+ wr32(hw, GLV_REPC(vsi_num), 0);
+ return;
+ }
+
+ repc = rd32(hw, GLV_REPC(vsi_num));
+ no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S;
+ error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S;
+
+ /* Clear the count by writing to the stats register */
+ wr32(hw, GLV_REPC(vsi_num), 0);
+
+ cur_stats->rx_no_desc += no_desc;
+ cur_stats->rx_errors += error_cnt;
+}
+
/**
* ice_sched_query_elem - query element information from HW
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index a8104dfa2..1fd256a42 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -211,6 +211,9 @@ void
ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
u64 *prev_stat, u64 *cur_stat);
void
+ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
+ struct ice_eth_stats *cur_stats);
+void
ice_get_nvm_version(struct ice_hw *hw, u8 *oem_ver, u16 *oem_build,
u8 *oem_patch, u8 *ver_hi, u8 *ver_lo);
enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw);
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 7194cb9ec..0dba94a53 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -833,6 +833,8 @@ struct ice_eth_stats {
u64 tx_broadcast; /* bptc */
u64 tx_discards; /* tdpc */
u64 tx_errors; /* tepc */
+ u64 rx_no_desc; /* repc */
+ u64 rx_errors; /* repc */
};
#define ICE_MAX_UP 8
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 14/63] net/ice/base: adjust DCB INIT for SW mode
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (12 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 13/63] net/ice/base: add support for reading REPC statistics Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 15/63] net/ice/base: add NVM pkg flag Qi Zhang
` (49 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dave Ertman, Paul M Stillwell Jr
Adjust ice_init_dcb to set the is_sw_lldp boolean
in the case where the FW has been detected to be
in an untenable state such that the driver
should forcibly make sure it is off.
This will ensure that the FW is in a known state.
Signed-off-by: Dave Ertman <david.m.ertman@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_dcb.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ice/base/ice_dcb.c b/drivers/net/ice/base/ice_dcb.c
index a6fbedd18..7048dbd02 100644
--- a/drivers/net/ice/base/ice_dcb.c
+++ b/drivers/net/ice/base/ice_dcb.c
@@ -966,9 +966,9 @@ enum ice_status ice_init_dcb(struct ice_hw *hw, bool enable_mib_change)
pi->dcbx_status == ICE_DCBX_STATUS_NOT_STARTED) {
/* Get current DCBX configuration */
ret = ice_get_dcb_cfg(pi);
- pi->is_sw_lldp = (hw->adminq.sq_last_status == ICE_AQ_RC_EPERM);
if (ret)
return ret;
+ pi->is_sw_lldp = false;
} else if (pi->dcbx_status == ICE_DCBX_STATUS_DIS) {
return ICE_ERR_NOT_READY;
}
@@ -976,8 +976,8 @@ enum ice_status ice_init_dcb(struct ice_hw *hw, bool enable_mib_change)
/* Configure the LLDP MIB change event */
if (enable_mib_change) {
ret = ice_aq_cfg_lldp_mib_change(hw, true, NULL);
- if (!ret)
- pi->is_sw_lldp = false;
+ if (ret)
+ pi->is_sw_lldp = true;
}
return ret;
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 15/63] net/ice/base: add NVM pkg flag
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (13 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 14/63] net/ice/base: adjust DCB INIT for SW mode Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 16/63] net/ice/base: move VSI to VSI group Qi Zhang
` (48 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Ashish Shah, Paul M Stillwell Jr
Add flag for case where active package has been loaded from NVM.
Signed-off-by: Ashish Shah <ashish.n.shah@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flex_pipe.c | 1 +
drivers/net/ice/base/ice_type.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index afb867877..5a5dbff5b 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -1144,6 +1144,7 @@ static enum ice_status ice_get_pkg_info(struct ice_hw *hw)
pkg_info->pkg_info[i].name,
sizeof(hw->active_pkg_name),
ICE_NONDMA_TO_NONDMA);
+ hw->active_pkg_in_nvm = pkg_info->pkg_info[i].is_in_nvm;
}
if (pkg_info->pkg_info[i].is_active_at_boot)
flags[place++] = 'B';
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 0dba94a53..79d7bb1dd 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -773,6 +773,7 @@ struct ice_hw {
/* Active package version (currently active) */
struct ice_pkg_ver active_pkg_ver;
u8 active_pkg_name[ICE_PKG_NAME_SIZE];
+ u8 active_pkg_in_nvm;
/* Driver's package ver - (from the Metadata seg) */
struct ice_pkg_ver pkg_ver;
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 16/63] net/ice/base: move VSI to VSI group
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (14 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 15/63] net/ice/base: add NVM pkg flag Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 17/63] net/ice/base: enable masking for RSS and FD field vectors Qi Zhang
` (47 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Vignesh Sridhar, Paul M Stillwell Jr
Add function to add a VSI to a given VSIG and update package with this
entry. The usual flow in XLT management would iterate through all
characteristics of the input VSI and create a new VSIG and TCAMs till a
matching characteristic is found. When a match is found the VSI is moved
into a matching VSIG and entries are collapsed, leading to added package
update calls. This function serves as an optimization if we know
beforehand that the input VSI has characteristics same as VSI configured
previously added to a VSIG. This is particularly useful for VF VSIs
which are all usually programmed with the same configurations.
Signed-off-by: Vignesh Sridhar <vignesh.sridhar@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flex_pipe.c | 41 ++++++++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_flex_pipe.h | 2 ++
drivers/net/ice/base/ice_flow.c | 28 ++++++++++++++++++++++++
drivers/net/ice/base/ice_flow.h | 4 +++-
4 files changed, 74 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index 5a5dbff5b..00e1ec7bd 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -4772,6 +4772,47 @@ ice_find_prof_vsig(struct ice_hw *hw, enum ice_block blk, u64 hdl, u16 *vsig)
}
/**
+ * ice_add_vsi_flow - add VSI flow
+ * @hw: pointer to the HW struct
+ * @blk: hardware block
+ * @vsi: input VSI
+ * @vsig: target VSIG to include the input VSI
+ *
+ * Calling this function will add the VSI to a given VSIG and
+ * update the HW tables accordingly. This call can be used to
+ * add multiple VSIs to a VSIG if we know beforehand that those
+ * VSIs have the same characteristics of the VSIG. This will
+ * save time in generating a new VSIG and TCAMs till a match is
+ * found and subsequent rollback when a matching VSIG is found.
+ */
+enum ice_status
+ice_add_vsi_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u16 vsig)
+{
+ struct ice_chs_chg *tmp, *del;
+ struct LIST_HEAD_TYPE chg;
+ enum ice_status status;
+
+ /* if target VSIG is default the move is invalid */
+ if ((vsig & ICE_VSIG_IDX_M) == ICE_DEFAULT_VSIG)
+ return ICE_ERR_PARAM;
+
+ INIT_LIST_HEAD(&chg);
+
+ /* move VSI to the VSIG that matches */
+ status = ice_move_vsi(hw, blk, vsi, vsig, &chg);
+ /* update hardware if success */
+ if (!status)
+ status = ice_upd_prof_hw(hw, blk, &chg);
+
+ LIST_FOR_EACH_ENTRY_SAFE(del, tmp, &chg, ice_chs_chg, list_entry) {
+ LIST_DEL(&del->list_entry);
+ ice_free(hw, del);
+ }
+
+ return status;
+}
+
+/**
* ice_add_prof_id_flow - add profile flow
* @hw: pointer to the HW struct
* @blk: hardware block
diff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h
index 2801e1b50..f01dfbb98 100644
--- a/drivers/net/ice/base/ice_flex_pipe.h
+++ b/drivers/net/ice/base/ice_flex_pipe.h
@@ -50,6 +50,8 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],
struct ice_prof_map *
ice_search_prof_id(struct ice_hw *hw, enum ice_block blk, u64 id);
enum ice_status
+ice_add_vsi_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u16 vsig);
+enum ice_status
ice_add_prof_id_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u64 hdl);
enum ice_status
ice_rem_prof_id_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u64 hdl);
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 36d31fa13..fb9041b3e 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -1112,6 +1112,34 @@ ice_flow_rem_prof_sync(struct ice_hw *hw, enum ice_block blk,
}
/**
+ * ice_flow_assoc_vsig_vsi - associate a VSI with VSIG
+ * @hw: pointer to the hardware structure
+ * @blk: classification stage
+ * @vsi_handle: software VSI handle
+ * @vsig: target VSI group
+ *
+ * Assumption: the caller has already verified that the VSI to
+ * be added has the same characteristics as the VSIG and will
+ * thereby have access to all resources added to that VSIG.
+ */
+enum ice_status
+ice_flow_assoc_vsig_vsi(struct ice_hw *hw, enum ice_block blk, u16 vsi_handle,
+ u16 vsig)
+{
+ enum ice_status status;
+
+ if (!ice_is_vsi_valid(hw, vsi_handle) || blk >= ICE_BLK_COUNT)
+ return ICE_ERR_PARAM;
+
+ ice_acquire_lock(&hw->fl_profs_locks[blk]);
+ status = ice_add_vsi_flow(hw, blk, ice_get_hw_vsi_num(hw, vsi_handle),
+ vsig);
+ ice_release_lock(&hw->fl_profs_locks[blk]);
+
+ return status;
+}
+
+/**
* ice_flow_assoc_prof - associate a VSI with a flow profile
* @hw: pointer to the hardware structure
* @blk: classification stage
diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h
index c6442dc14..3a0fd23c4 100644
--- a/drivers/net/ice/base/ice_flow.h
+++ b/drivers/net/ice/base/ice_flow.h
@@ -317,7 +317,9 @@ ice_flow_add_prof(struct ice_hw *hw, enum ice_block blk, enum ice_flow_dir dir,
struct ice_flow_prof **prof);
enum ice_status
ice_flow_rem_prof(struct ice_hw *hw, enum ice_block blk, u64 prof_id);
-
+enum ice_status
+ice_flow_assoc_vsig_vsi(struct ice_hw *hw, enum ice_block blk, u16 vsi_handle,
+ u16 vsig);
enum ice_status
ice_flow_get_hw_prof(struct ice_hw *hw, enum ice_block blk, u64 prof_id,
u8 *hw_prof);
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 17/63] net/ice/base: enable masking for RSS and FD field vectors
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (15 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 16/63] net/ice/base: move VSI to VSI group Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 18/63] net/ice/base: resolve static analysis issues Qi Zhang
` (46 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
Allow masking per word field on RSS and FD field vectors.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flex_pipe.c | 540 ++++++++++++++++++++++++++++++++++-
drivers/net/ice/base/ice_flex_pipe.h | 5 +
drivers/net/ice/base/ice_flex_type.h | 17 ++
drivers/net/ice/base/ice_flow.c | 21 +-
4 files changed, 578 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index 00e1ec7bd..29888df76 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -2500,6 +2500,102 @@ ice_vsig_add_mv_vsi(struct ice_hw *hw, enum ice_block blk, u16 vsi, u16 vsig)
}
/**
+ * ice_prof_has_mask_idx - determine if profile index masking is identical
+ * @hw: pointer to the hardware structure
+ * @blk: HW block
+ * @prof: profile to check
+ * @idx: profile index to check
+ * @masks: masks to match
+ */
+static bool
+ice_prof_has_mask_idx(struct ice_hw *hw, enum ice_block blk, u8 prof, u16 idx,
+ u16 mask)
+{
+ bool expect_no_mask = false;
+ bool found = false;
+ bool match = false;
+ u16 i;
+
+ /* If mask is 0x0000 or 0xffff, then there is no masking */
+ if (mask == 0 || mask == 0xffff)
+ expect_no_mask = true;
+
+ /* Scan the enabled masks on this profile, for the specified idx */
+ for (i = 0; i < ICE_PROFILE_MASK_COUNT; i++)
+ if (hw->blk[blk].es.mask_ena[prof] & BIT(i))
+ if (hw->blk[blk].masks.masks[i].in_use &&
+ hw->blk[blk].masks.masks[i].idx == idx) {
+ found = true;
+ if (hw->blk[blk].masks.masks[i].mask == mask)
+ match = true;
+ break;
+ }
+
+ if (expect_no_mask) {
+ if (found)
+ return false;
+ } else {
+ if (!match)
+ return false;
+ }
+
+ return true;
+}
+
+/**
+ * ice_prof_has_mask - determine if profile masking is identical
+ * @hw: pointer to the hardware structure
+ * @blk: HW block
+ * @prof: profile to check
+ * @masks: masks to match
+ */
+static bool
+ice_prof_has_mask(struct ice_hw *hw, enum ice_block blk, u8 prof, u16 *masks)
+{
+ u16 i;
+
+ /* es->mask_ena[prof] will have the mask */
+ for (i = 0; i < hw->blk[blk].es.fvw; i++)
+ if (!ice_prof_has_mask_idx(hw, blk, prof, i, masks[i]))
+ return false;
+
+ return true;
+}
+
+/**
+ * ice_find_prof_id_with_mask - find profile ID for a given field vector
+ * @hw: pointer to the hardware structure
+ * @blk: HW block
+ * @fv: field vector to search for
+ * @masks: masks for fv
+ * @prof_id: receives the profile ID
+ */
+static enum ice_status
+ice_find_prof_id_with_mask(struct ice_hw *hw, enum ice_block blk,
+ struct ice_fv_word *fv, u16 *masks, u8 *prof_id)
+{
+ struct ice_es *es = &hw->blk[blk].es;
+ u16 i;
+
+ for (i = 0; i < es->count; i++) {
+ u16 off = i * es->fvw;
+ u16 j;
+
+ if (memcmp(&es->t[off], fv, es->fvw * sizeof(*fv)))
+ continue;
+
+ /* check if masks settings are the same for this profile */
+ if (!ice_prof_has_mask(hw, blk, i, masks))
+ continue;
+
+ *prof_id = i;
+ return ICE_SUCCESS;
+ }
+
+ return ICE_ERR_DOES_NOT_EXIST;
+}
+
+/**
* ice_find_prof_id - find profile ID for a given field vector
* @hw: pointer to the hardware structure
* @blk: HW block
@@ -2687,6 +2783,334 @@ ice_prof_inc_ref(struct ice_hw *hw, enum ice_block blk, u8 prof_id)
}
/**
+ * ice_write_prof_mask_reg - write profile mask register
+ * @hw: pointer to the HW struct
+ * @blk: hardware block
+ * @mask_idx: mask index
+ * @idx: index of the FV which will use the mask
+ * @mask: the 16-bit mask
+ */
+static void
+ice_write_prof_mask_reg(struct ice_hw *hw, enum ice_block blk, u16 mask_idx,
+ u16 idx, u16 mask)
+{
+ u32 offset;
+ u32 val;
+
+ switch (blk) {
+ case ICE_BLK_RSS:
+ offset = GLQF_HMASK(mask_idx);
+ val = (idx << GLQF_HMASK_MSK_INDEX_S) &
+ GLQF_HMASK_MSK_INDEX_M;
+ val |= (mask << GLQF_HMASK_MASK_S) & GLQF_HMASK_MASK_M;
+ break;
+ case ICE_BLK_FD:
+ offset = GLQF_FDMASK(mask_idx);
+ val = (idx << GLQF_FDMASK_MSK_INDEX_S) &
+ GLQF_FDMASK_MSK_INDEX_M;
+ val |= (mask << GLQF_FDMASK_MASK_S) &
+ GLQF_FDMASK_MASK_M;
+ break;
+ default:
+ ice_debug(hw, ICE_DBG_PKG, "No profile masks for block %d\n",
+ blk);
+ return;
+ }
+
+ wr32(hw, offset, val);
+ ice_debug(hw, ICE_DBG_PKG, "write mask, blk %d (%d): %x = %x\n",
+ blk, idx, offset, val);
+}
+
+/**
+ * ice_write_prof_mask_enable_res - write profile mask enable register
+ * @hw: pointer to the HW struct
+ * @blk: hardware block
+ * @prof_id: profile id
+ * @enable_mask: enable mask
+ */
+static void
+ice_write_prof_mask_enable_res(struct ice_hw *hw, enum ice_block blk,
+ u16 prof_id, u32 enable_mask)
+{
+ u32 offset;
+
+ switch (blk) {
+ case ICE_BLK_RSS:
+ offset = GLQF_HMASK_SEL(prof_id);
+ break;
+ case ICE_BLK_FD:
+ offset = GLQF_FDMASK_SEL(prof_id);
+ break;
+ default:
+ ice_debug(hw, ICE_DBG_PKG, "No profile masks for block %d\n",
+ blk);
+ return;
+ }
+
+ wr32(hw, offset, enable_mask);
+ ice_debug(hw, ICE_DBG_PKG, "write mask enable, blk %d (%d): %x = %x\n",
+ blk, prof_id, offset, enable_mask);
+}
+
+/**
+ * ice_init_prof_masks - initial prof masks
+ * @hw: pointer to the HW struct
+ * @blk: hardware block
+ */
+static void ice_init_prof_masks(struct ice_hw *hw, enum ice_block blk)
+{
+#define MAX_NUM_PORTS 8
+ u16 num_ports = MAX_NUM_PORTS;
+ u16 i;
+
+ ice_init_lock(&hw->blk[blk].masks.lock);
+
+ hw->blk[blk].masks.count = ICE_PROFILE_MASK_COUNT / num_ports;
+ hw->blk[blk].masks.first = hw->pf_id * hw->blk[blk].masks.count;
+
+ ice_memset(hw->blk[blk].masks.masks, 0,
+ sizeof(hw->blk[blk].masks.masks), ICE_NONDMA_MEM);
+
+ for (i = hw->blk[blk].masks.first;
+ i < hw->blk[blk].masks.first + hw->blk[blk].masks.count; i++)
+ ice_write_prof_mask_reg(hw, blk, i, 0, 0);
+}
+
+/**
+ * ice_init_all_prof_masks - initial all prof masks
+ * @hw: pointer to the HW struct
+ */
+void ice_init_all_prof_masks(struct ice_hw *hw)
+{
+ ice_init_prof_masks(hw, ICE_BLK_RSS);
+ ice_init_prof_masks(hw, ICE_BLK_FD);
+}
+
+/**
+ * ice_alloc_prof_mask - allocate profile mask
+ * @hw: pointer to the HW struct
+ * @blk: hardware block
+ * @idx: index of FV which will use the mask
+ * @mask: the 16-bit mask
+ * @mask_idx: variable to receive the mask index
+ */
+static enum ice_status
+ice_alloc_prof_mask(struct ice_hw *hw, enum ice_block blk, u16 idx, u16 mask,
+ u16 *mask_idx)
+{
+ bool found_unused = false, found_copy = false;
+ enum ice_status status = ICE_ERR_MAX_LIMIT;
+ u16 unused_idx = 0, copy_idx = 0;
+ u16 i;
+
+ if (blk != ICE_BLK_RSS && blk != ICE_BLK_FD)
+ return ICE_ERR_PARAM;
+
+ ice_acquire_lock(&hw->blk[blk].masks.lock);
+
+ for (i = hw->blk[blk].masks.first;
+ i < hw->blk[blk].masks.first + hw->blk[blk].masks.count; i++)
+ if (hw->blk[blk].masks.masks[i].in_use) {
+ /* if mask is in use and it exactly duplicates the
+ * desired mask and index, then in can be reused
+ */
+ if (hw->blk[blk].masks.masks[i].mask == mask &&
+ hw->blk[blk].masks.masks[i].idx == idx) {
+ found_copy = true;
+ copy_idx = i;
+ break;
+ }
+ } else {
+ /* save off unused index, but keep searching in case
+ * there is an exact match later on
+ */
+ if (!found_unused) {
+ found_unused = true;
+ unused_idx = i;
+ }
+ }
+
+ if (found_copy)
+ i = copy_idx;
+ else if (found_unused)
+ i = unused_idx;
+ else
+ goto err_ice_alloc_prof_mask;
+
+ /* update mask for a new entry */
+ if (found_unused) {
+ hw->blk[blk].masks.masks[i].in_use = true;
+ hw->blk[blk].masks.masks[i].mask = mask;
+ hw->blk[blk].masks.masks[i].idx = idx;
+ hw->blk[blk].masks.masks[i].ref = 0;
+ ice_write_prof_mask_reg(hw, blk, i, idx, mask);
+ }
+
+ hw->blk[blk].masks.masks[i].ref++;
+ *mask_idx = i;
+ status = ICE_SUCCESS;
+
+err_ice_alloc_prof_mask:
+ ice_release_lock(&hw->blk[blk].masks.lock);
+
+ return status;
+}
+
+/**
+ * ice_free_prof_mask - free profile mask
+ * @hw: pointer to the HW struct
+ * @blk: hardware block
+ * @mask_idx: index of mask
+ */
+static enum ice_status
+ice_free_prof_mask(struct ice_hw *hw, enum ice_block blk, u16 mask_idx)
+{
+ if (blk != ICE_BLK_RSS && blk != ICE_BLK_FD)
+ return ICE_ERR_PARAM;
+
+ if (!(mask_idx >= hw->blk[blk].masks.first &&
+ mask_idx < hw->blk[blk].masks.first + hw->blk[blk].masks.count))
+ return ICE_ERR_DOES_NOT_EXIST;
+
+ ice_acquire_lock(&hw->blk[blk].masks.lock);
+
+ if (!hw->blk[blk].masks.masks[mask_idx].in_use)
+ goto exit_ice_free_prof_mask;
+
+ if (hw->blk[blk].masks.masks[mask_idx].ref > 1) {
+ hw->blk[blk].masks.masks[mask_idx].ref--;
+ goto exit_ice_free_prof_mask;
+ }
+
+ /* remove mask */
+ hw->blk[blk].masks.masks[mask_idx].in_use = false;
+ hw->blk[blk].masks.masks[mask_idx].mask = 0;
+ hw->blk[blk].masks.masks[mask_idx].idx = 0;
+
+ /* update mask as unused entry */
+ ice_debug(hw, ICE_DBG_PKG, "Free mask, blk %d, mask %d", blk, mask_idx);
+ ice_write_prof_mask_reg(hw, blk, mask_idx, 0, 0);
+
+exit_ice_free_prof_mask:
+ ice_release_lock(&hw->blk[blk].masks.lock);
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_free_prof_masks - free all profile masks for a profile
+ * @hw: pointer to the HW struct
+ * @blk: hardware block
+ * @prof_id: profile id
+ */
+static enum ice_status
+ice_free_prof_masks(struct ice_hw *hw, enum ice_block blk, u16 prof_id)
+{
+ u32 mask_bm;
+ u16 i;
+
+ if (blk != ICE_BLK_RSS && blk != ICE_BLK_FD)
+ return ICE_ERR_PARAM;
+
+ mask_bm = hw->blk[blk].es.mask_ena[prof_id];
+ for (i = 0; i < BITS_PER_BYTE * sizeof(mask_bm); i++)
+ if (mask_bm & BIT(i))
+ ice_free_prof_mask(hw, blk, i);
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_shutdown_prof_masks - releases lock for masking
+ * @hw: pointer to the HW struct
+ * @blk: hardware block
+ *
+ * This should be called before unloading the driver
+ */
+static void ice_shutdown_prof_masks(struct ice_hw *hw, enum ice_block blk)
+{
+ u16 i;
+
+ ice_acquire_lock(&hw->blk[blk].masks.lock);
+
+ for (i = hw->blk[blk].masks.first;
+ i < hw->blk[blk].masks.first + hw->blk[blk].masks.count; i++) {
+ ice_write_prof_mask_reg(hw, blk, i, 0, 0);
+
+ hw->blk[blk].masks.masks[i].in_use = false;
+ hw->blk[blk].masks.masks[i].idx = 0;
+ hw->blk[blk].masks.masks[i].mask = 0;
+ }
+
+ ice_release_lock(&hw->blk[blk].masks.lock);
+ ice_destroy_lock(&hw->blk[blk].masks.lock);
+}
+
+/**
+ * ice_shutdown_all_prof_masks - releases all locks for masking
+ * @hw: pointer to the HW struct
+ * @blk: hardware block
+ *
+ * This should be called before unloading the driver
+ */
+void ice_shutdown_all_prof_masks(struct ice_hw *hw)
+{
+ ice_shutdown_prof_masks(hw, ICE_BLK_RSS);
+ ice_shutdown_prof_masks(hw, ICE_BLK_FD);
+}
+
+/**
+ * ice_update_prof_masking - set registers according to masking
+ * @hw: pointer to the HW struct
+ * @blk: hardware block
+ * @prof_id: profile id
+ * @es: field vector
+ * @masks: masks
+ */
+static enum ice_status
+ice_update_prof_masking(struct ice_hw *hw, enum ice_block blk, u16 prof_id,
+ struct ice_fv_word *es, u16 *masks)
+{
+ bool err = false;
+ u32 ena_mask = 0;
+ u16 idx;
+ u16 i;
+
+ /* Only support FD and RSS masking, otherwise nothing to be done */
+ if (blk != ICE_BLK_RSS && blk != ICE_BLK_FD)
+ return ICE_SUCCESS;
+
+ for (i = 0; i < hw->blk[blk].es.fvw; i++)
+ if (masks[i] && masks[i] != 0xFFFF) {
+ if (!ice_alloc_prof_mask(hw, blk, i, masks[i], &idx)) {
+ ena_mask |= BIT(idx);
+ } else {
+ /* not enough bitmaps */
+ err = true;
+ break;
+ }
+ }
+
+ if (err) {
+ /* free any bitmaps we have allocated */
+ for (i = 0; i < BITS_PER_BYTE * sizeof(ena_mask); i++)
+ if (ena_mask & BIT(i))
+ ice_free_prof_mask(hw, blk, i);
+
+ return ICE_ERR_OUT_OF_RANGE;
+ }
+
+ /* enable the masks for this profile */
+ ice_write_prof_mask_enable_res(hw, blk, prof_id, ena_mask);
+
+ /* store enabled masks with profile so that they can be freed later */
+ hw->blk[blk].es.mask_ena[prof_id] = ena_mask;
+
+ return ICE_SUCCESS;
+}
+
+/**
* ice_write_es - write an extraction sequence to hardware
* @hw: pointer to the HW struct
* @blk: the block in which to write the extraction sequence
@@ -2725,6 +3149,7 @@ ice_prof_dec_ref(struct ice_hw *hw, enum ice_block blk, u8 prof_id)
if (hw->blk[blk].es.ref_count[prof_id] > 0) {
if (!--hw->blk[blk].es.ref_count[prof_id]) {
ice_write_es(hw, blk, prof_id, NULL);
+ ice_free_prof_masks(hw, blk, prof_id);
return ice_free_prof_id(hw, blk, prof_id);
}
}
@@ -3089,6 +3514,7 @@ void ice_free_hw_tbls(struct ice_hw *hw)
ice_free(hw, hw->blk[i].es.t);
ice_free(hw, hw->blk[i].es.ref_count);
ice_free(hw, hw->blk[i].es.written);
+ ice_free(hw, hw->blk[i].es.mask_ena);
}
LIST_FOR_EACH_ENTRY_SAFE(r, rt, &hw->rss_list_head,
@@ -3097,6 +3523,7 @@ void ice_free_hw_tbls(struct ice_hw *hw)
ice_free(hw, r);
}
ice_destroy_lock(&hw->rss_locks);
+ ice_shutdown_all_prof_masks(hw);
ice_memset(hw->blk, 0, sizeof(hw->blk), ICE_NONDMA_MEM);
}
@@ -3121,6 +3548,7 @@ enum ice_status ice_init_hw_tbls(struct ice_hw *hw)
ice_init_lock(&hw->rss_locks);
INIT_LIST_HEAD(&hw->rss_list_head);
+ ice_init_all_prof_masks(hw);
for (i = 0; i < ICE_BLK_COUNT; i++) {
struct ice_prof_redir *prof_redir = &hw->blk[i].prof_redir;
struct ice_prof_tcam *prof = &hw->blk[i].prof;
@@ -3212,7 +3640,8 @@ enum ice_status ice_init_hw_tbls(struct ice_hw *hw)
es->written = (u8 *)
ice_calloc(hw, es->count, sizeof(*es->written));
-
+ es->mask_ena = (u32 *)
+ ice_calloc(hw, es->count, sizeof(*es->mask_ena));
if (!es->ref_count)
goto err;
}
@@ -3854,6 +4283,115 @@ ice_update_fd_swap(struct ice_hw *hw, u16 prof_id, struct ice_fv_word *es)
}
/**
+ * ice_add_prof_with_mask - add profile
+ * @hw: pointer to the HW struct
+ * @blk: hardware block
+ * @id: profile tracking ID
+ * @ptypes: array of bitmaps indicating ptypes (ICE_FLOW_PTYPE_MAX bits)
+ * @es: extraction sequence (length of array is determined by the block)
+ * @masks: extraction sequence (length of array is determined by the block)
+ *
+ * This function registers a profile, which matches a set of PTYPES with a
+ * particular extraction sequence. While the hardware profile is allocated
+ * it will not be written until the first call to ice_add_flow that specifies
+ * the ID value used here.
+ */
+enum ice_status
+ice_add_prof_with_mask(struct ice_hw *hw, enum ice_block blk, u64 id,
+ u8 ptypes[], struct ice_fv_word *es, u16 *masks)
+{
+ u32 bytes = DIVIDE_AND_ROUND_UP(ICE_FLOW_PTYPE_MAX, BITS_PER_BYTE);
+ struct ice_prof_map *prof;
+ enum ice_status status;
+ u32 byte = 0;
+ u8 prof_id;
+
+ ice_acquire_lock(&hw->blk[blk].es.prof_map_lock);
+
+ /* search for existing profile */
+ status = ice_find_prof_id_with_mask(hw, blk, es, masks, &prof_id);
+ if (status) {
+ /* allocate profile ID */
+ status = ice_alloc_prof_id(hw, blk, &prof_id);
+ if (status)
+ goto err_ice_add_prof;
+ if (blk == ICE_BLK_FD) {
+ /* For Flow Director block, the extraction sequence may
+ * need to be altered in the case where there are paired
+ * fields that have no match. This is necessary because
+ * for Flow Director, src and dest fields need to paired
+ * for filter programming and these values are swapped
+ * during Tx.
+ */
+ status = ice_update_fd_swap(hw, prof_id, es);
+ if (status)
+ goto err_ice_add_prof;
+ }
+ status = ice_update_prof_masking(hw, blk, prof_id, es, masks);
+ if (status)
+ goto err_ice_add_prof;
+
+ /* and write new es */
+ ice_write_es(hw, blk, prof_id, es);
+ }
+
+ ice_prof_inc_ref(hw, blk, prof_id);
+
+ /* add profile info */
+
+ prof = (struct ice_prof_map *)ice_malloc(hw, sizeof(*prof));
+ if (!prof)
+ goto err_ice_add_prof;
+
+ prof->profile_cookie = id;
+ prof->prof_id = prof_id;
+ prof->ptype_count = 0;
+ prof->context = 0;
+
+ /* build list of ptgs */
+ while (bytes && prof->ptype_count < ICE_MAX_PTYPE_PER_PROFILE) {
+ u32 bit;
+
+ if (!ptypes[byte]) {
+ bytes--;
+ byte++;
+ continue;
+ }
+ /* Examine 8 bits per byte */
+ for (bit = 0; bit < 8; bit++) {
+ if (ptypes[byte] & BIT(bit)) {
+ u16 ptype;
+ u8 m;
+
+ ptype = byte * BITS_PER_BYTE + bit;
+ if (ptype < ICE_FLOW_PTYPE_MAX) {
+ prof->ptype[prof->ptype_count] = ptype;
+
+ if (++prof->ptype_count >=
+ ICE_MAX_PTYPE_PER_PROFILE)
+ break;
+ }
+
+ /* nothing left in byte, then exit */
+ m = ~((1 << (bit + 1)) - 1);
+ if (!(ptypes[byte] & m))
+ break;
+ }
+ }
+
+ bytes--;
+ byte++;
+ }
+
+ LIST_ADD(&prof->list, &hw->blk[blk].es.prof_map);
+ status = ICE_SUCCESS;
+
+err_ice_add_prof:
+ ice_release_lock(&hw->blk[blk].es.prof_map_lock);
+ return status;
+}
+
+/**
* ice_add_prof - add profile
* @hw: pointer to the HW struct
* @blk: hardware block
diff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h
index f01dfbb98..6af24653b 100644
--- a/drivers/net/ice/base/ice_flex_pipe.h
+++ b/drivers/net/ice/base/ice_flex_pipe.h
@@ -45,8 +45,13 @@ ice_tunnel_get_type(struct ice_hw *hw, u16 port, enum ice_tunnel_type *type);
enum ice_status
ice_vsig_find_vsi(struct ice_hw *hw, enum ice_block blk, u16 vsi, u16 *vsig);
enum ice_status
+ice_add_prof_with_mask(struct ice_hw *hw, enum ice_block blk, u64 id,
+ u8 ptypes[], struct ice_fv_word *es, u16 *masks);
+enum ice_status
ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],
struct ice_fv_word *es);
+void ice_init_all_prof_masks(struct ice_hw *hw);
+void ice_shutdown_all_prof_masks(struct ice_hw *hw);
struct ice_prof_map *
ice_search_prof_id(struct ice_hw *hw, enum ice_block blk, u64 id);
enum ice_status
diff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h
index 837e1e872..634897a28 100644
--- a/drivers/net/ice/base/ice_flex_type.h
+++ b/drivers/net/ice/base/ice_flex_type.h
@@ -490,6 +490,7 @@ struct ice_es {
u16 count;
u16 fvw;
u16 *ref_count;
+ u32 *mask_ena;
struct LIST_HEAD_TYPE prof_map;
struct ice_fv_word *t;
struct ice_lock prof_map_lock; /* protect access to profiles list */
@@ -654,6 +655,21 @@ struct ice_prof_redir {
u16 count;
};
+struct ice_mask {
+ u16 mask; /* 16-bit mask */
+ u16 idx; /* index */
+ u16 ref; /* reference count */
+ u8 in_use; /* non-zero if used */
+};
+
+struct ice_masks {
+ struct ice_lock lock; /* lock to protect this structure */
+ u16 first; /* first mask owned by the PF */
+ u16 count; /* number of masks owned by the PF */
+#define ICE_PROFILE_MASK_COUNT 32
+ struct ice_mask masks[ICE_PROFILE_MASK_COUNT];
+};
+
/* Tables per block */
struct ice_blk_info {
struct ice_xlt1 xlt1;
@@ -661,6 +677,7 @@ struct ice_blk_info {
struct ice_prof_tcam prof;
struct ice_prof_redir prof_redir;
struct ice_es es;
+ struct ice_masks masks;
u8 overwrite; /* set to true to allow overwrite of table entries */
u8 is_list_init;
};
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index fb9041b3e..1530a72cc 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -34,12 +34,21 @@ struct ice_flow_field_info {
enum ice_flow_seg_hdr hdr;
s16 off; /* Offset from start of a protocol header, in bits */
u16 size; /* Size of fields in bits */
+ u16 mask; /* 16-bit mask for field */
};
#define ICE_FLOW_FLD_INFO(_hdr, _offset_bytes, _size_bytes) { \
.hdr = _hdr, \
- .off = _offset_bytes * BITS_PER_BYTE, \
- .size = _size_bytes * BITS_PER_BYTE, \
+ .off = (_offset_bytes) * BITS_PER_BYTE, \
+ .size = (_size_bytes) * BITS_PER_BYTE, \
+ .mask = 0, \
+}
+
+#define ICE_FLOW_FLD_INFO_MSK(_hdr, _offset_bytes, _size_bytes, _mask) { \
+ .hdr = _hdr, \
+ .off = (_offset_bytes) * BITS_PER_BYTE, \
+ .size = (_size_bytes) * BITS_PER_BYTE, \
+ .mask = _mask, \
}
/* Table containing properties of supported protocol header fields */
@@ -292,7 +301,7 @@ struct ice_flow_prof_params {
* This will give us the direction flags.
*/
struct ice_fv_word es[ICE_MAX_FV_WORDS];
-
+ u16 mask[ICE_MAX_FV_WORDS];
ice_declare_bitmap(ptypes, ICE_FLOW_PTYPE_MAX);
};
@@ -544,6 +553,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,
struct ice_flow_fld_info *flds;
u16 cnt, ese_bits, i;
s16 adj = 0;
+ u16 mask;
u16 off;
flds = params->prof->segs[seg].fields;
@@ -652,6 +662,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,
/* Fill in the extraction sequence entries needed for this field */
off = flds[fld].xtrct.off;
+ mask = ice_flds_info[fld].mask;
for (i = 0; i < cnt; i++) {
/* Only consume an extraction sequence entry if there is no
* sibling field associated with this field or the sibling entry
@@ -676,6 +687,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,
params->es[idx].prot_id = prot_id;
params->es[idx].off = off;
+ params->mask[idx] = mask;
params->es_cnt++;
}
@@ -1048,7 +1060,8 @@ ice_flow_add_prof_sync(struct ice_hw *hw, enum ice_block blk,
}
/* Add a HW profile for this flow profile */
- status = ice_add_prof(hw, blk, prof_id, (u8 *)params.ptypes, params.es);
+ status = ice_add_prof_with_mask(hw, blk, prof_id, (u8 *)params.ptypes,
+ params.es, params.mask);
if (status) {
ice_debug(hw, ICE_DBG_FLOW, "Error adding a HW flow profile\n");
goto out;
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 18/63] net/ice/base: resolve static analysis issues
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (16 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 17/63] net/ice/base: enable masking for RSS and FD field vectors Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 19/63] net/ice/base: fix memory leak issue Qi Zhang
` (45 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, stable, Dan Nowlin, Paul M Stillwell Jr
Coverity complains first_free can be -1 resulting in a negative shift left
when k equals 0; i.e. the expression 1 << (first_free - k). Fix this by
explicitly checking for this case.
Cc: stable@dpdk.org
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flex_pipe.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index 29888df76..73362c909 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -4200,7 +4200,7 @@ ice_update_fd_swap(struct ice_hw *hw, u16 prof_id, struct ice_fv_word *es)
index = i + 1;
/* check for room */
- if (first_free + 1 < ice_fd_pairs[index].count)
+ if (first_free + 1 < (s8)ice_fd_pairs[index].count)
return ICE_ERR_MAX_LIMIT;
/* place in extraction sequence */
@@ -4210,6 +4210,9 @@ ice_update_fd_swap(struct ice_hw *hw, u16 prof_id, struct ice_fv_word *es)
es[first_free - k].off =
ice_fd_pairs[index].off + (k * 2);
+ if (k > first_free)
+ return ICE_ERR_OUT_OF_RANGE;
+
/* keep track of non-relevant fields */
mask_sel |= 1 << (first_free - k);
}
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 19/63] net/ice/base: fix memory leak issue
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (17 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 18/63] net/ice/base: resolve static analysis issues Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 20/63] net/ice/base: check root pointer for validity Qi Zhang
` (44 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, stable, Paul M Stillwell Jr
Need to free new ice_vsig_prof if no valid ptype can be found.
Fixes: d935fb5bb091 ("net/ice/base: fix packet type size")
Cc: stable@dpdk.org
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flex_pipe.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index 73362c909..7daaf10b0 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -4918,8 +4918,10 @@ ice_add_prof_to_lst(struct ice_hw *hw, enum ice_block blk,
p->tcam[i].prof_id = map->prof_id;
p->tcam[i].tcam_idx = ICE_INVALID_TCAM;
- if (ice_ptg_find_ptype(hw, blk, map->ptype[i], &ptg))
+ if (ice_ptg_find_ptype(hw, blk, map->ptype[i], &ptg)) {
+ ice_free(hw, p);
return ICE_ERR_CFG;
+ }
p->tcam[i].ptg = ptg;
}
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 20/63] net/ice/base: check root pointer for validity
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (18 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 19/63] net/ice/base: fix memory leak issue Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 21/63] net/ice/base: fix type-mismatch Qi Zhang
` (43 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Anirudh Venkataramanan, Paul M Stillwell Jr
ice_sched_get_tc_node uses pi->root without checking for NULL. Add a
check to prevent NULL pointer dereference.
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_sched.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index d16f256c9..84a033f1c 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -284,7 +284,7 @@ struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc)
{
u8 i;
- if (!pi)
+ if (!pi || !pi->root)
return NULL;
for (i = 0; i < pi->root->num_children; i++)
if (pi->root->children[i]->tc_num == tc)
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 21/63] net/ice/base: fix type-mismatch
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (19 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 20/63] net/ice/base: check root pointer for validity Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 22/63] net/ice/base: correct overrun Coverty hit Qi Zhang
` (42 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, stable, Jeb Cramer, Paul M Stillwell Jr
The iterators are u8, but the values being compared against are u16s.
It may not ever be the case that the comparison is against a value
larger than the upper bound of the smaller type, but code analysis tools
don't know that.
Fixes: 93e84b1bfc92 ("net/ice/base: add basic Tx scheduler")
Cc: stable@dpdk.org
Signed-off-by: Jeb Cramer <jeb.j.cramer@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_sched.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index 84a033f1c..01c8defae 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -735,7 +735,7 @@ ice_sched_del_rl_profile(struct ice_hw *hw,
*/
static void ice_sched_clear_rl_prof(struct ice_port_info *pi)
{
- u8 ln;
+ u16 ln;
for (ln = 0; ln < pi->hw->num_tx_sched_layers; ln++) {
struct ice_aqc_rl_profile_info *rl_prof_elem;
@@ -2181,12 +2181,11 @@ static enum ice_status
ice_sched_move_nodes(struct ice_port_info *pi, struct ice_sched_node *parent,
u16 num_items, u32 *list)
{
+ enum ice_status status = ICE_SUCCESS;
struct ice_aqc_move_elem *buf;
struct ice_sched_node *node;
- enum ice_status status = ICE_SUCCESS;
+ u16 i, grps_movd = 0;
struct ice_hw *hw;
- u16 grps_movd = 0;
- u8 i;
hw = pi->hw;
@@ -2802,7 +2801,7 @@ ice_sched_assoc_vsi_to_agg(struct ice_port_info *pi, u32 agg_id,
*/
static void ice_sched_rm_unused_rl_prof(struct ice_port_info *pi)
{
- u8 ln;
+ u16 ln;
for (ln = 0; ln < pi->hw->num_tx_sched_layers; ln++) {
struct ice_aqc_rl_profile_info *rl_prof_elem;
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 22/63] net/ice/base: correct overrun Coverty hit
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (20 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 21/63] net/ice/base: fix type-mismatch Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 23/63] net/ice/base: update Boot Configuration Section read of NVM Qi Zhang
` (41 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, stable, Paul M Stillwell Jr
Added boundary check for layer_num in function ice_sched_rm_rl_profile,
and ice_sched_add_rl_profile.
Cc: stable@dpdk.org
Tarun Singh <tarun.k.singh@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_sched.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index 01c8defae..1cfc3bc20 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -3799,10 +3799,12 @@ ice_sched_add_rl_profile(struct ice_port_info *pi,
struct ice_aqc_rl_profile_generic_elem *buf;
struct ice_aqc_rl_profile_info *rl_prof_elem;
u16 profiles_added = 0, num_profiles = 1;
- enum ice_status status = ICE_ERR_PARAM;
+ enum ice_status status;
struct ice_hw *hw;
u8 profile_type;
+ if (layer_num >= ICE_AQC_TOPO_MAX_LEVEL_NUM)
+ return NULL;
switch (rl_type) {
case ICE_MIN_BW:
profile_type = ICE_AQC_RL_PROFILE_TYPE_CIR;
@@ -4049,6 +4051,8 @@ ice_sched_rm_rl_profile(struct ice_port_info *pi, u8 layer_num, u8 profile_type,
struct ice_aqc_rl_profile_info *rl_prof_elem;
enum ice_status status = ICE_SUCCESS;
+ if (layer_num >= ICE_AQC_TOPO_MAX_LEVEL_NUM)
+ return ICE_ERR_PARAM;
/* Check the existing list for RL profile */
LIST_FOR_EACH_ENTRY(rl_prof_elem, &pi->rl_prof_list[layer_num],
ice_aqc_rl_profile_info, list_entry)
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 23/63] net/ice/base: update Boot Configuration Section read of NVM
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (21 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 22/63] net/ice/base: correct overrun Coverty hit Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 24/63] net/ice/base: add support for NVM access commands Qi Zhang
` (40 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Md Fahad Iqbal Polash, Paul M Stillwell Jr
Boot Configuration Section Block has been moved to the
Preserved Field Area (PFA) of NVM. So, this patch updates
the NVM reads that involve Boot Configuration Section.
Signed-off-by: Md Fahad Iqbal Polash <md.fahad.iqbal.polash@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_devids.h | 6 +++
drivers/net/ice/base/ice_nvm.c | 39 +++++++++++++-----
drivers/net/ice/base/ice_nvm.h | 87 +++++++++++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_type.h | 4 +-
4 files changed, 124 insertions(+), 12 deletions(-)
create mode 100644 drivers/net/ice/base/ice_nvm.h
diff --git a/drivers/net/ice/base/ice_devids.h b/drivers/net/ice/base/ice_devids.h
index 5f1ac0422..c9a567fb1 100644
--- a/drivers/net/ice/base/ice_devids.h
+++ b/drivers/net/ice/base/ice_devids.h
@@ -13,5 +13,11 @@
#define ICE_DEV_ID_E810C_QSFP 0x1592
/* Intel(R) Ethernet Controller E810-C for SFP */
#define ICE_DEV_ID_E810C_SFP 0x1593
+/* Intel(R) Ethernet Connection C822N for backplane */
+#define ICE_DEV_ID_C822N_BACKPLANE 0x1890
+/* Intel(R) Ethernet Connection C822N for QSFP */
+#define ICE_DEV_ID_C822N_QSFP 0x1891
+/* Intel(R) Ethernet Connection C822N for SFP */
+#define ICE_DEV_ID_C822N_SFP 0x1892
#endif /* _ICE_DEVIDS_H_ */
diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c
index c0f9e353e..95a6c9ab6 100644
--- a/drivers/net/ice/base/ice_nvm.c
+++ b/drivers/net/ice/base/ice_nvm.c
@@ -263,9 +263,9 @@ enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
enum ice_status ice_init_nvm(struct ice_hw *hw)
{
struct ice_nvm_info *nvm = &hw->nvm;
- u16 oem_hi, oem_lo, cfg_ptr;
+ u16 oem_hi, oem_lo, boot_cfg_tlv, boot_cfg_tlv_len;
u16 eetrack_lo, eetrack_hi;
- enum ice_status status = ICE_SUCCESS;
+ enum ice_status status;
u32 fla, gens_stat;
u8 sr_size;
@@ -284,12 +284,12 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)
fla = rd32(hw, GLNVM_FLA);
if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */
nvm->blank_nvm_mode = false;
- } else { /* Blank programming mode */
+ } else {
+ /* Blank programming mode */
nvm->blank_nvm_mode = true;
- status = ICE_ERR_NVM_BLANK_MODE;
ice_debug(hw, ICE_DBG_NVM,
"NVM init error: unsupported blank mode.\n");
- return status;
+ return ICE_ERR_NVM_BLANK_MODE;
}
status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &nvm->ver);
@@ -312,19 +312,37 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)
nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
- status = ice_read_sr_word(hw, ICE_SR_BOOT_CFG_PTR, &cfg_ptr);
+ /* the following devices do not have boot_cfg_tlv yet */
+ if (hw->device_id == ICE_DEV_ID_C822N_BACKPLANE ||
+ hw->device_id == ICE_DEV_ID_C822N_QSFP ||
+ hw->device_id == ICE_DEV_ID_C822N_SFP)
+ return status;
+
+ status = ice_get_pfa_module_tlv(hw, &boot_cfg_tlv, &boot_cfg_tlv_len,
+ ICE_SR_BOOT_CFG_PTR);
if (status) {
- ice_debug(hw, ICE_DBG_INIT, "Failed to read BOOT_CONFIG_PTR.\n");
+ ice_debug(hw, ICE_DBG_INIT,
+ "Failed to read Boot Configuration Block TLV.\n");
return status;
}
- status = ice_read_sr_word(hw, (cfg_ptr + ICE_NVM_OEM_VER_OFF), &oem_hi);
+ /* Boot Configuration Block must have length at least 2 words
+ * (Combo Image Version High and Combo Image Version Low)
+ */
+ if (boot_cfg_tlv_len < 2) {
+ ice_debug(hw, ICE_DBG_INIT,
+ "Invalid Boot Configuration Block TLV size.\n");
+ return ICE_ERR_INVAL_SIZE;
+ }
+
+ status = ice_read_sr_word(hw, (boot_cfg_tlv + ICE_NVM_OEM_VER_OFF),
+ &oem_hi);
if (status) {
ice_debug(hw, ICE_DBG_INIT, "Failed to read OEM_VER hi.\n");
return status;
}
- status = ice_read_sr_word(hw, (cfg_ptr + (ICE_NVM_OEM_VER_OFF + 1)),
+ status = ice_read_sr_word(hw, (boot_cfg_tlv + ICE_NVM_OEM_VER_OFF + 1),
&oem_lo);
if (status) {
ice_debug(hw, ICE_DBG_INIT, "Failed to read OEM_VER lo.\n");
@@ -332,7 +350,8 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)
}
nvm->oem_ver = ((u32)oem_hi << 16) | oem_lo;
- return status;
+
+ return ICE_SUCCESS;
}
diff --git a/drivers/net/ice/base/ice_nvm.h b/drivers/net/ice/base/ice_nvm.h
new file mode 100644
index 000000000..da76b2674
--- /dev/null
+++ b/drivers/net/ice/base/ice_nvm.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2001-2019
+ */
+
+#ifndef _ICE_NVM_H_
+#define _ICE_NVM_H_
+
+#define ICE_NVM_CMD_READ 0x0000000B
+#define ICE_NVM_CMD_WRITE 0x0000000C
+
+/* NVM Access config bits */
+#define ICE_NVM_CFG_MODULE_M MAKEMASK(0xFF, 0)
+#define ICE_NVM_CFG_MODULE_S 0
+#define ICE_NVM_CFG_FLAGS_M MAKEMASK(0xF, 8)
+#define ICE_NVM_CFG_FLAGS_S 8
+#define ICE_NVM_CFG_EXT_FLAGS_M MAKEMASK(0xF, 12)
+#define ICE_NVM_CFG_EXT_FLAGS_S 12
+#define ICE_NVM_CFG_ADAPTER_INFO_M MAKEMASK(0xFFFF, 16)
+#define ICE_NVM_CFG_ADAPTER_INFO_S 16
+
+/* NVM Read Get Driver Features */
+#define ICE_NVM_GET_FEATURES_MODULE 0xE
+#define ICE_NVM_GET_FEATURES_FLAGS 0xF
+
+/* NVM Read/Write Mapped Space */
+#define ICE_NVM_REG_RW_MODULE 0x0
+#define ICE_NVM_REG_RW_FLAGS 0x1
+
+#define ICE_NVM_ACCESS_MAJOR_VER 0
+#define ICE_NVM_ACCESS_MINOR_VER 5
+
+/* NVM Access feature flags. Other bits in the features field are reserved and
+ * should be set to zero when reporting the ice_nvm_features structure.
+ */
+#define ICE_NVM_FEATURES_0_REG_ACCESS BIT(1)
+
+/* NVM Access Features */
+struct ice_nvm_features {
+ u8 major; /* Major version (informational only) */
+ u8 minor; /* Minor version (informational only) */
+ u16 size; /* size of ice_nvm_features structure */
+ u8 features[12]; /* Array of feature bits */
+};
+
+/* NVM Access command */
+struct ice_nvm_access_cmd {
+ u32 command; /* NVM command: READ or WRITE */
+ u32 config; /* NVM command configuration */
+ u32 offset; /* offset to read/write, in bytes */
+ u32 data_size; /* size of data field, in bytes */
+};
+
+/* NVM Access data */
+union ice_nvm_access_data {
+ u32 regval; /* Storage for register value */
+ struct ice_nvm_features drv_features; /* NVM features */
+};
+
+/* NVM Access registers */
+#define GL_HIDA(_i) (0x00082000 + ((_i) * 4))
+#define GL_HIBA(_i) (0x00081000 + ((_i) * 4))
+#define GL_HICR 0x00082040
+#define GL_HICR_EN 0x00082044
+#define GLGEN_CSR_DEBUG_C 0x00075750
+#define GLPCI_LBARCTRL 0x0009DE74
+#define GLNVM_GENS 0x000B6100
+#define GLNVM_FLA 0x000B6108
+
+#define ICE_NVM_ACCESS_GL_HIDA_MAX 15
+#define ICE_NVM_ACCESS_GL_HIBA_MAX 1023
+
+u32 ice_nvm_access_get_module(struct ice_nvm_access_cmd *cmd);
+u32 ice_nvm_access_get_flags(struct ice_nvm_access_cmd *cmd);
+u32 ice_nvm_access_get_adapter(struct ice_nvm_access_cmd *cmd);
+enum ice_status
+ice_nvm_access_read(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
+ union ice_nvm_access_data *data);
+enum ice_status
+ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
+ union ice_nvm_access_data *data);
+enum ice_status
+ice_nvm_access_get_features(struct ice_nvm_access_cmd *cmd,
+ union ice_nvm_access_data *data);
+enum ice_status
+ice_handle_nvm_access(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
+ union ice_nvm_access_data *data);
+#endif /* _ICE_NVM_H_ */
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 79d7bb1dd..dc041760d 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -916,9 +916,9 @@ enum ice_sw_fwd_act_type {
#define ICE_SR_MNG_CFG_PTR 0x0E
#define ICE_SR_EMP_MODULE_PTR 0x0F
#define ICE_SR_PBA_BLOCK_PTR 0x16
-#define ICE_SR_BOOT_CFG_PTR 0x17
+#define ICE_SR_BOOT_CFG_PTR 0x132
#define ICE_SR_NVM_WOL_CFG 0x19
-#define ICE_NVM_OEM_VER_OFF 0x83
+#define ICE_NVM_OEM_VER_OFF 0x02
#define ICE_SR_NVM_DEV_STARTER_VER 0x18
#define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27
#define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 24/63] net/ice/base: add support for NVM access commands
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (22 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 23/63] net/ice/base: update Boot Configuration Section read of NVM Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 25/63] net/ice/base: add support for GTP and PPPoE protocols Qi Zhang
` (39 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Jacob Keller, Paul M Stillwell Jr
Add a new structure, ice_nvm_access, used to request access to read or
write certain NVM related registers.
The structure is used by NVM Update to request read or write of specific
NVM registers in order to perform updates.
Additionally, there is a command to request the driver "features"
structure which represents data about what features of the NVM access
interface the driver supports.
Implement ice_handle_nvm_access to parse the access request and perform
the necessary function.
This function verifies that the access request is valid. If so, the
function will delegate to perform the register read, register write, or
copying of the driver ice_nvm_features structure.
If the request is invalid, the function will report a suitable error
codition that can be propagated out.
Only a subset of registers is accessible, and all other registers will
be rejected with ICE_ERR_OUT_OF_RANGE.
When reading, the contents of the variable sized data buffer will be
used as storage for returning the register value. When writing, the
contents will be used as input for the value to write to the register.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.h | 1 +
drivers/net/ice/base/ice_nvm.c | 237 ++++++++++++++++++++++++++++++++++++++
2 files changed, 238 insertions(+)
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index 1fd256a42..a55f7eeba 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -6,6 +6,7 @@
#define _ICE_COMMON_H_
#include "ice_type.h"
+#include "ice_nvm.h"
#include "ice_flex_pipe.h"
#include "ice_switch.h"
#include "ice_fdir.h"
diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c
index 95a6c9ab6..66cfec641 100644
--- a/drivers/net/ice/base/ice_nvm.c
+++ b/drivers/net/ice/base/ice_nvm.c
@@ -411,3 +411,240 @@ enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw)
return status;
}
+
+/**
+ * ice_nvm_access_get_features - Return the NVM access features structure
+ * @cmd: NVM access command to process
+ * @data: storage for the driver NVM features
+ *
+ * Fill in the data section of the NVM access request with a copy of the NVM
+ * features structure.
+ */
+enum ice_status
+ice_nvm_access_get_features(struct ice_nvm_access_cmd *cmd,
+ union ice_nvm_access_data *data)
+{
+ /* The provided data_size must be at least as large as our NVM
+ * features structure. A larger size should not be treated as an
+ * error, to allow future extensions to to the features structure to
+ * work on older drivers.
+ */
+ if (cmd->data_size < sizeof(struct ice_nvm_features))
+ return ICE_ERR_NO_MEMORY;
+
+ /* Initialize the data buffer to zeros */
+ ice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);
+
+ /* Fill in the features data */
+ data->drv_features.major = ICE_NVM_ACCESS_MAJOR_VER;
+ data->drv_features.minor = ICE_NVM_ACCESS_MINOR_VER;
+ data->drv_features.size = sizeof(struct ice_nvm_features);
+ data->drv_features.features[0] = ICE_NVM_FEATURES_0_REG_ACCESS;
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_nvm_access_get_module - Helper function to read module value
+ * @cmd: NVM access command structure
+ *
+ * Reads the module value out of the NVM access config field.
+ */
+u32 ice_nvm_access_get_module(struct ice_nvm_access_cmd *cmd)
+{
+ return ((cmd->config & ICE_NVM_CFG_MODULE_M) >> ICE_NVM_CFG_MODULE_S);
+}
+
+/**
+ * ice_nvm_access_get_flags - Helper function to read flags value
+ * @cmd: NVM access command structure
+ *
+ * Reads the flags value out of the NVM access config field.
+ */
+u32 ice_nvm_access_get_flags(struct ice_nvm_access_cmd *cmd)
+{
+ return ((cmd->config & ICE_NVM_CFG_FLAGS_M) >> ICE_NVM_CFG_FLAGS_S);
+}
+
+/**
+ * ice_nvm_access_get_adapter - Helper function to read adapter info
+ * @cmd: NVM access command structure
+ *
+ * Read the adapter info value out of the NVM access config field.
+ */
+u32 ice_nvm_access_get_adapter(struct ice_nvm_access_cmd *cmd)
+{
+ return ((cmd->config & ICE_NVM_CFG_ADAPTER_INFO_M) >>
+ ICE_NVM_CFG_ADAPTER_INFO_S);
+}
+
+/**
+ * ice_validate_nvm_rw_reg - Check than an NVM access request is valid
+ * @cmd: NVM access command structure
+ *
+ * Validates that an NVM access structure is request to read or write a valid
+ * register offset. First validates that the module and flags are correct, and
+ * then ensures that the register offset is one of the accepted registers.
+ */
+static enum ice_status
+ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd *cmd)
+{
+ u32 module, flags, offset;
+ u16 i;
+
+ module = ice_nvm_access_get_module(cmd);
+ flags = ice_nvm_access_get_flags(cmd);
+ offset = cmd->offset;
+
+ /* Make sure the module and flags indicate a read/write request */
+ if (module != ICE_NVM_REG_RW_MODULE ||
+ flags != ICE_NVM_REG_RW_FLAGS ||
+ cmd->data_size != FIELD_SIZEOF(union ice_nvm_access_data, regval))
+ return ICE_ERR_PARAM;
+
+ switch (offset) {
+ case GL_HICR:
+ case GL_HICR_EN: /* Note, this register is read only */
+ case GL_FWSTS:
+ case GL_MNG_FWSM:
+ case GLGEN_CSR_DEBUG_C:
+ case GLPCI_LBARCTRL:
+ case GLNVM_GENS:
+ case GLNVM_FLA:
+ case PF_FUNC_RID:
+ return ICE_SUCCESS;
+ default:
+ break;
+ }
+
+ for (i = 0; i <= ICE_NVM_ACCESS_GL_HIDA_MAX; i++)
+ if (offset == (u32)GL_HIDA(i))
+ return ICE_SUCCESS;
+
+ for (i = 0; i <= ICE_NVM_ACCESS_GL_HIBA_MAX; i++)
+ if (offset == (u32)GL_HIBA(i))
+ return ICE_SUCCESS;
+
+ /* All other register offsets are not valid */
+ return ICE_ERR_OUT_OF_RANGE;
+}
+
+/**
+ * ice_nvm_access_read - Handle an NVM read request
+ * @hw: pointer to the HW struct
+ * @cmd: NVM access command to process
+ * @data: storage for the register value read
+ *
+ * Process an NVM access request to read a register.
+ */
+enum ice_status
+ice_nvm_access_read(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
+ union ice_nvm_access_data *data)
+{
+ enum ice_status status;
+
+ ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
+
+ /* Always initialize the output data, even on failure */
+ ice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);
+
+ /* Make sure this is a valid read/write access request */
+ status = ice_validate_nvm_rw_reg(cmd);
+ if (status)
+ return status;
+
+ ice_debug(hw, ICE_DBG_NVM, "NVM access: reading register %08x\n",
+ cmd->offset);
+
+ /* Read the register and store the contents in the data field */
+ data->regval = rd32(hw, cmd->offset);
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_nvm_access_write - Handle an NVM write request
+ * @hw: pointer to the HW struct
+ * @cmd: NVM access command to process
+ * @data: NVM access data to write
+ *
+ * Process an NVM access request to write a register.
+ */
+enum ice_status
+ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
+ union ice_nvm_access_data *data)
+{
+ enum ice_status status;
+
+ ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
+
+ /* Make sure this is a valid read/write access request */
+ status = ice_validate_nvm_rw_reg(cmd);
+ if (status)
+ return status;
+
+ /* The HICR_EN register is read-only */
+ if (cmd->offset == GL_HICR_EN)
+ return ICE_ERR_OUT_OF_RANGE;
+
+ ice_debug(hw, ICE_DBG_NVM,
+ "NVM access: writing register %08x with value %08x\n",
+ cmd->offset, data->regval);
+
+ /* Write the data field to the specified register */
+ wr32(hw, cmd->offset, data->regval);
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_handle_nvm_access - Handle an NVM access request
+ * @hw: pointer to the HW struct
+ * @cmd: NVM access command info
+ * @data: pointer to read or return data
+ *
+ * Process an NVM access request. Read the command structure information and
+ * determine if it is valid. If not, report an error indicating the command
+ * was invalid.
+ *
+ * For valid commands, perform the necessary function, copying the data into
+ * the provided data buffer.
+ */
+enum ice_status
+ice_handle_nvm_access(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
+ union ice_nvm_access_data *data)
+{
+ u32 module, flags, adapter_info;
+
+ ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
+
+ /* Extended flags are currently reserved and must be zero */
+ if ((cmd->config & ICE_NVM_CFG_EXT_FLAGS_M) != 0)
+ return ICE_ERR_PARAM;
+
+ /* Adapter info must match the HW device ID */
+ adapter_info = ice_nvm_access_get_adapter(cmd);
+ if (adapter_info != hw->device_id)
+ return ICE_ERR_PARAM;
+
+ switch (cmd->command) {
+ case ICE_NVM_CMD_READ:
+ module = ice_nvm_access_get_module(cmd);
+ flags = ice_nvm_access_get_flags(cmd);
+
+ /* Getting the driver's NVM features structure shares the same
+ * command type as reading a register. Read the config field
+ * to determine if this is a request to get features.
+ */
+ if (module == ICE_NVM_GET_FEATURES_MODULE &&
+ flags == ICE_NVM_GET_FEATURES_FLAGS &&
+ cmd->offset == 0)
+ return ice_nvm_access_get_features(cmd, data);
+ else
+ return ice_nvm_access_read(hw, cmd, data);
+ case ICE_NVM_CMD_WRITE:
+ return ice_nvm_access_write(hw, cmd, data);
+ default:
+ return ICE_ERR_PARAM;
+ }
+}
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 25/63] net/ice/base: add support for GTP and PPPoE protocols
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (23 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 24/63] net/ice/base: add support for NVM access commands Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 26/63] net/ice/base: add locks for flow functions Qi Zhang
` (38 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
Added switch protocol segments for both GTP and PPPOE protocols.
Added RSS protocol segments for both GTP and PPPOE protocols.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flow.c | 105 ++++++++++++++++++++++++++-----
drivers/net/ice/base/ice_flow.h | 61 ++++++++++++++----
drivers/net/ice/base/ice_protocol_type.h | 33 +++++++++-
drivers/net/ice/base/ice_switch.c | 79 ++++++++++++++++++++++-
4 files changed, 251 insertions(+), 27 deletions(-)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 1530a72cc..0f52b3379 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -19,6 +19,8 @@
#define ICE_FLOW_FLD_SZ_ICMP_CODE 1
#define ICE_FLOW_FLD_SZ_ARP_OPER 2
#define ICE_FLOW_FLD_SZ_GRE_KEYID 4
+#define ICE_FLOW_FLD_SZ_GTP_TEID 4
+#define ICE_FLOW_FLD_SZ_PPPOE_SESS_ID 2
/* Protocol header fields are extracted at the word boundaries as word-sized
* values. Specify the displacement value of some non-word-aligned fields needed
@@ -115,6 +117,23 @@ struct ice_flow_field_info ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = {
/* GRE */
/* ICE_FLOW_FIELD_IDX_GRE_KEYID */
ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GRE, 12, ICE_FLOW_FLD_SZ_GRE_KEYID),
+ /* GTP */
+ /* ICE_FLOW_FIELD_IDX_GTPC_TEID */
+ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GTPC_TEID, 12,
+ ICE_FLOW_FLD_SZ_GTP_TEID),
+ /* ICE_FLOW_FIELD_IDX_GTPU_IP_TEID */
+ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GTPU_IP, 12,
+ ICE_FLOW_FLD_SZ_GTP_TEID),
+ /* ICE_FLOW_FIELD_IDX_GTPU_UP_TEID */
+ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GTPU_UP, 12,
+ ICE_FLOW_FLD_SZ_GTP_TEID),
+ /* ICE_FLOW_FIELD_IDX_GTPU_DWN_TEID */
+ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GTPU_DWN, 12,
+ ICE_FLOW_FLD_SZ_GTP_TEID),
+ /* PPPOE */
+ /* ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID */
+ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_PPPOE, 2,
+ ICE_FLOW_FLD_SZ_PPPOE_SESS_ID),
};
/* Bitmaps indicating relevant packet types for a particular protocol header
@@ -290,6 +309,42 @@ static const u32 ice_ptypes_mac_il[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
+/* Packet types for GTPC */
+static const u32 ice_ptypes_gtpc[] = {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000180, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+/* Packet types for GTPC with TEID */
+static const u32 ice_ptypes_gtpc_tid[] = {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000060, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+/* Packet types for GTPU */
+static const u32 ice_ptypes_gtpu[] = {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x7FFFF800, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
/* Manage parameters and info. used during the creation of a flow profile */
struct ice_flow_prof_params {
enum ice_block blk;
@@ -317,10 +372,13 @@ static bool ice_is_pow2(u64 val)
#define ICE_FLOW_SEG_HDRS_L2_MASK \
(ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN)
#define ICE_FLOW_SEG_HDRS_L3_MASK \
- (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_ARP)
+ (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6 | \
+ ICE_FLOW_SEG_HDR_ARP | ICE_FLOW_SEG_HDR_PPPOE)
#define ICE_FLOW_SEG_HDRS_L4_MASK \
(ICE_FLOW_SEG_HDR_ICMP | ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_UDP | \
- ICE_FLOW_SEG_HDR_SCTP)
+ ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_GTPC | \
+ ICE_FLOW_SEG_HDR_GTPC_TEID | ICE_FLOW_SEG_HDR_GTPU_IP | \
+ ICE_FLOW_SEG_HDR_GTPU_UP | ICE_FLOW_SEG_HDR_GTPU_DWN)
/**
* ice_flow_val_hdrs - validates packet segments for valid protocol headers
@@ -431,21 +489,18 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params)
(const ice_bitmap_t *)ice_ptypes_mac_il;
ice_and_bitmap(params->ptypes, params->ptypes, src,
ICE_FLOW_PTYPE_MAX);
- hdrs &= ~ICE_FLOW_SEG_HDR_ETH;
}
if (i && hdrs & ICE_FLOW_SEG_HDR_VLAN) {
src = (const ice_bitmap_t *)ice_ptypes_macvlan_il;
ice_and_bitmap(params->ptypes, params->ptypes, src,
ICE_FLOW_PTYPE_MAX);
- hdrs &= ~ICE_FLOW_SEG_HDR_VLAN;
}
if (!i && hdrs & ICE_FLOW_SEG_HDR_ARP) {
ice_and_bitmap(params->ptypes, params->ptypes,
(const ice_bitmap_t *)ice_ptypes_arp_of,
ICE_FLOW_PTYPE_MAX);
- hdrs &= ~ICE_FLOW_SEG_HDR_ARP;
}
if (hdrs & ICE_FLOW_SEG_HDR_IPV4) {
@@ -453,13 +508,11 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params)
(const ice_bitmap_t *)ice_ptypes_ipv4_il;
ice_and_bitmap(params->ptypes, params->ptypes, src,
ICE_FLOW_PTYPE_MAX);
- hdrs &= ~ICE_FLOW_SEG_HDR_IPV4;
} else if (hdrs & ICE_FLOW_SEG_HDR_IPV6) {
src = !i ? (const ice_bitmap_t *)ice_ptypes_ipv6_ofos :
(const ice_bitmap_t *)ice_ptypes_ipv6_il;
ice_and_bitmap(params->ptypes, params->ptypes, src,
ICE_FLOW_PTYPE_MAX);
- hdrs &= ~ICE_FLOW_SEG_HDR_IPV6;
}
if (hdrs & ICE_FLOW_SEG_HDR_ICMP) {
@@ -467,29 +520,42 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params)
(const ice_bitmap_t *)ice_ptypes_icmp_il;
ice_and_bitmap(params->ptypes, params->ptypes, src,
ICE_FLOW_PTYPE_MAX);
- hdrs &= ~ICE_FLOW_SEG_HDR_ICMP;
} else if (hdrs & ICE_FLOW_SEG_HDR_UDP) {
src = (const ice_bitmap_t *)ice_ptypes_udp_il;
ice_and_bitmap(params->ptypes, params->ptypes, src,
ICE_FLOW_PTYPE_MAX);
- hdrs &= ~ICE_FLOW_SEG_HDR_UDP;
} else if (hdrs & ICE_FLOW_SEG_HDR_TCP) {
ice_and_bitmap(params->ptypes, params->ptypes,
(const ice_bitmap_t *)ice_ptypes_tcp_il,
ICE_FLOW_PTYPE_MAX);
- hdrs &= ~ICE_FLOW_SEG_HDR_TCP;
} else if (hdrs & ICE_FLOW_SEG_HDR_SCTP) {
src = (const ice_bitmap_t *)ice_ptypes_sctp_il;
ice_and_bitmap(params->ptypes, params->ptypes, src,
ICE_FLOW_PTYPE_MAX);
- hdrs &= ~ICE_FLOW_SEG_HDR_SCTP;
} else if (hdrs & ICE_FLOW_SEG_HDR_GRE) {
if (!i) {
src = (const ice_bitmap_t *)ice_ptypes_gre_of;
ice_and_bitmap(params->ptypes, params->ptypes,
src, ICE_FLOW_PTYPE_MAX);
}
- hdrs &= ~ICE_FLOW_SEG_HDR_GRE;
+ } else if (hdrs & ICE_FLOW_SEG_HDR_GTPC) {
+ if (!i) {
+ src = (const ice_bitmap_t *)ice_ptypes_gtpc;
+ ice_and_bitmap(params->ptypes, params->ptypes,
+ src, ICE_FLOW_PTYPE_MAX);
+ }
+ } else if (hdrs & ICE_FLOW_SEG_HDR_GTPC_TEID) {
+ if (!i) {
+ src = (const ice_bitmap_t *)ice_ptypes_gtpc_tid;
+ ice_and_bitmap(params->ptypes, params->ptypes,
+ src, ICE_FLOW_PTYPE_MAX);
+ }
+ } else if (hdrs & ICE_FLOW_SEG_HDR_GTPU) {
+ if (!i) {
+ src = (const ice_bitmap_t *)ice_ptypes_gtpu;
+ ice_and_bitmap(params->ptypes, params->ptypes,
+ src, ICE_FLOW_PTYPE_MAX);
+ }
}
}
@@ -619,6 +685,16 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,
case ICE_FLOW_FIELD_IDX_SCTP_DST_PORT:
prot_id = ICE_PROT_SCTP_IL;
break;
+ case ICE_FLOW_FIELD_IDX_GTPC_TEID:
+ case ICE_FLOW_FIELD_IDX_GTPU_IP_TEID:
+ case ICE_FLOW_FIELD_IDX_GTPU_UP_TEID:
+ case ICE_FLOW_FIELD_IDX_GTPU_DWN_TEID:
+ /* GTP is accessed through UDP OF protocol */
+ prot_id = ICE_PROT_UDP_OF;
+ break;
+ case ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID:
+ prot_id = ICE_PROT_PPPOE;
+ break;
case ICE_FLOW_FIELD_IDX_ARP_SIP:
case ICE_FLOW_FIELD_IDX_ARP_DIP:
case ICE_FLOW_FIELD_IDX_ARP_SHA:
@@ -1601,11 +1677,12 @@ ice_flow_add_fld_raw(struct ice_flow_seg_info *seg, u16 off, u8 len,
}
#define ICE_FLOW_RSS_SEG_HDR_L3_MASKS \
- (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6)
+ (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_PPPOE)
#define ICE_FLOW_RSS_SEG_HDR_L4_MASKS \
(ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_UDP | \
- ICE_FLOW_SEG_HDR_SCTP)
+ ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_GTPC_TEID)
+
#define ICE_FLOW_RSS_SEG_HDR_VAL_MASKS \
(ICE_FLOW_RSS_SEG_HDR_L3_MASKS | \
diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h
index 3a0fd23c4..eb8e1b733 100644
--- a/drivers/net/ice/base/ice_flow.h
+++ b/drivers/net/ice/base/ice_flow.h
@@ -41,6 +41,17 @@
#define ICE_HASH_SCTP_IPV4 (ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_SCTP_PORT)
#define ICE_HASH_SCTP_IPV6 (ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_SCTP_PORT)
+#define ICE_FLOW_HASH_GTP_TEID \
+ (ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_GTPC_TEID))
+
+#define ICE_FLOW_HASH_GTP_IPV4_TEID \
+ (ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_GTP_TEID)
+#define ICE_FLOW_HASH_GTP_IPV6_TEID \
+ (ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_GTP_TEID)
+
+#define ICE_FLOW_HASH_PPPOE_SESS_ID \
+ (ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID))
+
/* Protocol header fields within a packet segment. A segment consists of one or
* more protocol headers that make up a logical group of protocol headers. Each
* logical group of protocol headers encapsulates or is encapsulated using/by
@@ -48,19 +59,37 @@
* VxLAN, etc.
*/
enum ice_flow_seg_hdr {
- ICE_FLOW_SEG_HDR_NONE = 0x00000000,
- ICE_FLOW_SEG_HDR_ETH = 0x00000001,
- ICE_FLOW_SEG_HDR_VLAN = 0x00000002,
- ICE_FLOW_SEG_HDR_IPV4 = 0x00000004,
- ICE_FLOW_SEG_HDR_IPV6 = 0x00000008,
- ICE_FLOW_SEG_HDR_ARP = 0x00000010,
- ICE_FLOW_SEG_HDR_ICMP = 0x00000020,
- ICE_FLOW_SEG_HDR_TCP = 0x00000040,
- ICE_FLOW_SEG_HDR_UDP = 0x00000080,
- ICE_FLOW_SEG_HDR_SCTP = 0x00000100,
- ICE_FLOW_SEG_HDR_GRE = 0x00000200,
+ ICE_FLOW_SEG_HDR_NONE = 0x00000000,
+ ICE_FLOW_SEG_HDR_ETH = 0x00000001,
+ ICE_FLOW_SEG_HDR_VLAN = 0x00000002,
+ ICE_FLOW_SEG_HDR_IPV4 = 0x00000004,
+ ICE_FLOW_SEG_HDR_IPV6 = 0x00000008,
+ ICE_FLOW_SEG_HDR_ARP = 0x00000010,
+ ICE_FLOW_SEG_HDR_ICMP = 0x00000020,
+ ICE_FLOW_SEG_HDR_TCP = 0x00000040,
+ ICE_FLOW_SEG_HDR_UDP = 0x00000080,
+ ICE_FLOW_SEG_HDR_SCTP = 0x00000100,
+ ICE_FLOW_SEG_HDR_GRE = 0x00000200,
+ ICE_FLOW_SEG_HDR_GTPC = 0x00000400,
+ ICE_FLOW_SEG_HDR_GTPC_TEID = 0x00000800,
+ ICE_FLOW_SEG_HDR_GTPU_IP = 0x00001000,
+ ICE_FLOW_SEG_HDR_GTPU_DWN = 0x00002000,
+ ICE_FLOW_SEG_HDR_GTPU_UP = 0x00004000,
+ ICE_FLOW_SEG_HDR_PPPOE = 0x00008000,
};
+/* These segements all have the same PTYPES, but are otherwise distinguished by
+ * the value of the gtp_eh_pdu and gtp_eh_pdu_link flags:
+ *
+ * gtp_eh_pdu gtp_eh_pdu_link
+ * ICE_FLOW_SEG_HDR_GTPU_IP 0 0
+ * ICE_FLOW_SEG_HDR_GTPU_DWN 1 0
+ * ICE_FLOW_SEG_HDR_GTPU_UP 1 1
+ */
+#define ICE_FLOW_SEG_HDR_GTPU (ICE_FLOW_SEG_HDR_GTPU_IP | \
+ ICE_FLOW_SEG_HDR_GTPU_DWN | \
+ ICE_FLOW_SEG_HDR_GTPU_UP)
+
enum ice_flow_field {
/* L2 */
ICE_FLOW_FIELD_IDX_ETH_DA,
@@ -95,6 +124,16 @@ enum ice_flow_field {
ICE_FLOW_FIELD_IDX_ICMP_CODE,
/* GRE */
ICE_FLOW_FIELD_IDX_GRE_KEYID,
+ /* GTPC_TEID */
+ ICE_FLOW_FIELD_IDX_GTPC_TEID,
+ /* GTPU_IP */
+ ICE_FLOW_FIELD_IDX_GTPU_IP_TEID,
+ /* GTPU_UP */
+ ICE_FLOW_FIELD_IDX_GTPU_UP_TEID,
+ /* GTPU_DWN */
+ ICE_FLOW_FIELD_IDX_GTPU_DWN_TEID,
+ /* PPPOE */
+ ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID,
/* The total number of enums must not exceed 64 */
ICE_FLOW_FIELD_IDX_MAX
};
diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h
index cfbe3fbfa..29375d3ae 100644
--- a/drivers/net/ice/base/ice_protocol_type.h
+++ b/drivers/net/ice/base/ice_protocol_type.h
@@ -43,6 +43,8 @@ enum ice_protocol_type {
ICE_GENEVE,
ICE_VXLAN_GPE,
ICE_NVGRE,
+ ICE_GTP,
+ ICE_PPPOE,
ICE_PROTOCOL_LAST
};
@@ -55,6 +57,8 @@ enum ice_sw_tunnel_type {
ICE_SW_TUN_UDP, /* This means all "UDP" tunnel types: VXLAN-GPE, VXLAN
* and GENEVE
*/
+ ICE_SW_TUN_GTP,
+ ICE_SW_TUN_PPPOE,
ICE_ALL_TUNNELS /* All tunnel types including NVGRE */
};
@@ -97,6 +101,7 @@ enum ice_prot_id {
ICE_PROT_ICMPV6_IL = 100,
ICE_PROT_VRRP_F = 101,
ICE_PROT_OSPF = 102,
+ ICE_PROT_PPPOE = 103,
ICE_PROT_ATAOE_OF = 114,
ICE_PROT_CTRL_OF = 116,
ICE_PROT_LLDP_OF = 117,
@@ -115,9 +120,9 @@ enum ice_prot_id {
#define ICE_IPV6_OFOS_HW 40
#define ICE_IPV6_IL_HW 41
#define ICE_TCP_IL_HW 49
-#define ICE_UDP_OF_HW 52
#define ICE_UDP_ILOS_HW 53
#define ICE_SCTP_IL_HW 96
+#define ICE_PPPOE_HW 103
/* ICE_UDP_OF is used to identify all 3 tunnel types
* VXLAN, GENEVE and VXLAN_GPE. To differentiate further
@@ -198,6 +203,30 @@ struct ice_udp_tnl_hdr {
u32 vni; /* only use lower 24-bits */
};
+#pragma pack(1)
+struct ice_udp_gtp_hdr {
+ u8 flags;
+ u8 msg_type;
+ u16 rsrvd_len;
+ u32 teid;
+ u16 rsrvd_seq_nbr;
+ u8 rsrvd_n_pdu_nbr;
+ u8 rsrvd_next_ext;
+ u8 rsvrd_ext_len;
+ u8 pdu_type;
+ u8 qfi;
+ u8 rsvrd;
+};
+
+struct ice_pppoe_hdr {
+ u8 rsrvd_ver_type;
+ u8 rsrved_code;
+ u16 session_id;
+ u16 length;
+ u16 ppp_prot_id; /* control and data only */
+};
+#pragma pack()
+
struct ice_nvgre {
u16 flags;
u16 protocol;
@@ -213,6 +242,8 @@ union ice_prot_hdr {
struct ice_sctp_hdr sctp_hdr;
struct ice_udp_tnl_hdr tnl_hdr;
struct ice_nvgre nvgre_hdr;
+ struct ice_udp_gtp_hdr gtp_hdr;
+ struct ice_pppoe_hdr pppoe_hdr;
};
/* This is mapping table entry that maps every word within a given protocol
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index b249a3036..f88addec6 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -380,7 +380,64 @@ dummy_udp_ipv6_packet[] = {
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
-/* this is a recipe to profile bitmap association */
+static const
+struct ice_dummy_pkt_offsets dummy_udp_gtp_packet_offsets[] = {
+ { ICE_MAC_OFOS, 0 },
+ { ICE_IPV4_OFOS, 14 },
+ { ICE_UDP_OF, 34 },
+ { ICE_GTP, 42 },
+ { ICE_PROTOCOL_LAST, 0 },
+};
+
+static const u8
+dummy_udp_gtp_packet[] = {
+ 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x08, 0x00,
+
+ 0x45, 0x00, 0x00, 0x30, /* ICE_IPV4_OFOS 14 */
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x11, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+
+ 0x00, 0x00, 0x08, 0x68, /* ICE_UDP_OF 34 */
+ 0x00, 0x1c, 0x00, 0x00,
+
+ 0x34, 0xff, 0x00, 0x0c, /* ICE_GTP 42 */
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x85,
+
+ 0x02, 0x00, 0x00, 0x00, /* PDU Session extension header */
+ 0x00, 0x00, 0x00, 0x00,
+};
+
+static const
+struct ice_dummy_pkt_offsets dummy_pppoe_packet_offsets[] = {
+ { ICE_MAC_OFOS, 0 },
+ { ICE_PPPOE, 14 },
+ { ICE_PROTOCOL_LAST, 0 },
+};
+
+static const u8
+dummy_pppoe_packet[] = {
+ 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x88, 0x64,
+
+ 0x11, 0x00, 0x00, 0x01, /* ICE_PPPOE 14 */
+ 0x00, 0x4e, 0x00, 0x21,
+
+ 0x45, 0x00, 0x00, 0x30, /* PDU */
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x11, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+};
+
+/* this is a recipe to profile association bitmap */
static ice_declare_bitmap(recipe_to_profile[ICE_MAX_NUM_RECIPES],
ICE_MAX_NUM_PROFILES);
static ice_declare_bitmap(available_result_ids, ICE_CHAIN_FV_INDEX_START + 1);
@@ -4541,6 +4598,8 @@ static const struct ice_prot_ext_tbl_entry ice_prot_ext[] = {
{ ICE_GENEVE, { 8, 10, 12, 14 } },
{ ICE_VXLAN_GPE, { 0, 2, 4 } },
{ ICE_NVGRE, { 0, 2, 4, 6 } },
+ { ICE_GTP, { 8, 10, 12, 14, 16, 18, 20 } },
+ { ICE_PPPOE, { 0, 2, 4, 6 } },
{ ICE_PROTOCOL_LAST, { 0 } }
};
@@ -4577,6 +4636,8 @@ static const struct ice_protocol_entry ice_prot_id_tbl[] = {
{ ICE_GENEVE, ICE_UDP_OF_HW },
{ ICE_VXLAN_GPE, ICE_UDP_OF_HW },
{ ICE_NVGRE, ICE_GRE_OF_HW },
+ { ICE_GTP, ICE_UDP_OF_HW },
+ { ICE_PPPOE, ICE_PPPOE_HW },
{ ICE_PROTOCOL_LAST, 0 }
};
@@ -5418,6 +5479,18 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,
bool tcp = false, udp = false, ipv6 = false;
u16 i;
+ if (tun_type == ICE_SW_TUN_GTP) {
+ *pkt = dummy_udp_gtp_packet;
+ *pkt_len = sizeof(dummy_udp_gtp_packet);
+ *offsets = dummy_udp_gtp_packet_offsets;
+ return;
+ }
+ if (tun_type == ICE_SW_TUN_PPPOE) {
+ *pkt = dummy_pppoe_packet;
+ *pkt_len = sizeof(dummy_pppoe_packet);
+ *offsets = dummy_pppoe_packet_offsets;
+ return;
+ }
for (i = 0; i < lkups_cnt; i++) {
if (lkups[i].type == ICE_UDP_ILOS)
udp = true;
@@ -5564,6 +5637,10 @@ ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,
case ICE_VXLAN_GPE:
len = sizeof(struct ice_udp_tnl_hdr);
break;
+
+ case ICE_GTP:
+ len = sizeof(struct ice_udp_gtp_hdr);
+ break;
default:
return ICE_ERR_PARAM;
}
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 26/63] net/ice/base: add locks for flow functions
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (24 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 25/63] net/ice/base: add support for GTP and PPPoE protocols Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 27/63] net/ice/base: improve switch advanced rule Qi Zhang
` (37 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Vignesh Sridhar, Paul M Stillwell Jr
Wrap functions to search for flow profiles, add and remove RSS
configurations with flow profile locks. This is to ensure that if
several VFs and PFs are disabled at the same time functions that access
the flow profile lists are thread safe.
Signed-off-by: Vignesh Sridhar <vignesh.sridhar@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flow.c | 29 +++++++++++++++++------------
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 0f52b3379..9e93a1078 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -949,8 +949,9 @@ ice_flow_find_prof_conds(struct ice_hw *hw, enum ice_block blk,
enum ice_flow_dir dir, struct ice_flow_seg_info *segs,
u8 segs_cnt, u16 vsi_handle, u32 conds)
{
- struct ice_flow_prof *p;
+ struct ice_flow_prof *p, *prof = NULL;
+ ice_acquire_lock(&hw->fl_profs_locks[blk]);
LIST_FOR_EACH_ENTRY(p, &hw->fl_profs[blk], ice_flow_prof, l_entry) {
if ((p->dir == dir || conds & ICE_FLOW_FIND_PROF_NOT_CHK_DIR) &&
segs_cnt && segs_cnt == p->segs_cnt) {
@@ -972,12 +973,15 @@ ice_flow_find_prof_conds(struct ice_hw *hw, enum ice_block blk,
break;
/* A match is found if all segments are matched */
- if (i == segs_cnt)
- return p;
+ if (i == segs_cnt) {
+ prof = p;
+ break;
+ }
}
}
+ ice_release_lock(&hw->fl_profs_locks[blk]);
- return NULL;
+ return prof;
}
/**
@@ -994,10 +998,8 @@ ice_flow_find_prof(struct ice_hw *hw, enum ice_block blk, enum ice_flow_dir dir,
{
struct ice_flow_prof *p;
- ice_acquire_lock(&hw->fl_profs_locks[blk]);
p = ice_flow_find_prof_conds(hw, blk, dir, segs, segs_cnt,
ICE_MAX_VSI, ICE_FLOW_FIND_PROF_CHK_FLDS);
- ice_release_lock(&hw->fl_profs_locks[blk]);
return p ? p->id : ICE_FLOW_PROF_ID_INVAL;
}
@@ -1497,9 +1499,12 @@ ice_flow_add_entry(struct ice_hw *hw, enum ice_block blk, u64 prof_id,
goto out;
}
- ice_acquire_lock(&prof->entries_lock);
- LIST_ADD(&e->l_entry, &prof->entries);
- ice_release_lock(&prof->entries_lock);
+ if (blk != ICE_BLK_ACL) {
+ /* ACL will handle the entry management */
+ ice_acquire_lock(&prof->entries_lock);
+ LIST_ADD(&e->l_entry, &prof->entries);
+ ice_release_lock(&prof->entries_lock);
+ }
*entry_h = ICE_FLOW_ENTRY_HNDL(e);
@@ -1930,7 +1935,7 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
/* Remove profile if it has no VSIs associated */
if (!ice_is_any_bit_set(prof->vsis, ICE_MAX_VSI)) {
- status = ice_flow_rem_prof_sync(hw, blk, prof);
+ status = ice_flow_rem_prof(hw, blk, prof->id);
if (status)
goto exit;
}
@@ -1963,7 +1968,7 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
* be removed.
*/
if (status) {
- ice_flow_rem_prof_sync(hw, blk, prof);
+ ice_flow_rem_prof(hw, blk, prof->id);
goto exit;
}
@@ -2047,7 +2052,7 @@ ice_rem_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
ice_rem_rss_list(hw, vsi_handle, prof);
if (!ice_is_any_bit_set(prof->vsis, ICE_MAX_VSI))
- status = ice_flow_rem_prof_sync(hw, blk, prof);
+ status = ice_flow_rem_prof(hw, blk, prof->id);
out:
ice_free(hw, segs);
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 27/63] net/ice/base: improve switch advanced rule
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (25 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 26/63] net/ice/base: add locks for flow functions Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 28/63] net/ice/base: move function declaration Qi Zhang
` (36 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
Correct algorithm to detect free field vector indexes to be
used for recipe line result values. The code now scans all
recipes that are associated with all the field vector being
targed for a new recipe to detect which result indexes are
unused.
Change recipe chaining code to place recipe on a single line
if it will fit, rather than looking to break things apart
according to preferred combinations.
These improvements fix a condition where recipes were getting
added with conflicting result index values.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_bitops.h | 31 ++++
drivers/net/ice/base/ice_switch.c | 354 +++++++++++++++++++++++++++++---------
drivers/net/ice/base/ice_switch.h | 5 +
3 files changed, 309 insertions(+), 81 deletions(-)
diff --git a/drivers/net/ice/base/ice_bitops.h b/drivers/net/ice/base/ice_bitops.h
index a3a67eb4b..f0aa8ce88 100644
--- a/drivers/net/ice/base/ice_bitops.h
+++ b/drivers/net/ice/base/ice_bitops.h
@@ -229,6 +229,37 @@ ice_or_bitmap(ice_bitmap_t *dst, const ice_bitmap_t *bmp1,
}
/**
+ * ice_xor_bitmap - bitwise XOR 2 bitmaps and store result in dst bitmap
+ * @dst: Destination bitmap that receive the result of the operation
+ * @bmp1: The first bitmap of XOR operation
+ * @bmp2: The second bitmap to XOR with the first
+ * @size: Size of the bitmaps in bits
+ *
+ * This function performs a bitwise XOR on two "source" bitmaps of the same size
+ * and stores the result to "dst" bitmap. The "dst" bitmap must be of the same
+ * size as the "source" bitmaps to avoid buffer overflows.
+ */
+static inline void
+ice_xor_bitmap(ice_bitmap_t *dst, const ice_bitmap_t *bmp1,
+ const ice_bitmap_t *bmp2, u16 size)
+{
+ ice_bitmap_t mask;
+ u16 i;
+
+ /* Handle all but last chunk*/
+ for (i = 0; i < BITS_TO_CHUNKS(size) - 1; i++)
+ dst[i] = bmp1[i] ^ bmp2[i];
+
+ /* We want to only XOR bits within the size. Furthermore, we also do
+ * not want to modify destination bits which are beyond the specified
+ * size. Use a bitmask to ensure that we only modify the bits that are
+ * within the specified size.
+ */
+ mask = LAST_CHUNK_MASK(size);
+ dst[i] = (dst[i] & ~mask) | ((bmp1[i] ^ bmp2[i]) & mask);
+}
+
+/**
* ice_find_next_bit - Find the index of the next set bit of a bitmap
* @bitmap: the bitmap to scan
* @size: the size in bits of the bitmap
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index f88addec6..2b0c7c7a3 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -440,11 +440,47 @@ dummy_pppoe_packet[] = {
/* this is a recipe to profile association bitmap */
static ice_declare_bitmap(recipe_to_profile[ICE_MAX_NUM_RECIPES],
ICE_MAX_NUM_PROFILES);
-static ice_declare_bitmap(available_result_ids, ICE_CHAIN_FV_INDEX_START + 1);
+
+/* this is a profile to recipe association bitmap */
+static ice_declare_bitmap(profile_to_recipe[ICE_MAX_NUM_PROFILES],
+ ICE_MAX_NUM_RECIPES);
static void ice_get_recp_to_prof_map(struct ice_hw *hw);
/**
+ * ice_collect_result_idx - copy result index values
+ * @buf: buffer that contains the result index
+ * @recp: the recipe struct to copy data into
+ */
+static void ice_collect_result_idx(struct ice_aqc_recipe_data_elem *buf,
+ struct ice_sw_recipe *recp)
+{
+ if (buf->content.result_indx & ICE_AQ_RECIPE_ID_IS_ROOT)
+ ice_set_bit(buf->content.result_indx &
+ ~ICE_AQ_RECIPE_ID_IS_ROOT, recp->res_idxs);
+}
+
+/**
+ * ice_collect_result_idx_from_bitmap - copy result index values using bitmap
+ * @hw: pointer to hardware structure
+ * @recp: the recipe struct to copy data into
+ */
+static void
+ice_collect_result_idx_from_bitmap(struct ice_hw *hw,
+ struct ice_sw_recipe *recp)
+{
+ u16 bit = 0;
+
+ while (ICE_MAX_NUM_RECIPES >
+ (bit = ice_find_next_bit(recp->r_bitmap, ICE_MAX_NUM_RECIPES,
+ bit))) {
+ ice_collect_result_idx(hw->switch_info->recp_list[bit].root_buf,
+ recp);
+ bit++;
+ }
+}
+
+/**
* ice_get_recp_frm_fw - update SW bookkeeping from FW recipe entries
* @hw: pointer to hardware structure
* @recps: struct that we need to populate
@@ -466,6 +502,7 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
u16 num_recps = ICE_MAX_NUM_RECIPES;
struct ice_prot_lkup_ext *lkup_exts;
enum ice_status status;
+ u8 is_root;
/* we need a buffer big enough to accommodate all the recipes */
tmp = (struct ice_aqc_recipe_data_elem *)ice_calloc(hw,
@@ -507,14 +544,10 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
status = ICE_ERR_NO_MEMORY;
goto err_unroll;
}
- /* Avoid 8th bit since its result enable bit */
+ /* When copying, clear the result index enable bit */
result_idxs[result_idx] = root_bufs.content.result_indx &
~ICE_AQ_RECIPE_RESULT_EN;
- /* Check if result enable bit is set */
- if (root_bufs.content.result_indx & ICE_AQ_RECIPE_RESULT_EN)
- ice_clear_bit(ICE_CHAIN_FV_INDEX_START -
- result_idxs[result_idx++],
- available_result_ids);
+
ice_memcpy(r_bitmap,
recipe_to_profile[tmp[sub_recps].recipe_indx],
sizeof(r_bitmap), ICE_NONDMA_TO_NONDMA);
@@ -566,9 +599,29 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
ice_memcpy(recps[rid].root_buf, tmp, recps[rid].n_grp_count *
sizeof(*recps[rid].root_buf), ICE_NONDMA_TO_NONDMA);
+
+ ice_memcpy(recps[rid].r_bitmap, tmp->recipe_bitmap,
+ sizeof(recps[rid].r_bitmap), ICE_NONDMA_TO_NONDMA);
+
+ if (tmp->content.result_indx & ICE_AQ_RECIPE_RESULT_EN)
+ recps[rid].chain_idx = tmp->content.result_indx &
+ ~ICE_AQ_RECIPE_RESULT_EN;
+ else
+ recps[rid].chain_idx = ICE_INVAL_CHAIN_IND;
+
+ recps[rid].root_rid = tmp->content.rid & ~ICE_AQ_RECIPE_ID_IS_ROOT;
+ is_root = (tmp->content.rid & ICE_AQ_RECIPE_ID_IS_ROOT) != 0;
+ recps[rid].is_root = is_root;
+ recps[rid].big_recp = (is_root && recps[rid].n_grp_count > 1);
+
+ /* Copy non-result fv index values to recipe. This call will also update
+ * the result index bitmap appropriately.
+ */
+ ice_collect_result_idx_from_bitmap(hw, &recps[rid]);
+
+ recps[rid].priority = tmp->content.act_ctrl_fwd_priority;
recps[rid].recp_created = true;
- if (tmp[sub_recps].content.rid & ICE_AQ_RECIPE_ID_IS_ROOT)
- recps[rid].root_rid = rid;
+
err_unroll:
ice_free(hw, tmp);
return status;
@@ -591,10 +644,12 @@ ice_get_recp_to_prof_map(struct ice_hw *hw)
for (i = 0; i < ICE_MAX_NUM_PROFILES; i++) {
u16 j;
+ ice_zero_bitmap(profile_to_recipe[i], ICE_MAX_NUM_RECIPES);
ice_zero_bitmap(r_bitmap, ICE_MAX_NUM_RECIPES);
if (ice_aq_get_recipe_to_profile(hw, i, (u8 *)r_bitmap, NULL))
continue;
-
+ ice_memcpy(profile_to_recipe[i], r_bitmap,
+ sizeof(profile_to_recipe[i]), ICE_NONDMA_TO_NONDMA);
for (j = 0; j < ICE_MAX_NUM_RECIPES; j++)
if (ice_is_bit_set(r_bitmap, j))
ice_set_bit(i, recipe_to_profile[j]);
@@ -1443,7 +1498,7 @@ ice_aq_sw_rules(struct ice_hw *hw, void *rule_list, u16 rule_list_sz,
{
struct ice_aq_desc desc;
- ice_debug(hw, ICE_DBG_TRACE, "ice_aq_sw_rules");
+ ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
if (opc != ice_aqc_opc_add_sw_rules &&
opc != ice_aqc_opc_update_sw_rules &&
@@ -1476,7 +1531,7 @@ ice_aq_add_recipe(struct ice_hw *hw,
struct ice_aq_desc desc;
u16 buf_size;
- ice_debug(hw, ICE_DBG_TRACE, "ice_aq_add_recipe");
+ ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
cmd = &desc.params.add_get_recipe;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_recipe);
@@ -1518,7 +1573,7 @@ ice_aq_get_recipe(struct ice_hw *hw,
if (*num_recipes != ICE_MAX_NUM_RECIPES)
return ICE_ERR_PARAM;
- ice_debug(hw, ICE_DBG_TRACE, "ice_aq_get_recipe");
+ ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
cmd = &desc.params.add_get_recipe;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_recipe);
@@ -1549,7 +1604,7 @@ ice_aq_map_recipe_to_profile(struct ice_hw *hw, u32 profile_id, u8 *r_bitmap,
struct ice_aqc_recipe_to_profile *cmd;
struct ice_aq_desc desc;
- ice_debug(hw, ICE_DBG_TRACE, "ice_aq_assoc_recipe_to_prof");
+ ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
cmd = &desc.params.recipe_to_profile;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_recipe_to_profile);
cmd->profile_id = CPU_TO_LE16(profile_id);
@@ -1578,7 +1633,7 @@ ice_aq_get_recipe_to_profile(struct ice_hw *hw, u32 profile_id, u8 *r_bitmap,
struct ice_aq_desc desc;
enum ice_status status;
- ice_debug(hw, ICE_DBG_TRACE, "ice_aq_get_recipe_to_prof");
+ ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
cmd = &desc.params.recipe_to_profile;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_recipe_to_profile);
cmd->profile_id = CPU_TO_LE16(profile_id);
@@ -2917,7 +2972,7 @@ ice_aq_get_res_descs(struct ice_hw *hw, u16 num_entries,
struct ice_aq_desc desc;
enum ice_status status;
- ice_debug(hw, ICE_DBG_TRACE, "ice_aq_get_res_descs");
+ ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
cmd = &desc.params.get_res_desc;
@@ -4001,7 +4056,7 @@ ice_set_vsi_promisc(struct ice_hw *hw, u16 vsi_handle, u8 promisc_mask, u16 vid)
int pkt_type;
u8 recipe_id;
- ice_debug(hw, ICE_DBG_TRACE, "ice_set_vsi_promisc\n");
+ ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
if (!ice_is_vsi_valid(hw, vsi_handle))
return ICE_ERR_PARAM;
@@ -4219,7 +4274,7 @@ ice_remove_vsi_lkup_fltr(struct ice_hw *hw, u16 vsi_handle,
*/
void ice_remove_vsi_fltr(struct ice_hw *hw, u16 vsi_handle)
{
- ice_debug(hw, ICE_DBG_TRACE, "ice_remove_vsi_fltr\n");
+ ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
ice_remove_vsi_lkup_fltr(hw, vsi_handle, ICE_SW_LKUP_MAC);
ice_remove_vsi_lkup_fltr(hw, vsi_handle, ICE_SW_LKUP_MAC_VLAN);
@@ -4654,11 +4709,6 @@ static u16 ice_find_recp(struct ice_hw *hw, struct ice_prot_lkup_ext *lkup_exts)
struct ice_sw_recipe *recp;
u16 i;
- /* Initialize available_result_ids which tracks available result idx */
- for (i = 0; i <= ICE_CHAIN_FV_INDEX_START; i++)
- ice_set_bit(ICE_CHAIN_FV_INDEX_START - i,
- available_result_ids);
-
/* Walk through existing recipes to find a match */
recp = hw->switch_info->recp_list;
for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
@@ -4942,19 +4992,102 @@ ice_fill_fv_word_index(struct ice_hw *hw, struct LIST_HEAD_TYPE *fv_list,
}
/**
+ * ice_find_free_recp_res_idx - find free result indexes for recipe
+ * @hw: pointer to hardware structure
+ * @profiles: bitmap of profiles that will be associated with the new recipe
+ * @free_idx: pointer to variable to receive the free index bitmap
+ *
+ * The algorithm used here is:
+ * 1. When creating a new recipe, create a set P which contains all
+ * Profiles that will be associated with our new recipe
+ *
+ * 2. For each Profile p in set P:
+ * a. Add all recipes associated with Profile p into set R
+ * b. Optional : PossibleIndexes &= profile[p].possibleIndexes
+ * [initially PossibleIndexes should be 0xFFFFFFFFFFFFFFFF]
+ * i. Or just assume they all have the same possible indexes:
+ * 44, 45, 46, 47
+ * i.e., PossibleIndexes = 0x0000F00000000000
+ *
+ * 3. For each Recipe r in set R:
+ * a. UsedIndexes |= (bitwise or ) recipe[r].res_indexes
+ * b. FreeIndexes = UsedIndexes ^ PossibleIndexes
+ *
+ * FreeIndexes will contain the bits indicating the indexes free for use,
+ * then the code needs to update the recipe[r].used_result_idx_bits to
+ * indicate which indexes were selected for use by this recipe.
+ */
+static u16
+ice_find_free_recp_res_idx(struct ice_hw *hw, const ice_bitmap_t *profiles,
+ ice_bitmap_t *free_idx)
+{
+ ice_declare_bitmap(possible_idx, ICE_MAX_FV_WORDS);
+ ice_declare_bitmap(used_idx, ICE_MAX_FV_WORDS);
+ ice_declare_bitmap(recipes, ICE_MAX_NUM_RECIPES);
+ u16 count = 0;
+ u16 bit;
+
+ ice_zero_bitmap(possible_idx, ICE_MAX_FV_WORDS);
+ ice_zero_bitmap(free_idx, ICE_MAX_FV_WORDS);
+ ice_zero_bitmap(used_idx, ICE_MAX_FV_WORDS);
+ ice_zero_bitmap(recipes, ICE_MAX_NUM_RECIPES);
+
+ for (bit = 0; bit < ICE_MAX_FV_WORDS; bit++)
+ if (ICE_POSSIBLE_RES_IDX & BIT_ULL(bit))
+ ice_set_bit(bit, possible_idx);
+
+ /* For each profile we are going to associate the recipe with, add the
+ * recipes that are associated with that profile. This will give us
+ * the set of recipes that our recipe may collide with.
+ */
+ bit = 0;
+ while (ICE_MAX_NUM_PROFILES >
+ (bit = ice_find_next_bit(profiles, ICE_MAX_NUM_PROFILES, bit))) {
+ ice_or_bitmap(recipes, recipes, profile_to_recipe[bit],
+ ICE_MAX_NUM_RECIPES);
+
+ bit++;
+ }
+
+ /* For each recipe that our new recipe may collide with, determine
+ * which indexes have been used.
+ */
+ for (bit = 0; bit < ICE_MAX_NUM_RECIPES; bit++)
+ if (ice_is_bit_set(recipes, bit))
+ ice_or_bitmap(used_idx, used_idx,
+ hw->switch_info->recp_list[bit].res_idxs,
+ ICE_MAX_FV_WORDS);
+
+ ice_xor_bitmap(free_idx, used_idx, possible_idx, ICE_MAX_FV_WORDS);
+
+ /* return number of free indexes */
+ bit = 0;
+ while (ICE_MAX_FV_WORDS >
+ (bit = ice_find_next_bit(free_idx, ICE_MAX_FV_WORDS, bit))) {
+ count++;
+ bit++;
+ }
+
+ return count;
+}
+
+/**
* ice_add_sw_recipe - function to call AQ calls to create switch recipe
* @hw: pointer to hardware structure
* @rm: recipe management list entry
* @match_tun: if field vector index for tunnel needs to be programmed
+ * @profiles: bitmap of profiles that will be assocated.
*/
static enum ice_status
ice_add_sw_recipe(struct ice_hw *hw, struct ice_sw_recipe *rm,
- bool match_tun)
+ bool match_tun, ice_bitmap_t *profiles)
{
+ ice_declare_bitmap(result_idx_bm, ICE_MAX_FV_WORDS);
struct ice_aqc_recipe_data_elem *tmp;
struct ice_aqc_recipe_data_elem *buf;
struct ice_recp_grp_entry *entry;
enum ice_status status;
+ u16 free_res_idx;
u16 recipe_count;
u8 chain_idx;
u8 recps = 0;
@@ -4964,11 +5097,16 @@ ice_add_sw_recipe(struct ice_hw *hw, struct ice_sw_recipe *rm,
* the match fields in the chaining recipe reducing the number of
* chained recipes by one.
*/
- if (rm->n_grp_count > 1)
+ /* check number of free result indices */
+ ice_zero_bitmap(result_idx_bm, ICE_MAX_FV_WORDS);
+ free_res_idx = ice_find_free_recp_res_idx(hw, profiles, result_idx_bm);
+
+ if (rm->n_grp_count > 1) {
+ if (rm->n_grp_count > free_res_idx)
+ return ICE_ERR_MAX_LIMIT;
+
rm->n_grp_count++;
- if (rm->n_grp_count > ICE_MAX_CHAIN_RECIPE ||
- (match_tun && rm->n_grp_count > (ICE_MAX_CHAIN_RECIPE - 1)))
- return ICE_ERR_MAX_LIMIT;
+ }
tmp = (struct ice_aqc_recipe_data_elem *)ice_calloc(hw,
ICE_MAX_NUM_RECIPES,
@@ -4993,9 +5131,7 @@ ice_add_sw_recipe(struct ice_hw *hw, struct ice_sw_recipe *rm,
/* Allocate the recipe resources, and configure them according to the
* match fields from protocol headers and extracted field vectors.
*/
- chain_idx = ICE_CHAIN_FV_INDEX_START -
- ice_find_first_bit(available_result_ids,
- ICE_CHAIN_FV_INDEX_START + 1);
+ chain_idx = ice_find_first_bit(result_idx_bm, ICE_MAX_FV_WORDS);
LIST_FOR_EACH_ENTRY(entry, &rm->rg_list, ice_recp_grp_entry, l_entry) {
u8 i;
@@ -5037,17 +5173,24 @@ ice_add_sw_recipe(struct ice_hw *hw, struct ice_sw_recipe *rm,
}
if (rm->n_grp_count > 1) {
+ /* Checks to see if there really is a valid result index
+ * that can be used.
+ */
+ if (chain_idx >= ICE_MAX_FV_WORDS) {
+ ice_debug(hw, ICE_DBG_SW,
+ "No chain index available\n");
+ status = ICE_ERR_MAX_LIMIT;
+ goto err_unroll;
+ }
+
entry->chain_idx = chain_idx;
buf[recps].content.result_indx =
ICE_AQ_RECIPE_RESULT_EN |
((chain_idx << ICE_AQ_RECIPE_RESULT_DATA_S) &
ICE_AQ_RECIPE_RESULT_DATA_M);
- ice_clear_bit(ICE_CHAIN_FV_INDEX_START - chain_idx,
- available_result_ids);
- chain_idx = ICE_CHAIN_FV_INDEX_START -
- ice_find_first_bit(available_result_ids,
- ICE_CHAIN_FV_INDEX_START +
- 1);
+ ice_clear_bit(chain_idx, result_idx_bm);
+ chain_idx = ice_find_first_bit(result_idx_bm,
+ ICE_MAX_FV_WORDS);
}
/* fill recipe dependencies */
@@ -5172,19 +5315,55 @@ ice_add_sw_recipe(struct ice_hw *hw, struct ice_sw_recipe *rm,
*/
LIST_FOR_EACH_ENTRY(entry, &rm->rg_list, ice_recp_grp_entry, l_entry) {
struct ice_switch_info *sw = hw->switch_info;
+ bool is_root, idx_found = false;
struct ice_sw_recipe *recp;
+ u16 idx, buf_idx = 0;
+
+ /* find buffer index for copying some data */
+ for (idx = 0; idx < rm->n_grp_count; idx++)
+ if (buf[idx].recipe_indx == entry->rid) {
+ buf_idx = idx;
+ idx_found = true;
+ }
+
+ if (!idx_found) {
+ status = ICE_ERR_OUT_OF_RANGE;
+ goto err_unroll;
+ }
recp = &sw->recp_list[entry->rid];
+ is_root = (rm->root_rid == entry->rid);
+ recp->is_root = is_root;
+
recp->root_rid = entry->rid;
+ recp->big_recp = (is_root && rm->n_grp_count > 1);
+
ice_memcpy(&recp->ext_words, entry->r_group.pairs,
entry->r_group.n_val_pairs *
sizeof(struct ice_fv_word),
ICE_NONDMA_TO_NONDMA);
+ ice_memcpy(recp->r_bitmap, buf[buf_idx].recipe_bitmap,
+ sizeof(recp->r_bitmap), ICE_NONDMA_TO_NONDMA);
+
+ /* Copy non-result fv index values and masks to recipe. This
+ * call will also update the result recipe bitmask.
+ */
+ ice_collect_result_idx(&buf[buf_idx], recp);
+
+ /* for non-root recipes, also copy to the root, this allows
+ * easier matching of a complete chained recipe
+ */
+ if (!is_root)
+ ice_collect_result_idx(&buf[buf_idx],
+ &sw->recp_list[rm->root_rid]);
+
recp->n_ext_words = entry->r_group.n_val_pairs;
recp->chain_idx = entry->chain_idx;
+ recp->priority = buf[buf_idx].content.act_ctrl_fwd_priority;
+ recp->tun_type = rm->tun_type;
recp->recp_created = true;
- recp->big_recp = false;
+ recp->adv_rule = 1;
}
rm->root_buf = buf;
ice_free(hw, tmp);
@@ -5215,36 +5394,42 @@ ice_create_recipe_group(struct ice_hw *hw, struct ice_sw_recipe *rm,
rm->n_grp_count = 0;
- /* Each switch recipe can match up to 5 words or metadata. One word in
- * each recipe is used to match the switch ID. Four words are left for
- * matching other values. If the new advanced recipe requires more than
- * 4 words, it needs to be split into multiple recipes which are chained
- * together using the intermediate result that each produces as input to
- * the other recipes in the sequence.
- */
- groups = ARRAY_SIZE(ice_recipe_pack);
- /* Check if any of the preferred recipes from the grouping policy
- * matches.
- */
- for (i = 0; i < groups; i++)
- /* Check if the recipe from the preferred grouping matches
- * or is a subset of the fields that needs to be looked up.
+ if (lkup_exts->n_val_words > ICE_NUM_WORDS_RECIPE) {
+ /* Each switch recipe can match up to 5 words or metadata. One
+ * word in each recipe is used to match the switch ID. Four
+ * words are left for matching other values. If the new advanced
+ * recipe requires more than 4 words, it needs to be split into
+ * multiple recipes which are chained together using the
+ * intermediate result that each produces as input to the other
+ * recipes in the sequence.
*/
- if (ice_is_recipe_subset(lkup_exts, &ice_recipe_pack[i])) {
- /* This recipe can be used by itself or grouped with
- * other recipes.
+ groups = ARRAY_SIZE(ice_recipe_pack);
+
+ /* Check if any of the preferred recipes from the grouping
+ * policy matches.
+ */
+ for (i = 0; i < groups; i++)
+ /* Check if the recipe from the preferred grouping
+ * matches or is a subset of the fields that needs to be
+ * looked up.
*/
- entry = (struct ice_recp_grp_entry *)
- ice_malloc(hw, sizeof(*entry));
- if (!entry) {
- status = ICE_ERR_NO_MEMORY;
- goto err_unroll;
+ if (ice_is_recipe_subset(lkup_exts,
+ &ice_recipe_pack[i])) {
+ /* This recipe can be used by itself or grouped
+ * with other recipes.
+ */
+ entry = (struct ice_recp_grp_entry *)
+ ice_malloc(hw, sizeof(*entry));
+ if (!entry) {
+ status = ICE_ERR_NO_MEMORY;
+ goto err_unroll;
+ }
+ entry->r_group = ice_recipe_pack[i];
+ LIST_ADD(&entry->l_entry, &rm->rg_list);
+ rm->n_grp_count++;
}
- entry->r_group = ice_recipe_pack[i];
- LIST_ADD(&entry->l_entry, &rm->rg_list);
- rm->n_grp_count++;
- }
+ }
/* Create recipes for words that are marked not done by packing them
* as best fit.
@@ -5319,6 +5504,7 @@ static enum ice_status
ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
u16 lkups_cnt, struct ice_adv_rule_info *rinfo, u16 *rid)
{
+ ice_declare_bitmap(profiles, ICE_MAX_NUM_PROFILES);
struct ice_prot_lkup_ext *lkup_exts;
struct ice_recp_grp_entry *r_entry;
struct ice_sw_fv_list_entry *fvit;
@@ -5355,13 +5541,6 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
}
}
- *rid = ice_find_recp(hw, lkup_exts);
- if (*rid < ICE_MAX_NUM_RECIPES)
- /* Success if found a recipe that match the existing criteria */
- goto err_free_lkup_exts;
-
- /* Recipe we need does not exist, add a recipe */
-
rm = (struct ice_sw_recipe *)ice_malloc(hw, sizeof(*rm));
if (!rm) {
status = ICE_ERR_NO_MEMORY;
@@ -5401,7 +5580,23 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
* recipes.
*/
ice_fill_fv_word_index(hw, &rm->fv_list, &rm->rg_list);
- status = ice_add_sw_recipe(hw, rm, match_tun);
+
+ /* get bitmap of all profiles the recipe will be associated with */
+ ice_zero_bitmap(profiles, ICE_MAX_NUM_PROFILES);
+ LIST_FOR_EACH_ENTRY(fvit, &rm->fv_list, ice_sw_fv_list_entry,
+ list_entry) {
+ ice_debug(hw, ICE_DBG_SW, "profile: %d\n", fvit->profile_id);
+ ice_set_bit((u16)fvit->profile_id, profiles);
+ }
+
+ /* Look for a recipe which matches our requested fv / mask list */
+ *rid = ice_find_recp(hw, lkup_exts);
+ if (*rid < ICE_MAX_NUM_RECIPES)
+ /* Success if found a recipe that match the existing criteria */
+ goto err_unroll;
+
+ /* Recipe we need does not exist, add a recipe */
+ status = ice_add_sw_recipe(hw, rm, match_tun, profiles);
if (status)
goto err_unroll;
@@ -5851,27 +6046,24 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
struct ice_switch_info *sw;
enum ice_status status;
const u8 *pkt = NULL;
- bool found = false;
+ u16 word_cnt;
u32 act = 0;
u8 q_rgn;
if (!lkups_cnt)
return ICE_ERR_PARAM;
+ /* get # of words we need to match */
+ word_cnt = 0;
for (i = 0; i < lkups_cnt; i++) {
u16 j, *ptr;
- /* Validate match masks to make sure that there is something
- * to match.
- */
ptr = (u16 *)&lkups[i].m_u;
for (j = 0; j < sizeof(lkups->m_u) / sizeof(u16); j++)
- if (ptr[j] != 0) {
- found = true;
- break;
- }
+ if (ptr[j] != 0)
+ word_cnt++;
}
- if (!found)
+ if (!word_cnt || word_cnt > ICE_MAX_CHAIN_WORDS)
return ICE_ERR_PARAM;
/* make sure that we can locate a dummy packet */
diff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h
index 4c34bc2ea..515ad3bb6 100644
--- a/drivers/net/ice/base/ice_switch.h
+++ b/drivers/net/ice/base/ice_switch.h
@@ -183,6 +183,7 @@ struct ice_sw_recipe {
/* For a chained recipe the root recipe is what should be used for
* programming rules
*/
+ u8 is_root;
u8 root_rid;
u8 recp_created;
@@ -226,6 +227,10 @@ struct ice_sw_recipe {
/* Profiles this recipe is associated with */
u8 num_profs, *prof_ids;
+ /* Possible result indexes are 44, 45, 46 and 47 */
+#define ICE_POSSIBLE_RES_IDX 0x0000F00000000000ULL
+ ice_declare_bitmap(res_idxs, ICE_MAX_FV_WORDS);
+
/* This allows user to specify the recipe priority.
* For now, this becomes 'fwd_priority' when recipe
* is created, usually recipes can have 'fwd' and 'join'
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 28/63] net/ice/base: move function declaration
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (26 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 27/63] net/ice/base: improve switch advanced rule Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 29/63] net/ice/base: add 16-byte Flex Rx Descriptor Qi Zhang
` (35 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang; +Cc: dev, xiaolong.ye, Qi Zhang, Paul M Stillwell Jr
Improve code orgnization, move declaration of ice_cfg_tc_nod_bw_alloc and
ice_cfg_rl_burst_size from ice_common.h to ice_nvm.h.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.h | 8 --------
drivers/net/ice/base/ice_nvm.h | 4 ++++
drivers/net/ice/base/ice_sched.h | 4 ++++
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index a55f7eeba..67adc9c59 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -50,10 +50,6 @@ enum ice_status
ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
enum ice_adminq_opc opc, struct ice_sq_cd *cd);
-enum ice_status ice_init_nvm(struct ice_hw *hw);
-enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data);
-enum ice_status
-ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data);
enum ice_status
ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
struct ice_aq_desc *desc, void *buf, u16 buf_size,
@@ -201,10 +197,6 @@ enum ice_status
ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx);
struct ice_q_ctx *
ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle);
-enum ice_status
-ice_cfg_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc,
- enum ice_rl_type rl_type, u8 bw_alloc);
-enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes);
void
ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
u64 *prev_stat, u64 *cur_stat);
diff --git a/drivers/net/ice/base/ice_nvm.h b/drivers/net/ice/base/ice_nvm.h
index da76b2674..d5b7b2d19 100644
--- a/drivers/net/ice/base/ice_nvm.h
+++ b/drivers/net/ice/base/ice_nvm.h
@@ -84,4 +84,8 @@ ice_nvm_access_get_features(struct ice_nvm_access_cmd *cmd,
enum ice_status
ice_handle_nvm_access(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
union ice_nvm_access_data *data);
+enum ice_status ice_init_nvm(struct ice_hw *hw);
+enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data);
+enum ice_status
+ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data);
#endif /* _ICE_NVM_H_ */
diff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h
index 932ae075f..d6b467477 100644
--- a/drivers/net/ice/base/ice_sched.h
+++ b/drivers/net/ice/base/ice_sched.h
@@ -185,4 +185,8 @@ ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw);
enum ice_status
ice_sched_cfg_sibl_node_prio(struct ice_port_info *pi,
struct ice_sched_node *node, u8 priority);
+enum ice_status
+ice_cfg_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc,
+ enum ice_rl_type rl_type, u8 bw_alloc);
+enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes);
#endif /* _ICE_SCHED_H_ */
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 29/63] net/ice/base: add 16-byte Flex Rx Descriptor
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (27 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 28/63] net/ice/base: move function declaration Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 30/63] net/ice/base: add 32-byte Flex Rx Desc for Comms package Qi Zhang
` (34 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
Add 16-byte Flex RX descriptor structure definition.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_lan_tx_rx.h | 28 ++++++++++++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h
index 2cba6bc1e..7c3927ac2 100644
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -373,10 +373,34 @@ enum ice_rx_prog_status_desc_error_bits {
ICE_RX_PROG_STATUS_DESC_NO_FD_ENTRY_S = 1,
};
-/* Rx Flex Descriptor
- * This descriptor is used instead of the legacy version descriptor when
+/* Rx Flex Descriptors
+ * These descriptors are used instead of the legacy version descriptors when
* ice_rlan_ctx.adv_desc is set
*/
+union ice_16b_rx_flex_desc {
+ struct {
+ __le64 pkt_addr; /* Packet buffer address */
+ __le64 hdr_addr; /* Header buffer address */
+ /* bit 0 of hdr_addr is DD bit */
+ } read;
+ struct {
+ /* Qword 0 */
+ u8 rxdid; /* descriptor builder profile ID */
+ u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
+ __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
+ __le16 pkt_len; /* [15:14] are reserved */
+ __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
+ /* sph=[11:11] */
+ /* ff1/ext=[15:12] */
+
+ /* Qword 1 */
+ __le16 status_error0;
+ __le16 l2tag1;
+ __le16 flex_meta0;
+ __le16 flex_meta1;
+ } wb; /* writeback */
+};
+
union ice_32b_rx_flex_desc {
struct {
__le64 pkt_addr; /* Packet buffer address */
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 30/63] net/ice/base: add 32-byte Flex Rx Desc for Comms package
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (28 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 29/63] net/ice/base: add 16-byte Flex Rx Descriptor Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 31/63] net/ice/base: update flag bits to current specification Qi Zhang
` (33 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Junfeng Guo, Paul M Stillwell Jr
Add 32-byte Flex RX Descriptor structure definition to match the
Comms package's design.
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_lan_tx_rx.h | 40 ++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h
index 7c3927ac2..e1c2f0d01 100644
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -619,6 +619,46 @@ struct ice_32b_rx_flex_desc_nic_2 {
} flex_ts;
};
+/* Rx Flex Descriptor for Comms Package Profile
+ * RxDID Profile ID 16-21
+ * Flex-field 0: RSS hash lower 16-bits
+ * Flex-field 1: RSS hash upper 16-bits
+ * Flex-field 2: Flow ID lower 16-bits
+ * Flex-field 3: Flow ID upper 16-bits
+ * Flex-field 4: AUX0
+ * Flex-field 5: AUX1
+ */
+struct ice_32b_rx_flex_desc_comms {
+ /* Qword 0 */
+ u8 rxdid;
+ u8 mir_id_umb_cast;
+ __le16 ptype_flexi_flags0;
+ __le16 pkt_len;
+ __le16 hdr_len_sph_flex_flags1;
+
+ /* Qword 1 */
+ __le16 status_error0;
+ __le16 l2tag1;
+ __le32 rss_hash;
+
+ /* Qword 2 */
+ __le16 status_error1;
+ u8 flexi_flags2;
+ u8 ts_low;
+ __le16 l2tag2_1st;
+ __le16 l2tag2_2nd;
+
+ /* Qword 3 */
+ __le32 flow_id;
+ union {
+ struct {
+ __le16 aux0;
+ __le16 aux1;
+ } flex;
+ __le32 ts_high;
+ } flex_ts;
+};
+
/* Receive Flex Descriptor profile IDs: There are a total
* of 64 profiles where profile IDs 0/1 are for legacy; and
* profiles 2-63 are flex profiles that can be programmed
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 31/63] net/ice/base: update flag bits to current specification
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (29 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 30/63] net/ice/base: add 32-byte Flex Rx Desc for Comms package Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 32/63] net/ice/base: add more opcode and macros Qi Zhang
` (32 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Brett Creeley, Paul M Stillwell Jr
Currently the VLAN ice_flg64_bits are off by 1. Fix this by
setting the ICE_FLG_EVLAN_x8100 flag to 14, which also updates
ICE_FLG_EVLAN_x9100 to 15 and ICE_FLG_VLAN_x8100 to 16.
Signed-off-by: Brett Creeley <brett.creeley@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_lan_tx_rx.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h
index e1c2f0d01..e77d4bf50 100644
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -737,7 +737,7 @@ enum ice_flg64_bits {
ICE_FLG_PKT_DSI = 0,
/* If there is a 1 in this bit position then that means Rx packet */
ICE_FLG_PKT_DIR = 4,
- ICE_FLG_EVLAN_x8100 = 15,
+ ICE_FLG_EVLAN_x8100 = 14,
ICE_FLG_EVLAN_x9100,
ICE_FLG_VLAN_x8100,
ICE_FLG_TNL_MAC = 22,
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 32/63] net/ice/base: add more opcode and macros
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (30 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 31/63] net/ice/base: update flag bits to current specification Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 33/63] net/ice/base: set status when global cfg lock is unavailable Qi Zhang
` (31 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang; +Cc: dev, xiaolong.ye, Qi Zhang, Paul M Stillwell Jr
Add more opcode and macros according to hardware spec.
1. Add opcode for the NVM Update EMPR command.
2. Add opcode for NVM save factory settings
3. Add opcode for NVM Write/Write Activate calls
4. Add loopback reporting to get link response macros
5. Add link event defines macros
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_adminq_cmd.h | 28 +++++++++++++++++++++++-----
1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index cc42180ea..b9e3bd5fa 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1575,7 +1575,12 @@ struct ice_aqc_get_link_status_data {
#define ICE_AQ_LINK_TX_ACTIVE 0
#define ICE_AQ_LINK_TX_DRAINED 1
#define ICE_AQ_LINK_TX_FLUSHED 3
- u8 reserved2;
+ u8 lb_status;
+#define ICE_AQ_LINK_LB_PHY_LCL BIT(0)
+#define ICE_AQ_LINK_LB_PHY_RMT BIT(1)
+#define ICE_AQ_LINK_LB_MAC_LCL BIT(2)
+#define ICE_AQ_LINK_LB_PHY_IDX_S 3
+#define ICE_AQ_LINK_LB_PHY_IDX_M (0x7 << ICE_AQ_LB_PHY_IDX_S)
__le16 max_frame_size;
u8 cfg;
#define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
@@ -1631,6 +1636,8 @@ struct ice_aqc_set_event_mask {
#define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
#define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
#define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
+#define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10)
+#define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11)
u8 reserved1[6];
};
@@ -1690,20 +1697,26 @@ struct ice_aqc_sff_eeprom {
/* NVM Read command (indirect 0x0701)
* NVM Erase commands (direct 0x0702)
- * NVM Update commands (indirect 0x0703)
+ * NVM Write commands (indirect 0x0703)
+ * NVM Write Activate commands (direct 0x0707)
+ * NVM Shadow RAM Dump commands (direct 0x0707)
*/
struct ice_aqc_nvm {
__le16 offset_low;
u8 offset_high;
u8 cmd_flags;
#define ICE_AQC_NVM_LAST_CMD BIT(0)
-#define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */
-#define ICE_AQC_NVM_PRESERVATION_S 1
+#define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */
+#define ICE_AQC_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */
#define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
#define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
#define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
#define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S)
#define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
+#define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */
+#define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4)
+#define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5)
+#define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3)
#define ICE_AQC_NVM_FLASH_ONLY BIT(7)
__le16 module_typeid;
__le16 length;
@@ -2292,6 +2305,7 @@ struct ice_aq_desc {
struct ice_aqc_set_mac_cfg set_mac_cfg;
struct ice_aqc_set_event_mask set_event_mask;
struct ice_aqc_get_link_status get_link_status;
+ struct ice_aqc_event_lan_overflow lan_overflow;
} params;
};
@@ -2465,10 +2479,14 @@ enum ice_adminq_opc {
/* NVM commands */
ice_aqc_opc_nvm_read = 0x0701,
ice_aqc_opc_nvm_erase = 0x0702,
- ice_aqc_opc_nvm_update = 0x0703,
+ ice_aqc_opc_nvm_write = 0x0703,
ice_aqc_opc_nvm_cfg_read = 0x0704,
ice_aqc_opc_nvm_cfg_write = 0x0705,
ice_aqc_opc_nvm_checksum = 0x0706,
+ ice_aqc_opc_nvm_write_activate = 0x0707,
+ ice_aqc_opc_nvm_sr_dump = 0x0707,
+ ice_aqc_opc_nvm_save_factory_settings = 0x0708,
+ ice_aqc_opc_nvm_update_empr = 0x0709,
/* LLDP commands */
ice_aqc_opc_lldp_get_mib = 0x0A00,
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 33/63] net/ice/base: set status when global cfg lock is unavailable
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (31 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 32/63] net/ice/base: add more opcode and macros Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 34/63] net/ice/base: initialize driver NVM data earlier Qi Zhang
` (30 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Anirudh Venkataramanan, Paul M Stillwell Jr
To download the DDP file to the device, a PF first has to grab the
global configuration lock. When a PF can't grab this lock, set
hw->pkg_dwnld_status to ICE_AQ_RC_EEXIST.
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flex_pipe.c | 15 ++++++++++++++-
drivers/net/ice/base/ice_type.h | 2 ++
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index 7daaf10b0..f8dd1c4d1 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -961,9 +961,19 @@ ice_dwnld_cfg_bufs(struct ice_hw *hw, struct ice_buf *bufs, u32 count)
if (LE32_TO_CPU(bh->section_entry[0].type) & ICE_METADATA_BUF)
return ICE_SUCCESS;
+ /* reset pkg_dwnld_status in case this function is called in the
+ * reset/rebuild flow
+ */
+ hw->pkg_dwnld_status = ICE_AQ_RC_OK;
+
status = ice_acquire_global_cfg_lock(hw, ICE_RES_WRITE);
- if (status)
+ if (status) {
+ if (status == ICE_ERR_AQ_NO_WORK)
+ hw->pkg_dwnld_status = ICE_AQ_RC_EEXIST;
+ else
+ hw->pkg_dwnld_status = hw->adminq.sq_last_status;
return status;
+ }
for (i = 0; i < count; i++) {
bool last = ((i + 1) == count);
@@ -986,6 +996,9 @@ ice_dwnld_cfg_bufs(struct ice_hw *hw, struct ice_buf *bufs, u32 count)
status = ice_aq_download_pkg(hw, bh, ICE_PKG_BUF_SIZE, last,
&offset, &info, NULL);
+
+ /* Save AQ status from download package */
+ hw->pkg_dwnld_status = hw->adminq.sq_last_status;
if (status) {
ice_debug(hw, ICE_DBG_PKG,
"Pkg download failed: err %d off %d inf %d\n",
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index dc041760d..541e29851 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -775,6 +775,8 @@ struct ice_hw {
u8 active_pkg_name[ICE_PKG_NAME_SIZE];
u8 active_pkg_in_nvm;
+ enum ice_aq_err pkg_dwnld_status;
+
/* Driver's package ver - (from the Metadata seg) */
struct ice_pkg_ver pkg_ver;
u8 pkg_name[ICE_PKG_NAME_SIZE];
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 34/63] net/ice/base: initialize driver NVM data earlier
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (32 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 33/63] net/ice/base: set status when global cfg lock is unavailable Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 35/63] net/ice/base: add function to configure Tx AQ command Qi Zhang
` (29 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Anirudh Venkataramanan, Paul M Stillwell Jr
The driver detects and warns about FW rollback mode before getting the NVM
version (through ice_init_nvm) which results in "0.00 0x0 0.0.0" being
printed. Fix this by calling ice_init_nvm earlier.
This could have been fixed by moving ice_print_rollback_msg as well, but
it made more sense to move ice_init_nvm closer to the flow that gets the
FW version information (i.e. control queue init flow).
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 36434ee42..e19ce733c 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -759,10 +759,13 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
if (status)
goto err_unroll_cqinit;
+ status = ice_init_nvm(hw);
+ if (status)
+ goto err_unroll_cqinit;
+
if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
ice_print_rollback_msg(hw);
-
status = ice_clear_pf_cfg(hw);
if (status)
goto err_unroll_cqinit;
@@ -773,9 +776,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
ice_clear_pxe_mode(hw);
- status = ice_init_nvm(hw);
- if (status)
- goto err_unroll_cqinit;
status = ice_get_caps(hw);
if (status)
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 35/63] net/ice/base: add function to configure Tx AQ command
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (33 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 34/63] net/ice/base: initialize driver NVM data earlier Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 36/63] net/ice/base: add support for not locking sideband queue Qi Zhang
` (28 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Ben Shelton, Paul M Stillwell Jr
This function is needed by the driver to move PSM leaf nodes to a new
parent.
Additionally, add struct ice_aqc_move_txqs to struct ice_aq_desc so
driver code can access it.
Signed-off-by: Ben Shelton <benjamin.h.shelton@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_adminq_cmd.h | 1 +
drivers/net/ice/base/ice_common.c | 71 +++++++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_common.h | 6 +++
3 files changed, 78 insertions(+)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index b9e3bd5fa..9a063592f 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -2292,6 +2292,7 @@ struct ice_aq_desc {
struct ice_aqc_clear_fd_table clear_fd_table;
struct ice_aqc_add_txqs add_txqs;
struct ice_aqc_dis_txqs dis_txqs;
+ struct ice_aqc_move_txqs move_txqs;
struct ice_aqc_txqs_cleanup txqs_cleanup;
struct ice_aqc_add_get_update_free_vsi vsi_cmd;
struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index e19ce733c..c2d4f1f05 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -3415,6 +3415,77 @@ ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
return status;
}
+/**
+ * ice_aq_move_recfg_lan_txq
+ * @hw: pointer to the hardware structure
+ * @num_qs: number of queues to move/reconfigure
+ * @is_move: true if this operation involves node movement
+ * @is_tc_change: true if this operation involves a TC change
+ * @subseq_call: true if this operation is a subsequent call
+ * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN
+ * @timeout: timeout in units of 100 usec (valid values 0-50)
+ * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN
+ * @buf: struct containing src/dest TEID and per-queue info
+ * @buf_size: size of buffer for indirect command
+ * @txqs_moved: out param, number of queues successfully moved
+ * @cd: pointer to command details structure or NULL
+ *
+ * Move / Reconfigure Tx LAN queues (0x0C32)
+ */
+enum ice_status
+ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
+ bool is_tc_change, bool subseq_call, bool flush_pipe,
+ u8 timeout, u32 *blocked_cgds,
+ struct ice_aqc_move_txqs_data *buf, u16 buf_size,
+ u8 *txqs_moved, struct ice_sq_cd *cd)
+{
+ struct ice_aqc_move_txqs *cmd;
+ struct ice_aq_desc desc;
+ enum ice_status status;
+
+ cmd = &desc.params.move_txqs;
+ ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs);
+
+#define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50
+ if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX)
+ return ICE_ERR_PARAM;
+
+ if (is_tc_change && !flush_pipe && !blocked_cgds)
+ return ICE_ERR_PARAM;
+
+ if (!is_move && !is_tc_change)
+ return ICE_ERR_PARAM;
+
+ desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
+
+ if (is_move)
+ cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE;
+
+ if (is_tc_change)
+ cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE;
+
+ if (subseq_call)
+ cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL;
+
+ if (flush_pipe)
+ cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE;
+
+ cmd->num_qs = num_qs;
+ cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) &
+ ICE_AQC_Q_CMD_TIMEOUT_M);
+
+ status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
+
+ if (!status && txqs_moved)
+ *txqs_moved = cmd->num_qs;
+
+ if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN &&
+ is_tc_change && !flush_pipe)
+ *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds);
+
+ return status;
+}
+
/* End of FW Admin Queue command wrappers */
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index 67adc9c59..c42c58670 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -106,6 +106,12 @@ enum ice_status
ice_aq_add_lan_txq(struct ice_hw *hw, u8 count,
struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
struct ice_sq_cd *cd);
+enum ice_status
+ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
+ bool is_tc_change, bool subseq_call, bool flush_pipe,
+ u8 timeout, u32 *blocked_cgds,
+ struct ice_aqc_move_txqs_data *buf, u16 buf_size,
+ u8 *txqs_moved, struct ice_sq_cd *cd);
bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq);
enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 36/63] net/ice/base: add support for not locking sideband queue
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (34 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 35/63] net/ice/base: add function to configure Tx AQ command Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 37/63] net/ice/base: associate recipes by profile type Qi Zhang
` (27 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Ben Shelton, Paul M Stillwell Jr
For certain PTP clock adjustments, there is a use case for locking the
sideband queue at a higher level and performing an atomic series of
operations while the sideband queue is locked. To accommodate this use
case, split ice_sw_send_cmd() into a version that takes the lock and a
version that does not.
Signed-off-by: Ben Shelton <benjamin.h.shelton@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_controlq.c | 40 +++++++++++++++++++++++++++++++------
1 file changed, 34 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c
index 8070bb9a7..70a50bff4 100644
--- a/drivers/net/ice/base/ice_controlq.c
+++ b/drivers/net/ice/base/ice_controlq.c
@@ -859,7 +859,7 @@ static bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq)
}
/**
- * ice_sq_send_cmd - send command to Control Queue (ATQ)
+ * ice_sq_send_cmd_nolock - send command to Control Queue (ATQ)
* @hw: pointer to the HW struct
* @cq: pointer to the specific Control queue
* @desc: prefilled descriptor describing the command (non DMA mem)
@@ -870,10 +870,10 @@ static bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq)
* This is the main send command routine for the ATQ. It runs the queue,
* cleans the queue, etc.
*/
-enum ice_status
-ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
- struct ice_aq_desc *desc, void *buf, u16 buf_size,
- struct ice_sq_cd *cd)
+static enum ice_status
+ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
+ struct ice_aq_desc *desc, void *buf, u16 buf_size,
+ struct ice_sq_cd *cd)
{
struct ice_dma_mem *dma_buf = NULL;
struct ice_aq_desc *desc_on_ring;
@@ -887,7 +887,6 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
/* if reset is in progress return a soft error */
if (hw->reset_ongoing)
return ICE_ERR_RESET_ONGOING;
- ice_acquire_lock(&cq->sq_lock);
cq->sq_last_status = ICE_AQ_RC_OK;
@@ -1040,7 +1039,36 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
}
sq_send_command_error:
+ return status;
+}
+
+/**
+ * ice_sq_send_cmd - send command to Control Queue (ATQ)
+ * @hw: pointer to the HW struct
+ * @cq: pointer to the specific Control queue
+ * @desc: prefilled descriptor describing the command (non DMA mem)
+ * @buf: buffer to use for indirect commands (or NULL for direct commands)
+ * @buf_size: size of buffer for indirect commands (or 0 for direct commands)
+ * @cd: pointer to command details structure
+ *
+ * This is the main send command routine for the ATQ. It runs the queue,
+ * cleans the queue, etc.
+ */
+enum ice_status
+ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
+ struct ice_aq_desc *desc, void *buf, u16 buf_size,
+ struct ice_sq_cd *cd)
+{
+ enum ice_status status = ICE_SUCCESS;
+
+ /* if reset is in progress return a soft error */
+ if (hw->reset_ongoing)
+ return ICE_ERR_RESET_ONGOING;
+
+ ice_acquire_lock(&cq->sq_lock);
+ status = ice_sq_send_cmd_nolock(hw, cq, desc, buf, buf_size, cd);
ice_release_lock(&cq->sq_lock);
+
return status;
}
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 37/63] net/ice/base: associate recipes by profile type
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (35 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 36/63] net/ice/base: add support for not locking sideband queue Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 38/63] net/ice/base: return switch error on invalid match criteria Qi Zhang
` (26 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
Change recipe to profile association logic to determine the profile type
to determine if a profile is compatible with the rule being added.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flex_pipe.c | 87 ++++++++++++++++++++++++++++++--
drivers/net/ice/base/ice_flex_pipe.h | 5 +-
drivers/net/ice/base/ice_flex_type.h | 8 +++
drivers/net/ice/base/ice_protocol_type.h | 5 +-
drivers/net/ice/base/ice_switch.c | 54 ++++++++++++++++++--
5 files changed, 151 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index f8dd1c4d1..3beb4d961 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -1506,10 +1506,83 @@ ice_sw_fv_handler(u32 sect_type, void *section, u32 index, u32 *offset)
}
/**
+ * ice_get_sw_prof_type - determine switch profile type
+ * @hw: pointer to the HW structure
+ * @fv: pointer to the switch field vector
+ */
+static enum ice_prof_type
+ice_get_sw_prof_type(struct ice_hw *hw, struct ice_fv *fv)
+{
+ u16 i;
+
+ for (i = 0; i < hw->blk[ICE_BLK_SW].es.fvw; i++) {
+ /* UDP tunnel will have UDP_OF protocol ID and VNI offset */
+ if (fv->ew[i].prot_id == (u8)ICE_PROT_UDP_OF &&
+ fv->ew[i].off == ICE_VNI_OFFSET)
+ return ICE_PROF_TUN_UDP;
+
+ /* GRE tunnel will have GRE protocol */
+ if (fv->ew[i].prot_id == (u8)ICE_PROT_GRE_OF)
+ return ICE_PROF_TUN_GRE;
+
+ /* PPPOE tunnel will have PPPOE protocol */
+ if (fv->ew[i].prot_id == (u8)ICE_PROT_PPPOE)
+ return ICE_PROF_TUN_PPPOE;
+ }
+
+ return ICE_PROF_NON_TUN;
+}
+
+/**
+ * ice_get_sw_fv_bitmap - Get switch field vector bitmap based on profile type
+ * @hw: pointer to hardware structure
+ * @type: type of profiles requested
+ * @bm: pointer to memory for returning the bitmap of field vectors
+ */
+void
+ice_get_sw_fv_bitmap(struct ice_hw *hw, enum ice_prof_type type,
+ ice_bitmap_t *bm)
+{
+ struct ice_pkg_enum state;
+ struct ice_seg *ice_seg;
+ struct ice_fv *fv;
+
+ if (type == ICE_PROF_ALL) {
+ u16 i;
+
+ for (i = 0; i < ICE_MAX_NUM_PROFILES; i++)
+ ice_set_bit(i, bm);
+ return;
+ }
+
+ ice_zero_bitmap(bm, ICE_MAX_NUM_PROFILES);
+
+ ice_seg = hw->seg;
+ do {
+ enum ice_prof_type prof_type;
+ u32 offset;
+
+ fv = (struct ice_fv *)
+ ice_pkg_enum_entry(ice_seg, &state, ICE_SID_FLD_VEC_SW,
+ &offset, ice_sw_fv_handler);
+ ice_seg = NULL;
+
+ if (fv) {
+ /* Determine field vector type */
+ prof_type = ice_get_sw_prof_type(hw, fv);
+
+ if (type & prof_type)
+ ice_set_bit((u16)offset, bm);
+ }
+ } while (fv);
+}
+
+/**
* ice_get_sw_fv_list
* @hw: pointer to the HW structure
* @prot_ids: field vector to search for with a given protocol ID
* @ids_cnt: lookup/protocol count
+ * @bm: bitmap of field vectors to consider
* @fv_list: Head of a list
*
* Finds all the field vector entries from switch block that contain
@@ -1521,7 +1594,7 @@ ice_sw_fv_handler(u32 sect_type, void *section, u32 index, u32 *offset)
*/
enum ice_status
ice_get_sw_fv_list(struct ice_hw *hw, u16 *prot_ids, u8 ids_cnt,
- struct LIST_HEAD_TYPE *fv_list)
+ ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list)
{
struct ice_sw_fv_list_entry *fvl;
struct ice_sw_fv_list_entry *tmp;
@@ -1540,8 +1613,17 @@ ice_get_sw_fv_list(struct ice_hw *hw, u16 *prot_ids, u8 ids_cnt,
fv = (struct ice_fv *)
ice_pkg_enum_entry(ice_seg, &state, ICE_SID_FLD_VEC_SW,
&offset, ice_sw_fv_handler);
+ if (!fv)
+ break;
+ ice_seg = NULL;
- for (i = 0; i < ids_cnt && fv; i++) {
+ /* If field vector is not in the bitmap list, then skip this
+ * profile.
+ */
+ if (!ice_is_bit_set(bm, (u16)offset))
+ continue;
+
+ for (i = 0; i < ids_cnt; i++) {
int j;
/* This code assumes that if a switch field vector line
@@ -1565,7 +1647,6 @@ ice_get_sw_fv_list(struct ice_hw *hw, u16 *prot_ids, u8 ids_cnt,
break;
}
}
- ice_seg = NULL;
} while (fv);
if (LIST_EMPTY(fv_list))
return ICE_ERR_CFG;
diff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h
index 6af24653b..17285efe0 100644
--- a/drivers/net/ice/base/ice_flex_pipe.h
+++ b/drivers/net/ice/base/ice_flex_pipe.h
@@ -30,9 +30,12 @@ ice_find_prot_off(struct ice_hw *hw, enum ice_block blk, u8 prof, u8 fv_idx,
enum ice_status
ice_find_label_value(struct ice_seg *ice_seg, char const *name, u32 type,
u16 *value);
+void
+ice_get_sw_fv_bitmap(struct ice_hw *hw, enum ice_prof_type type,
+ ice_bitmap_t *bm);
enum ice_status
ice_get_sw_fv_list(struct ice_hw *hw, u16 *prot_ids, u8 ids_cnt,
- struct LIST_HEAD_TYPE *fv_list);
+ ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list);
enum ice_status
ice_create_tunnel(struct ice_hw *hw, enum ice_tunnel_type type, u16 port);
enum ice_status ice_destroy_tunnel(struct ice_hw *hw, u16 port, bool all);
diff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h
index 634897a28..3a70668d9 100644
--- a/drivers/net/ice/base/ice_flex_type.h
+++ b/drivers/net/ice/base/ice_flex_type.h
@@ -710,4 +710,12 @@ struct ice_chs_chg {
#define ICE_FLOW_PTYPE_MAX ICE_XLT1_CNT
+enum ice_prof_type {
+ ICE_PROF_NON_TUN = 0x1,
+ ICE_PROF_TUN_UDP = 0x2,
+ ICE_PROF_TUN_GRE = 0x4,
+ ICE_PROF_TUN_PPPOE = 0x8,
+ ICE_PROF_TUN_ALL = 0xE,
+ ICE_PROF_ALL = 0xFF,
+};
#endif /* _ICE_FLEX_TYPE_H_ */
diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h
index 29375d3ae..ee40bdc30 100644
--- a/drivers/net/ice/base/ice_protocol_type.h
+++ b/drivers/net/ice/base/ice_protocol_type.h
@@ -49,7 +49,8 @@ enum ice_protocol_type {
};
enum ice_sw_tunnel_type {
- ICE_NON_TUN,
+ ICE_NON_TUN = 0,
+ ICE_SW_TUN_AND_NON_TUN,
ICE_SW_TUN_VXLAN_GPE,
ICE_SW_TUN_GENEVE,
ICE_SW_TUN_VXLAN,
@@ -111,6 +112,8 @@ enum ice_prot_id {
ICE_PROT_INVALID = 255 /* when offset == 0xFF */
};
+#define ICE_VNI_OFFSET 12 /* offset of VNI from ICE_PROT_UDP_OF */
+
#define ICE_MAC_OFOS_HW 1
#define ICE_MAC_IL_HW 4
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 2b0c7c7a3..2a7ffc7aa 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -5463,11 +5463,12 @@ ice_create_recipe_group(struct ice_hw *hw, struct ice_sw_recipe *rm,
* @lkups: lookup elements or match criteria for the advanced recipe, one
* structure per protocol header
* @lkups_cnt: number of protocols
+ * @bm: bitmap of field vectors to consider
* @fv_list: pointer to a list that holds the returned field vectors
*/
static enum ice_status
ice_get_fv(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,
- struct LIST_HEAD_TYPE *fv_list)
+ ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list)
{
enum ice_status status;
u16 *prot_ids;
@@ -5484,13 +5485,53 @@ ice_get_fv(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,
}
/* Find field vectors that include all specified protocol types */
- status = ice_get_sw_fv_list(hw, prot_ids, lkups_cnt, fv_list);
+ status = ice_get_sw_fv_list(hw, prot_ids, lkups_cnt, bm, fv_list);
free_mem:
ice_free(hw, prot_ids);
return status;
}
+/* ice_get_compat_fv_bitmap - Get compatible field vector bitmap for rule
+ * @hw: pointer to hardware structure
+ * @rinfo: other information regarding the rule e.g. priority and action info
+ * @bm: pointer to memory for returning the bitmap of field vectors
+ */
+static void
+ice_get_compat_fv_bitmap(struct ice_hw *hw, struct ice_adv_rule_info *rinfo,
+ ice_bitmap_t *bm)
+{
+ enum ice_prof_type type;
+
+ switch (rinfo->tun_type) {
+ case ICE_NON_TUN:
+ type = ICE_PROF_NON_TUN;
+ break;
+ case ICE_ALL_TUNNELS:
+ type = ICE_PROF_TUN_ALL;
+ break;
+ case ICE_SW_TUN_VXLAN_GPE:
+ case ICE_SW_TUN_GENEVE:
+ case ICE_SW_TUN_VXLAN:
+ case ICE_SW_TUN_UDP:
+ case ICE_SW_TUN_GTP:
+ type = ICE_PROF_TUN_UDP;
+ break;
+ case ICE_SW_TUN_NVGRE:
+ type = ICE_PROF_TUN_GRE;
+ break;
+ case ICE_SW_TUN_PPPOE:
+ type = ICE_PROF_TUN_PPPOE;
+ break;
+ case ICE_SW_TUN_AND_NON_TUN:
+ default:
+ type = ICE_PROF_ALL;
+ break;
+ }
+
+ ice_get_sw_fv_bitmap(hw, type, bm);
+}
+
/**
* ice_add_adv_recipe - Add an advanced recipe that is not part of the default
* @hw: pointer to hardware structure
@@ -5504,6 +5545,7 @@ static enum ice_status
ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
u16 lkups_cnt, struct ice_adv_rule_info *rinfo, u16 *rid)
{
+ ice_declare_bitmap(fv_bitmap, ICE_MAX_NUM_PROFILES);
ice_declare_bitmap(profiles, ICE_MAX_NUM_PROFILES);
struct ice_prot_lkup_ext *lkup_exts;
struct ice_recp_grp_entry *r_entry;
@@ -5553,7 +5595,13 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
INIT_LIST_HEAD(&rm->fv_list);
INIT_LIST_HEAD(&rm->rg_list);
- status = ice_get_fv(hw, lkups, lkups_cnt, &rm->fv_list);
+ /* Get bitmap of field vectors (profiles) that are compatible with the
+ * rule request; only these will be searched in the subsequent call to
+ * ice_get_fv.
+ */
+ ice_get_compat_fv_bitmap(hw, rinfo, fv_bitmap);
+
+ status = ice_get_fv(hw, lkups, lkups_cnt, fv_bitmap, &rm->fv_list);
if (status)
goto err_unroll;
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 38/63] net/ice/base: return switch error on invalid match criteria
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (36 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 37/63] net/ice/base: associate recipes by profile type Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 39/63] net/ice/base: update UDP tunnel switch training packets Qi Zhang
` (25 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
Fixing ice_add_adv_rule to return an error when an invalid match
criteria is requested by the caller. This happens when the protocol
and offset pair is not supported by the package.
This change required a fix for the offset in the VXLAN GPE header,
and also found an issue with NVGRE where the package does not seem
to extract the correct offsets. Disabling the TDD test for NVGRE
until the time the shared code and package can align correctly.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 21 +++++++++++++++++----
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 2a7ffc7aa..bc7caf1a8 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -4651,7 +4651,7 @@ static const struct ice_prot_ext_tbl_entry ice_prot_ext[] = {
{ ICE_SCTP_IL, { 0, 2 } },
{ ICE_VXLAN, { 8, 10, 12, 14 } },
{ ICE_GENEVE, { 8, 10, 12, 14 } },
- { ICE_VXLAN_GPE, { 0, 2, 4 } },
+ { ICE_VXLAN_GPE, { 8, 10, 12, 14 } },
{ ICE_NVGRE, { 0, 2, 4, 6 } },
{ ICE_GTP, { 8, 10, 12, 14, 16, 18, 20 } },
{ ICE_PPPOE, { 0, 2, 4, 6 } },
@@ -4950,7 +4950,7 @@ ice_create_first_fit_recp_def(struct ice_hw *hw,
* Helper function to fill in the field vector indices for protocol-offset
* pairs. These indexes are then ultimately programmed into a recipe.
*/
-static void
+static enum ice_status
ice_fill_fv_word_index(struct ice_hw *hw, struct LIST_HEAD_TYPE *fv_list,
struct LIST_HEAD_TYPE *rg_list)
{
@@ -4959,7 +4959,7 @@ ice_fill_fv_word_index(struct ice_hw *hw, struct LIST_HEAD_TYPE *fv_list,
struct ice_fv_word *fv_ext;
if (LIST_EMPTY(fv_list))
- return;
+ return ICE_SUCCESS;
fv = LIST_FIRST_ENTRY(fv_list, struct ice_sw_fv_list_entry, list_entry);
fv_ext = fv->fv_ptr->ew;
@@ -4969,6 +4969,7 @@ ice_fill_fv_word_index(struct ice_hw *hw, struct LIST_HEAD_TYPE *fv_list,
for (i = 0; i < rg->r_group.n_val_pairs; i++) {
struct ice_fv_word *pr;
+ bool found = false;
u16 mask;
u8 j;
@@ -4978,6 +4979,8 @@ ice_fill_fv_word_index(struct ice_hw *hw, struct LIST_HEAD_TYPE *fv_list,
for (j = 0; j < hw->blk[ICE_BLK_SW].es.fvw; j++)
if (fv_ext[j].prot_id == pr->prot_id &&
fv_ext[j].off == pr->off) {
+ found = true;
+
/* Store index of field vector */
rg->fv_idx[i] = j;
/* Mask is given by caller as big
@@ -4987,8 +4990,16 @@ ice_fill_fv_word_index(struct ice_hw *hw, struct LIST_HEAD_TYPE *fv_list,
rg->fv_mask[i] = mask << 8 | mask >> 8;
break;
}
+
+ /* Protocol/offset could not be found, caller gave an
+ * invalid pair
+ */
+ if (!found)
+ return ICE_ERR_PARAM;
}
}
+
+ return ICE_SUCCESS;
}
/**
@@ -5627,7 +5638,9 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
/* Find offsets from the field vector. Pick the first one for all the
* recipes.
*/
- ice_fill_fv_word_index(hw, &rm->fv_list, &rm->rg_list);
+ status = ice_fill_fv_word_index(hw, &rm->fv_list, &rm->rg_list);
+ if (status)
+ goto err_unroll;
/* get bitmap of all profiles the recipe will be associated with */
ice_zero_bitmap(profiles, ICE_MAX_NUM_PROFILES);
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 39/63] net/ice/base: update UDP tunnel switch training packets
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (37 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 38/63] net/ice/base: return switch error on invalid match criteria Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 40/63] net/ice/base: improve switch chained recipe Qi Zhang
` (24 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
Change UDP tunnel training packets for the switch to work for both
Geneve and VXLAN cases.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index bc7caf1a8..65ec1bb93 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -179,7 +179,7 @@ u8 dummy_udp_tun_tcp_packet[] = {
0x00, 0x00, 0x12, 0xb5, /* ICE_UDP_OF 34 */
0x00, 0x46, 0x00, 0x00,
- 0x04, 0x00, 0x00, 0x03, /* ICE_VXLAN 42 */
+ 0x00, 0x00, 0x65, 0x58, /* ICE_VXLAN 42 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 50 */
@@ -230,7 +230,7 @@ u8 dummy_udp_tun_udp_packet[] = {
0x00, 0x00, 0x12, 0xb5, /* ICE_UDP_OF 34 */
0x00, 0x3a, 0x00, 0x00,
- 0x0c, 0x00, 0x00, 0x03, /* ICE_VXLAN 42 */
+ 0x00, 0x00, 0x65, 0x58, /* ICE_VXLAN 42 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 50 */
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 40/63] net/ice/base: improve switch chained recipe
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (38 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 39/63] net/ice/base: update UDP tunnel switch training packets Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 41/63] net/ice/base: move and add some help function and macros Qi Zhang
` (23 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
When updating switch database with chained recipes from
firmware, where a null pointer derefence was occurring due to looking
into a sub-recipe entry which is not filled in.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_protocol_type.h | 2 +
drivers/net/ice/base/ice_switch.c | 164 ++++++++++++++++++++-----------
2 files changed, 108 insertions(+), 58 deletions(-)
diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h
index ee40bdc30..91f56f3fa 100644
--- a/drivers/net/ice/base/ice_protocol_type.h
+++ b/drivers/net/ice/base/ice_protocol_type.h
@@ -135,6 +135,8 @@ enum ice_prot_id {
#define ICE_GRE_OF_HW 64 /* NVGRE */
#define ICE_META_DATA_ID_HW 255 /* this is used for tunnel type */
+#define ICE_MDID_SIZE 2
+#define ICE_TUN_FLAG_MDID 21
#define ICE_TUN_FLAG_MASK 0xFF
#define ICE_TUN_FLAG_FV_IND 2
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 65ec1bb93..b4f50e0e5 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -455,29 +455,24 @@ static void ice_get_recp_to_prof_map(struct ice_hw *hw);
static void ice_collect_result_idx(struct ice_aqc_recipe_data_elem *buf,
struct ice_sw_recipe *recp)
{
- if (buf->content.result_indx & ICE_AQ_RECIPE_ID_IS_ROOT)
+ if (buf->content.result_indx & ICE_AQ_RECIPE_RESULT_EN)
ice_set_bit(buf->content.result_indx &
- ~ICE_AQ_RECIPE_ID_IS_ROOT, recp->res_idxs);
+ ~ICE_AQ_RECIPE_RESULT_EN, recp->res_idxs);
}
/**
- * ice_collect_result_idx_from_bitmap - copy result index values using bitmap
- * @hw: pointer to hardware structure
- * @recp: the recipe struct to copy data into
+ * ice_init_possible_res_bm - initialize possible result bitmap
+ * @pos_result_bm: pointer to the bitmap to initialize
*/
-static void
-ice_collect_result_idx_from_bitmap(struct ice_hw *hw,
- struct ice_sw_recipe *recp)
+static void ice_init_possible_res_bm(ice_bitmap_t *pos_result_bm)
{
- u16 bit = 0;
+ u16 bit;
- while (ICE_MAX_NUM_RECIPES >
- (bit = ice_find_next_bit(recp->r_bitmap, ICE_MAX_NUM_RECIPES,
- bit))) {
- ice_collect_result_idx(hw->switch_info->recp_list[bit].root_buf,
- recp);
- bit++;
- }
+ ice_zero_bitmap(pos_result_bm, ICE_MAX_FV_WORDS);
+
+ for (bit = 0; bit < ICE_MAX_FV_WORDS; bit++)
+ if (ICE_POSSIBLE_RES_IDX & BIT_ULL(bit))
+ ice_set_bit(bit, pos_result_bm);
}
/**
@@ -495,14 +490,16 @@ static enum ice_status
ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
bool *refresh_required)
{
- u16 i, sub_recps, fv_word_idx = 0, result_idx = 0;
- ice_declare_bitmap(r_bitmap, ICE_MAX_NUM_PROFILES);
- u16 result_idxs[ICE_MAX_CHAIN_RECIPE] = { 0 };
+ ice_declare_bitmap(possible_idx, ICE_MAX_FV_WORDS);
+ ice_declare_bitmap(result_bm, ICE_MAX_FV_WORDS);
struct ice_aqc_recipe_data_elem *tmp;
u16 num_recps = ICE_MAX_NUM_RECIPES;
struct ice_prot_lkup_ext *lkup_exts;
+ u16 i, sub_recps, fv_word_idx = 0;
enum ice_status status;
- u8 is_root;
+
+ ice_zero_bitmap(result_bm, ICE_MAX_FV_WORDS);
+ ice_init_possible_res_bm(possible_idx);
/* we need a buffer big enough to accommodate all the recipes */
tmp = (struct ice_aqc_recipe_data_elem *)ice_calloc(hw,
@@ -528,14 +525,18 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
ice_get_recp_to_prof_map(hw);
*refresh_required = false;
}
- lkup_exts = &recps[rid].lkup_exts;
- /* start populating all the entries for recps[rid] based on lkups from
- * firmware
+
+ /* Start populating all the entries for recps[rid] based on lkups from
+ * firmware. Note that we are only creating the root recipe in our
+ * database.
*/
+ lkup_exts = &recps[rid].lkup_exts;
+
for (sub_recps = 0; sub_recps < num_recps; sub_recps++) {
struct ice_aqc_recipe_data_elem root_bufs = tmp[sub_recps];
struct ice_recp_grp_entry *rg_entry;
- u8 prof_id, prot = 0;
+ u8 prof_id, idx, prot = 0;
+ bool is_root;
u16 off = 0;
rg_entry = (struct ice_recp_grp_entry *)
@@ -544,15 +545,18 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
status = ICE_ERR_NO_MEMORY;
goto err_unroll;
}
- /* When copying, clear the result index enable bit */
- result_idxs[result_idx] = root_bufs.content.result_indx &
- ~ICE_AQ_RECIPE_RESULT_EN;
- ice_memcpy(r_bitmap,
- recipe_to_profile[tmp[sub_recps].recipe_indx],
- sizeof(r_bitmap), ICE_NONDMA_TO_NONDMA);
+ idx = root_bufs.recipe_indx;
+ is_root = root_bufs.content.rid & ICE_AQ_RECIPE_ID_IS_ROOT;
+
+ /* Mark all result indices in this chain */
+ if (root_bufs.content.result_indx & ICE_AQ_RECIPE_RESULT_EN)
+ ice_set_bit(root_bufs.content.result_indx &
+ ~ICE_AQ_RECIPE_RESULT_EN, result_bm);
+
/* get the first profile that is associated with rid */
- prof_id = ice_find_first_bit(r_bitmap, ICE_MAX_NUM_PROFILES);
+ prof_id = ice_find_first_bit(recipe_to_profile[idx],
+ ICE_MAX_NUM_PROFILES);
for (i = 0; i < ICE_NUM_WORDS_RECIPE; i++) {
u8 lkup_indx = root_bufs.content.lkup_indx[i + 1];
@@ -569,12 +573,8 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
* has ICE_AQ_RECIPE_LKUP_IGNORE or 0 since it isn't a
* valid offset value.
*/
- if (result_idxs[0] == rg_entry->fv_idx[i] ||
- result_idxs[1] == rg_entry->fv_idx[i] ||
- result_idxs[2] == rg_entry->fv_idx[i] ||
- result_idxs[3] == rg_entry->fv_idx[i] ||
- result_idxs[4] == rg_entry->fv_idx[i] ||
- rg_entry->fv_idx[i] == ICE_AQ_RECIPE_LKUP_IGNORE ||
+ if (ice_is_bit_set(possible_idx, rg_entry->fv_idx[i]) ||
+ rg_entry->fv_idx[i] & ICE_AQ_RECIPE_LKUP_IGNORE ||
rg_entry->fv_idx[i] == 0)
continue;
@@ -588,7 +588,29 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
* recipe
*/
LIST_ADD(&rg_entry->l_entry, &recps[rid].rg_list);
+
+ /* Propagate some data to the recipe database */
+ recps[idx].is_root = is_root;
+ recps[idx].priority = root_bufs.content.act_ctrl_fwd_priority;
+ if (root_bufs.content.result_indx & ICE_AQ_RECIPE_RESULT_EN)
+ recps[idx].chain_idx = root_bufs.content.result_indx &
+ ~ICE_AQ_RECIPE_RESULT_EN;
+ else
+ recps[idx].chain_idx = ICE_INVAL_CHAIN_IND;
+
+ if (!is_root)
+ continue;
+
+ /* Only do the following for root recipes entries */
+ ice_memcpy(recps[idx].r_bitmap, root_bufs.recipe_bitmap,
+ sizeof(recps[idx].r_bitmap), ICE_NONDMA_TO_NONDMA);
+ recps[idx].root_rid = root_bufs.content.rid &
+ ~ICE_AQ_RECIPE_ID_IS_ROOT;
+ recps[idx].priority = root_bufs.content.act_ctrl_fwd_priority;
+ recps[idx].big_recp = (recps[rid].n_grp_count > 1);
}
+
+ /* Complete initialization of the root recipe entry */
lkup_exts->n_val_words = fv_word_idx;
recps[rid].n_grp_count = num_recps;
recps[rid].root_buf = (struct ice_aqc_recipe_data_elem *)
@@ -600,26 +622,9 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
ice_memcpy(recps[rid].root_buf, tmp, recps[rid].n_grp_count *
sizeof(*recps[rid].root_buf), ICE_NONDMA_TO_NONDMA);
- ice_memcpy(recps[rid].r_bitmap, tmp->recipe_bitmap,
- sizeof(recps[rid].r_bitmap), ICE_NONDMA_TO_NONDMA);
-
- if (tmp->content.result_indx & ICE_AQ_RECIPE_RESULT_EN)
- recps[rid].chain_idx = tmp->content.result_indx &
- ~ICE_AQ_RECIPE_RESULT_EN;
- else
- recps[rid].chain_idx = ICE_INVAL_CHAIN_IND;
-
- recps[rid].root_rid = tmp->content.rid & ~ICE_AQ_RECIPE_ID_IS_ROOT;
- is_root = (tmp->content.rid & ICE_AQ_RECIPE_ID_IS_ROOT) != 0;
- recps[rid].is_root = is_root;
- recps[rid].big_recp = (is_root && recps[rid].n_grp_count > 1);
-
- /* Copy non-result fv index values to recipe. This call will also update
- * the result index bitmap appropriately.
- */
- ice_collect_result_idx_from_bitmap(hw, &recps[rid]);
-
- recps[rid].priority = tmp->content.act_ctrl_fwd_priority;
+ /* Copy result indexes */
+ ice_memcpy(recps[rid].res_idxs, result_bm, sizeof(recps[rid].res_idxs),
+ ICE_NONDMA_TO_NONDMA);
recps[rid].recp_created = true;
err_unroll:
@@ -5038,10 +5043,10 @@ ice_find_free_recp_res_idx(struct ice_hw *hw, const ice_bitmap_t *profiles,
u16 count = 0;
u16 bit;
- ice_zero_bitmap(possible_idx, ICE_MAX_FV_WORDS);
ice_zero_bitmap(free_idx, ICE_MAX_FV_WORDS);
ice_zero_bitmap(used_idx, ICE_MAX_FV_WORDS);
ice_zero_bitmap(recipes, ICE_MAX_NUM_RECIPES);
+ ice_init_possible_res_bm(possible_idx);
for (bit = 0; bit < ICE_MAX_FV_WORDS; bit++)
if (ICE_POSSIBLE_RES_IDX & BIT_ULL(bit))
@@ -5503,6 +5508,34 @@ ice_get_fv(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,
return status;
}
+/**
+ * ice_add_special_words - Add words that are not protocols, such as metadata
+ * @rinfo: other information regarding the rule e.g. priority and action info
+ * @lkup_exts: lookup word structure
+ */
+static enum ice_status
+ice_add_special_words(struct ice_adv_rule_info *rinfo,
+ struct ice_prot_lkup_ext *lkup_exts)
+{
+ /* If this is a tunneled packet, then add recipe index to match the
+ * tunnel bit in the packet metadata flags.
+ */
+ if (rinfo->tun_type != ICE_NON_TUN) {
+ if (lkup_exts->n_val_words < ICE_MAX_CHAIN_WORDS) {
+ u8 word = lkup_exts->n_val_words++;
+
+ lkup_exts->fv_words[word].prot_id = ICE_META_DATA_ID_HW;
+ lkup_exts->fv_words[word].off = ICE_TUN_FLAG_MDID *
+ ICE_MDID_SIZE;
+ lkup_exts->field_mask[word] = ICE_TUN_FLAG_MASK;
+ } else {
+ return ICE_ERR_MAX_LIMIT;
+ }
+ }
+
+ return ICE_SUCCESS;
+}
+
/* ice_get_compat_fv_bitmap - Get compatible field vector bitmap for rule
* @hw: pointer to hardware structure
* @rinfo: other information regarding the rule e.g. priority and action info
@@ -5650,6 +5683,13 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
ice_set_bit((u16)fvit->profile_id, profiles);
}
+ /* Create any special protocol/offset pairs, such as looking at tunnel
+ * bits by extracting metadata
+ */
+ status = ice_add_special_words(rinfo, lkup_exts);
+ if (status)
+ goto err_free_lkup_exts;
+
/* Look for a recipe which matches our requested fv / mask list */
*rid = ice_find_recp(hw, lkup_exts);
if (*rid < ICE_MAX_NUM_RECIPES)
@@ -6424,6 +6464,14 @@ ice_rem_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
if (!count)
return ICE_ERR_CFG;
}
+
+ /* Create any special protocol/offset pairs, such as looking at tunnel
+ * bits by extracting metadata
+ */
+ status = ice_add_special_words(rinfo, &lkup_exts);
+ if (status)
+ return status;
+
rid = ice_find_recp(hw, &lkup_exts);
/* If did not find a recipe that match the existing criteria */
if (rid == ICE_MAX_NUM_RECIPES)
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 41/63] net/ice/base: move and add some help function and macros
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (39 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 40/63] net/ice/base: improve switch chained recipe Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 42/63] net/ice/base: add routine for tunnel port query Qi Zhang
` (22 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Bruce Allan, Paul M Stillwell Jr
ice_ilog2 computes the integer log base 2 of the value (0 is undefined)
ice_is_pow2 returns true if the value is a power of 2 (0 is not a power
of 2). Move the functions to ice_type.h and wrap them so that components
can strip or conditionally-compile out these implementations in lieu of
their own via osdep/other.
The patch also add help macro ROUND_UP and IS_ETHER_ADDR_EQUAL.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flow.c | 9 ---------
drivers/net/ice/base/ice_switch.c | 15 ---------------
drivers/net/ice/base/ice_type.h | 39 +++++++++++++++++++++++++++++++++++++++
3 files changed, 39 insertions(+), 24 deletions(-)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 9e93a1078..477cf5dfe 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -360,15 +360,6 @@ struct ice_flow_prof_params {
ice_declare_bitmap(ptypes, ICE_FLOW_PTYPE_MAX);
};
-/**
- * ice_is_pow2 - check if integer value is a power of 2
- * @val: unsigned integer to be validated
- */
-static bool ice_is_pow2(u64 val)
-{
- return (val && !(val & (val - 1)));
-}
-
#define ICE_FLOW_SEG_HDRS_L2_MASK \
(ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN)
#define ICE_FLOW_SEG_HDRS_L3_MASK \
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index b4f50e0e5..ef3a919ec 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -1849,21 +1849,6 @@ static void ice_fill_sw_info(struct ice_hw *hw, struct ice_fltr_info *fi)
}
/**
- * ice_ilog2 - Calculates integer log base 2 of a number
- * @n: number on which to perform operation
- */
-static int ice_ilog2(u64 n)
-{
- int i;
-
- for (i = 63; i >= 0; i--)
- if (((u64)1 << i) & n)
- return i;
-
- return -1;
-}
-
-/**
* ice_fill_sw_rule - Helper function to fill switch rule structure
* @hw: pointer to the hardware structure
* @f_info: entry containing packet forwarding information
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 541e29851..403fb7668 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -22,6 +22,16 @@
#define ICE_BYTES_PER_DWORD 4
#define ICE_MAX_TRAFFIC_CLASS 8
+/**
+ * ROUND_UP - round up to next arbitrary multiple (not a power of 2)
+ * @a: value to round up
+ * @b: arbitrary multiple
+ *
+ * Round up to the next multiple of the arbitrary b.
+ * Note, when b is a power of 2 use ICE_ALIGN() instead.
+ */
+#define ROUND_UP(a, b) ((b) * DIVIDE_AND_ROUND_UP((a), (b)))
+
#define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b))
#define IS_ASCII(_ch) ((_ch) < 0x80)
@@ -36,6 +46,30 @@
#include "ice_flex_type.h"
#include "ice_protocol_type.h"
+/**
+ * ice_is_pow2 - check if integer value is a power of 2
+ * @val: unsigned integer to be validated
+ */
+static inline bool ice_is_pow2(u64 val)
+{
+ return (val && !(val & (val - 1)));
+}
+
+/**
+ * ice_ilog2 - Calculates integer log base 2 of a number
+ * @n: number on which to perform operation
+ */
+static inline int ice_ilog2(u64 n)
+{
+ int i;
+
+ for (i = 63; i >= 0; i--)
+ if (((u64)1 << i) & n)
+ return i;
+
+ return -1;
+}
+
static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
{
return ice_is_bit_set(&bitmap, tc);
@@ -104,6 +138,11 @@ static inline u32 ice_round_to_num(u32 N, u32 R)
+#define IS_ETHER_ADDR_EQUAL(addr1, addr2) \
+ (((bool)((((u16 *)(addr1))[0] == ((u16 *)(addr2))[0]))) && \
+ ((bool)((((u16 *)(addr1))[1] == ((u16 *)(addr2))[1]))) && \
+ ((bool)((((u16 *)(addr1))[2] == ((u16 *)(addr2))[2]))))
+
enum ice_aq_res_ids {
ICE_NVM_RES_ID = 1,
ICE_SPD_RES_ID,
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 42/63] net/ice/base: add routine for tunnel port query
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (40 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 41/63] net/ice/base: move and add some help function and macros Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 43/63] net/ice/base: ptype group consolidation Qi Zhang
` (21 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
Add ice_get_open_tunnel_port routine, which can be used to find
an open tunnel port for creating switch and flow director training
packets.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flex_pipe.c | 22 ++++++++++++++++++++++
drivers/net/ice/base/ice_flex_pipe.h | 3 +++
2 files changed, 25 insertions(+)
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index 3beb4d961..8161ccaec 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -1874,6 +1874,28 @@ ice_find_free_tunnel_entry(struct ice_hw *hw, enum ice_tunnel_type type,
}
/**
+ * ice_get_tunnel_port - retrieve an open tunnel port
+ * @hw: pointer to the HW structure
+ * @type: tunnel type (TNL_ALL will return any open port)
+ * @port: returns open port
+ */
+bool
+ice_get_open_tunnel_port(struct ice_hw *hw, enum ice_tunnel_type type,
+ u16 *port)
+{
+ u16 i;
+
+ for (i = 0; i < hw->tnl.count && i < ICE_TUNNEL_MAX_ENTRIES; i++)
+ if (hw->tnl.tbl[i].valid && hw->tnl.tbl[i].in_use &&
+ (type == TNL_ALL || hw->tnl.tbl[i].type == type)) {
+ *port = hw->tnl.tbl[i].port;
+ return true;
+ }
+
+ return false;
+}
+
+/**
* ice_create_tunnel
* @hw: pointer to the HW structure
* @type: type of tunnel
diff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h
index 17285efe0..ab1663574 100644
--- a/drivers/net/ice/base/ice_flex_pipe.h
+++ b/drivers/net/ice/base/ice_flex_pipe.h
@@ -36,6 +36,9 @@ ice_get_sw_fv_bitmap(struct ice_hw *hw, enum ice_prof_type type,
enum ice_status
ice_get_sw_fv_list(struct ice_hw *hw, u16 *prot_ids, u8 ids_cnt,
ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list);
+bool
+ice_get_open_tunnel_port(struct ice_hw *hw, enum ice_tunnel_type type,
+ u16 *port);
enum ice_status
ice_create_tunnel(struct ice_hw *hw, enum ice_tunnel_type type, u16 port);
enum ice_status ice_destroy_tunnel(struct ice_hw *hw, u16 port, bool all);
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 43/63] net/ice/base: ptype group consolidation
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (41 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 42/63] net/ice/base: add routine for tunnel port query Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 44/63] net/ice/base: fix for RSS hash on inner UDP port Qi Zhang
` (20 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
This patch is an optimization to decrease the number of TCAM entries
used in the profile blocks, especially for RSS. To be most effective
this will also require a package change in order to decrease the number
of PTYPE groups necessary to program RSS, FD and ACL rules.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flex_pipe.c | 214 ++++++++++++++---------------------
drivers/net/ice/base/ice_flex_pipe.h | 2 +-
drivers/net/ice/base/ice_flex_type.h | 8 +-
3 files changed, 89 insertions(+), 135 deletions(-)
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index 8161ccaec..6ae71e698 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -2121,29 +2121,6 @@ void ice_ptg_alloc_val(struct ice_hw *hw, enum ice_block blk, u8 ptg)
hw->blk[blk].xlt1.ptg_tbl[ptg].in_use = true;
}
-/**
- * ice_ptg_alloc - Find a free entry and allocates a new packet type group ID
- * @hw: pointer to the hardware structure
- * @blk: HW block
- *
- * This function allocates and returns a new packet type group ID. Note
- * that 0 is the default packet type group, so successfully created PTGs will
- * have a non-zero ID value; which means a 0 return value indicates an error.
- */
-static u8 ice_ptg_alloc(struct ice_hw *hw, enum ice_block blk)
-{
- u16 i;
-
- /* Skip the default PTG of 0 */
- for (i = 1; i < ICE_MAX_PTGS; i++)
- if (!hw->blk[blk].xlt1.ptg_tbl[i].in_use) {
- /* found a free PTG ID */
- ice_ptg_alloc_val(hw, blk, i);
- return (u8)i;
- }
-
- return 0;
-}
/**
* ice_ptg_remove_ptype - Removes ptype from a particular packet type group
@@ -3884,43 +3861,6 @@ ice_vsig_get_ref(struct ice_hw *hw, enum ice_block blk, u16 vsig, u16 *refs)
}
/**
- * ice_get_ptg - get or allocate a ptg for a ptype
- * @hw: pointer to the hardware structure
- * @blk: HW block
- * @ptype: the ptype to retrieve the PTG for
- * @ptg: receives the PTG of the ptype
- * @add: receive boolean indicating whether PTG was added or not
- */
-static enum ice_status
-ice_get_ptg(struct ice_hw *hw, enum ice_block blk, u16 ptype, u8 *ptg,
- bool *add)
-{
- enum ice_status status;
-
- *ptg = ICE_DEFAULT_PTG;
- *add = false;
-
- status = ice_ptg_find_ptype(hw, blk, ptype, ptg);
- if (status)
- return status;
-
- if (*ptg == ICE_DEFAULT_PTG) {
- /* need to allocate a PTG, and add ptype to it */
- *ptg = ice_ptg_alloc(hw, blk);
- if (*ptg == ICE_DEFAULT_PTG)
- return ICE_ERR_HW_TABLE;
-
- status = ice_ptg_add_mv_ptype(hw, blk, ptype, *ptg);
- if (status)
- return ICE_ERR_HW_TABLE;
-
- *add = true;
- }
-
- return ICE_SUCCESS;
-};
-
-/**
* ice_has_prof_vsig - check to see if VSIG has a specific profile
* @hw: pointer to the hardware structure
* @blk: HW block
@@ -4420,11 +4360,14 @@ ice_add_prof_with_mask(struct ice_hw *hw, enum ice_block blk, u64 id,
u8 ptypes[], struct ice_fv_word *es, u16 *masks)
{
u32 bytes = DIVIDE_AND_ROUND_UP(ICE_FLOW_PTYPE_MAX, BITS_PER_BYTE);
+ ice_declare_bitmap(ptgs_used, ICE_XLT1_CNT);
struct ice_prof_map *prof;
enum ice_status status;
u32 byte = 0;
u8 prof_id;
+ ice_zero_bitmap(ptgs_used, ICE_XLT1_CNT);
+
ice_acquire_lock(&hw->blk[blk].es.prof_map_lock);
/* search for existing profile */
@@ -4464,11 +4407,11 @@ ice_add_prof_with_mask(struct ice_hw *hw, enum ice_block blk, u64 id,
prof->profile_cookie = id;
prof->prof_id = prof_id;
- prof->ptype_count = 0;
+ prof->ptg_cnt = 0;
prof->context = 0;
/* build list of ptgs */
- while (bytes && prof->ptype_count < ICE_MAX_PTYPE_PER_PROFILE) {
+ while (bytes && prof->ptg_cnt < ICE_MAX_PTG_PER_PROFILE) {
u32 bit;
if (!ptypes[byte]) {
@@ -4480,16 +4423,27 @@ ice_add_prof_with_mask(struct ice_hw *hw, enum ice_block blk, u64 id,
for (bit = 0; bit < 8; bit++) {
if (ptypes[byte] & BIT(bit)) {
u16 ptype;
+ u8 ptg;
u8 m;
ptype = byte * BITS_PER_BYTE + bit;
- if (ptype < ICE_FLOW_PTYPE_MAX) {
- prof->ptype[prof->ptype_count] = ptype;
- if (++prof->ptype_count >=
- ICE_MAX_PTYPE_PER_PROFILE)
- break;
- }
+ /* The package should place all ptypes in a
+ * non-zero PTG, so the following call should
+ * never fail.
+ */
+ if (ice_ptg_find_ptype(hw, blk, ptype, &ptg))
+ continue;
+
+ /* If PTG is already added, skip and continue */
+ if (ice_is_bit_set(ptgs_used, ptg))
+ continue;
+
+ ice_set_bit(ptg, ptgs_used);
+ prof->ptg[prof->ptg_cnt] = ptg;
+
+ if (++prof->ptg_cnt >= ICE_MAX_PTG_PER_PROFILE)
+ break;
/* nothing left in byte, then exit */
m = ~((1 << (bit + 1)) - 1);
@@ -4518,7 +4472,7 @@ ice_add_prof_with_mask(struct ice_hw *hw, enum ice_block blk, u64 id,
* @ptypes: array of bitmaps indicating ptypes (ICE_FLOW_PTYPE_MAX bits)
* @es: extraction sequence (length of array is determined by the block)
*
- * This function registers a profile, which matches a set of PTYPES with a
+ * This function registers a profile, which matches a set of PTGs with a
* particular extraction sequence. While the hardware profile is allocated
* it will not be written until the first call to ice_add_flow that specifies
* the ID value used here.
@@ -4528,11 +4482,14 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],
struct ice_fv_word *es)
{
u32 bytes = DIVIDE_AND_ROUND_UP(ICE_FLOW_PTYPE_MAX, BITS_PER_BYTE);
+ ice_declare_bitmap(ptgs_used, ICE_XLT1_CNT);
struct ice_prof_map *prof;
enum ice_status status;
u32 byte = 0;
u8 prof_id;
+ ice_zero_bitmap(ptgs_used, ICE_XLT1_CNT);
+
ice_acquire_lock(&hw->blk[blk].es.prof_map_lock);
/* search for existing profile */
@@ -4569,11 +4526,11 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],
prof->profile_cookie = id;
prof->prof_id = prof_id;
- prof->ptype_count = 0;
+ prof->ptg_cnt = 0;
prof->context = 0;
/* build list of ptgs */
- while (bytes && prof->ptype_count < ICE_MAX_PTYPE_PER_PROFILE) {
+ while (bytes && prof->ptg_cnt < ICE_MAX_PTG_PER_PROFILE) {
u32 bit;
if (!ptypes[byte]) {
@@ -4583,18 +4540,29 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],
}
/* Examine 8 bits per byte */
for (bit = 0; bit < 8; bit++) {
- if (ptypes[byte] & 1 << bit) {
+ if (ptypes[byte] & BIT(bit)) {
u16 ptype;
+ u8 ptg;
u8 m;
ptype = byte * BITS_PER_BYTE + bit;
- if (ptype < ICE_FLOW_PTYPE_MAX) {
- prof->ptype[prof->ptype_count] = ptype;
- if (++prof->ptype_count >=
- ICE_MAX_PTYPE_PER_PROFILE)
- break;
- }
+ /* The package should place all ptypes in a
+ * non-zero PTG, so the following call should
+ * never fail.
+ */
+ if (ice_ptg_find_ptype(hw, blk, ptype, &ptg))
+ continue;
+
+ /* If PTG is already added, skip and continue */
+ if (ice_is_bit_set(ptgs_used, ptg))
+ continue;
+
+ ice_set_bit(ptg, ptgs_used);
+ prof->ptg[prof->ptg_cnt] = ptg;
+
+ if (++prof->ptg_cnt >= ICE_MAX_PTG_PER_PROFILE)
+ break;
/* nothing left in byte, then exit */
m = ~((1 << (bit + 1)) - 1);
@@ -4722,10 +4690,13 @@ ice_rem_prof_id(struct ice_hw *hw, enum ice_block blk,
u16 i;
for (i = 0; i < prof->tcam_count; i++) {
- prof->tcam[i].in_use = false;
- status = ice_rel_tcam_idx(hw, blk, prof->tcam[i].tcam_idx);
- if (status)
- return ICE_ERR_HW_TABLE;
+ if (prof->tcam[i].in_use) {
+ prof->tcam[i].in_use = false;
+ status = ice_rel_tcam_idx(hw, blk,
+ prof->tcam[i].tcam_idx);
+ if (status)
+ return ICE_ERR_HW_TABLE;
+ }
}
return ICE_SUCCESS;
@@ -4905,15 +4876,15 @@ enum ice_status ice_rem_prof(struct ice_hw *hw, enum ice_block blk, u64 id)
}
/**
- * ice_get_prof_ptgs - get ptgs for profile
+ * ice_get_prof - get profile
* @hw: pointer to the HW struct
* @blk: hardware block
* @hdl: profile handle
* @chg: change list
*/
static enum ice_status
-ice_get_prof_ptgs(struct ice_hw *hw, enum ice_block blk, u64 hdl,
- struct LIST_HEAD_TYPE *chg)
+ice_get_prof(struct ice_hw *hw, enum ice_block blk, u64 hdl,
+ struct LIST_HEAD_TYPE *chg)
{
struct ice_prof_map *map;
struct ice_chs_chg *p;
@@ -4924,27 +4895,19 @@ ice_get_prof_ptgs(struct ice_hw *hw, enum ice_block blk, u64 hdl,
if (!map)
return ICE_ERR_DOES_NOT_EXIST;
- for (i = 0; i < map->ptype_count; i++) {
- enum ice_status status;
- bool add;
- u8 ptg;
-
- status = ice_get_ptg(hw, blk, map->ptype[i], &ptg, &add);
- if (status)
- goto err_ice_get_prof_ptgs;
-
- if (add || !hw->blk[blk].es.written[map->prof_id]) {
- /* add PTG to change list */
+ for (i = 0; i < map->ptg_cnt; i++) {
+ if (!hw->blk[blk].es.written[map->prof_id]) {
+ /* add ES to change list */
p = (struct ice_chs_chg *)ice_malloc(hw, sizeof(*p));
if (!p)
- goto err_ice_get_prof_ptgs;
+ goto err_ice_get_prof;
p->type = ICE_PTG_ES_ADD;
- p->ptype = map->ptype[i];
- p->ptg = ptg;
- p->add_ptg = add;
+ p->ptype = 0;
+ p->ptg = map->ptg[i];
+ p->add_ptg = 0;
- p->add_prof = !hw->blk[blk].es.written[map->prof_id];
+ p->add_prof = 1;
p->prof_id = map->prof_id;
hw->blk[blk].es.written[map->prof_id] = true;
@@ -4955,7 +4918,7 @@ ice_get_prof_ptgs(struct ice_hw *hw, enum ice_block blk, u64 hdl,
return ICE_SUCCESS;
-err_ice_get_prof_ptgs:
+err_ice_get_prof:
/* let caller clean up the change list */
return ICE_ERR_NO_MEMORY;
}
@@ -5026,20 +4989,12 @@ ice_add_prof_to_lst(struct ice_hw *hw, enum ice_block blk,
p->profile_cookie = map->profile_cookie;
p->prof_id = map->prof_id;
- p->tcam_count = map->ptype_count;
-
- for (i = 0; i < map->ptype_count; i++) {
- u8 ptg;
+ p->tcam_count = map->ptg_cnt;
+ for (i = 0; i < map->ptg_cnt; i++) {
p->tcam[i].prof_id = map->prof_id;
p->tcam[i].tcam_idx = ICE_INVALID_TCAM;
-
- if (ice_ptg_find_ptype(hw, blk, map->ptype[i], &ptg)) {
- ice_free(hw, p);
- return ICE_ERR_CFG;
- }
-
- p->tcam[i].ptg = ptg;
+ p->tcam[i].ptg = map->ptg[i];
}
LIST_ADD(&p->list, lst);
@@ -5110,12 +5065,19 @@ ice_prof_tcam_ena_dis(struct ice_hw *hw, enum ice_block blk, bool enable,
u8 nm_msk[ICE_TCAM_KEY_VAL_SZ] = { 0x00, 0x00, 0x00, 0x00, 0x00 };
u8 vl_msk[ICE_TCAM_KEY_VAL_SZ] = { 0x01, 0x00, 0x00, 0x00, 0x00 };
- /* If disabled, change the low flag bit to never match */
+ /* if disabling, free the tcam */
if (!enable) {
- dc_msk[0] = 0x00;
- nm_msk[0] = 0x01;
+ status = ice_free_tcam_ent(hw, blk, tcam->tcam_idx);
+ tcam->tcam_idx = 0;
+ tcam->in_use = 0;
+ return status;
}
+ /* for re-enabling, reallocate a tcam */
+ status = ice_alloc_tcam_ent(hw, blk, &tcam->tcam_idx);
+ if (status)
+ return status;
+
/* add TCAM to change list */
p = (struct ice_chs_chg *)ice_malloc(hw, sizeof(*p));
if (!p)
@@ -5127,7 +5089,7 @@ ice_prof_tcam_ena_dis(struct ice_hw *hw, enum ice_block blk, bool enable,
if (status)
goto err_ice_prof_tcam_ena_dis;
- tcam->in_use = enable;
+ tcam->in_use = 1;
p->type = ICE_TCAM_ADD;
p->add_tcam_idx = true;
@@ -5252,21 +5214,12 @@ ice_add_prof_id_vsig(struct ice_hw *hw, enum ice_block blk, u16 vsig, u64 hdl,
t->profile_cookie = map->profile_cookie;
t->prof_id = map->prof_id;
- t->tcam_count = map->ptype_count;
+ t->tcam_count = map->ptg_cnt;
/* create TCAM entries */
- for (i = 0; i < map->ptype_count; i++) {
+ for (i = 0; i < map->ptg_cnt; i++) {
enum ice_status status;
u16 tcam_idx;
- bool add;
- u8 ptg;
-
- /* If properly sequenced, we should never have to allocate new
- * PTGs
- */
- status = ice_get_ptg(hw, blk, map->ptype[i], &ptg, &add);
- if (status)
- goto err_ice_add_prof_id_vsig;
/* add TCAM to change list */
p = (struct ice_chs_chg *)ice_malloc(hw, sizeof(*p));
@@ -5280,7 +5233,7 @@ ice_add_prof_id_vsig(struct ice_hw *hw, enum ice_block blk, u16 vsig, u64 hdl,
goto err_ice_add_prof_id_vsig;
}
- t->tcam[i].ptg = ptg;
+ t->tcam[i].ptg = map->ptg[i];
t->tcam[i].prof_id = map->prof_id;
t->tcam[i].tcam_idx = tcam_idx;
t->tcam[i].in_use = true;
@@ -5497,7 +5450,8 @@ ice_add_prof_id_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u64 hdl)
INIT_LIST_HEAD(&chrs);
INIT_LIST_HEAD(&chg);
- status = ice_get_prof_ptgs(hw, blk, hdl, &chg);
+ /* Get profile */
+ status = ice_get_prof(hw, blk, hdl, &chg);
if (status)
return status;
diff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h
index ab1663574..3b5c1c39a 100644
--- a/drivers/net/ice/base/ice_flex_pipe.h
+++ b/drivers/net/ice/base/ice_flex_pipe.h
@@ -9,7 +9,7 @@
/* Package minimal version supported */
#define ICE_PKG_SUPP_VER_MAJ 1
-#define ICE_PKG_SUPP_VER_MNR 2
+#define ICE_PKG_SUPP_VER_MNR 3
/* Package format version */
#define ICE_PKG_FMT_VER_MAJ 1
diff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h
index 3a70668d9..baf53d881 100644
--- a/drivers/net/ice/base/ice_flex_type.h
+++ b/drivers/net/ice/base/ice_flex_type.h
@@ -518,16 +518,16 @@ struct ice_ptg_ptype {
u8 ptg;
};
-#define ICE_MAX_TCAM_PER_PROFILE 8
-#define ICE_MAX_PTYPE_PER_PROFILE 8
+#define ICE_MAX_TCAM_PER_PROFILE 32
+#define ICE_MAX_PTG_PER_PROFILE 32
struct ice_prof_map {
struct LIST_ENTRY_TYPE list;
u64 profile_cookie;
u64 context;
u8 prof_id;
- u8 ptype_count;
- u16 ptype[ICE_MAX_PTYPE_PER_PROFILE];
+ u8 ptg_cnt;
+ u8 ptg[ICE_MAX_PTG_PER_PROFILE];
};
#define ICE_INVALID_TCAM 0xFFFF
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 44/63] net/ice/base: fix for RSS hash on inner UDP port
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (42 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 43/63] net/ice/base: ptype group consolidation Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 45/63] net/ice/base: packet encapsulation for RSS Qi Zhang
` (19 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, stable, Zhirun Yan, Paul M Stillwell Jr
Before this patch, only outer IP with inner UDP port can appear in
RSS hash, because the extraction sequence uses outer IP protocol
ID with Inner UDP protocol ID. ICE_PROT_UDP_OF always extracts the
TUNNELED UDP port values (i.e., 4789 for VXLAN). ICE_PROT_UDP_IL_OR_S
will extract NON-TUNNELED UDP port or inner UDP port.
Fixes: aa1cd410fa64 ("net/ice/base: add flow module")
Cc: stable@dpdk.org
Signed-off-by: Zhirun Yan <zhirun.yan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flow.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 477cf5dfe..9a35a11d5 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -670,7 +670,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,
break;
case ICE_FLOW_FIELD_IDX_UDP_SRC_PORT:
case ICE_FLOW_FIELD_IDX_UDP_DST_PORT:
- prot_id = seg == 0 ? ICE_PROT_UDP_IL_OR_S : ICE_PROT_UDP_OF;
+ prot_id = ICE_PROT_UDP_IL_OR_S;
break;
case ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT:
case ICE_FLOW_FIELD_IDX_SCTP_DST_PORT:
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 45/63] net/ice/base: packet encapsulation for RSS
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (43 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 44/63] net/ice/base: fix for RSS hash on inner UDP port Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 46/63] net/ice/base: add RSS support for PPPoE and GTPU Qi Zhang
` (18 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Vignesh Sridhar, Paul M Stillwell Jr
RSS configurations calls currently support only non-tunneled packets,
which uses outer-first IPs. Adding another call to configure RSS for
tunneled packets which will enable hashing on inner-last IP. RSS hash
will only be done on the innermost IP.
- Update RSS configuration calls to take packet segment count as input
argument
- Update flow profile ID to include identifier for encapsulated packet
[0:31] : Packet match fields
[32:62]: Protocol header header
[63]: Encapsulation flag, 0 if non-tunneled, 1 if tunneled
Signed-off-by: Vignesh Sridhar <vignesh.sridhar@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flow.c | 132 ++++++++++++++++++++++++----------------
1 file changed, 80 insertions(+), 52 deletions(-)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 9a35a11d5..a49196c1c 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -379,16 +379,9 @@ struct ice_flow_prof_params {
static enum ice_status
ice_flow_val_hdrs(struct ice_flow_seg_info *segs, u8 segs_cnt)
{
- const u32 masks = (ICE_FLOW_SEG_HDRS_L2_MASK |
- ICE_FLOW_SEG_HDRS_L3_MASK |
- ICE_FLOW_SEG_HDRS_L4_MASK);
u8 i;
for (i = 0; i < segs_cnt; i++) {
- /* No header specified */
- if (!(segs[i].hdrs & masks) || (segs[i].hdrs & ~masks))
- return ICE_ERR_PARAM;
-
/* Multiple L3 headers */
if (segs[i].hdrs & ICE_FLOW_SEG_HDRS_L3_MASK &&
!ice_is_pow2(segs[i].hdrs & ICE_FLOW_SEG_HDRS_L3_MASK))
@@ -1866,11 +1859,22 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof)
#define ICE_FLOW_PROF_HASH_S 0
#define ICE_FLOW_PROF_HASH_M (0xFFFFFFFFULL << ICE_FLOW_PROF_HASH_S)
#define ICE_FLOW_PROF_HDR_S 32
-#define ICE_FLOW_PROF_HDR_M (0xFFFFFFFFULL << ICE_FLOW_PROF_HDR_S)
+#define ICE_FLOW_PROF_HDR_M (0x3FFFFFFFULL << ICE_FLOW_PROF_HDR_S)
+#define ICE_FLOW_PROF_ENCAP_S 63
+#define ICE_FLOW_PROF_ENCAP_M (BIT_ULL(ICE_FLOW_PROF_ENCAP_S))
+
+#define ICE_RSS_OUTER_HEADERS 1
+#define ICE_RSS_INNER_HEADERS 2
-#define ICE_FLOW_GEN_PROFID(hash, hdr) \
+/* Flow profile ID format:
+ * [0:31] - Packet match fields
+ * [32:62] - Protocol header
+ * [63] - Encapsulation flag, 0 if non-tunneled, 1 if tunneled
+ */
+#define ICE_FLOW_GEN_PROFID(hash, hdr, segs_cnt) \
(u64)(((u64)(hash) & ICE_FLOW_PROF_HASH_M) | \
- (((u64)(hdr) << ICE_FLOW_PROF_HDR_S) & ICE_FLOW_PROF_HDR_M))
+ (((u64)(hdr) << ICE_FLOW_PROF_HDR_S) & ICE_FLOW_PROF_HDR_M) | \
+ ((u8)((segs_cnt) - 1) ? ICE_FLOW_PROF_ENCAP_M : 0))
/**
* ice_add_rss_cfg_sync - add an RSS configuration
@@ -1878,24 +1882,30 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof)
* @vsi_handle: software VSI handle
* @hashed_flds: hash bit fields (ICE_FLOW_HASH_*) to configure
* @addl_hdrs: protocol header fields
+ * @segs_cnt: packet segment count
*
* Assumption: lock has already been acquired for RSS list
*/
static enum ice_status
ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
- u32 addl_hdrs)
+ u32 addl_hdrs, u8 segs_cnt)
{
const enum ice_block blk = ICE_BLK_RSS;
struct ice_flow_prof *prof = NULL;
struct ice_flow_seg_info *segs;
enum ice_status status = ICE_SUCCESS;
- segs = (struct ice_flow_seg_info *)ice_malloc(hw, sizeof(*segs));
+ if (!segs_cnt || segs_cnt > ICE_FLOW_SEG_MAX)
+ return ICE_ERR_PARAM;
+
+ segs = (struct ice_flow_seg_info *)ice_calloc(hw, segs_cnt,
+ sizeof(*segs));
if (!segs)
return ICE_ERR_NO_MEMORY;
/* Construct the packet segment info from the hashed fields */
- status = ice_flow_set_rss_seg_info(segs, hashed_flds, addl_hdrs);
+ status = ice_flow_set_rss_seg_info(&segs[segs_cnt - 1], hashed_flds,
+ addl_hdrs);
if (status)
goto exit;
@@ -1903,7 +1913,7 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
* and has the input VSI associated to it. If found, no further
* operations required and exit.
*/
- prof = ice_flow_find_prof_conds(hw, blk, ICE_FLOW_RX, segs, 1,
+ prof = ice_flow_find_prof_conds(hw, blk, ICE_FLOW_RX, segs, segs_cnt,
vsi_handle,
ICE_FLOW_FIND_PROF_CHK_FLDS |
ICE_FLOW_FIND_PROF_CHK_VSI);
@@ -1915,7 +1925,7 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
* this profile. The VSI will be added to a new profile created with
* the protocol header and new hash field configuration.
*/
- prof = ice_flow_find_prof_conds(hw, blk, ICE_FLOW_RX, segs, 1,
+ prof = ice_flow_find_prof_conds(hw, blk, ICE_FLOW_RX, segs, segs_cnt,
vsi_handle, ICE_FLOW_FIND_PROF_CHK_VSI);
if (prof) {
status = ice_flow_disassoc_prof(hw, blk, prof, vsi_handle);
@@ -1935,7 +1945,7 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
/* Search for a profile that has same match fields only. If this
* exists then associate the VSI to this profile.
*/
- prof = ice_flow_find_prof_conds(hw, blk, ICE_FLOW_RX, segs, 1,
+ prof = ice_flow_find_prof_conds(hw, blk, ICE_FLOW_RX, segs, segs_cnt,
vsi_handle,
ICE_FLOW_FIND_PROF_CHK_FLDS);
if (prof) {
@@ -1949,8 +1959,10 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
* segment information.
*/
status = ice_flow_add_prof(hw, blk, ICE_FLOW_RX,
- ICE_FLOW_GEN_PROFID(hashed_flds, segs->hdrs),
- segs, 1, NULL, 0, &prof);
+ ICE_FLOW_GEN_PROFID(hashed_flds,
+ segs[segs_cnt - 1].hdrs,
+ segs_cnt),
+ segs, segs_cnt, NULL, 0, &prof);
if (status)
goto exit;
@@ -1992,7 +2004,11 @@ ice_add_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
return ICE_ERR_PARAM;
ice_acquire_lock(&hw->rss_locks);
- status = ice_add_rss_cfg_sync(hw, vsi_handle, hashed_flds, addl_hdrs);
+ status = ice_add_rss_cfg_sync(hw, vsi_handle, hashed_flds, addl_hdrs,
+ ICE_RSS_OUTER_HEADERS);
+ if (!status)
+ status = ice_add_rss_cfg_sync(hw, vsi_handle, hashed_flds,
+ addl_hdrs, ICE_RSS_INNER_HEADERS);
ice_release_lock(&hw->rss_locks);
return status;
@@ -2004,12 +2020,13 @@ ice_add_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
* @vsi_handle: software VSI handle
* @hashed_flds: Packet hash types (ICE_FLOW_HASH_*) to remove
* @addl_hdrs: Protocol header fields within a packet segment
+ * @segs_cnt: packet segment count
*
* Assumption: lock has already been acquired for RSS list
*/
static enum ice_status
ice_rem_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
- u32 addl_hdrs)
+ u32 addl_hdrs, u8 segs_cnt)
{
const enum ice_block blk = ICE_BLK_RSS;
struct ice_flow_seg_info *segs;
@@ -2025,7 +2042,7 @@ ice_rem_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
if (status)
goto out;
- prof = ice_flow_find_prof_conds(hw, blk, ICE_FLOW_RX, segs, 1,
+ prof = ice_flow_find_prof_conds(hw, blk, ICE_FLOW_RX, segs, segs_cnt,
vsi_handle,
ICE_FLOW_FIND_PROF_CHK_FLDS);
if (!prof) {
@@ -2050,6 +2067,40 @@ ice_rem_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
return status;
}
+/**
+ * ice_rem_rss_cfg - remove an existing RSS config with matching hashed fields
+ * @hw: pointer to the hardware structure
+ * @vsi_handle: software VSI handle
+ * @hashed_flds: Packet hash types (ICE_FLOW_HASH_*) to remove
+ * @addl_hdrs: Protocol header fields within a packet segment
+ *
+ * This function will lookup the flow profile based on the input
+ * hash field bitmap, iterate through the profile entry list of
+ * that profile and find entry associated with input VSI to be
+ * removed. Calls are made to underlying flow apis which will in
+ * turn build or update buffers for RSS XLT1 section.
+ */
+enum ice_status
+ice_rem_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
+ u32 addl_hdrs)
+{
+ enum ice_status status;
+
+ if (hashed_flds == ICE_HASH_INVALID ||
+ !ice_is_vsi_valid(hw, vsi_handle))
+ return ICE_ERR_PARAM;
+
+ ice_acquire_lock(&hw->rss_locks);
+ status = ice_rem_rss_cfg_sync(hw, vsi_handle, hashed_flds, addl_hdrs,
+ ICE_RSS_OUTER_HEADERS);
+ if (!status)
+ status = ice_rem_rss_cfg_sync(hw, vsi_handle, hashed_flds,
+ addl_hdrs, ICE_RSS_INNER_HEADERS);
+ ice_release_lock(&hw->rss_locks);
+
+ return status;
+}
+
/* Mapping of AVF hash bit fields to an L3-L4 hash combination.
* As the ice_flow_avf_hdr_field represent individual bit shifts in a hash,
* convert its values to their appropriate flow L3, L4 values.
@@ -2179,36 +2230,6 @@ ice_add_avf_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 avf_hash)
}
/**
- * ice_rem_rss_cfg - remove an existing RSS config with matching hashed fields
- * @hw: pointer to the hardware structure
- * @vsi_handle: software VSI handle
- * @hashed_flds: Packet hash types (ICE_FLOW_HASH_*) to remove
- * @addl_hdrs: Protocol header fields within a packet segment
- *
- * This function will lookup the flow profile based on the input
- * hash field bitmap, iterate through the profile entry list of
- * that profile and find entry associated with input VSI to be
- * removed. Calls are made to underlying flow apis which will in
- * turn build or update buffers for RSS XLT1 section.
- */
-enum ice_status
-ice_rem_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
- u32 addl_hdrs)
-{
- enum ice_status status;
-
- if (hashed_flds == ICE_HASH_INVALID ||
- !ice_is_vsi_valid(hw, vsi_handle))
- return ICE_ERR_PARAM;
-
- ice_acquire_lock(&hw->rss_locks);
- status = ice_rem_rss_cfg_sync(hw, vsi_handle, hashed_flds, addl_hdrs);
- ice_release_lock(&hw->rss_locks);
-
- return status;
-}
-
-/**
* ice_replay_rss_cfg - replay RSS configurations associated with VSI
* @hw: pointer to the hardware structure
* @vsi_handle: software VSI handle
@@ -2227,7 +2248,14 @@ enum ice_status ice_replay_rss_cfg(struct ice_hw *hw, u16 vsi_handle)
if (ice_is_bit_set(r->vsis, vsi_handle)) {
status = ice_add_rss_cfg_sync(hw, vsi_handle,
r->hashed_flds,
- r->packet_hdr);
+ r->packet_hdr,
+ ICE_RSS_OUTER_HEADERS);
+ if (status)
+ break;
+ status = ice_add_rss_cfg_sync(hw, vsi_handle,
+ r->hashed_flds,
+ r->packet_hdr,
+ ICE_RSS_INNER_HEADERS);
if (status)
break;
}
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 46/63] net/ice/base: add RSS support for PPPoE and GTPU
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (44 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 45/63] net/ice/base: packet encapsulation for RSS Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 47/63] net/ice/base: remove unnecessary conditional check Qi Zhang
` (17 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Zhirun Yan, Paul M Stillwell Jr
Added RSS support for PPPoE with inner TCP and UDP.
Added RSS support for GTPU with IPv4 and IPv6.
Signed-off-by: Zhirun Yan <zhirun.yan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flow.c | 38 ++++++++++++++++++++++++++++----------
drivers/net/ice/base/ice_flow.h | 17 +++++++++++++++--
2 files changed, 43 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index a49196c1c..f71ac50d6 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -167,7 +167,7 @@ static const u32 ice_ptypes_macvlan_il[] = {
static const u32 ice_ptypes_ipv4_ofos[] = {
0xFDC00000, 0xBFBF7F7E, 0x00EFDFDF, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x0003000F, 0x00000000, 0x00000000, 0x00000000,
+ 0x0003000F, 0x000FC000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -179,7 +179,7 @@ static const u32 ice_ptypes_ipv4_ofos[] = {
static const u32 ice_ptypes_ipv4_il[] = {
0xE0000000, 0xB807700E, 0x8001DC03, 0xE01DC03B,
0x0007700E, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x000FF800, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -191,7 +191,7 @@ static const u32 ice_ptypes_ipv4_il[] = {
static const u32 ice_ptypes_ipv6_ofos[] = {
0x00000000, 0x00000000, 0xF7000000, 0xFEFDFDFB,
0x03BF7F7E, 0x00000000, 0x00000000, 0x00000000,
- 0x00080F00, 0x00000000, 0x00000000, 0x00000000,
+ 0x00080F00, 0x03F00000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -203,7 +203,7 @@ static const u32 ice_ptypes_ipv6_ofos[] = {
static const u32 ice_ptypes_ipv6_il[] = {
0x00000000, 0x03B80770, 0x00EE01DC, 0x0EE00000,
0x03B80770, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x7FE00000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -229,7 +229,7 @@ static const u32 ice_ptypes_arp_of[] = {
static const u32 ice_ptypes_udp_il[] = {
0x81000000, 0x20204040, 0x04081010, 0x80810102,
0x00204040, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00410000, 0x10842000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -241,7 +241,7 @@ static const u32 ice_ptypes_udp_il[] = {
static const u32 ice_ptypes_tcp_il[] = {
0x04000000, 0x80810102, 0x10204040, 0x42040408,
0x00810102, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00820000, 0x21084000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -277,7 +277,7 @@ static const u32 ice_ptypes_icmp_of[] = {
static const u32 ice_ptypes_icmp_il[] = {
0x00000000, 0x02040408, 0x40810102, 0x08101020,
0x02040408, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x42108000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -345,6 +345,18 @@ static const u32 ice_ptypes_gtpu[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
+/* Packet types for pppoe */
+static const u32 ice_ptypes_pppoe[] = {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x03FFF000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
/* Manage parameters and info. used during the creation of a flow profile */
struct ice_flow_prof_params {
enum ice_block blk;
@@ -368,8 +380,7 @@ struct ice_flow_prof_params {
#define ICE_FLOW_SEG_HDRS_L4_MASK \
(ICE_FLOW_SEG_HDR_ICMP | ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_UDP | \
ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_GTPC | \
- ICE_FLOW_SEG_HDR_GTPC_TEID | ICE_FLOW_SEG_HDR_GTPU_IP | \
- ICE_FLOW_SEG_HDR_GTPU_UP | ICE_FLOW_SEG_HDR_GTPU_DWN)
+ ICE_FLOW_SEG_HDR_GTPC_TEID | ICE_FLOW_SEG_HDR_GTPU)
/**
* ice_flow_val_hdrs - validates packet segments for valid protocol headers
@@ -487,6 +498,12 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params)
ICE_FLOW_PTYPE_MAX);
}
+ if (hdrs & ICE_FLOW_SEG_HDR_PPPOE) {
+ src = (const ice_bitmap_t *)ice_ptypes_pppoe;
+ ice_and_bitmap(params->ptypes, params->ptypes, src,
+ ICE_FLOW_PTYPE_MAX);
+ }
+
if (hdrs & ICE_FLOW_SEG_HDR_IPV4) {
src = !i ? (const ice_bitmap_t *)ice_ptypes_ipv4_ofos :
(const ice_bitmap_t *)ice_ptypes_ipv4_il;
@@ -1670,7 +1687,8 @@ ice_flow_add_fld_raw(struct ice_flow_seg_info *seg, u16 off, u8 len,
#define ICE_FLOW_RSS_SEG_HDR_L4_MASKS \
(ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_UDP | \
- ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_GTPC_TEID)
+ ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_GTPC_TEID | \
+ ICE_FLOW_SEG_HDR_GTPU)
#define ICE_FLOW_RSS_SEG_HDR_VAL_MASKS \
diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h
index eb8e1b733..0bb3efca0 100644
--- a/drivers/net/ice/base/ice_flow.h
+++ b/drivers/net/ice/base/ice_flow.h
@@ -42,15 +42,28 @@
#define ICE_HASH_SCTP_IPV6 (ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_SCTP_PORT)
#define ICE_FLOW_HASH_GTP_TEID \
- (ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_GTPC_TEID))
+ (BIT_ULL(ICE_FLOW_FIELD_IDX_GTPC_TEID))
#define ICE_FLOW_HASH_GTP_IPV4_TEID \
(ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_GTP_TEID)
#define ICE_FLOW_HASH_GTP_IPV6_TEID \
(ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_GTP_TEID)
+#define ICE_FLOW_HASH_GTP_U_TEID \
+ (BIT_ULL(ICE_FLOW_FIELD_IDX_GTPU_IP_TEID))
+
+#define ICE_FLOW_HASH_GTP_U_IPV4_TEID \
+ (ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_GTP_U_TEID)
+#define ICE_FLOW_HASH_GTP_U_IPV6_TEID \
+ (ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_GTP_U_TEID)
+
#define ICE_FLOW_HASH_PPPOE_SESS_ID \
- (ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID))
+ (BIT_ULL(ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID))
+
+#define ICE_FLOW_HASH_PPPOE_TCP_ID \
+ (ICE_FLOW_HASH_TCP_PORT | ICE_FLOW_HASH_PPPOE_SESS_ID)
+#define ICE_FLOW_HASH_PPPOE_UDP_ID \
+ (ICE_FLOW_HASH_UDP_PORT | ICE_FLOW_HASH_PPPOE_SESS_ID)
/* Protocol header fields within a packet segment. A segment consists of one or
* more protocol headers that make up a logical group of protocol headers. Each
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 47/63] net/ice/base: remove unnecessary conditional check
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (45 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 46/63] net/ice/base: add RSS support for PPPoE and GTPU Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 48/63] net/ice/base: fix flag settings in AQ call Qi Zhang
` (16 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Bruce Allan, Paul M Stillwell Jr
There is no reason to do this conditional check before the assignment so
simply remove it.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index ef3a919ec..a4966d0a1 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -1145,8 +1145,7 @@ ice_add_vsi(struct ice_hw *hw, u16 vsi_handle, struct ice_vsi_ctx *vsi_ctx,
ice_save_vsi_ctx(hw, vsi_handle, tmp_vsi_ctx);
} else {
/* update with new HW VSI num */
- if (tmp_vsi_ctx->vsi_num != vsi_ctx->vsi_num)
- tmp_vsi_ctx->vsi_num = vsi_ctx->vsi_num;
+ tmp_vsi_ctx->vsi_num = vsi_ctx->vsi_num;
}
return ICE_SUCCESS;
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 48/63] net/ice/base: fix flag settings in AQ call
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (46 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 47/63] net/ice/base: remove unnecessary conditional check Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 49/63] net/ice/base: refactor removal of VLAN promiscuous rules Qi Zhang
` (15 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, stable, Dan Nowlin, Paul M Stillwell Jr
Removed setting Read flag in the Get Allocated Resource Descriptors AQ
command (0x020A). The read flag is not required for this command and
causes the FW to return an error.
Fixes: d781ccbdd15d ("net/ice/base: add functions to get allocated resources")
Cc: stable@dpdk.org
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index a4966d0a1..9e85da530 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -2978,8 +2978,6 @@ ice_aq_get_res_descs(struct ice_hw *hw, u16 num_entries,
ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
cmd->ops.cmd.first_desc = CPU_TO_LE16(*desc_id);
- desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
-
status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
if (!status)
*desc_id = LE16_TO_CPU(cmd->ops.resp.next_desc);
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 49/63] net/ice/base: refactor removal of VLAN promiscuous rules
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (47 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 48/63] net/ice/base: fix flag settings in AQ call Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 50/63] net/ice/base: maximize switch recipe words per line Qi Zhang
` (14 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Brett Creeley, Paul M Stillwell Jr
Currently ice_clear_vsi_promisc() detects if the VLAN ID sent is not 0
and sets the recipe_id to ICE_SW_LKUP_PROMISC_VLAN in that case and
ICE_SW_LKUP_PROMISC if the VLAN_ID is 0. However this doesn't allow VLAN
0 promiscuous rules to be removed, but they can be added. Fix this by
checking if the promisc_mask contains ICE_PROMISC_VLAN_RX or
ICE_PROMISC_VLAN_TX. This change was made to match what is being done
for ice_set_vsi_promisc().
Signed-off-by: Brett Creeley <brett.creeley@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 9e85da530..1f077d562 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -3977,7 +3977,7 @@ ice_clear_vsi_promisc(struct ice_hw *hw, u16 vsi_handle, u8 promisc_mask,
if (!ice_is_vsi_valid(hw, vsi_handle))
return ICE_ERR_PARAM;
- if (vid)
+ if (promisc_mask & (ICE_PROMISC_VLAN_RX | ICE_PROMISC_VLAN_TX))
recipe_id = ICE_SW_LKUP_PROMISC_VLAN;
else
recipe_id = ICE_SW_LKUP_PROMISC;
@@ -3990,13 +3990,18 @@ ice_clear_vsi_promisc(struct ice_hw *hw, u16 vsi_handle, u8 promisc_mask,
ice_acquire_lock(rule_lock);
LIST_FOR_EACH_ENTRY(itr, rule_head,
ice_fltr_mgmt_list_entry, list_entry) {
+ struct ice_fltr_info *fltr_info;
u8 fltr_promisc_mask = 0;
if (!ice_vsi_uses_fltr(itr, vsi_handle))
continue;
+ fltr_info = &itr->fltr_info;
+
+ if (recipe_id == ICE_SW_LKUP_PROMISC_VLAN &&
+ vid != fltr_info->l_data.mac_vlan.vlan_id)
+ continue;
- fltr_promisc_mask |=
- ice_determine_promisc_mask(&itr->fltr_info);
+ fltr_promisc_mask |= ice_determine_promisc_mask(fltr_info);
/* Skip if filter is not completely specified by given mask */
if (fltr_promisc_mask & ~promisc_mask)
@@ -4004,7 +4009,7 @@ ice_clear_vsi_promisc(struct ice_hw *hw, u16 vsi_handle, u8 promisc_mask,
status = ice_add_entry_to_vsi_fltr_list(hw, vsi_handle,
&remove_list_head,
- &itr->fltr_info);
+ fltr_info);
if (status) {
ice_release_lock(rule_lock);
goto free_fltr_list;
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 50/63] net/ice/base: maximize switch recipe words per line
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (48 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 49/63] net/ice/base: refactor removal of VLAN promiscuous rules Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 51/63] net/ice/base: update switch training packets with open ports Qi Zhang
` (13 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
Remove grouping rules to maximize the number of words placed into
a recipe line. This will allow more recipes to be added by reducing
the number of result indices required.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 128 --------------------------------------
1 file changed, 128 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 1f077d562..ef12df5db 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -4655,17 +4655,6 @@ static const struct ice_prot_ext_tbl_entry ice_prot_ext[] = {
* following combinations, then the recipe needs to be chained as per the
* following policy.
*/
-static const struct ice_pref_recipe_group ice_recipe_pack[] = {
- {3, { { ICE_MAC_OFOS_HW, 0, 0 }, { ICE_MAC_OFOS_HW, 2, 0 },
- { ICE_MAC_OFOS_HW, 4, 0 } }, { 0xffff, 0xffff, 0xffff, 0xffff } },
- {4, { { ICE_MAC_IL_HW, 0, 0 }, { ICE_MAC_IL_HW, 2, 0 },
- { ICE_MAC_IL_HW, 4, 0 }, { ICE_META_DATA_ID_HW, 44, 0 } },
- { 0xffff, 0xffff, 0xffff, 0xffff } },
- {2, { { ICE_IPV4_IL_HW, 0, 0 }, { ICE_IPV4_IL_HW, 2, 0 } },
- { 0xffff, 0xffff, 0xffff, 0xffff } },
- {2, { { ICE_IPV4_IL_HW, 12, 0 }, { ICE_IPV4_IL_HW, 14, 0 } },
- { 0xffff, 0xffff, 0xffff, 0xffff } },
-};
static const struct ice_protocol_entry ice_prot_id_tbl[] = {
{ ICE_MAC_OFOS, ICE_MAC_OFOS_HW },
@@ -4812,75 +4801,7 @@ ice_fill_valid_words(struct ice_adv_lkup_elem *rule,
return ret_val;
}
-/**
- * ice_find_prot_off_ind - check for specific ID and offset in rule
- * @lkup_exts: an array of protocol header extractions
- * @prot_type: protocol type to check
- * @off: expected offset of the extraction
- *
- * Check if the prot_ext has given protocol ID and offset
- */
-static u8
-ice_find_prot_off_ind(struct ice_prot_lkup_ext *lkup_exts, u8 prot_type,
- u16 off)
-{
- u8 j;
-
- for (j = 0; j < lkup_exts->n_val_words; j++)
- if (lkup_exts->fv_words[j].off == off &&
- lkup_exts->fv_words[j].prot_id == prot_type)
- return j;
-
- return ICE_MAX_CHAIN_WORDS;
-}
-
-/**
- * ice_is_recipe_subset - check if recipe group policy is a subset of lookup
- * @lkup_exts: an array of protocol header extractions
- * @r_policy: preferred recipe grouping policy
- *
- * Helper function to check if given recipe group is subset we need to check if
- * all the words described by the given recipe group exist in the advanced rule
- * look up information
- */
-static bool
-ice_is_recipe_subset(struct ice_prot_lkup_ext *lkup_exts,
- const struct ice_pref_recipe_group *r_policy)
-{
- u8 ind[ICE_NUM_WORDS_RECIPE];
- u8 count = 0;
- u8 i;
-
- /* check if everything in the r_policy is part of the entire rule */
- for (i = 0; i < r_policy->n_val_pairs; i++) {
- u8 j;
-
- j = ice_find_prot_off_ind(lkup_exts, r_policy->pairs[i].prot_id,
- r_policy->pairs[i].off);
- if (j >= ICE_MAX_CHAIN_WORDS)
- return false;
-
- /* store the indexes temporarily found by the find function
- * this will be used to mark the words as 'done'
- */
- ind[count++] = j;
- }
-
- /* If the entire policy recipe was a true match, then mark the fields
- * that are covered by the recipe as 'done' meaning that these words
- * will be clumped together in one recipe.
- * "Done" here means in our searching if certain recipe group
- * matches or is subset of the given rule, then we mark all
- * the corresponding offsets as found. So the remaining recipes should
- * be created with whatever words that were left.
- */
- for (i = 0; i < count; i++) {
- u8 in = ind[i];
- ice_set_bit(in, lkup_exts->done);
- }
- return true;
-}
/**
* ice_create_first_fit_recp_def - Create a recipe grouping
@@ -5389,51 +5310,11 @@ static enum ice_status
ice_create_recipe_group(struct ice_hw *hw, struct ice_sw_recipe *rm,
struct ice_prot_lkup_ext *lkup_exts)
{
- struct ice_recp_grp_entry *entry;
- struct ice_recp_grp_entry *tmp;
enum ice_status status;
u8 recp_count = 0;
- u16 groups, i;
rm->n_grp_count = 0;
-
- if (lkup_exts->n_val_words > ICE_NUM_WORDS_RECIPE) {
- /* Each switch recipe can match up to 5 words or metadata. One
- * word in each recipe is used to match the switch ID. Four
- * words are left for matching other values. If the new advanced
- * recipe requires more than 4 words, it needs to be split into
- * multiple recipes which are chained together using the
- * intermediate result that each produces as input to the other
- * recipes in the sequence.
- */
- groups = ARRAY_SIZE(ice_recipe_pack);
-
- /* Check if any of the preferred recipes from the grouping
- * policy matches.
- */
- for (i = 0; i < groups; i++)
- /* Check if the recipe from the preferred grouping
- * matches or is a subset of the fields that needs to be
- * looked up.
- */
- if (ice_is_recipe_subset(lkup_exts,
- &ice_recipe_pack[i])) {
- /* This recipe can be used by itself or grouped
- * with other recipes.
- */
- entry = (struct ice_recp_grp_entry *)
- ice_malloc(hw, sizeof(*entry));
- if (!entry) {
- status = ICE_ERR_NO_MEMORY;
- goto err_unroll;
- }
- entry->r_group = ice_recipe_pack[i];
- LIST_ADD(&entry->l_entry, &rm->rg_list);
- rm->n_grp_count++;
- }
- }
-
/* Create recipes for words that are marked not done by packing them
* as best fit.
*/
@@ -5446,17 +5327,8 @@ ice_create_recipe_group(struct ice_hw *hw, struct ice_sw_recipe *rm,
sizeof(rm->ext_words), ICE_NONDMA_TO_NONDMA);
ice_memcpy(rm->word_masks, lkup_exts->field_mask,
sizeof(rm->word_masks), ICE_NONDMA_TO_NONDMA);
- goto out;
}
-err_unroll:
- LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rm->rg_list, ice_recp_grp_entry,
- l_entry) {
- LIST_DEL(&entry->l_entry);
- ice_free(hw, entry);
- }
-
-out:
return status;
}
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 51/63] net/ice/base: update switch training packets with open ports
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (49 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 50/63] net/ice/base: maximize switch recipe words per line Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 52/63] net/ice/base: remove unnecessary dummy packet finding Qi Zhang
` (12 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
This patch updates UDP tunneled training packets with an appropriate
UDP dest port. For the correct profile to be chosen, an open tunnel
port must be included in the training packet.
Added GENEVE tunnel labels in the test package in order to test GENEVE
tunnel rule creation.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 57 +++++++++++++++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index ef12df5db..c39a77a0f 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -5826,6 +5826,55 @@ ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,
}
/**
+ * ice_fill_adv_packet_tun - fill dummy packet with udp tunnel port
+ * @hw: pointer to the hardware structure
+ * @tun_type: tunnel type
+ * @pkt: dummy packet to fill in
+ * @offsets: offset info for the dummy packet
+ */
+static enum ice_status
+ice_fill_adv_packet_tun(struct ice_hw *hw, enum ice_sw_tunnel_type tun_type,
+ u8 *pkt, const struct ice_dummy_pkt_offsets *offsets)
+{
+ u16 open_port, i;
+
+ switch (tun_type) {
+ case ICE_SW_TUN_AND_NON_TUN:
+ case ICE_SW_TUN_VXLAN_GPE:
+ case ICE_SW_TUN_VXLAN:
+ case ICE_SW_TUN_UDP:
+ if (!ice_get_open_tunnel_port(hw, TNL_VXLAN, &open_port))
+ return ICE_ERR_CFG;
+ break;
+
+ case ICE_SW_TUN_GENEVE:
+ if (!ice_get_open_tunnel_port(hw, TNL_GENEVE, &open_port))
+ return ICE_ERR_CFG;
+ break;
+
+ default:
+ /* Nothing needs to be done for this tunnel type */
+ return ICE_SUCCESS;
+ }
+
+ /* Find the outer UDP protocol header and insert the port number */
+ for (i = 0; offsets[i].type != ICE_PROTOCOL_LAST; i++) {
+ if (offsets[i].type == ICE_UDP_OF) {
+ struct ice_l4_hdr *hdr;
+ u16 offset;
+
+ offset = offsets[i].offset;
+ hdr = (struct ice_l4_hdr *)&pkt[offset];
+ hdr->dst_port = open_port << 8 | open_port >> 8;
+
+ return ICE_SUCCESS;
+ }
+ }
+
+ return ICE_ERR_CFG;
+}
+
+/**
* ice_find_adv_rule_entry - Search a rule entry
* @hw: pointer to the hardware structure
* @lkups: lookup elements or match criteria for the advanced recipe, one
@@ -6129,6 +6178,14 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
ice_fill_adv_dummy_packet(lkups, lkups_cnt, s_rule, pkt, pkt_len,
pkt_offsets);
+ if (rinfo->tun_type != ICE_NON_TUN) {
+ status = ice_fill_adv_packet_tun(hw, rinfo->tun_type,
+ s_rule->pdata.lkup_tx_rx.hdr,
+ pkt_offsets);
+ if (status)
+ goto err_ice_add_adv_rule;
+ }
+
status = ice_aq_sw_rules(hw, (struct ice_aqc_sw_rules *)s_rule,
rule_buf_sz, 1, ice_aqc_opc_add_sw_rules,
NULL);
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 52/63] net/ice/base: remove unnecessary dummy packet finding
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (50 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 51/63] net/ice/base: update switch training packets with open ports Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 53/63] net/ice/base: remove unnecessary if branch Qi Zhang
` (11 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang; +Cc: dev, xiaolong.ye, Qi Zhang, Paul M Stillwell Jr
We don't need to find a dummy packet when removing a rule so remove
the call to get the dummy packet. This also obviates some variables
so remove them also.
Also reduce the scope of rule_buf_sz.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 10 +++-------
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index c39a77a0f..063a26ec5 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -6360,14 +6360,11 @@ ice_rem_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
u16 lkups_cnt, struct ice_adv_rule_info *rinfo)
{
struct ice_adv_fltr_mgmt_list_entry *list_elem;
- const struct ice_dummy_pkt_offsets *offsets;
struct ice_prot_lkup_ext lkup_exts;
- u16 rule_buf_sz, pkt_len, i, rid;
struct ice_lock *rule_lock; /* Lock to protect filter rule list */
enum ice_status status = ICE_SUCCESS;
bool remove_rule = false;
- const u8 *pkt = NULL;
- u16 vsi_handle;
+ u16 i, rid, vsi_handle;
ice_memset(&lkup_exts, 0, sizeof(lkup_exts), ICE_NONDMA_MEM);
for (i = 0; i < lkups_cnt; i++) {
@@ -6419,10 +6416,9 @@ ice_rem_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
ice_release_lock(rule_lock);
if (remove_rule) {
struct ice_aqc_sw_rules_elem *s_rule;
+ u16 rule_buf_sz;
- ice_find_dummy_packet(lkups, lkups_cnt, rinfo->tun_type, &pkt,
- &pkt_len, &offsets);
- rule_buf_sz = ICE_SW_RULE_RX_TX_NO_HDR_SIZE + pkt_len;
+ rule_buf_sz = ICE_SW_RULE_RX_TX_NO_HDR_SIZE;
s_rule =
(struct ice_aqc_sw_rules_elem *)ice_malloc(hw,
rule_buf_sz);
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 53/63] net/ice/base: remove unnecessary if branch
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (51 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 52/63] net/ice/base: remove unnecessary dummy packet finding Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 54/63] net/ice/base: correct abbreviations Qi Zhang
` (10 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang; +Cc: dev, xiaolong.ye, Qi Zhang, Paul M Stillwell Jr
We are already in the branch "if (fm_list->vsi_count == 1)"
no need to exit and re-enter.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 063a26ec5..3ae53d3d8 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -6319,9 +6319,7 @@ ice_adv_rem_update_vsi_list(struct ice_hw *hw, u16 vsi_handle,
tmp_fltr.fwd_id.hw_vsi_id, status);
return status;
}
- }
- if (fm_list->vsi_count == 1) {
/* Remove the VSI list since it is no longer used */
status = ice_remove_vsi_list_rule(hw, vsi_list_id, lkup_type);
if (status) {
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 54/63] net/ice/base: correct abbreviations
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (52 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 53/63] net/ice/base: remove unnecessary if branch Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 55/63] net/ice/base: update to register definition file Qi Zhang
` (9 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Tony Nguyen, Paul M Stillwell Jr
Correct abbreviation issues found by running abbrevcheck.
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 4 ++--
drivers/net/ice/base/ice_controlq.c | 2 +-
drivers/net/ice/base/ice_controlq.h | 2 +-
drivers/net/ice/base/ice_flex_pipe.c | 22 +++++++++++-----------
drivers/net/ice/base/ice_flex_type.h | 2 +-
drivers/net/ice/base/ice_flow.c | 2 +-
drivers/net/ice/base/ice_type.h | 2 +-
7 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index c2d4f1f05..feb7676f8 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -655,10 +655,10 @@ static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
/**
- * ice_get_itr_intrl_gran - determine int/intrl granularity
+ * ice_get_itr_intrl_gran
* @hw: pointer to the HW struct
*
- * Determines the itr/intrl granularities based on the maximum aggregate
+ * Determines the ITR/INTRL granularities based on the maximum aggregate
* bandwidth according to the device's configuration during power-on.
*/
static void ice_get_itr_intrl_gran(struct ice_hw *hw)
diff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c
index 70a50bff4..501f986b9 100644
--- a/drivers/net/ice/base/ice_controlq.c
+++ b/drivers/net/ice/base/ice_controlq.c
@@ -412,7 +412,7 @@ do { \
/* free the buffer info list */ \
if ((qi)->ring.cmd_buf) \
ice_free(hw, (qi)->ring.cmd_buf); \
- /* free dma head */ \
+ /* free DMA head */ \
ice_free(hw, (qi)->ring.dma_head); \
} while (0)
diff --git a/drivers/net/ice/base/ice_controlq.h b/drivers/net/ice/base/ice_controlq.h
index 21c8722e5..acb4ab49e 100644
--- a/drivers/net/ice/base/ice_controlq.h
+++ b/drivers/net/ice/base/ice_controlq.h
@@ -37,7 +37,7 @@ enum ice_ctl_q {
#define ICE_CTL_Q_SQ_CMD_TIMEOUT 250 /* msecs */
struct ice_ctl_q_ring {
- void *dma_head; /* Virtual address to dma head */
+ void *dma_head; /* Virtual address to DMA head */
struct ice_dma_mem desc_buf; /* descriptor ring memory */
void *cmd_buf; /* command buffer memory */
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index 6ae71e698..4ad816874 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -1921,7 +1921,7 @@ ice_create_tunnel(struct ice_hw *hw, enum ice_tunnel_type type, u16 port)
if (!bld)
return ICE_ERR_NO_MEMORY;
- /* allocate 2 sections, one for RX parser, one for TX parser */
+ /* allocate 2 sections, one for Rx parser, one for Tx parser */
if (ice_pkg_buf_reserve_section(bld, 2))
goto ice_create_tunnel_err;
@@ -1951,7 +1951,7 @@ ice_create_tunnel(struct ice_hw *hw, enum ice_tunnel_type type, u16 port)
offsetof(struct ice_boost_key_value, hv_dst_port_key),
sizeof(sect_rx->tcam[0].key.key.hv_dst_port_key));
- /* exact copy of entry to TX section entry */
+ /* exact copy of entry to Tx section entry */
ice_memcpy(sect_tx->tcam, sect_rx->tcam, sizeof(*sect_tx->tcam),
ICE_NONDMA_TO_NONDMA);
@@ -2002,7 +2002,7 @@ enum ice_status ice_destroy_tunnel(struct ice_hw *hw, u16 port, bool all)
if (!bld)
return ICE_ERR_NO_MEMORY;
- /* allocate 2 sections, one for RX parser, one for TX parser */
+ /* allocate 2 sections, one for Rx parser, one for Tx parser */
if (ice_pkg_buf_reserve_section(bld, 2))
goto ice_destroy_tunnel_err;
@@ -2020,8 +2020,8 @@ enum ice_status ice_destroy_tunnel(struct ice_hw *hw, u16 port, bool all)
goto ice_destroy_tunnel_err;
sect_tx->count = CPU_TO_LE16(1);
- /* copy original boost entry to update package buffer, one copy to RX
- * section, another copy to the TX section
+ /* copy original boost entry to update package buffer, one copy to Rx
+ * section, another copy to the Tx section
*/
for (i = 0; i < hw->tnl.count && i < ICE_TUNNEL_MAX_ENTRIES; i++)
if (hw->tnl.tbl[i].valid && hw->tnl.tbl[i].in_use &&
@@ -2919,7 +2919,7 @@ ice_write_prof_mask_reg(struct ice_hw *hw, enum ice_block blk, u16 mask_idx,
* ice_write_prof_mask_enable_res - write profile mask enable register
* @hw: pointer to the HW struct
* @blk: hardware block
- * @prof_id: profile id
+ * @prof_id: profile ID
* @enable_mask: enable mask
*/
static void
@@ -3095,7 +3095,7 @@ ice_free_prof_mask(struct ice_hw *hw, enum ice_block blk, u16 mask_idx)
* ice_free_prof_masks - free all profile masks for a profile
* @hw: pointer to the HW struct
* @blk: hardware block
- * @prof_id: profile id
+ * @prof_id: profile ID
*/
static enum ice_status
ice_free_prof_masks(struct ice_hw *hw, enum ice_block blk, u16 prof_id)
@@ -3157,7 +3157,7 @@ void ice_shutdown_all_prof_masks(struct ice_hw *hw)
* ice_update_prof_masking - set registers according to masking
* @hw: pointer to the HW struct
* @blk: hardware block
- * @prof_id: profile id
+ * @prof_id: profile ID
* @es: field vector
* @masks: masks
*/
@@ -3377,7 +3377,7 @@ static void ice_fill_tbl(struct ice_hw *hw, enum ice_block block_id, u32 sid)
void *sect;
/* if the HW segment pointer is null then the first iteration of
- * ice_pkg_enum_section() will fail. In this case the Hw tables will
+ * ice_pkg_enum_section() will fail. In this case the HW tables will
* not be filled and return success.
*/
if (!hw->seg) {
@@ -3469,7 +3469,7 @@ static void ice_fill_tbl(struct ice_hw *hw, enum ice_block block_id, u32 sid)
return;
/* if the sum of section size and offset exceed destination size
- * then we are out of bounds of the Hw table size for that PF.
+ * then we are out of bounds of the HW table size for that PF.
* Changing section length to fill the remaining table space
* of that PF.
*/
@@ -3488,7 +3488,7 @@ static void ice_fill_tbl(struct ice_hw *hw, enum ice_block block_id, u32 sid)
*
* Reads the current package contents and populates the driver
* database with the data iteratively for all advanced feature
- * blocks. Assume that the Hw tables have been allocated.
+ * blocks. Assume that the HW tables have been allocated.
*/
void ice_fill_blk_tbls(struct ice_hw *hw)
{
diff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h
index baf53d881..c30d407c2 100644
--- a/drivers/net/ice/base/ice_flex_type.h
+++ b/drivers/net/ice/base/ice_flex_type.h
@@ -577,7 +577,7 @@ struct ice_xlt1 {
/* Vsig bit layout:
* [0:12]: incremental vsig index 1 to ICE_MAX_VSIGS
- * [13:15]: pf number of device
+ * [13:15]: PF number of device
*/
#define ICE_VSIG_IDX_M (0x1FFF)
#define ICE_PF_NUM_S 13
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index f71ac50d6..abdf10b94 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -567,7 +567,7 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params)
* ice_flow_xtract_pkt_flags - Create an extr sequence entry for packet flags
* @hw: pointer to the HW struct
* @params: information about the flow to be processed
- * @flags: The value of pkt_flags[x:x] in RX/TX MDID metadata.
+ * @flags: The value of pkt_flags[x:x] in Rx/Tx MDID metadata.
*
* This function will allocate an extraction sequence entries for a DWORD size
* chunk of the packet flags.
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 403fb7668..deb614e37 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -789,7 +789,7 @@ struct ice_hw {
/* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
- * register. Used for determining the itr/intrl granularity during
+ * register. Used for determining the ITR/INTRL granularity during
* initialization.
*/
#define ICE_MAX_AGG_BW_200G 0x0
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 55/63] net/ice/base: update to register definition file
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (53 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 54/63] net/ice/base: correct abbreviations Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 56/63] net/ice/base: replace open-code duplication Qi Zhang
` (8 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Bruce Allan, Paul M Stillwell Jr
Added register definitions for GL_MDCK_TX_TDPU and GL_MDET_TX_TDPU.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_hw_autogen.h | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/drivers/net/ice/base/ice_hw_autogen.h b/drivers/net/ice/base/ice_hw_autogen.h
index 2b423baf8..6f227adb8 100644
--- a/drivers/net/ice/base/ice_hw_autogen.h
+++ b/drivers/net/ice/base/ice_hw_autogen.h
@@ -5330,6 +5330,29 @@
#define GL_MDCK_RX 0x0029422C /* Reset Source: CORER */
#define GL_MDCK_RX_DESC_ADDR_S 0
#define GL_MDCK_RX_DESC_ADDR_M BIT(0)
+#define GL_MDCK_TX_TDPU 0x00049348 /* Reset Source: CORER */
+#define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_S 0
+#define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_M BIT(0)
+#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_S 1
+#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)
+#define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_S 2
+#define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_M BIT(2)
+#define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_S 3
+#define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_M BIT(3)
+#define GL_MDCK_TX_TDPU_MAL_CMD_ITR_DIS_S 4
+#define GL_MDCK_TX_TDPU_MAL_CMD_ITR_DIS_M BIT(4)
+#define GL_MDCK_TX_TDPU_BIG_PKT_SIZE_ITR_DIS_S 5
+#define GL_MDCK_TX_TDPU_BIG_PKT_SIZE_ITR_DIS_M BIT(5)
+#define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_S 6
+#define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_M BIT(6)
+#define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_S 7
+#define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_M BIT(7)
+#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_S 8
+#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_M BIT(8)
+#define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_S 9
+#define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_M BIT(9)
+#define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_S 10
+#define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_M BIT(10)
#define GL_MDET_RX 0x00294C00 /* Reset Source: CORER */
#define GL_MDET_RX_QNUM_S 0
#define GL_MDET_RX_QNUM_M MAKEMASK(0x7FFF, 0)
@@ -5363,6 +5386,17 @@
#define GL_MDET_TX_TCLAN_MAL_TYPE_M MAKEMASK(0x1F, 26)
#define GL_MDET_TX_TCLAN_VALID_S 31
#define GL_MDET_TX_TCLAN_VALID_M BIT(31)
+#define GL_MDET_TX_TDPU 0x00049350 /* Reset Source: CORER */
+#define GL_MDET_TX_TDPU_QNUM_S 0
+#define GL_MDET_TX_TDPU_QNUM_M MAKEMASK(0x7FFF, 0)
+#define GL_MDET_TX_TDPU_VF_NUM_S 15
+#define GL_MDET_TX_TDPU_VF_NUM_M MAKEMASK(0xFF, 15)
+#define GL_MDET_TX_TDPU_PF_NUM_S 23
+#define GL_MDET_TX_TDPU_PF_NUM_M MAKEMASK(0x7, 23)
+#define GL_MDET_TX_TDPU_MAL_TYPE_S 26
+#define GL_MDET_TX_TDPU_MAL_TYPE_M MAKEMASK(0x1F, 26)
+#define GL_MDET_TX_TDPU_VALID_S 31
+#define GL_MDET_TX_TDPU_VALID_M BIT(31)
#define GLRLAN_MDET 0x00294200 /* Reset Source: CORER */
#define GLRLAN_MDET_PCKT_EXTRCT_ERR_S 0
#define GLRLAN_MDET_PCKT_EXTRCT_ERR_M BIT(0)
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 56/63] net/ice/base: replace open-code duplication
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (54 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 55/63] net/ice/base: update to register definition file Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:50 ` [dpdk-dev] [PATCH 57/63] net/ice/base: delay less Qi Zhang
` (7 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Bruce Allan, Paul M Stillwell Jr
Use BIT_ULL() instead of ICE_FLOW_HASH_FLD() which does the same bit shift
operation.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flow.h | 24 +++++++++++-------------
1 file changed, 11 insertions(+), 13 deletions(-)
diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h
index 0bb3efca0..2ec9bb022 100644
--- a/drivers/net/ice/base/ice_flow.h
+++ b/drivers/net/ice/base/ice_flow.h
@@ -14,24 +14,22 @@
#define ICE_FLOW_VSI_INVAL 0xffff
#define ICE_FLOW_FLD_OFF_INVAL 0xffff
-/* Use any of the type from flow field to generate a equivalent hash field */
-#define ICE_FLOW_HASH_FLD(t) (1ULL << (t))
-
+/* Generate flow hash field from flow field type(s) */
#define ICE_FLOW_HASH_IPV4 \
- (ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_IPV4_SA) | \
- ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_IPV4_DA))
+ (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) | \
+ BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA))
#define ICE_FLOW_HASH_IPV6 \
- (ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_IPV6_SA) | \
- ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_IPV6_DA))
+ (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_SA) | \
+ BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_DA))
#define ICE_FLOW_HASH_TCP_PORT \
- (ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_TCP_SRC_PORT) | \
- ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_TCP_DST_PORT))
+ (BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_SRC_PORT) | \
+ BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_DST_PORT))
#define ICE_FLOW_HASH_UDP_PORT \
- (ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_UDP_SRC_PORT) | \
- ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_UDP_DST_PORT))
+ (BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_SRC_PORT) | \
+ BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_DST_PORT))
#define ICE_FLOW_HASH_SCTP_PORT \
- (ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT) | \
- ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_SCTP_DST_PORT))
+ (BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT) | \
+ BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_DST_PORT))
#define ICE_HASH_INVALID 0
#define ICE_HASH_TCP_IPV4 (ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_TCP_PORT)
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 57/63] net/ice/base: delay less
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (55 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 56/63] net/ice/base: replace open-code duplication Qi Zhang
@ 2019-08-26 10:50 ` Qi Zhang
2019-08-26 10:51 ` [dpdk-dev] [PATCH 58/63] net/ice/base: add AQC get link topology handle support Qi Zhang
` (6 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:50 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Mitch Williams, Paul M Stillwell Jr
Shorten the delay for SQ responses, but increase the number of loops.
Max delay time is unchanged, but some operations complete much more
quickly.
In the process, add a new define to make the delay count and delay time
more explicit, and simplify the code so it's the same for both switch
and NIC mode. Add comments to make things more explicit.
Signed-off-by: Mitch Williams <mitch.a.williams@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_controlq.c | 2 +-
drivers/net/ice/base/ice_controlq.h | 5 +++--
drivers/net/ice/base/ice_osdep.h | 2 +-
3 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c
index 501f986b9..1ea8f3a24 100644
--- a/drivers/net/ice/base/ice_controlq.c
+++ b/drivers/net/ice/base/ice_controlq.c
@@ -982,7 +982,7 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
if (ice_sq_done(hw, cq))
break;
- ice_msec_delay(1, false);
+ ice_usec_delay(ICE_CTL_Q_SQ_CMD_USEC, false);
total_delay++;
} while (total_delay < cq->sq_cmd_timeout);
diff --git a/drivers/net/ice/base/ice_controlq.h b/drivers/net/ice/base/ice_controlq.h
index acb4ab49e..b1214f670 100644
--- a/drivers/net/ice/base/ice_controlq.h
+++ b/drivers/net/ice/base/ice_controlq.h
@@ -33,8 +33,9 @@ enum ice_ctl_q {
ICE_CTL_Q_MAILBOX,
};
-/* Control Queue default settings */
-#define ICE_CTL_Q_SQ_CMD_TIMEOUT 250 /* msecs */
+/* Control Queue timeout settings - max delay 250ms */
+#define ICE_CTL_Q_SQ_CMD_TIMEOUT 2500 /* Count 2500 times */
+#define ICE_CTL_Q_SQ_CMD_USEC 100 /* Check every 100usec */
struct ice_ctl_q_ring {
void *dma_head; /* Virtual address to DMA head */
diff --git a/drivers/net/ice/base/ice_osdep.h b/drivers/net/ice/base/ice_osdep.h
index 35a17b941..27c1830c5 100644
--- a/drivers/net/ice/base/ice_osdep.h
+++ b/drivers/net/ice/base/ice_osdep.h
@@ -292,7 +292,7 @@ ice_hweight32(u32 num)
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
#define DELAY(x) rte_delay_us(x)
-#define ice_usec_delay(x) rte_delay_us(x)
+#define ice_usec_delay(x, y) rte_delay_us(x)
#define ice_msec_delay(x, y) rte_delay_us(1000 * (x))
#define udelay(x) DELAY(x)
#define msleep(x) DELAY(1000 * (x))
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 58/63] net/ice/base: add AQC get link topology handle support
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (56 preceding siblings ...)
2019-08-26 10:50 ` [dpdk-dev] [PATCH 57/63] net/ice/base: delay less Qi Zhang
@ 2019-08-26 10:51 ` Qi Zhang
2019-08-26 10:51 ` [dpdk-dev] [PATCH 59/63] net/ice/base: remove Rx flex descriptor programming Qi Zhang
` (5 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:51 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Paul Greenwalt, Paul M Stillwell Jr
Add AQC get link topology handle support. This is needed to determine
Direct Attach (DA) or backplane media type for PHY types that support
either. Get link topology handle cage node type request can be used to
determine if a cage is present or not. If a cage is present for PHY
types that supports both DA and backplane media type, then the media
type is DA, else the media type is backplane.
Signed-off-by: Paul Greenwalt <paul.greenwalt@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_adminq_cmd.h | 52 +++++++++++++++++++++++++++
drivers/net/ice/base/ice_common.c | 68 ++++++++++++++++++++++++++++++++++-
2 files changed, 119 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index 9a063592f..8e1d6a07d 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1654,6 +1654,56 @@ struct ice_aqc_set_mac_lb {
+struct ice_aqc_link_topo_addr {
+ u8 lport_num;
+ u8 lport_num_valid;
+#define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)
+ u8 node_type_ctx;
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8
+#define ICE_AQC_LINK_TOPO_NODE_CTX_S 4
+#define ICE_AQC_LINK_TOPO_NODE_CTX_M \
+ (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
+#define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0
+#define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1
+#define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2
+#define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3
+#define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4
+#define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5
+ u8 index;
+ __le16 handle;
+#define ICE_AQC_LINK_TOPO_HANDLE_S 0
+#define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
+/* Used to decode the handle field */
+#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9)
+#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9)
+#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0
+#define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0
+/* In case of a Mezzanine type */
+#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \
+ (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
+#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6
+#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)
+/* In case of a LOM type */
+#define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \
+ (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
+};
+
+/* Get Link Topology Handle (direct, 0x06E0) */
+struct ice_aqc_get_link_topo {
+ struct ice_aqc_link_topo_addr addr;
+ u8 node_part_num;
+ u8 rsvd[9];
+};
/* Set Port Identification LED (direct, 0x06E9) */
struct ice_aqc_set_port_id_led {
@@ -2307,6 +2357,7 @@ struct ice_aq_desc {
struct ice_aqc_set_event_mask set_event_mask;
struct ice_aqc_get_link_status get_link_status;
struct ice_aqc_event_lan_overflow lan_overflow;
+ struct ice_aqc_get_link_topo get_link_topo;
} params;
};
@@ -2470,6 +2521,7 @@ enum ice_adminq_opc {
ice_aqc_opc_get_link_status = 0x0607,
ice_aqc_opc_set_event_mask = 0x0613,
ice_aqc_opc_set_mac_lb = 0x0620,
+ ice_aqc_opc_get_link_topo = 0x06E0,
ice_aqc_opc_set_port_id_led = 0x06E9,
ice_aqc_opc_get_port_options = 0x06EA,
ice_aqc_opc_set_port_option = 0x06EB,
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index feb7676f8..d2f903329 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -188,6 +188,59 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
}
/**
+ * ice_aq_get_link_topo_handle - get link topology node return status
+ * @pi: port information structure
+ * @node_type: requested node type
+ * @cd: pointer to command details structure or NULL
+ *
+ * Get link topology node return status for specified node type (0x06E0)
+ *
+ * Node type cage can be used to determine if cage is present. If AQC
+ * returns error (ENOENT), then no cage present. If no cage present, then
+ * connection type is backplane or BASE-T.
+ */
+static enum ice_status
+ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
+ struct ice_sq_cd *cd)
+{
+ struct ice_aqc_get_link_topo *cmd;
+ struct ice_aq_desc desc;
+
+ cmd = &desc.params.get_link_topo;
+
+ if (!cmd)
+ return ICE_ERR_PARAM;
+
+ ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
+
+ cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
+ ICE_AQC_LINK_TOPO_NODE_CTX_S);
+
+ /* set node type */
+ cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
+
+ return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
+}
+
+/**
+ * ice_is_media_cage_present
+ * @pi: port information structure
+ *
+ * Returns true if media cage is present, else false. If no cage, then
+ * media type is backplane or BASE-T.
+ */
+static bool ice_is_media_cage_present(struct ice_port_info *pi)
+{
+ /* Node type cage can be used to determine if cage is present. If AQC
+ * returns error (ENOENT), then no cage present. If no cage present then
+ * connection type is backplane or BASE-T.
+ */
+ return !ice_aq_get_link_topo_handle(pi,
+ ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
+ NULL);
+}
+
+/**
* ice_get_media_type - Gets media type
* @pi: port information structure
*/
@@ -212,7 +265,6 @@ static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
case ICE_PHY_TYPE_LOW_25GBASE_SR:
case ICE_PHY_TYPE_LOW_25GBASE_LR:
- case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
case ICE_PHY_TYPE_LOW_40GBASE_SR4:
case ICE_PHY_TYPE_LOW_40GBASE_LR4:
case ICE_PHY_TYPE_LOW_50GBASE_SR2:
@@ -243,6 +295,16 @@ static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
case ICE_PHY_TYPE_LOW_100GBASE_CP2:
return ICE_MEDIA_DA;
+ case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
+ case ICE_PHY_TYPE_LOW_40G_XLAUI:
+ case ICE_PHY_TYPE_LOW_50G_LAUI2:
+ case ICE_PHY_TYPE_LOW_50G_AUI2:
+ case ICE_PHY_TYPE_LOW_50G_AUI1:
+ case ICE_PHY_TYPE_LOW_100G_AUI4:
+ case ICE_PHY_TYPE_LOW_100G_CAUI4:
+ if (ice_is_media_cage_present(pi))
+ return ICE_MEDIA_DA;
+ /* fall-through */
case ICE_PHY_TYPE_LOW_1000BASE_KX:
case ICE_PHY_TYPE_LOW_2500BASE_KX:
case ICE_PHY_TYPE_LOW_2500BASE_X:
@@ -260,6 +322,10 @@ static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
}
} else {
switch (hw_link_info->phy_type_high) {
+ case ICE_PHY_TYPE_HIGH_100G_AUI2:
+ if (ice_is_media_cage_present(pi))
+ return ICE_MEDIA_DA;
+ /* fall-through */
case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
return ICE_MEDIA_BACKPLANE;
}
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 59/63] net/ice/base: remove Rx flex descriptor programming
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (57 preceding siblings ...)
2019-08-26 10:51 ` [dpdk-dev] [PATCH 58/63] net/ice/base: add AQC get link topology handle support Qi Zhang
@ 2019-08-26 10:51 ` Qi Zhang
2019-08-26 10:51 ` [dpdk-dev] [PATCH 60/63] net/ice/base: enable RSS with ether layer for PPPoE Qi Zhang
` (4 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:51 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Vignesh Sridhar, Paul M Stillwell Jr
Removing Rx flex descriptor metadata and flag programming from shared
code. As per HAS these registers cannot be written to as they are read
only. While non-secure NVMs allow write access to them, secure images
will not. The programming for all fields per RxDID is now handled in the
comms package.
Signed-off-by: Vignesh Sridhar <vignesh.sridhar@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 195 --------------------------------------
1 file changed, 195 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index d2f903329..11e902ea1 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -11,35 +11,6 @@
#define ICE_PF_RESET_WAIT_COUNT 200
-#define ICE_PROG_FLEX_ENTRY(hw, rxdid, mdid, idx) \
- wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \
- ((ICE_RX_OPC_MDID << \
- GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
- GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
- (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
- GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M))
-
-#define ICE_PROG_FLEX_ENTRY_EXTRACT(hw, rxdid, protid, off, idx) \
- wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \
- ((ICE_RX_OPC_EXTRACT << \
- GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
- GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
- (((protid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
- GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M) | \
- (((off) << GLFLXP_RXDID_FLX_WRD_##idx##_EXTRACTION_OFFSET_S) & \
- GLFLXP_RXDID_FLX_WRD_##idx##_EXTRACTION_OFFSET_M))
-
-#define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \
- wr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \
- (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \
- GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \
- (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \
- GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \
- (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \
- GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \
- (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \
- GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M))
-
/**
* ice_set_mac_type - Sets MAC type
@@ -431,163 +402,6 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
}
/**
- * ice_init_flex_flags
- * @hw: pointer to the hardware structure
- * @prof_id: Rx Descriptor Builder profile ID
- *
- * Function to initialize Rx flex flags
- */
-static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)
-{
- u8 idx = 0;
-
- /* Flex-flag fields (0-2) are programmed with FLG64 bits with layout:
- * flexiflags0[5:0] - TCP flags, is_packet_fragmented, is_packet_UDP_GRE
- * flexiflags1[3:0] - Not used for flag programming
- * flexiflags2[7:0] - Tunnel and VLAN types
- * 2 invalid fields in last index
- */
- switch (prof_id) {
- /* Rx flex flags are currently programmed for the NIC profiles only.
- * Different flag bit programming configurations can be added per
- * profile as needed.
- */
- case ICE_RXDID_FLEX_NIC:
- case ICE_RXDID_FLEX_NIC_2:
- ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_FRG,
- ICE_FLG_UDP_GRE, ICE_FLG_PKT_DSI,
- ICE_FLG_FIN, idx++);
- /* flex flag 1 is not used for flexi-flag programming, skipping
- * these four FLG64 bits.
- */
- ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_SYN, ICE_FLG_RST,
- ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx++);
- ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_DSI,
- ICE_FLG_PKT_DSI, ICE_FLG_EVLAN_x8100,
- ICE_FLG_EVLAN_x9100, idx++);
- ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_VLAN_x8100,
- ICE_FLG_TNL_VLAN, ICE_FLG_TNL_MAC,
- ICE_FLG_TNL0, idx++);
- ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_TNL1, ICE_FLG_TNL2,
- ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx);
- break;
-
- default:
- ice_debug(hw, ICE_DBG_INIT,
- "Flag programming for profile ID %d not supported\n",
- prof_id);
- }
-}
-
-/**
- * ice_init_flex_flds
- * @hw: pointer to the hardware structure
- * @prof_id: Rx Descriptor Builder profile ID
- *
- * Function to initialize flex descriptors
- */
-static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)
-{
- enum ice_prot_id protid_0, protid_1;
- u16 offset_0, offset_1;
- enum ice_flex_mdid mdid;
-
- switch (prof_id) {
- case ICE_RXDID_FLEX_NIC:
- case ICE_RXDID_FLEX_NIC_2:
- ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_LOW, 0);
- ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_HIGH, 1);
- ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_LOWER, 2);
-
- mdid = (prof_id == ICE_RXDID_FLEX_NIC_2) ?
- ICE_MDID_SRC_VSI : ICE_MDID_FLOW_ID_HIGH;
-
- ICE_PROG_FLEX_ENTRY(hw, prof_id, mdid, 3);
-
- ice_init_flex_flags(hw, prof_id);
- break;
- case ICE_RXDID_COMMS_GENERIC:
- case ICE_RXDID_COMMS_AUX_VLAN:
- case ICE_RXDID_COMMS_AUX_IPV4:
- case ICE_RXDID_COMMS_AUX_IPV6:
- case ICE_RXDID_COMMS_AUX_IPV6_FLOW:
- case ICE_RXDID_COMMS_AUX_TCP:
- ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_LOW, 0);
- ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_HIGH, 1);
- ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_LOWER, 2);
- ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_HIGH, 3);
-
- if (prof_id == ICE_RXDID_COMMS_AUX_VLAN) {
- /* FlexiMD.4: VLAN1 - single or EVLAN (first for QinQ).
- * FlexiMD.5: VLAN2 - C-VLAN (second for QinQ).
- */
- protid_0 = ICE_PROT_EVLAN_O;
- offset_0 = 0;
- protid_1 = ICE_PROT_VLAN_O;
- offset_1 = 0;
- } else if (prof_id == ICE_RXDID_COMMS_AUX_IPV4) {
- /* FlexiMD.4: IPHDR1 - IPv4 header word 4, "TTL" and
- * "Protocol" fields.
- * FlexiMD.5: IPHDR0 - IPv4 header word 0, "Ver",
- * "Hdr Len" and "Type of Service" fields.
- */
- protid_0 = ICE_PROT_IPV4_OF_OR_S;
- offset_0 = 8;
- protid_1 = ICE_PROT_IPV4_OF_OR_S;
- offset_1 = 0;
- } else if (prof_id == ICE_RXDID_COMMS_AUX_IPV6) {
- /* FlexiMD.4: IPHDR1 - IPv6 header word 3,
- * "Next Header" and "Hop Limit" fields.
- * FlexiMD.5: IPHDR0 - IPv6 header word 0,
- * "Ver", "Traffic class" and high 4 bits of
- * "Flow Label" fields.
- */
- protid_0 = ICE_PROT_IPV6_OF_OR_S;
- offset_0 = 6;
- protid_1 = ICE_PROT_IPV6_OF_OR_S;
- offset_1 = 0;
- } else if (prof_id == ICE_RXDID_COMMS_AUX_IPV6_FLOW) {
- /* FlexiMD.4: IPHDR1 - IPv6 header word 1,
- * 16 low bits of the "Flow Label" field.
- * FlexiMD.5: IPHDR0 - IPv6 header word 0,
- * "Ver", "Traffic class" and high 4 bits
- * of "Flow Label" fields.
- */
- protid_0 = ICE_PROT_IPV6_OF_OR_S;
- offset_0 = 2;
- protid_1 = ICE_PROT_IPV6_OF_OR_S;
- offset_1 = 0;
- } else if (prof_id == ICE_RXDID_COMMS_AUX_TCP) {
- /* FlexiMD.4: TCPHDR - TCP header word 6,
- * "Data Offset" and "Flags" fields.
- * FlexiMD.5: Reserved
- */
- protid_0 = ICE_PROT_TCP_IL;
- offset_0 = 12;
- protid_1 = ICE_PROT_ID_INVAL;
- offset_1 = 0;
- } else {
- protid_0 = ICE_PROT_ID_INVAL;
- offset_0 = 0;
- protid_1 = ICE_PROT_ID_INVAL;
- offset_1 = 0;
- }
-
- ICE_PROG_FLEX_ENTRY_EXTRACT(hw, prof_id,
- protid_0, offset_0, 4);
- ICE_PROG_FLEX_ENTRY_EXTRACT(hw, prof_id,
- protid_1, offset_1, 5);
-
- ice_init_flex_flags(hw, prof_id);
- break;
- default:
- ice_debug(hw, ICE_DBG_INIT,
- "Field init for profile ID %d not supported\n",
- prof_id);
- }
-}
-
-/**
* ice_aq_set_mac_cfg
* @hw: pointer to the HW struct
* @max_frame_size: Maximum Frame Size to be supported
@@ -928,15 +742,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
if (status)
goto err_unroll_fltr_mgmt_struct;
-
- ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC);
- ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC_2);
- ice_init_flex_flds(hw, ICE_RXDID_COMMS_GENERIC);
- ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_VLAN);
- ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_IPV4);
- ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_IPV6);
- ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_IPV6_FLOW);
- ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_TCP);
/* Obtain counter base index which would be used by flow director */
status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
if (status)
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 60/63] net/ice/base: enable RSS with ether layer for PPPoE
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (58 preceding siblings ...)
2019-08-26 10:51 ` [dpdk-dev] [PATCH 59/63] net/ice/base: remove Rx flex descriptor programming Qi Zhang
@ 2019-08-26 10:51 ` Qi Zhang
2019-08-26 10:51 ` [dpdk-dev] [PATCH 61/63] net/ice/base: add GENEVE offset Qi Zhang
` (3 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:51 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Zhirun Yan, Paul M Stillwell Jr
Add these two ptype(MAC_PPPOD_PAY and MAC_PPPOE_PAY) in outer mac
bitmap, so it can hash for outer mac.
Signed-off-by: Zhirun Yan <zhirun.yan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flow.c | 8 ++++++--
drivers/net/ice/base/ice_flow.h | 5 +++++
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index abdf10b94..769fd2da7 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -143,7 +143,7 @@ struct ice_flow_field_info ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = {
static const u32 ice_ptypes_mac_ofos[] = {
0xFDC00CC6, 0xBFBF7F7E, 0xF7EFDFDF, 0xFEFDFDFB,
0x03BF7F7E, 0x00000000, 0x00000000, 0x00000000,
- 0x000B0F0F, 0x00000000, 0x00000000, 0x00000000,
+ 0x000B0F0F, 0x00003000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -1682,6 +1682,9 @@ ice_flow_add_fld_raw(struct ice_flow_seg_info *seg, u16 off, u8 len,
seg->raws_cnt++;
}
+#define ICE_FLOW_RSS_SEG_HDR_L2_MASKS \
+(ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN)
+
#define ICE_FLOW_RSS_SEG_HDR_L3_MASKS \
(ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_PPPOE)
@@ -1692,7 +1695,8 @@ ice_flow_add_fld_raw(struct ice_flow_seg_info *seg, u16 off, u8 len,
#define ICE_FLOW_RSS_SEG_HDR_VAL_MASKS \
- (ICE_FLOW_RSS_SEG_HDR_L3_MASKS | \
+ (ICE_FLOW_RSS_SEG_HDR_L2_MASKS | \
+ ICE_FLOW_RSS_SEG_HDR_L3_MASKS | \
ICE_FLOW_RSS_SEG_HDR_L4_MASKS)
/**
diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h
index 2ec9bb022..3afd201c4 100644
--- a/drivers/net/ice/base/ice_flow.h
+++ b/drivers/net/ice/base/ice_flow.h
@@ -15,6 +15,9 @@
#define ICE_FLOW_FLD_OFF_INVAL 0xffff
/* Generate flow hash field from flow field type(s) */
+#define ICE_FLOW_HASH_ETH \
+ (BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_DA) | \
+ BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_SA))
#define ICE_FLOW_HASH_IPV4 \
(BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) | \
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA))
@@ -58,6 +61,8 @@
#define ICE_FLOW_HASH_PPPOE_SESS_ID \
(BIT_ULL(ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID))
+#define ICE_FLOW_HASH_PPPOE_SESS_ID_ETH \
+ (ICE_FLOW_HASH_ETH | ICE_FLOW_HASH_PPPOE_SESS_ID)
#define ICE_FLOW_HASH_PPPOE_TCP_ID \
(ICE_FLOW_HASH_TCP_PORT | ICE_FLOW_HASH_PPPOE_SESS_ID)
#define ICE_FLOW_HASH_PPPOE_UDP_ID \
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 61/63] net/ice/base: add GENEVE offset
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (59 preceding siblings ...)
2019-08-26 10:51 ` [dpdk-dev] [PATCH 60/63] net/ice/base: enable RSS with ether layer for PPPoE Qi Zhang
@ 2019-08-26 10:51 ` Qi Zhang
2019-08-26 17:53 ` Dziggel, Douglas A
2019-08-26 10:51 ` [dpdk-dev] [PATCH 62/63] net/ice/base: update profile to recipe bitmap array Qi Zhang
` (2 subsequent siblings)
63 siblings, 1 reply; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:51 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Doug Dziggel, Paul M Stillwell Jr
Add Geneve offset for tunneled packets to allow dummy packets to be
properly created.
Signed-off-by: Doug Dziggel <douglas.a.dziggel@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 3ae53d3d8..8f20b9ed6 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -156,6 +156,7 @@ struct ice_dummy_pkt_offsets dummy_udp_tun_tcp_packet_offsets[] = {
{ ICE_IPV4_OFOS, 14 },
{ ICE_UDP_OF, 34 },
{ ICE_VXLAN, 42 },
+ { ICE_GENEVE, 42 },
{ ICE_MAC_IL, 50 },
{ ICE_IPV4_IL, 64 },
{ ICE_TCP_IL, 84 },
@@ -207,6 +208,7 @@ struct ice_dummy_pkt_offsets dummy_udp_tun_udp_packet_offsets[] = {
{ ICE_IPV4_OFOS, 14 },
{ ICE_UDP_OF, 34 },
{ ICE_VXLAN, 42 },
+ { ICE_GENEVE, 42 },
{ ICE_MAC_IL, 50 },
{ ICE_IPV4_IL, 64 },
{ ICE_UDP_ILOS, 84 },
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* Re: [dpdk-dev] [PATCH 61/63] net/ice/base: add GENEVE offset
2019-08-26 10:51 ` [dpdk-dev] [PATCH 61/63] net/ice/base: add GENEVE offset Qi Zhang
@ 2019-08-26 17:53 ` Dziggel, Douglas A
0 siblings, 0 replies; 130+ messages in thread
From: Dziggel, Douglas A @ 2019-08-26 17:53 UTC (permalink / raw)
To: Zhang, Qi Z, Lu, Wenzhuo, Yang, Qiming
Cc: dev, Ye, Xiaolong, Stillwell Jr, Paul M
Looks good, +2
-Doug
-----Original Message-----
From: Zhang, Qi Z
Sent: Monday, August 26, 2019 3:51 AM
To: Lu, Wenzhuo <wenzhuo.lu@intel.com>; Yang, Qiming <qiming.yang@intel.com>
Cc: dev@dpdk.org; Ye, Xiaolong <xiaolong.ye@intel.com>; Zhang, Qi Z <qi.z.zhang@intel.com>; Dziggel, Douglas A <douglas.a.dziggel@intel.com>; Stillwell Jr, Paul M <paul.m.stillwell.jr@intel.com>
Subject: [PATCH 61/63] net/ice/base: add GENEVE offset
Add Geneve offset for tunneled packets to allow dummy packets to be properly created.
Signed-off-by: Doug Dziggel <douglas.a.dziggel@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 3ae53d3d8..8f20b9ed6 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -156,6 +156,7 @@ struct ice_dummy_pkt_offsets dummy_udp_tun_tcp_packet_offsets[] = {
{ ICE_IPV4_OFOS, 14 },
{ ICE_UDP_OF, 34 },
{ ICE_VXLAN, 42 },
+ { ICE_GENEVE, 42 },
{ ICE_MAC_IL, 50 },
{ ICE_IPV4_IL, 64 },
{ ICE_TCP_IL, 84 },
@@ -207,6 +208,7 @@ struct ice_dummy_pkt_offsets dummy_udp_tun_udp_packet_offsets[] = {
{ ICE_IPV4_OFOS, 14 },
{ ICE_UDP_OF, 34 },
{ ICE_VXLAN, 42 },
+ { ICE_GENEVE, 42 },
{ ICE_MAC_IL, 50 },
{ ICE_IPV4_IL, 64 },
{ ICE_UDP_ILOS, 84 },
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread
* [dpdk-dev] [PATCH 62/63] net/ice/base: update profile to recipe bitmap array
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (60 preceding siblings ...)
2019-08-26 10:51 ` [dpdk-dev] [PATCH 61/63] net/ice/base: add GENEVE offset Qi Zhang
@ 2019-08-26 10:51 ` Qi Zhang
2019-08-26 10:51 ` [dpdk-dev] [PATCH 63/63] net/ice/base: ignore inverse switch recipes Qi Zhang
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:51 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
Correctly update profile to recipe bitmap array after adding and
associating recipes. This fixes an issue where determining unused
recipe result index slots was incorrect.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 21 ++++++++++++++++++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 8f20b9ed6..59da7eaa8 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -594,11 +594,14 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
/* Propagate some data to the recipe database */
recps[idx].is_root = is_root;
recps[idx].priority = root_bufs.content.act_ctrl_fwd_priority;
- if (root_bufs.content.result_indx & ICE_AQ_RECIPE_RESULT_EN)
+ ice_zero_bitmap(recps[idx].res_idxs, ICE_MAX_FV_WORDS);
+ if (root_bufs.content.result_indx & ICE_AQ_RECIPE_RESULT_EN) {
recps[idx].chain_idx = root_bufs.content.result_indx &
~ICE_AQ_RECIPE_RESULT_EN;
- else
+ ice_set_bit(recps[idx].chain_idx, recps[idx].res_idxs);
+ } else {
recps[idx].chain_idx = ICE_INVAL_CHAIN_IND;
+ }
if (!is_root)
continue;
@@ -609,11 +612,11 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
recps[idx].root_rid = root_bufs.content.rid &
~ICE_AQ_RECIPE_ID_IS_ROOT;
recps[idx].priority = root_bufs.content.act_ctrl_fwd_priority;
- recps[idx].big_recp = (recps[rid].n_grp_count > 1);
}
/* Complete initialization of the root recipe entry */
lkup_exts->n_val_words = fv_word_idx;
+ recps[rid].big_recp = (num_recps > 1);
recps[rid].n_grp_count = num_recps;
recps[rid].root_buf = (struct ice_aqc_recipe_data_elem *)
ice_calloc(hw, recps[rid].n_grp_count,
@@ -5287,6 +5290,7 @@ ice_add_sw_recipe(struct ice_hw *hw, struct ice_sw_recipe *rm,
recp->n_ext_words = entry->r_group.n_val_pairs;
recp->chain_idx = entry->chain_idx;
recp->priority = buf[buf_idx].content.act_ctrl_fwd_priority;
+ recp->n_grp_count = rm->n_grp_count;
recp->tun_type = rm->tun_type;
recp->recp_created = true;
recp->adv_rule = 1;
@@ -5568,6 +5572,7 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
LIST_FOR_EACH_ENTRY(fvit, &rm->fv_list, ice_sw_fv_list_entry,
list_entry) {
ice_declare_bitmap(r_bitmap, ICE_MAX_NUM_RECIPES);
+ u16 j;
status = ice_aq_get_recipe_to_profile(hw, fvit->profile_id,
(u8 *)r_bitmap, NULL);
@@ -5587,6 +5592,16 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
if (status)
goto err_unroll;
+
+ /* Update profile to recipe bitmap array */
+ ice_memcpy(profile_to_recipe[fvit->profile_id], rm->r_bitmap,
+ sizeof(rm->r_bitmap), ICE_NONDMA_TO_NONDMA);
+
+ /* Update recipe to profile bitmap array */
+ for (j = 0; j < ICE_MAX_NUM_RECIPES; j++)
+ if (ice_is_bit_set(rm->r_bitmap, j))
+ ice_set_bit((u16)fvit->profile_id,
+ recipe_to_profile[j]);
}
*rid = rm->root_rid;
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 63/63] net/ice/base: ignore inverse switch recipes
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (61 preceding siblings ...)
2019-08-26 10:51 ` [dpdk-dev] [PATCH 62/63] net/ice/base: update profile to recipe bitmap array Qi Zhang
@ 2019-08-26 10:51 ` Qi Zhang
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-26 10:51 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
When looking for an existing recipes, never choose an inverse
recipe as these are used for anti-spoofing. Choosing inverse
recipes for source MAC address rules was causing errors while
adding the rule.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 59da7eaa8..2437faead 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -4709,6 +4709,11 @@ static u16 ice_find_recp(struct ice_hw *hw, struct ice_prot_lkup_ext *lkup_exts)
&refresh_required))
continue;
+ /* Skip inverse action recipes */
+ if (recp[i].root_buf && recp[i].root_buf->content.act_ctrl &
+ ICE_AQ_RECIPE_ACT_INV_ACT)
+ continue;
+
/* if number of words we are looking for match */
if (lkup_exts->n_val_words == recp[i].lkup_exts.n_val_words) {
struct ice_fv_word *a = lkup_exts->fv_words;
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code
2019-08-26 10:50 [dpdk-dev] [PATCH 00/63] net/ice/base: update base code Qi Zhang
` (62 preceding siblings ...)
2019-08-26 10:51 ` [dpdk-dev] [PATCH 63/63] net/ice/base: ignore inverse switch recipes Qi Zhang
@ 2019-08-29 2:35 ` Qi Zhang
2019-08-29 2:35 ` [dpdk-dev] [PATCH v2 01/63] net/ice/base: enhance NVM read Qi Zhang
` (63 more replies)
63 siblings, 64 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:35 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang; +Cc: dev, xiaolong.ye, Qi Zhang
Key Features:
1) Add PPPoE, GTP protocol support for switch, FDIR, RSS
2) Add Flexible Descriptor support.
3) Improved package download.
4) Improved RSS to support inner header
5) Improved recipe management for switch rule
v2:
- improved commit log
Qi Zhang (63):
net/ice/base: enhance NVM read
net/ice/base: add function to get FW mode
net/ice/base: add support for NVM rollback detection
net/ice/base: add support to init RXDID descs fields
net/ice/base: store number of functions for the device
net/ice/base: add read PBA module function
net/ice/base: correct argument port info
net/ice/base: remove debug code
net/ice/base: add SFF EEPROM AQ Command
net/ice/base: improve debug print message
net/ice/base: add capabilities when in safe mode
net/ice/base: add helper functions for PHY caching
net/ice/base: add support for reading REPC statistics
net/ice/base: adjust DCB INIT for SW mode
net/ice/base: add NVM pkg flag
net/ice/base: move VSI to VSI group
net/ice/base: enable masking for RSS and FD field vectors
net/ice/base: resolve static analysis issues
net/ice/base: fix memory leak issue
net/ice/base: check root pointer for validity
net/ice/base: fix type-mismatch
net/ice/base: correct overrun Coverty hit
net/ice/base: update Boot Configuration Section read of NVM
net/ice/base: add support for NVM access commands
net/ice/base: add support for GTP and PPPoE protocols
net/ice/base: add locks for flow functions
net/ice/base: improve switch advanced rule
net/ice/base: move function declaration
net/ice/base: add 16-byte Flex Rx Descriptor
net/ice/base: add 32-byte Flex Rx Desc for Comms package
net/ice/base: update flag bits to current specification
net/ice/base: add more opcode and macros
net/ice/base: set status when global cfg lock is unavailable
net/ice/base: initialize driver NVM data earlier
net/ice/base: add function to configure Tx AQ command
net/ice/base: add support for not locking sideband queue
net/ice/base: associate recipes by profile type
net/ice/base: return switch error on invalid match criteria
net/ice/base: update UDP tunnel switch training packets
net/ice/base: improve switch chained recipe
net/ice/base: move and add some help function and macros
net/ice/base: add routine for tunnel port query
net/ice/base: ptype group consolidation
net/ice/base: fix for RSS hash on inner UDP port
net/ice/base: packet encapsulation for RSS
net/ice/base: add RSS support for PPPoE and GTPU
net/ice/base: remove unnecessary conditional check
net/ice/base: fix flag settings in AQ call
net/ice/base: refactor removal of VLAN promiscuous rules
net/ice/base: maximize switch recipe words per line
net/ice/base: update switch training packets with open ports
net/ice/base: remove unnecessary dummy packet finding
net/ice/base: remove unnecessary if branch
net/ice/base: correct abbreviations
net/ice/base: update to register definition file
net/ice/base: replace open-code duplication
net/ice/base: delay less
net/ice/base: add AQC get link topology handle support
net/ice/base: remove Rx flex descriptor programming
net/ice/base: enable RSS with ether layer for PPPoE
net/ice/base: add GENEVE offset
net/ice/base: update profile to recipe bitmap array
net/ice/base: ignore inverse switch recipes
drivers/net/ice/base/ice_adminq_cmd.h | 221 ++++----
drivers/net/ice/base/ice_bitops.h | 31 ++
drivers/net/ice/base/ice_common.c | 902 ++++++++++++++++++------------
drivers/net/ice/base/ice_common.h | 48 +-
drivers/net/ice/base/ice_controlq.c | 54 +-
drivers/net/ice/base/ice_controlq.h | 7 +-
drivers/net/ice/base/ice_dcb.c | 6 +-
drivers/net/ice/base/ice_dcb.h | 1 +
drivers/net/ice/base/ice_devids.h | 6 +
drivers/net/ice/base/ice_flex_pipe.c | 923 ++++++++++++++++++++++++++-----
drivers/net/ice/base/ice_flex_pipe.h | 17 +-
drivers/net/ice/base/ice_flex_type.h | 35 +-
drivers/net/ice/base/ice_flow.c | 368 ++++++++----
drivers/net/ice/base/ice_flow.h | 107 +++-
drivers/net/ice/base/ice_hw_autogen.h | 34 ++
drivers/net/ice/base/ice_lan_tx_rx.h | 76 ++-
drivers/net/ice/base/ice_nvm.c | 294 +++++++++-
drivers/net/ice/base/ice_nvm.h | 91 +++
drivers/net/ice/base/ice_osdep.h | 2 +-
drivers/net/ice/base/ice_protocol_type.h | 40 +-
drivers/net/ice/base/ice_sched.c | 87 +--
drivers/net/ice/base/ice_sched.h | 8 +-
drivers/net/ice/base/ice_switch.c | 784 ++++++++++++++++++--------
drivers/net/ice/base/ice_switch.h | 5 +
drivers/net/ice/base/ice_type.h | 77 ++-
25 files changed, 3142 insertions(+), 1082 deletions(-)
create mode 100644 drivers/net/ice/base/ice_nvm.h
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 01/63] net/ice/base: enhance NVM read
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
@ 2019-08-29 2:35 ` Qi Zhang
2019-08-29 2:35 ` [dpdk-dev] [PATCH v2 02/63] net/ice/base: add function to get FW mode Qi Zhang
` (62 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:35 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang; +Cc: dev, xiaolong.ye, Qi Zhang, Paul M Stillwell Jr
Add an option to read NVM from flash directly.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_adminq_cmd.h | 22 ++++++++++++++++++++++
drivers/net/ice/base/ice_dcb.h | 1 +
drivers/net/ice/base/ice_nvm.c | 12 +++++++++---
3 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index 7afdb6578..b5faa5bf6 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1684,6 +1684,28 @@ struct ice_aqc_nvm {
__le32 addr_low;
};
+/* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */
+#define ICE_AQC_NVM_SECTOR_UNIT 4096 /* In Bytes */
+#define ICE_AQC_NVM_WORD_UNIT 2 /* In Bytes */
+
+#define ICE_AQC_NVM_START_POINT 0
+#define ICE_AQC_NVM_EMP_SR_PTR_OFFSET 0x90
+#define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN 2 /* In Bytes */
+#define ICE_AQC_NVM_EMP_SR_PTR_M MAKEMASK(0x7FFF, 0)
+#define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S 15
+#define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M BIT(15)
+#define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR 1
+
+#define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET 0x46
+#define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN 2 /* In Bytes */
+#define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */
+
+#define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129
+#define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */
+#define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0)
+#define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */
+#define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */
+
/* Used for 0x0704 as well as for 0x0705 commands */
struct ice_aqc_nvm_cfg {
diff --git a/drivers/net/ice/base/ice_dcb.h b/drivers/net/ice/base/ice_dcb.h
index 47127096b..9a0968f5b 100644
--- a/drivers/net/ice/base/ice_dcb.h
+++ b/drivers/net/ice/base/ice_dcb.h
@@ -6,6 +6,7 @@
#define _ICE_DCB_H_
#include "ice_type.h"
+#include "ice_common.h"
#define ICE_DCBX_OFFLOAD_DIS 0
#define ICE_DCBX_OFFLOAD_ENABLED 1
diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c
index 6178cd4ac..f4567ca8f 100644
--- a/drivers/net/ice/base/ice_nvm.c
+++ b/drivers/net/ice/base/ice_nvm.c
@@ -13,13 +13,15 @@
* @length: length of the section to be read (in bytes from the offset)
* @data: command buffer (size [bytes] = length)
* @last_command: tells if this is the last command in a series
+ * @read_shadow_ram: tell if this is a shadow RAM read
* @cd: pointer to command details structure or NULL
*
* Read the NVM using the admin queue commands (0x0701)
*/
static enum ice_status
ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,
- void *data, bool last_command, struct ice_sq_cd *cd)
+ void *data, bool last_command, bool read_shadow_ram,
+ struct ice_sq_cd *cd)
{
struct ice_aq_desc desc;
struct ice_aqc_nvm *cmd;
@@ -34,6 +36,9 @@ ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);
+ if (!read_shadow_ram && module_typeid == ICE_AQC_NVM_START_POINT)
+ cmd->cmd_flags |= ICE_AQC_NVM_FLASH_ONLY;
+
/* If this is the last command in a series, set the proper flag. */
if (last_command)
cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
@@ -104,8 +109,9 @@ ice_read_sr_aq(struct ice_hw *hw, u32 offset, u16 words, u16 *data,
* So do this conversion while calling ice_aq_read_nvm.
*/
if (!status)
- status = ice_aq_read_nvm(hw, 0, 2 * offset, 2 * words, data,
- last_command, NULL);
+ status = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT,
+ 2 * offset, 2 * words, data,
+ last_command, true, NULL);
return status;
}
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 02/63] net/ice/base: add function to get FW mode
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
2019-08-29 2:35 ` [dpdk-dev] [PATCH v2 01/63] net/ice/base: enhance NVM read Qi Zhang
@ 2019-08-29 2:35 ` Qi Zhang
2019-08-29 2:35 ` [dpdk-dev] [PATCH v2 03/63] net/ice/base: add support for NVM rollback detection Qi Zhang
` (61 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:35 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Anirudh Venkataramanan, Paul M Stillwell Jr
Add a helper function to get FW mode. The FW mode can be normal,
debug, recovery or rollback.
This makes ice_is_fw_in_rec_mode redundant, so remove it.
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 23 ++++++++++++++++-------
drivers/net/ice/base/ice_common.h | 4 ++--
2 files changed, 18 insertions(+), 9 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 52fd8c897..681740cee 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -4102,16 +4102,25 @@ ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
}
/**
- * ice_is_fw_in_rec_mode
+ * ice_get_fw_mode - returns FW mode
* @hw: pointer to the HW struct
- *
- * This function returns true if fw is in recovery mode
*/
-bool ice_is_fw_in_rec_mode(struct ice_hw *hw)
+enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)
{
- u32 reg;
+#define ICE_FW_MODE_DBG_M BIT(0)
+#define ICE_FW_MODE_REC_M BIT(1)
+#define ICE_FW_MODE_ROLLBACK_M BIT(2)
+ u32 fw_mode;
/* check the current FW mode */
- reg = rd32(hw, GL_MNG_FWSM);
- return (reg & GL_MNG_FWSM_FW_MODES_M) > ICE_FW_MODE_DBG;
+ fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M;
+
+ if (fw_mode & ICE_FW_MODE_DBG_M)
+ return ICE_FW_MODE_DBG;
+ else if (fw_mode & ICE_FW_MODE_REC_M)
+ return ICE_FW_MODE_REC;
+ else if (fw_mode & ICE_FW_MODE_ROLLBACK_M)
+ return ICE_FW_MODE_ROLLBACK;
+ else
+ return ICE_FW_MODE_NORMAL;
}
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index 2063295ce..1d8701d64 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -14,7 +14,7 @@ enum ice_fw_modes {
ICE_FW_MODE_NORMAL,
ICE_FW_MODE_DBG,
ICE_FW_MODE_REC,
- ICE_FW_MODE_DBG_REC
+ ICE_FW_MODE_ROLLBACK
};
enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw);
@@ -198,8 +198,8 @@ ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
void
ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
u64 *prev_stat, u64 *cur_stat);
+enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw);
enum ice_status
ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
struct ice_aqc_get_elem *buf);
-bool ice_is_fw_in_rec_mode(struct ice_hw *hw);
#endif /* _ICE_COMMON_H_ */
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 03/63] net/ice/base: add support for NVM rollback detection
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
2019-08-29 2:35 ` [dpdk-dev] [PATCH v2 01/63] net/ice/base: enhance NVM read Qi Zhang
2019-08-29 2:35 ` [dpdk-dev] [PATCH v2 02/63] net/ice/base: add function to get FW mode Qi Zhang
@ 2019-08-29 2:35 ` Qi Zhang
2019-08-29 2:35 ` [dpdk-dev] [PATCH v2 04/63] net/ice/base: add support to init RXDID descs fields Qi Zhang
` (60 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:35 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Anirudh Venkataramanan, Paul M Stillwell Jr
This patch adds code to detect NVM rollback. The rollback detection
is done as part of the HW init flow. When NVM rollback is detected,
a warning message is printed along with the FW/NVM version data.
To do this, this patch adds a helper function ice_get_nvm_version.
Also, a pointer to hw->nvm is already available in ice_init_nvm. Just use
this instead of &hw->nvm.
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 46 +++++++++++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_common.h | 4 ++++
drivers/net/ice/base/ice_nvm.c | 6 ++---
drivers/net/ice/base/ice_type.h | 4 +++-
4 files changed, 56 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 681740cee..4968808fa 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -814,6 +814,49 @@ static void ice_get_itr_intrl_gran(struct ice_hw *hw)
}
/**
+ * ice_get_nvm_version - get cached NVM version data
+ * @hw: pointer to the hardware structure
+ * @oem_ver: 8 bit NVM version
+ * @oem_build: 16 bit NVM build number
+ * @oem_patch: 8 NVM patch number
+ * @ver_hi: high 16 bits of the NVM version
+ * @ver_lo: low 16 bits of the NVM version
+ */
+void
+ice_get_nvm_version(struct ice_hw *hw, u8 *oem_ver, u16 *oem_build,
+ u8 *oem_patch, u8 *ver_hi, u8 *ver_lo)
+{
+ struct ice_nvm_info *nvm = &hw->nvm;
+
+ *oem_ver = (u8)((nvm->oem_ver & ICE_OEM_VER_MASK) >> ICE_OEM_VER_SHIFT);
+ *oem_patch = (u8)(nvm->oem_ver & ICE_OEM_VER_PATCH_MASK);
+ *oem_build = (u16)((nvm->oem_ver & ICE_OEM_VER_BUILD_MASK) >>
+ ICE_OEM_VER_BUILD_SHIFT);
+ *ver_hi = (nvm->ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
+ *ver_lo = (nvm->ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT;
+}
+
+/**
+ * ice_print_rollback_msg - print FW rollback message
+ * @hw: pointer to the hardware structure
+ */
+void ice_print_rollback_msg(struct ice_hw *hw)
+{
+ char nvm_str[ICE_NVM_VER_LEN] = { 0 };
+ u8 oem_ver, oem_patch, ver_hi, ver_lo;
+ u16 oem_build;
+
+ ice_get_nvm_version(hw, &oem_ver, &oem_build, &oem_patch, &ver_hi,
+ &ver_lo);
+ SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d", ver_hi,
+ ver_lo, hw->nvm.eetrack, oem_ver, oem_build, oem_patch);
+
+ ice_warn(hw,
+ "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode",
+ nvm_str, hw->fw_maj_ver, hw->fw_min_ver);
+}
+
+/**
* ice_init_hw - main hardware initialization routine
* @hw: pointer to the hardware structure
*/
@@ -848,6 +891,9 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
if (status)
goto err_unroll_cqinit;
+ if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
+ ice_print_rollback_msg(hw);
+
/* Enable FW logging. Not fatal if this fails. */
status = ice_cfg_fw_log(hw, true);
if (status)
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index 1d8701d64..009c052ca 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -198,7 +198,11 @@ ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
void
ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
u64 *prev_stat, u64 *cur_stat);
+void
+ice_get_nvm_version(struct ice_hw *hw, u8 *oem_ver, u16 *oem_build,
+ u8 *oem_patch, u8 *ver_hi, u8 *ver_lo);
enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw);
+void ice_print_rollback_msg(struct ice_hw *hw);
enum ice_status
ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
struct ice_aqc_get_elem *buf);
diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c
index f4567ca8f..c0f9e353e 100644
--- a/drivers/net/ice/base/ice_nvm.c
+++ b/drivers/net/ice/base/ice_nvm.c
@@ -292,7 +292,7 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)
return status;
}
- status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &hw->nvm.ver);
+ status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &nvm->ver);
if (status) {
ice_debug(hw, ICE_DBG_INIT,
"Failed to read DEV starter version.\n");
@@ -310,7 +310,7 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)
return status;
}
- hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo;
+ nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
status = ice_read_sr_word(hw, ICE_SR_BOOT_CFG_PTR, &cfg_ptr);
if (status) {
@@ -331,7 +331,7 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)
return status;
}
- hw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo;
+ nvm->oem_ver = ((u32)oem_hi << 16) | oem_lo;
return status;
}
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index b03f18d16..2d010e643 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -436,10 +436,12 @@ struct ice_nvm_info {
u32 eetrack; /* NVM data version */
u32 oem_ver; /* OEM version info */
u16 sr_words; /* Shadow RAM size in words */
- u16 ver; /* NVM package version */
+ u16 ver; /* dev starter version */
u8 blank_nvm_mode; /* is NVM empty (no FW present)*/
};
+#define ICE_NVM_VER_LEN 32
+
/* Max number of port to queue branches w.r.t topology */
#define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 04/63] net/ice/base: add support to init RXDID descs fields
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (2 preceding siblings ...)
2019-08-29 2:35 ` [dpdk-dev] [PATCH v2 03/63] net/ice/base: add support for NVM rollback detection Qi Zhang
@ 2019-08-29 2:35 ` Qi Zhang
2019-08-29 2:35 ` [dpdk-dev] [PATCH v2 05/63] net/ice/base: store number of functions for the device Qi Zhang
` (59 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:35 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Junfeng Guo, Haiyue Wang,
Paul M Stillwell Jr
Add new switch cases to init RXDID descs MD fields.
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 91 ++++++++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_lan_tx_rx.h | 6 +++
2 files changed, 97 insertions(+)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 4968808fa..58dd01ea1 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -19,6 +19,16 @@
(((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M))
+#define ICE_PROG_FLEX_ENTRY_EXTRACT(hw, rxdid, protid, off, idx) \
+ wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \
+ ((ICE_RX_OPC_EXTRACT << \
+ GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
+ GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
+ (((protid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
+ GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M) | \
+ (((off) << GLFLXP_RXDID_FLX_WRD_##idx##_EXTRACTION_OFFSET_S) & \
+ GLFLXP_RXDID_FLX_WRD_##idx##_EXTRACTION_OFFSET_M))
+
#define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \
wr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \
(((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \
@@ -412,6 +422,8 @@ static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)
*/
static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)
{
+ enum ice_prot_id protid_0, protid_1;
+ u16 offset_0, offset_1;
enum ice_flex_mdid mdid;
switch (prof_id) {
@@ -428,7 +440,80 @@ static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)
ice_init_flex_flags(hw, prof_id);
break;
+ case ICE_RXDID_COMMS_GENERIC:
+ case ICE_RXDID_COMMS_AUX_VLAN:
+ case ICE_RXDID_COMMS_AUX_IPV4:
+ case ICE_RXDID_COMMS_AUX_IPV6:
+ case ICE_RXDID_COMMS_AUX_IPV6_FLOW:
+ case ICE_RXDID_COMMS_AUX_TCP:
+ ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_LOW, 0);
+ ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_HIGH, 1);
+ ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_LOWER, 2);
+ ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_HIGH, 3);
+
+ if (prof_id == ICE_RXDID_COMMS_AUX_VLAN) {
+ /* FlexiMD.4: VLAN1 - single or EVLAN (first for QinQ).
+ * FlexiMD.5: VLAN2 - C-VLAN (second for QinQ).
+ */
+ protid_0 = ICE_PROT_EVLAN_O;
+ offset_0 = 0;
+ protid_1 = ICE_PROT_VLAN_O;
+ offset_1 = 0;
+ } else if (prof_id == ICE_RXDID_COMMS_AUX_IPV4) {
+ /* FlexiMD.4: IPHDR1 - IPv4 header word 4, "TTL" and
+ * "Protocol" fields.
+ * FlexiMD.5: IPHDR0 - IPv4 header word 0, "Ver",
+ * "Hdr Len" and "Type of Service" fields.
+ */
+ protid_0 = ICE_PROT_IPV4_OF_OR_S;
+ offset_0 = 8;
+ protid_1 = ICE_PROT_IPV4_OF_OR_S;
+ offset_1 = 0;
+ } else if (prof_id == ICE_RXDID_COMMS_AUX_IPV6) {
+ /* FlexiMD.4: IPHDR1 - IPv6 header word 3,
+ * "Next Header" and "Hop Limit" fields.
+ * FlexiMD.5: IPHDR0 - IPv6 header word 0,
+ * "Ver", "Traffic class" and high 4 bits of
+ * "Flow Label" fields.
+ */
+ protid_0 = ICE_PROT_IPV6_OF_OR_S;
+ offset_0 = 6;
+ protid_1 = ICE_PROT_IPV6_OF_OR_S;
+ offset_1 = 0;
+ } else if (prof_id == ICE_RXDID_COMMS_AUX_IPV6_FLOW) {
+ /* FlexiMD.4: IPHDR1 - IPv6 header word 1,
+ * 16 low bits of the "Flow Label" field.
+ * FlexiMD.5: IPHDR0 - IPv6 header word 0,
+ * "Ver", "Traffic class" and high 4 bits
+ * of "Flow Label" fields.
+ */
+ protid_0 = ICE_PROT_IPV6_OF_OR_S;
+ offset_0 = 2;
+ protid_1 = ICE_PROT_IPV6_OF_OR_S;
+ offset_1 = 0;
+ } else if (prof_id == ICE_RXDID_COMMS_AUX_TCP) {
+ /* FlexiMD.4: TCPHDR - TCP header word 6,
+ * "Data Offset" and "Flags" fields.
+ * FlexiMD.5: Reserved
+ */
+ protid_0 = ICE_PROT_TCP_IL;
+ offset_0 = 12;
+ protid_1 = ICE_PROT_ID_INVAL;
+ offset_1 = 0;
+ } else {
+ protid_0 = ICE_PROT_ID_INVAL;
+ offset_0 = 0;
+ protid_1 = ICE_PROT_ID_INVAL;
+ offset_1 = 0;
+ }
+ ICE_PROG_FLEX_ENTRY_EXTRACT(hw, prof_id,
+ protid_0, offset_0, 4);
+ ICE_PROG_FLEX_ENTRY_EXTRACT(hw, prof_id,
+ protid_1, offset_1, 5);
+
+ ice_init_flex_flags(hw, prof_id);
+ break;
default:
ice_debug(hw, ICE_DBG_INIT,
"Field init for profile ID %d not supported\n",
@@ -1001,6 +1086,12 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC);
ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC_2);
+ ice_init_flex_flds(hw, ICE_RXDID_COMMS_GENERIC);
+ ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_VLAN);
+ ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_IPV4);
+ ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_IPV6);
+ ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_IPV6_FLOW);
+ ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_TCP);
/* Obtain counter base index which would be used by flow director */
status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
if (status)
diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h
index 02c54e818..2cba6bc1e 100644
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -606,6 +606,12 @@ enum ice_rxdid {
ICE_RXDID_FLEX_NIC = 2,
ICE_RXDID_FLEX_NIC_2 = 6,
ICE_RXDID_HW = 7,
+ ICE_RXDID_COMMS_GENERIC = 16,
+ ICE_RXDID_COMMS_AUX_VLAN = 17,
+ ICE_RXDID_COMMS_AUX_IPV4 = 18,
+ ICE_RXDID_COMMS_AUX_IPV6 = 19,
+ ICE_RXDID_COMMS_AUX_IPV6_FLOW = 20,
+ ICE_RXDID_COMMS_AUX_TCP = 21,
ICE_RXDID_LAST = 63,
};
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 05/63] net/ice/base: store number of functions for the device
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (3 preceding siblings ...)
2019-08-29 2:35 ` [dpdk-dev] [PATCH v2 04/63] net/ice/base: add support to init RXDID descs fields Qi Zhang
@ 2019-08-29 2:35 ` Qi Zhang
2019-08-29 2:35 ` [dpdk-dev] [PATCH v2 06/63] net/ice/base: add read PBA module function Qi Zhang
` (58 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:35 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Kevin Scott, Paul M Stillwell Jr
Store the number of functions the device has. This value can be
very useful when calculating how to best allocate global resources.
Signed-off-by: Kevin Scott <kevin.c.scott@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 6 +++++-
drivers/net/ice/base/ice_type.h | 1 +
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 58dd01ea1..fa97b792e 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -2114,6 +2114,10 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
ice_debug(hw, ICE_DBG_INIT,
"%s: valid functions = %d\n", prefix,
caps->valid_functions);
+
+ /* store func count for resource management purposes */
+ if (dev_p)
+ dev_p->num_funcs = ice_hweight32(number);
break;
case ICE_AQC_CAPS_VSI:
if (dev_p) {
@@ -2230,7 +2234,7 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
* physical ports; i.e. some features are not supported or function
* differently on devices with more than 4 ports.
*/
- if (caps && (ice_hweight32(caps->valid_functions) > 4)) {
+ if (hw->dev_caps.num_funcs > 4) {
/* Max 4 TCs per port */
caps->maxtc = 4;
ice_debug(hw, ICE_DBG_INIT,
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 2d010e643..88846e042 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -359,6 +359,7 @@ struct ice_hw_dev_caps {
struct ice_hw_common_caps common_cap;
u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
u32 num_flow_director_fltr; /* Number of FD filters available */
+ u32 num_funcs;
};
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 06/63] net/ice/base: add read PBA module function
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (4 preceding siblings ...)
2019-08-29 2:35 ` [dpdk-dev] [PATCH v2 05/63] net/ice/base: store number of functions for the device Qi Zhang
@ 2019-08-29 2:35 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 07/63] net/ice/base: correct argument port info Qi Zhang
` (57 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:35 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Tarun Singh, Paul M Stillwell Jr
New support function added - ice_get_pfa_module_tlv(), the driver or
other modules can make use of this function to read the pfa area.
Signed-off-by: Tarun Singh <tarun.k.singh@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 66 +++++++++++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_common.h | 3 ++
2 files changed, 69 insertions(+)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index fa97b792e..0356537a4 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -1283,6 +1283,72 @@ enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
return ice_check_reset(hw);
}
+/**
+ * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA
+ * @hw: pointer to hardware structure
+ * @module_tlv: pointer to module TLV to return
+ * @module_tlv_len: pointer to module TLV length to return
+ * @module_type: module type requested
+ *
+ * Finds the requested sub module TLV type from the Preserved Field
+ * Area (PFA) and returns the TLV pointer and length. The caller can
+ * use these to read the variable length TLV value.
+ */
+enum ice_status
+ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
+ u16 module_type)
+{
+ enum ice_status status;
+ u16 pfa_len, pfa_ptr;
+ u16 next_tlv;
+
+ status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr);
+ if (status != ICE_SUCCESS) {
+ ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n");
+ return status;
+ }
+ status = ice_read_sr_word(hw, pfa_ptr, &pfa_len);
+ if (status != ICE_SUCCESS) {
+ ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n");
+ return status;
+ }
+ /* Starting with first TLV after PFA length, iterate through the list
+ * of TLVs to find the requested one.
+ */
+ next_tlv = pfa_ptr + 1;
+ while (next_tlv < pfa_ptr + pfa_len) {
+ u16 tlv_sub_module_type;
+ u16 tlv_len;
+
+ /* Read TLV type */
+ status = ice_read_sr_word(hw, next_tlv, &tlv_sub_module_type);
+ if (status != ICE_SUCCESS) {
+ ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV type.\n");
+ break;
+ }
+ /* Read TLV length */
+ status = ice_read_sr_word(hw, next_tlv + 1, &tlv_len);
+ if (status != ICE_SUCCESS) {
+ ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n");
+ break;
+ }
+ if (tlv_sub_module_type == module_type) {
+ if (tlv_len) {
+ *module_tlv = next_tlv;
+ *module_tlv_len = tlv_len;
+ return ICE_SUCCESS;
+ }
+ return ICE_ERR_INVAL_SIZE;
+ }
+ /* Check next TLV, i.e. current TLV pointer + length + 2 words
+ * (for current TLV's type and length)
+ */
+ next_tlv = next_tlv + tlv_len + 2;
+ }
+ /* Module does not exist */
+ return ICE_ERR_DOES_NOT_EXIST;
+}
+
/**
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index 009c052ca..c5170f705 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -21,6 +21,9 @@ enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw);
enum ice_status ice_init_hw(struct ice_hw *hw);
void ice_deinit_hw(struct ice_hw *hw);
+enum ice_status
+ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
+ u16 module_type);
enum ice_status ice_check_reset(struct ice_hw *hw);
enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req);
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 07/63] net/ice/base: correct argument port info
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (5 preceding siblings ...)
2019-08-29 2:35 ` [dpdk-dev] [PATCH v2 06/63] net/ice/base: add read PBA module function Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 08/63] net/ice/base: remove debug code Qi Zhang
` (56 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Tarun Singh, Paul M Stillwell Jr
correct argument pi(port_info) passed in function
ice_sched_get_first_node(), otherwise it will return the incorrect
node.
functions ice_sched_get_agg_node and ice_sched_cfg_sibl_node_prio:
change argument from hw to pi for it to align to correct port.
Moved saving tc node bw info from hardware structure(hw) to port info
structure(pi). This change allows multiple ports to save and replay
the information correctly.
Signed-off-by: Tarun Singh <tarun.k.singh@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 2 +-
drivers/net/ice/base/ice_common.h | 2 +-
drivers/net/ice/base/ice_sched.c | 70 ++++++++++++++++++++-------------------
drivers/net/ice/base/ice_sched.h | 4 +--
drivers/net/ice/base/ice_type.h | 2 +-
5 files changed, 41 insertions(+), 39 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 0356537a4..b4f0b964d 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -4158,7 +4158,7 @@ static enum ice_status ice_replay_pre_init(struct ice_hw *hw)
&sw->recp_list[i].filt_replay_rules);
ice_sched_replay_agg_vsi_preinit(hw);
- return ice_sched_replay_tc_node_bw(hw);
+ return ice_sched_replay_tc_node_bw(hw->port_info);
}
/**
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index c5170f705..4ecfa6b9b 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -184,7 +184,7 @@ enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle);
void ice_replay_post(struct ice_hw *hw);
void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw);
void ice_sched_replay_agg(struct ice_hw *hw);
-enum ice_status ice_sched_replay_tc_node_bw(struct ice_hw *hw);
+enum ice_status ice_sched_replay_tc_node_bw(struct ice_port_info *pi);
enum ice_status ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle);
enum ice_status
ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx);
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index 2d80af731..d16f256c9 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -1480,7 +1480,7 @@ ice_sched_get_vsi_node(struct ice_port_info *pi, struct ice_sched_node *tc_node,
/**
* ice_sched_get_agg_node - Get an aggregator node based on aggregator ID
- * @hw: pointer to the HW struct
+ * @pi: pointer to the port information structure
* @tc_node: pointer to the TC node
* @agg_id: aggregator ID
*
@@ -1488,14 +1488,17 @@ ice_sched_get_vsi_node(struct ice_port_info *pi, struct ice_sched_node *tc_node,
* a given TC branch
*/
static struct ice_sched_node *
-ice_sched_get_agg_node(struct ice_hw *hw, struct ice_sched_node *tc_node,
+ice_sched_get_agg_node(struct ice_port_info *pi, struct ice_sched_node *tc_node,
u32 agg_id)
{
struct ice_sched_node *node;
+ struct ice_hw *hw = pi->hw;
u8 agg_layer;
+ if (!hw)
+ return NULL;
agg_layer = ice_sched_get_agg_layer(hw);
- node = ice_sched_get_first_node(hw->port_info, tc_node, agg_layer);
+ node = ice_sched_get_first_node(pi, tc_node, agg_layer);
/* Check whether it already exists */
while (node) {
@@ -2251,7 +2254,7 @@ ice_sched_move_vsi_to_agg(struct ice_port_info *pi, u16 vsi_handle, u32 agg_id,
if (!tc_node)
return ICE_ERR_CFG;
- agg_node = ice_sched_get_agg_node(pi->hw, tc_node, agg_id);
+ agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id);
if (!agg_node)
return ICE_ERR_DOES_NOT_EXIST;
@@ -2388,7 +2391,7 @@ ice_sched_rm_agg_cfg(struct ice_port_info *pi, u32 agg_id, u8 tc)
if (!tc_node)
return ICE_ERR_CFG;
- agg_node = ice_sched_get_agg_node(hw, tc_node, agg_id);
+ agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id);
if (!agg_node)
return ICE_ERR_DOES_NOT_EXIST;
@@ -2497,7 +2500,7 @@ ice_sched_add_agg_cfg(struct ice_port_info *pi, u32 agg_id, u8 tc)
if (!tc_node)
return ICE_ERR_CFG;
- agg_node = ice_sched_get_agg_node(hw, tc_node, agg_id);
+ agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id);
/* Does Agg node already exist ? */
if (agg_node)
return status;
@@ -3445,7 +3448,6 @@ ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 num_qs, u32 *q_ids,
u8 *q_prio)
{
enum ice_status status = ICE_ERR_PARAM;
- struct ice_hw *hw = pi->hw;
u16 i;
ice_acquire_lock(&pi->sched_lock);
@@ -3460,7 +3462,7 @@ ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 num_qs, u32 *q_ids,
break;
}
/* Configure Priority */
- status = ice_sched_cfg_sibl_node_prio(hw, node, q_prio[i]);
+ status = ice_sched_cfg_sibl_node_prio(pi, node, q_prio[i]);
if (status)
break;
}
@@ -3508,7 +3510,7 @@ ice_cfg_agg_vsi_priority_per_tc(struct ice_port_info *pi, u32 agg_id,
if (!tc_node)
goto exit_agg_priority_per_tc;
- agg_node = ice_sched_get_agg_node(hw, tc_node, agg_id);
+ agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id);
if (!agg_node)
goto exit_agg_priority_per_tc;
@@ -3542,7 +3544,7 @@ ice_cfg_agg_vsi_priority_per_tc(struct ice_port_info *pi, u32 agg_id,
if (ice_sched_find_node_in_subtree(hw, agg_node, vsi_node)) {
/* Configure Priority */
- status = ice_sched_cfg_sibl_node_prio(hw, vsi_node,
+ status = ice_sched_cfg_sibl_node_prio(pi, vsi_node,
node_prio[i]);
if (status)
break;
@@ -3654,7 +3656,7 @@ ice_cfg_agg_bw_alloc(struct ice_port_info *pi, u32 agg_id, u8 ena_tcmap,
if (!tc_node)
continue;
- agg_node = ice_sched_get_agg_node(hw, tc_node, agg_id);
+ agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id);
if (!agg_node)
continue;
@@ -4453,19 +4455,17 @@ static enum ice_status
ice_sched_save_tc_node_bw(struct ice_port_info *pi, u8 tc,
enum ice_rl_type rl_type, u32 bw)
{
- struct ice_hw *hw = pi->hw;
-
if (tc >= ICE_MAX_TRAFFIC_CLASS)
return ICE_ERR_PARAM;
switch (rl_type) {
case ICE_MIN_BW:
- ice_set_clear_cir_bw(&hw->tc_node_bw_t_info[tc], bw);
+ ice_set_clear_cir_bw(&pi->tc_node_bw_t_info[tc], bw);
break;
case ICE_MAX_BW:
- ice_set_clear_eir_bw(&hw->tc_node_bw_t_info[tc], bw);
+ ice_set_clear_eir_bw(&pi->tc_node_bw_t_info[tc], bw);
break;
case ICE_SHARED_BW:
- ice_set_clear_shared_bw(&hw->tc_node_bw_t_info[tc], bw);
+ ice_set_clear_shared_bw(&pi->tc_node_bw_t_info[tc], bw);
break;
default:
return ICE_ERR_PARAM;
@@ -4552,17 +4552,15 @@ static enum ice_status
ice_sched_save_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc,
enum ice_rl_type rl_type, u16 bw_alloc)
{
- struct ice_hw *hw = pi->hw;
-
if (tc >= ICE_MAX_TRAFFIC_CLASS)
return ICE_ERR_PARAM;
switch (rl_type) {
case ICE_MIN_BW:
- ice_set_clear_cir_bw_alloc(&hw->tc_node_bw_t_info[tc],
+ ice_set_clear_cir_bw_alloc(&pi->tc_node_bw_t_info[tc],
bw_alloc);
break;
case ICE_MAX_BW:
- ice_set_clear_eir_bw_alloc(&hw->tc_node_bw_t_info[tc],
+ ice_set_clear_eir_bw_alloc(&pi->tc_node_bw_t_info[tc],
bw_alloc);
break;
default:
@@ -4710,7 +4708,7 @@ ice_sched_get_node_by_id_type(struct ice_port_info *pi, u32 id,
tc_node = ice_sched_get_tc_node(pi, tc);
if (tc_node)
- node = ice_sched_get_agg_node(pi->hw, tc_node, id);
+ node = ice_sched_get_agg_node(pi, tc_node, id);
break;
}
@@ -4921,7 +4919,7 @@ ice_sched_validate_agg_srl_node(struct ice_port_info *pi, u32 agg_id)
if (!tc_node)
continue;
- agg_node = ice_sched_get_agg_node(pi->hw, tc_node, agg_id);
+ agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id);
if (!agg_node)
continue;
/* SRL bandwidth layer selection */
@@ -4992,7 +4990,7 @@ ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw)
if (!tc_node)
continue;
- agg_node = ice_sched_get_agg_node(pi->hw, tc_node, agg_id);
+ agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id);
if (!agg_node)
continue;
@@ -5017,7 +5015,7 @@ ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw)
/**
* ice_sched_cfg_sibl_node_prio - configure node sibling priority
- * @hw: pointer to the HW struct
+ * @pi: port information structure
* @node: sched node to configure
* @priority: sibling priority
*
@@ -5025,13 +5023,16 @@ ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw)
* function needs to be called with scheduler lock held.
*/
enum ice_status
-ice_sched_cfg_sibl_node_prio(struct ice_hw *hw, struct ice_sched_node *node,
- u8 priority)
+ice_sched_cfg_sibl_node_prio(struct ice_port_info *pi,
+ struct ice_sched_node *node, u8 priority)
{
struct ice_aqc_txsched_elem_data buf;
struct ice_aqc_txsched_elem *data;
+ struct ice_hw *hw = pi->hw;
enum ice_status status;
+ if (!hw)
+ return ICE_ERR_PARAM;
buf = node->info;
data = &buf.data;
data->valid_sections |= ICE_AQC_ELEM_VALID_GENERIC;
@@ -5198,7 +5199,7 @@ ice_sched_replay_agg_bw(struct ice_hw *hw, struct ice_sched_agg_info *agg_info)
status = ICE_ERR_PARAM;
break;
}
- agg_node = ice_sched_get_agg_node(hw, tc_node,
+ agg_node = ice_sched_get_agg_node(hw->port_info, tc_node,
agg_info->agg_id);
if (!agg_node) {
status = ICE_ERR_PARAM;
@@ -5310,26 +5311,27 @@ void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw)
/**
* ice_sched_replay_tc_node_bw - replay TC node(s) BW
- * @hw: pointer to the HW struct
+ * @pi: port information structure
*
- * This function replay TC nodes. The caller needs to hold the scheduler lock.
+ * This function replay TC nodes.
*/
enum ice_status
-ice_sched_replay_tc_node_bw(struct ice_hw *hw)
+ice_sched_replay_tc_node_bw(struct ice_port_info *pi)
{
- struct ice_port_info *pi = hw->port_info;
enum ice_status status = ICE_SUCCESS;
u8 tc;
+ if (!pi->hw)
+ return ICE_ERR_PARAM;
ice_acquire_lock(&pi->sched_lock);
ice_for_each_traffic_class(tc) {
struct ice_sched_node *tc_node;
- tc_node = ice_sched_get_tc_node(hw->port_info, tc);
+ tc_node = ice_sched_get_tc_node(pi, tc);
if (!tc_node)
continue; /* TC not present */
- status = ice_sched_replay_node_bw(hw, tc_node,
- &hw->tc_node_bw_t_info[tc]);
+ status = ice_sched_replay_node_bw(pi->hw, tc_node,
+ &pi->tc_node_bw_t_info[tc]);
if (status)
break;
}
diff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h
index 38f8f93d2..932ae075f 100644
--- a/drivers/net/ice/base/ice_sched.h
+++ b/drivers/net/ice/base/ice_sched.h
@@ -183,6 +183,6 @@ ice_sched_set_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle,
enum ice_status
ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw);
enum ice_status
-ice_sched_cfg_sibl_node_prio(struct ice_hw *hw, struct ice_sched_node *node,
- u8 priority);
+ice_sched_cfg_sibl_node_prio(struct ice_port_info *pi,
+ struct ice_sched_node *node, u8 priority);
#endif /* _ICE_SCHED_H_ */
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 88846e042..d8cb8eecd 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -674,6 +674,7 @@ struct ice_port_info {
sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
/* List contain profile ID(s) and other params per layer */
struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
+ struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
/* DCBX info */
struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
@@ -742,7 +743,6 @@ struct ice_hw {
u8 sw_entry_point_layer;
u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */
- struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
u8 evb_veb; /* true for VEB, false for VEPA */
u8 reset_ongoing; /* true if HW is in reset, false otherwise */
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 08/63] net/ice/base: remove debug code
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (6 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 07/63] net/ice/base: correct argument port info Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 09/63] net/ice/base: add SFF EEPROM AQ Command Qi Zhang
` (55 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang; +Cc: dev, xiaolong.ye, Qi Zhang, Paul M Stillwell Jr
Remove firmware logging debug code.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_adminq_cmd.h | 88 --------------
drivers/net/ice/base/ice_common.c | 223 ----------------------------------
drivers/net/ice/base/ice_common.h | 1 -
drivers/net/ice/base/ice_type.h | 20 ---
4 files changed, 332 deletions(-)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index b5faa5bf6..9e5853cca 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -2176,87 +2176,6 @@ struct ice_aqc_event_lan_overflow {
-/* Configure Firmware Logging Command (indirect 0xFF09)
- * Logging Information Read Response (indirect 0xFF10)
- * Note: The 0xFF10 command has no input parameters.
- */
-struct ice_aqc_fw_logging {
- u8 log_ctrl;
-#define ICE_AQC_FW_LOG_AQ_EN BIT(0)
-#define ICE_AQC_FW_LOG_UART_EN BIT(1)
- u8 rsvd0;
- u8 log_ctrl_valid; /* Not used by 0xFF10 Response */
-#define ICE_AQC_FW_LOG_AQ_VALID BIT(0)
-#define ICE_AQC_FW_LOG_UART_VALID BIT(1)
- u8 rsvd1[5];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-
-enum ice_aqc_fw_logging_mod {
- ICE_AQC_FW_LOG_ID_GENERAL = 0,
- ICE_AQC_FW_LOG_ID_CTRL,
- ICE_AQC_FW_LOG_ID_LINK,
- ICE_AQC_FW_LOG_ID_LINK_TOPO,
- ICE_AQC_FW_LOG_ID_DNL,
- ICE_AQC_FW_LOG_ID_I2C,
- ICE_AQC_FW_LOG_ID_SDP,
- ICE_AQC_FW_LOG_ID_MDIO,
- ICE_AQC_FW_LOG_ID_ADMINQ,
- ICE_AQC_FW_LOG_ID_HDMA,
- ICE_AQC_FW_LOG_ID_LLDP,
- ICE_AQC_FW_LOG_ID_DCBX,
- ICE_AQC_FW_LOG_ID_DCB,
- ICE_AQC_FW_LOG_ID_NETPROXY,
- ICE_AQC_FW_LOG_ID_NVM,
- ICE_AQC_FW_LOG_ID_AUTH,
- ICE_AQC_FW_LOG_ID_VPD,
- ICE_AQC_FW_LOG_ID_IOSF,
- ICE_AQC_FW_LOG_ID_PARSER,
- ICE_AQC_FW_LOG_ID_SW,
- ICE_AQC_FW_LOG_ID_SCHEDULER,
- ICE_AQC_FW_LOG_ID_TXQ,
- ICE_AQC_FW_LOG_ID_RSVD,
- ICE_AQC_FW_LOG_ID_POST,
- ICE_AQC_FW_LOG_ID_WATCHDOG,
- ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
- ICE_AQC_FW_LOG_ID_MNG,
- ICE_AQC_FW_LOG_ID_SYNCE,
- ICE_AQC_FW_LOG_ID_MAX,
-};
-
-/* This is the buffer for both of the logging commands.
- * The entry array size depends on the datalen parameter in the descriptor.
- * There will be a total of datalen / 2 entries.
- */
-struct ice_aqc_fw_logging_data {
- __le16 entry[1];
-#define ICE_AQC_FW_LOG_ID_S 0
-#define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S)
-
-#define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */
-#define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */
-
-#define ICE_AQC_FW_LOG_EN_S 12
-#define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S)
-#define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */
-#define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */
-#define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */
-#define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */
-};
-
-
-/* Get/Clear FW Log (indirect 0xFF11) */
-struct ice_aqc_get_clear_fw_log {
- u8 flags;
-#define ICE_AQC_FW_LOG_CLEAR BIT(0)
-#define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1)
- u8 rsvd1[7];
- __le32 addr_high;
- __le32 addr_low;
-};
-
/**
* struct ice_aq_desc - Admin Queue (AQ) descriptor
@@ -2337,8 +2256,6 @@ struct ice_aq_desc {
struct ice_aqc_get_vsi_resp get_vsi_resp;
struct ice_aqc_download_pkg download_pkg;
struct ice_aqc_get_pkg_info_list get_pkg_info_list;
- struct ice_aqc_fw_logging fw_logging;
- struct ice_aqc_get_clear_fw_log get_clear_fw_log;
struct ice_aqc_set_mac_lb set_mac_lb;
struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
struct ice_aqc_get_res_alloc get_res;
@@ -2558,11 +2475,6 @@ enum ice_adminq_opc {
/* Standalone Commands/Events */
ice_aqc_opc_event_lan_overflow = 0x1001,
-
- /* debug commands */
- ice_aqc_opc_fw_logging = 0xFF09,
- ice_aqc_opc_fw_logging_info = 0xFF10,
- ice_aqc_opc_get_clear_fw_log = 0xFF11
};
#endif /* _ICE_ADMINQ_CMD_H_ */
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index b4f0b964d..43c06948f 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -653,223 +653,6 @@ static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
ice_free(hw, sw);
}
-#define ICE_FW_LOG_DESC_SIZE(n) (sizeof(struct ice_aqc_fw_logging_data) + \
- (((n) - 1) * sizeof(((struct ice_aqc_fw_logging_data *)0)->entry)))
-#define ICE_FW_LOG_DESC_SIZE_MAX \
- ICE_FW_LOG_DESC_SIZE(ICE_AQC_FW_LOG_ID_MAX)
-
-/**
- * ice_get_fw_log_cfg - get FW logging configuration
- * @hw: pointer to the HW struct
- */
-static enum ice_status ice_get_fw_log_cfg(struct ice_hw *hw)
-{
- struct ice_aqc_fw_logging_data *config;
- struct ice_aq_desc desc;
- enum ice_status status;
- u16 size;
-
- size = ICE_FW_LOG_DESC_SIZE_MAX;
- config = (struct ice_aqc_fw_logging_data *)ice_malloc(hw, size);
- if (!config)
- return ICE_ERR_NO_MEMORY;
-
- ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info);
-
- desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_BUF);
- desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
-
- status = ice_aq_send_cmd(hw, &desc, config, size, NULL);
- if (!status) {
- u16 i;
-
- /* Save fw logging information into the HW structure */
- for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
- u16 v, m, flgs;
-
- v = LE16_TO_CPU(config->entry[i]);
- m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
- flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S;
-
- if (m < ICE_AQC_FW_LOG_ID_MAX)
- hw->fw_log.evnts[m].cur = flgs;
- }
- }
-
- ice_free(hw, config);
-
- return status;
-}
-
-/**
- * ice_cfg_fw_log - configure FW logging
- * @hw: pointer to the HW struct
- * @enable: enable certain FW logging events if true, disable all if false
- *
- * This function enables/disables the FW logging via Rx CQ events and a UART
- * port based on predetermined configurations. FW logging via the Rx CQ can be
- * enabled/disabled for individual PF's. However, FW logging via the UART can
- * only be enabled/disabled for all PFs on the same device.
- *
- * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in
- * hw->fw_log need to be set accordingly, e.g. based on user-provided input,
- * before initializing the device.
- *
- * When re/configuring FW logging, callers need to update the "cfg" elements of
- * the hw->fw_log.evnts array with the desired logging event configurations for
- * modules of interest. When disabling FW logging completely, the callers can
- * just pass false in the "enable" parameter. On completion, the function will
- * update the "cur" element of the hw->fw_log.evnts array with the resulting
- * logging event configurations of the modules that are being re/configured. FW
- * logging modules that are not part of a reconfiguration operation retain their
- * previous states.
- *
- * Before resetting the device, it is recommended that the driver disables FW
- * logging before shutting down the control queue. When disabling FW logging
- * ("enable" = false), the latest configurations of FW logging events stored in
- * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after
- * a device reset.
- *
- * When enabling FW logging to emit log messages via the Rx CQ during the
- * device's initialization phase, a mechanism alternative to interrupt handlers
- * needs to be used to extract FW log messages from the Rx CQ periodically and
- * to prevent the Rx CQ from being full and stalling other types of control
- * messages from FW to SW. Interrupts are typically disabled during the device's
- * initialization phase.
- */
-static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable)
-{
- struct ice_aqc_fw_logging_data *data = NULL;
- struct ice_aqc_fw_logging *cmd;
- enum ice_status status = ICE_SUCCESS;
- u16 i, chgs = 0, len = 0;
- struct ice_aq_desc desc;
- u8 actv_evnts = 0;
- void *buf = NULL;
-
- if (!hw->fw_log.cq_en && !hw->fw_log.uart_en)
- return ICE_SUCCESS;
-
- /* Disable FW logging only when the control queue is still responsive */
- if (!enable &&
- (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq)))
- return ICE_SUCCESS;
-
- /* Get current FW log settings */
- status = ice_get_fw_log_cfg(hw);
- if (status)
- return status;
-
- ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging);
- cmd = &desc.params.fw_logging;
-
- /* Indicate which controls are valid */
- if (hw->fw_log.cq_en)
- cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID;
-
- if (hw->fw_log.uart_en)
- cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID;
-
- if (enable) {
- /* Fill in an array of entries with FW logging modules and
- * logging events being reconfigured.
- */
- for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
- u16 val;
-
- /* Keep track of enabled event types */
- actv_evnts |= hw->fw_log.evnts[i].cfg;
-
- if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur)
- continue;
-
- if (!data) {
- data = (struct ice_aqc_fw_logging_data *)
- ice_malloc(hw,
- ICE_FW_LOG_DESC_SIZE_MAX);
- if (!data)
- return ICE_ERR_NO_MEMORY;
- }
-
- val = i << ICE_AQC_FW_LOG_ID_S;
- val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S;
- data->entry[chgs++] = CPU_TO_LE16(val);
- }
-
- /* Only enable FW logging if at least one module is specified.
- * If FW logging is currently enabled but all modules are not
- * enabled to emit log messages, disable FW logging altogether.
- */
- if (actv_evnts) {
- /* Leave if there is effectively no change */
- if (!chgs)
- goto out;
-
- if (hw->fw_log.cq_en)
- cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN;
-
- if (hw->fw_log.uart_en)
- cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN;
-
- buf = data;
- len = ICE_FW_LOG_DESC_SIZE(chgs);
- desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
- }
- }
-
- status = ice_aq_send_cmd(hw, &desc, buf, len, NULL);
- if (!status) {
- /* Update the current configuration to reflect events enabled.
- * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW
- * logging mode is enabled for the device. They do not reflect
- * actual modules being enabled to emit log messages. So, their
- * values remain unchanged even when all modules are disabled.
- */
- u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX;
-
- hw->fw_log.actv_evnts = actv_evnts;
- for (i = 0; i < cnt; i++) {
- u16 v, m;
-
- if (!enable) {
- /* When disabling all FW logging events as part
- * of device's de-initialization, the original
- * configurations are retained, and can be used
- * to reconfigure FW logging later if the device
- * is re-initialized.
- */
- hw->fw_log.evnts[i].cur = 0;
- continue;
- }
-
- v = LE16_TO_CPU(data->entry[i]);
- m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
- hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg;
- }
- }
-
-out:
- if (data)
- ice_free(hw, data);
-
- return status;
-}
-
-/**
- * ice_output_fw_log
- * @hw: pointer to the HW struct
- * @desc: pointer to the AQ message descriptor
- * @buf: pointer to the buffer accompanying the AQ message
- *
- * Formats a FW Log message and outputs it via the standard driver logs.
- */
-void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf)
-{
- ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n");
- ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf,
- LE16_TO_CPU(desc->datalen));
- ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n");
-}
/**
* ice_get_itr_intrl_gran - determine int/intrl granularity
@@ -979,10 +762,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
ice_print_rollback_msg(hw);
- /* Enable FW logging. Not fatal if this fails. */
- status = ice_cfg_fw_log(hw, true);
- if (status)
- ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n");
status = ice_clear_pf_cfg(hw);
if (status)
@@ -1136,8 +915,6 @@ void ice_deinit_hw(struct ice_hw *hw)
hw->port_info = NULL;
}
- /* Attempt to disable FW logging before shutting down control queues */
- ice_cfg_fw_log(hw, false);
ice_destroy_all_ctrlq(hw);
/* Clear VSI contexts if not already cleared */
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index 4ecfa6b9b..4e44c2f13 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -194,7 +194,6 @@ enum ice_status
ice_cfg_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc,
enum ice_rl_type rl_type, u8 bw_alloc);
enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes);
-void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf);
void
ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
u64 *prev_stat, u64 *cur_stat);
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index d8cb8eecd..7194cb9ec 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -690,25 +690,6 @@ struct ice_switch_info {
struct ice_sw_recipe *recp_list;
};
-/* FW logging configuration */
-struct ice_fw_log_evnt {
- u8 cfg : 4; /* New event enables to configure */
- u8 cur : 4; /* Current/active event enables */
-};
-
-struct ice_fw_log_cfg {
- u8 cq_en : 1; /* FW logging is enabled via the control queue */
- u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */
- u8 actv_evnts; /* Cumulation of currently enabled log events */
-
-#define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S)
-#define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S)
-#define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S)
-#define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S)
-#define ICE_FW_LOG_EVNT_ALL (ICE_FW_LOG_EVNT_INFO | ICE_FW_LOG_EVNT_INIT | \
- ICE_FW_LOG_EVNT_FLOW | ICE_FW_LOG_EVNT_ERR)
- struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX];
-};
/* Port hardware description */
struct ice_hw {
@@ -767,7 +748,6 @@ struct ice_hw {
u8 fw_patch; /* firmware patch version */
u32 fw_build; /* firmware build number */
- struct ice_fw_log_cfg fw_log;
/* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
* register. Used for determining the itr/intrl granularity during
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 09/63] net/ice/base: add SFF EEPROM AQ Command
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (7 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 08/63] net/ice/base: remove debug code Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 10/63] net/ice/base: improve debug print message Qi Zhang
` (54 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Scott W Taylor, Paul M Stillwell Jr
read/write module eeprom on i2c bus.
Signed-off-by: Scott W Taylor <scott.w.taylor@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_adminq_cmd.h | 29 ++++++++++++++++++++++
drivers/net/ice/base/ice_common.c | 46 +++++++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_common.h | 5 +++-
3 files changed, 79 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index 9e5853cca..4de69dd7a 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1660,6 +1660,33 @@ struct ice_aqc_set_port_id_led {
+/* Read/Write SFF EEPROM command (indirect 0x06EE) */
+struct ice_aqc_sff_eeprom {
+ u8 lport_num;
+ u8 lport_num_valid;
+#define ICE_AQC_SFF_PORT_NUM_VALID BIT(0)
+ __le16 i2c_bus_addr;
+#define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F
+#define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF
+#define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10)
+#define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0
+#define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M
+#define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11
+#define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S)
+#define ICE_AQC_SFF_NO_PAGE_CHANGE 0
+#define ICE_AQC_SFF_SET_23_ON_MISMATCH 1
+#define ICE_AQC_SFF_SET_22_ON_MISMATCH 2
+#define ICE_AQC_SFF_IS_WRITE BIT(15)
+ __le16 i2c_mem_addr;
+ __le16 eeprom_page;
+#define ICE_AQC_SFF_EEPROM_BANK_S 0
+#define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)
+#define ICE_AQC_SFF_EEPROM_PAGE_S 8
+#define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)
+ __le32 addr_high;
+ __le32 addr_low;
+};
+
/* NVM Read command (indirect 0x0701)
* NVM Erase commands (direct 0x0702)
* NVM Update commands (indirect 0x0703)
@@ -2218,6 +2245,7 @@ struct ice_aq_desc {
struct ice_aqc_get_phy_caps get_phy;
struct ice_aqc_set_phy_cfg set_phy;
struct ice_aqc_restart_an restart_an;
+ struct ice_aqc_sff_eeprom read_write_sff_param;
struct ice_aqc_set_port_id_led set_port_id_led;
struct ice_aqc_get_sw_cfg get_sw_conf;
struct ice_aqc_sw_rules sw_rules;
@@ -2431,6 +2459,7 @@ enum ice_adminq_opc {
ice_aqc_opc_set_port_option = 0x06EB,
ice_aqc_opc_set_gpio = 0x06EC,
ice_aqc_opc_get_gpio = 0x06ED,
+ ice_aqc_opc_sff_eeprom = 0x06EE,
/* NVM commands */
ice_aqc_opc_nvm_read = 0x0701,
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 43c06948f..cd94995f4 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -2860,6 +2860,52 @@ ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
}
/**
+ * ice_aq_sff_eeprom
+ * @hw: pointer to the HW struct
+ * @lport: bits [7:0] = logical port, bit [8] = logical port valid
+ * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
+ * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
+ * @page: QSFP page
+ * @set_page: set or ignore the page
+ * @data: pointer to data buffer to be read/written to the I2C device.
+ * @length: 1-16 for read, 1 for write.
+ * @write: 0 read, 1 for write.
+ * @cd: pointer to command details structure or NULL
+ *
+ * Read/Write SFF EEPROM (0x06EE)
+ */
+enum ice_status
+ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
+ u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
+ bool write, struct ice_sq_cd *cd)
+{
+ struct ice_aqc_sff_eeprom *cmd;
+ struct ice_aq_desc desc;
+ enum ice_status status;
+
+ if (!data || (mem_addr & 0xff00))
+ return ICE_ERR_PARAM;
+
+ ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
+ cmd = &desc.params.read_write_sff_param;
+ desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF);
+ cmd->lport_num = (u8)(lport & 0xff);
+ cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
+ cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) &
+ ICE_AQC_SFF_I2CBUS_7BIT_M) |
+ ((set_page <<
+ ICE_AQC_SFF_SET_EEPROM_PAGE_S) &
+ ICE_AQC_SFF_SET_EEPROM_PAGE_M));
+ cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff);
+ cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);
+ if (write)
+ cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE);
+
+ status = ice_aq_send_cmd(hw, &desc, data, length, cd);
+ return status;
+}
+
+/**
* __ice_aq_get_set_rss_lut
* @hw: pointer to the hardware structure
* @vsi_id: VSI FW index
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index 4e44c2f13..d865021bf 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -163,7 +163,10 @@ ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd);
enum ice_status
ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
struct ice_sq_cd *cd);
-
+enum ice_status
+ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
+ u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
+ bool write, struct ice_sq_cd *cd);
enum ice_status
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 10/63] net/ice/base: improve debug print message
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (8 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 09/63] net/ice/base: add SFF EEPROM AQ Command Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 11/63] net/ice/base: add capabilities when in safe mode Qi Zhang
` (53 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang; +Cc: dev, xiaolong.ye, Qi Zhang, Paul M Stillwell Jr
Improve debug print message.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 41 +++++++++++++++++++------------------
drivers/net/ice/base/ice_controlq.c | 10 +++++----
2 files changed, 27 insertions(+), 24 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index cd94995f4..ae7837149 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -1955,7 +1955,7 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
case ICE_AQC_CAPS_VALID_FUNCTIONS:
caps->valid_functions = number;
ice_debug(hw, ICE_DBG_INIT,
- "%s: valid functions = %d\n", prefix,
+ "%s: valid_functions (bitmap) = %d\n", prefix,
caps->valid_functions);
/* store func count for resource management purposes */
@@ -1966,17 +1966,17 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
if (dev_p) {
dev_p->num_vsi_allocd_to_host = number;
ice_debug(hw, ICE_DBG_INIT,
- "%s: num VSI alloc to host = %d\n",
+ "%s: num_vsi_allocd_to_host = %d\n",
prefix,
dev_p->num_vsi_allocd_to_host);
} else if (func_p) {
func_p->guar_num_vsi =
ice_get_num_per_func(hw, ICE_MAX_VSI);
ice_debug(hw, ICE_DBG_INIT,
- "%s: num guaranteed VSI (fw) = %d\n",
+ "%s: guar_num_vsi (fw) = %d\n",
prefix, number);
ice_debug(hw, ICE_DBG_INIT,
- "%s: num guaranteed VSI = %d\n",
+ "%s: guar_num_vsi = %d\n",
prefix, func_p->guar_num_vsi);
}
break;
@@ -1985,51 +1985,51 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
caps->active_tc_bitmap = logical_id;
caps->maxtc = phys_id;
ice_debug(hw, ICE_DBG_INIT,
- "%s: DCB = %d\n", prefix, caps->dcb);
+ "%s: dcb = %d\n", prefix, caps->dcb);
ice_debug(hw, ICE_DBG_INIT,
- "%s: active TC bitmap = %d\n", prefix,
+ "%s: active_tc_bitmap = %d\n", prefix,
caps->active_tc_bitmap);
ice_debug(hw, ICE_DBG_INIT,
- "%s: TC max = %d\n", prefix, caps->maxtc);
+ "%s: maxtc = %d\n", prefix, caps->maxtc);
break;
case ICE_AQC_CAPS_RSS:
caps->rss_table_size = number;
caps->rss_table_entry_width = logical_id;
ice_debug(hw, ICE_DBG_INIT,
- "%s: RSS table size = %d\n", prefix,
+ "%s: rss_table_size = %d\n", prefix,
caps->rss_table_size);
ice_debug(hw, ICE_DBG_INIT,
- "%s: RSS table width = %d\n", prefix,
+ "%s: rss_table_entry_width = %d\n", prefix,
caps->rss_table_entry_width);
break;
case ICE_AQC_CAPS_RXQS:
caps->num_rxq = number;
caps->rxq_first_id = phys_id;
ice_debug(hw, ICE_DBG_INIT,
- "%s: num Rx queues = %d\n", prefix,
+ "%s: num_rxq = %d\n", prefix,
caps->num_rxq);
ice_debug(hw, ICE_DBG_INIT,
- "%s: Rx first queue ID = %d\n", prefix,
+ "%s: rxq_first_id = %d\n", prefix,
caps->rxq_first_id);
break;
case ICE_AQC_CAPS_TXQS:
caps->num_txq = number;
caps->txq_first_id = phys_id;
ice_debug(hw, ICE_DBG_INIT,
- "%s: num Tx queues = %d\n", prefix,
+ "%s: num_txq = %d\n", prefix,
caps->num_txq);
ice_debug(hw, ICE_DBG_INIT,
- "%s: Tx first queue ID = %d\n", prefix,
+ "%s: txq_first_id = %d\n", prefix,
caps->txq_first_id);
break;
case ICE_AQC_CAPS_MSIX:
caps->num_msix_vectors = number;
caps->msix_vector_first_id = phys_id;
ice_debug(hw, ICE_DBG_INIT,
- "%s: MSIX vector count = %d\n", prefix,
+ "%s: num_msix_vectors = %d\n", prefix,
caps->num_msix_vectors);
ice_debug(hw, ICE_DBG_INIT,
- "%s: MSIX first vector index = %d\n", prefix,
+ "%s: msix_vector_first_id = %d\n", prefix,
caps->msix_vector_first_id);
break;
case ICE_AQC_CAPS_FD:
@@ -2039,7 +2039,8 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
if (dev_p) {
dev_p->num_flow_director_fltr = number;
ice_debug(hw, ICE_DBG_INIT,
- "%s: num FD filters = %d\n", prefix,
+ "%s: num_flow_director_fltr = %d\n",
+ prefix,
dev_p->num_flow_director_fltr);
}
if (func_p) {
@@ -2052,17 +2053,17 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
GLQF_FD_SIZE_FD_BSIZE_S;
func_p->fd_fltr_best_effort = val;
ice_debug(hw, ICE_DBG_INIT,
- "%s: num guaranteed FD filters = %d\n",
+ "%s: fd_fltr_guar = %d\n",
prefix, func_p->fd_fltr_guar);
ice_debug(hw, ICE_DBG_INIT,
- "%s: num best effort FD filters = %d\n",
+ "%s: fd_fltr_best_effort = %d\n",
prefix, func_p->fd_fltr_best_effort);
}
break;
}
case ICE_AQC_CAPS_MAX_MTU:
caps->max_mtu = number;
- ice_debug(hw, ICE_DBG_INIT, "%s: max MTU = %d\n",
+ ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
prefix, caps->max_mtu);
break;
default:
@@ -2081,7 +2082,7 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
/* Max 4 TCs per port */
caps->maxtc = 4;
ice_debug(hw, ICE_DBG_INIT,
- "%s: TC max = %d (based on #ports)\n", prefix,
+ "%s: maxtc = %d (based on #ports)\n", prefix,
caps->maxtc);
}
}
diff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c
index 80322e70d..8070bb9a7 100644
--- a/drivers/net/ice/base/ice_controlq.c
+++ b/drivers/net/ice/base/ice_controlq.c
@@ -968,7 +968,7 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
}
/* Debug desc and buffer */
- ice_debug(hw, ICE_DBG_AQ_MSG,
+ ice_debug(hw, ICE_DBG_AQ_DESC,
"ATQ: Control Send queue desc and buffer:\n");
ice_debug_cq(hw, (void *)desc_on_ring, buf, buf_size);
@@ -1008,7 +1008,8 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
retval = LE16_TO_CPU(desc->retval);
if (retval) {
ice_debug(hw, ICE_DBG_AQ_MSG,
- "Control Send Queue command completed with error 0x%x\n",
+ "Control Send Queue command 0x%04X completed with error 0x%X\n",
+ LE16_TO_CPU(desc->opcode),
retval);
/* strip off FW internal code */
@@ -1113,7 +1114,8 @@ ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
if (flags & ICE_AQ_FLAG_ERR) {
ret_code = ICE_ERR_AQ_ERROR;
ice_debug(hw, ICE_DBG_AQ_MSG,
- "Control Receive Queue Event received with error 0x%x\n",
+ "Control Receive Queue Event 0x%04X received with error 0x%X\n",
+ LE16_TO_CPU(desc->opcode),
cq->rq_last_status);
}
ice_memcpy(&e->desc, desc, sizeof(e->desc), ICE_DMA_TO_NONDMA);
@@ -1123,7 +1125,7 @@ ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
ice_memcpy(e->msg_buf, cq->rq.r.rq_bi[desc_idx].va,
e->msg_len, ICE_DMA_TO_NONDMA);
- ice_debug(hw, ICE_DBG_AQ_MSG, "ARQ: desc and buffer:\n");
+ ice_debug(hw, ICE_DBG_AQ_DESC, "ARQ: desc and buffer:\n");
ice_debug_cq(hw, (void *)desc, e->msg_buf,
cq->rq_buf_size);
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 11/63] net/ice/base: add capabilities when in safe mode
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (9 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 10/63] net/ice/base: improve debug print message Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 12/63] net/ice/base: add helper functions for PHY caching Qi Zhang
` (52 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Anirudh Venkataramanan, Paul M Stillwell Jr
The dynamic device personalization (DDP) file download onto the device
can fail, and when this happens the driver has to transition to "safe
mode" where only basic functionality is possible.
The device though doesn't understand safe mode, and so the opcodes to
discover device/function capabilities (0x000A and 0x000B) return all
the capabilities of the device, which includes capabilities that the
driver cannot support when in safe mode.
The initialization flows in the driver are based on the capabilities
information (obtained by the driver with the above mentioned opcodes).
To reuse the same initialization flows in safe mode, it becomes
necessary for the driver to override the currently stored capabilities
information with safe mode capabilities. This is done by a new function
introduced in this patch - ice_set_safe_mode_caps.
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 64 +++++++++++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_common.h | 2 ++
2 files changed, 66 insertions(+)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index ae7837149..9907d9dae 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -2172,6 +2172,70 @@ ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
}
/**
+ * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
+ * @hw: pointer to the hardware structure
+ */
+void ice_set_safe_mode_caps(struct ice_hw *hw)
+{
+ struct ice_hw_func_caps *func_caps = &hw->func_caps;
+ struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
+ u32 valid_func, rxq_first_id, txq_first_id;
+ u32 msix_vector_first_id, max_mtu;
+ u32 num_funcs;
+
+ /* cache some func_caps values that should be restored after memset */
+ valid_func = func_caps->common_cap.valid_functions;
+ txq_first_id = func_caps->common_cap.txq_first_id;
+ rxq_first_id = func_caps->common_cap.rxq_first_id;
+ msix_vector_first_id = func_caps->common_cap.msix_vector_first_id;
+ max_mtu = func_caps->common_cap.max_mtu;
+
+ /* unset func capabilities */
+ memset(func_caps, 0, sizeof(*func_caps));
+
+ /* restore cached values */
+ func_caps->common_cap.valid_functions = valid_func;
+ func_caps->common_cap.txq_first_id = txq_first_id;
+ func_caps->common_cap.rxq_first_id = rxq_first_id;
+ func_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
+ func_caps->common_cap.max_mtu = max_mtu;
+
+ /* one Tx and one Rx queue in safe mode */
+ func_caps->common_cap.num_rxq = 1;
+ func_caps->common_cap.num_txq = 1;
+
+ /* two MSIX vectors, one for traffic and one for misc causes */
+ func_caps->common_cap.num_msix_vectors = 2;
+ func_caps->guar_num_vsi = 1;
+
+ /* cache some dev_caps values that should be restored after memset */
+ valid_func = dev_caps->common_cap.valid_functions;
+ txq_first_id = dev_caps->common_cap.txq_first_id;
+ rxq_first_id = dev_caps->common_cap.rxq_first_id;
+ msix_vector_first_id = dev_caps->common_cap.msix_vector_first_id;
+ max_mtu = dev_caps->common_cap.max_mtu;
+ num_funcs = dev_caps->num_funcs;
+
+ /* unset dev capabilities */
+ memset(dev_caps, 0, sizeof(*dev_caps));
+
+ /* restore cached values */
+ dev_caps->common_cap.valid_functions = valid_func;
+ dev_caps->common_cap.txq_first_id = txq_first_id;
+ dev_caps->common_cap.rxq_first_id = rxq_first_id;
+ dev_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
+ dev_caps->common_cap.max_mtu = max_mtu;
+ dev_caps->num_funcs = num_funcs;
+
+ /* one Tx and one Rx queue per function in safe mode */
+ dev_caps->common_cap.num_rxq = num_funcs;
+ dev_caps->common_cap.num_txq = num_funcs;
+
+ /* two MSIX vectors per function */
+ dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
+}
+
+/**
* ice_get_caps - get info about the HW
* @hw: pointer to the hardware structure
*/
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index d865021bf..df1fecec5 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -61,6 +61,8 @@ void ice_clear_pxe_mode(struct ice_hw *hw);
enum ice_status ice_get_caps(struct ice_hw *hw);
+void ice_set_safe_mode_caps(struct ice_hw *hw);
+
/* Define a macro that will align a pointer to point to the next memory address
* that falls on the given power of 2 (i.e., 2, 4, 8, 16, 32, 64...). For
* example, given the variable pointer = 0x1006, then after the following call:
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 12/63] net/ice/base: add helper functions for PHY caching
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (10 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 11/63] net/ice/base: add capabilities when in safe mode Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 13/63] net/ice/base: add support for reading REPC statistics Qi Zhang
` (51 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Tony Nguyen, Paul M Stillwell Jr
Add additional functions to aide in caching PHY
configuration. In order to cache the initial modes,
we need to determine the operating mode based on
capabilities. Add helper functions for flow control
and FEC to take a set of capabilities and return the
operating mode matching those capabilities. Also add
a helper function to determine whether a PHY capability
matches a PHY configuration.
Introduce a mask for valid link speeds and unwrap
ice_copy_caps_to_cfg() for more builds so that we can utilize
it in more places.
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_adminq_cmd.h | 1 +
drivers/net/ice/base/ice_common.c | 83 +++++++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_common.h | 9 +++-
3 files changed, 91 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index 4de69dd7a..cc42180ea 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1598,6 +1598,7 @@ struct ice_aqc_get_link_status_data {
#define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
#define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
__le16 link_speed;
+#define ICE_AQ_LINK_SPEED_M 0x7FF
#define ICE_AQ_LINK_SPEED_10MB BIT(0)
#define ICE_AQ_LINK_SPEED_100MB BIT(1)
#define ICE_AQ_LINK_SPEED_1000MB BIT(2)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 9907d9dae..6b28f6230 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -2613,6 +2613,53 @@ ice_cache_phy_user_req(struct ice_port_info *pi,
}
/**
+ * ice_caps_to_fc_mode
+ * @caps: PHY capabilities
+ *
+ * Convert PHY FC capabilities to ice FC mode
+ */
+enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
+{
+ if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
+ caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
+ return ICE_FC_FULL;
+
+ if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
+ return ICE_FC_TX_PAUSE;
+
+ if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
+ return ICE_FC_RX_PAUSE;
+
+ return ICE_FC_NONE;
+}
+
+/**
+ * ice_caps_to_fec_mode
+ * @caps: PHY capabilities
+ * @fec_options: Link FEC options
+ *
+ * Convert PHY FEC capabilities to ice FEC mode
+ */
+enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
+{
+ if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
+ return ICE_FEC_AUTO;
+
+ if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
+ ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
+ ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
+ ICE_AQC_PHY_FEC_25G_KR_REQ))
+ return ICE_FEC_BASER;
+
+ if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
+ ICE_AQC_PHY_FEC_25G_RS_544_REQ |
+ ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
+ return ICE_FEC_RS;
+
+ return ICE_FEC_NONE;
+}
+
+/**
* ice_set_fc
* @pi: port information structure
* @aq_failures: pointer to status code, specific to ice_set_fc routine
@@ -2719,6 +2766,42 @@ ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
}
/**
+ * ice_phy_caps_equals_cfg
+ * @phy_caps: PHY capabilities
+ * @phy_cfg: PHY configuration
+ *
+ * Helper function to determine if PHY capabilities matches PHY
+ * configuration
+ */
+bool
+ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
+ struct ice_aqc_set_phy_cfg_data *phy_cfg)
+{
+ u8 caps_mask, cfg_mask;
+
+ if (!phy_caps || !phy_cfg)
+ return false;
+
+ /* These bits are not common between capabilities and configuration.
+ * Do not use them to determine equality.
+ */
+ caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
+ ICE_AQC_PHY_EN_MOD_QUAL);
+ cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
+
+ if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
+ phy_caps->phy_type_high != phy_cfg->phy_type_high ||
+ ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
+ phy_caps->low_power_ctrl != phy_cfg->low_power_ctrl ||
+ phy_caps->eee_cap != phy_cfg->eee_cap ||
+ phy_caps->eeer_value != phy_cfg->eeer_value ||
+ phy_caps->link_fec_options != phy_cfg->link_fec_opt)
+ return false;
+
+ return true;
+}
+
+/**
* ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
* @caps: PHY ability structure to copy date from
* @cfg: PHY configuration structure to copy data to
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index df1fecec5..a8104dfa2 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -139,14 +139,19 @@ enum ice_status ice_clear_pf_cfg(struct ice_hw *hw);
enum ice_status
ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd);
+enum ice_fc_mode ice_caps_to_fc_mode(u8 caps);
+enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options);
enum ice_status
ice_set_fc(struct ice_port_info *pi, u8 *aq_failures,
bool ena_auto_link_update);
-void
-ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec);
+bool
+ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps,
+ struct ice_aqc_set_phy_cfg_data *cfg);
void
ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,
struct ice_aqc_set_phy_cfg_data *cfg);
+void
+ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec);
enum ice_status
ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
struct ice_sq_cd *cd);
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 13/63] net/ice/base: add support for reading REPC statistics
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (11 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 12/63] net/ice/base: add helper functions for PHY caching Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 14/63] net/ice/base: adjust DCB INIT for SW mode Qi Zhang
` (50 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Jacob Keller, Paul M Stillwell Jr
The GLV_REPC register contains statistics for tracking received packets
that are discarded due to certain errors.
This register behaves differently from some of the other related
statistics registers in two ways. First, it contains two 16bit
statistics, and thus cannot be read as a 32bit or 40bit statistic.
Second, the two stats do not roll over, but instead cap at 0xFFFF.
Add a new ice_stat_update_repc function which will read the register and
increment the appropriate statistics in the ice_eth_stats structure.
Since the register does not roll over, make use of the "Write Clear"
behavior, and write to the register to reset it every time we read it.
Add extra space for the two statistics that are counted by this
register, rx_errors, and rx_no_desc.
For now, wrap the new function and stats counters in !LINUX_SUPPORT.
This can later be removed if and when the Linux driver implements
support for reading the statistics.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 51 +++++++++++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_common.h | 3 +++
drivers/net/ice/base/ice_type.h | 2 ++
3 files changed, 56 insertions(+)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 6b28f6230..36434ee42 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -4253,6 +4253,57 @@ ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
*prev_stat = new_data;
}
+/**
+ * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values
+ * @hw: ptr to the hardware info
+ * @vsi_handle: VSI handle
+ * @prev_stat_loaded: bool to specify if the previous stat values are loaded
+ * @cur_stats: ptr to current stats structure
+ *
+ * The GLV_REPC statistic register actually tracks two 16bit statistics, and
+ * thus cannot be read using the normal ice_stat_update32 function.
+ *
+ * Read the GLV_REPC register associated with the given VSI, and update the
+ * rx_no_desc and rx_error values in the ice_eth_stats structure.
+ *
+ * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be
+ * cleared each time it's read.
+ *
+ * Note that the GLV_RDPC register also counts the causes that would trigger
+ * GLV_REPC. However, it does not give the finer grained detail about why the
+ * packets are being dropped. The GLV_REPC values can be used to distinguish
+ * whether Rx packets are dropped due to errors or due to no available
+ * descriptors.
+ */
+void
+ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
+ struct ice_eth_stats *cur_stats)
+{
+ u16 vsi_num, no_desc, error_cnt;
+ u32 repc;
+
+ if (!ice_is_vsi_valid(hw, vsi_handle))
+ return;
+
+ vsi_num = ice_get_hw_vsi_num(hw, vsi_handle);
+
+ /* If we haven't loaded stats yet, just clear the current value */
+ if (!prev_stat_loaded) {
+ wr32(hw, GLV_REPC(vsi_num), 0);
+ return;
+ }
+
+ repc = rd32(hw, GLV_REPC(vsi_num));
+ no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S;
+ error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S;
+
+ /* Clear the count by writing to the stats register */
+ wr32(hw, GLV_REPC(vsi_num), 0);
+
+ cur_stats->rx_no_desc += no_desc;
+ cur_stats->rx_errors += error_cnt;
+}
+
/**
* ice_sched_query_elem - query element information from HW
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index a8104dfa2..1fd256a42 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -211,6 +211,9 @@ void
ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
u64 *prev_stat, u64 *cur_stat);
void
+ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
+ struct ice_eth_stats *cur_stats);
+void
ice_get_nvm_version(struct ice_hw *hw, u8 *oem_ver, u16 *oem_build,
u8 *oem_patch, u8 *ver_hi, u8 *ver_lo);
enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw);
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 7194cb9ec..0dba94a53 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -833,6 +833,8 @@ struct ice_eth_stats {
u64 tx_broadcast; /* bptc */
u64 tx_discards; /* tdpc */
u64 tx_errors; /* tepc */
+ u64 rx_no_desc; /* repc */
+ u64 rx_errors; /* repc */
};
#define ICE_MAX_UP 8
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 14/63] net/ice/base: adjust DCB INIT for SW mode
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (12 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 13/63] net/ice/base: add support for reading REPC statistics Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 15/63] net/ice/base: add NVM pkg flag Qi Zhang
` (49 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dave Ertman, Paul M Stillwell Jr
Adjust ice_init_dcb to set the is_sw_lldp boolean
in the case where the FW has been detected to be
in an untenable state such that the driver
should forcibly make sure it is off.
This will ensure that the FW is in a known state.
Signed-off-by: Dave Ertman <david.m.ertman@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_dcb.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ice/base/ice_dcb.c b/drivers/net/ice/base/ice_dcb.c
index a6fbedd18..7048dbd02 100644
--- a/drivers/net/ice/base/ice_dcb.c
+++ b/drivers/net/ice/base/ice_dcb.c
@@ -966,9 +966,9 @@ enum ice_status ice_init_dcb(struct ice_hw *hw, bool enable_mib_change)
pi->dcbx_status == ICE_DCBX_STATUS_NOT_STARTED) {
/* Get current DCBX configuration */
ret = ice_get_dcb_cfg(pi);
- pi->is_sw_lldp = (hw->adminq.sq_last_status == ICE_AQ_RC_EPERM);
if (ret)
return ret;
+ pi->is_sw_lldp = false;
} else if (pi->dcbx_status == ICE_DCBX_STATUS_DIS) {
return ICE_ERR_NOT_READY;
}
@@ -976,8 +976,8 @@ enum ice_status ice_init_dcb(struct ice_hw *hw, bool enable_mib_change)
/* Configure the LLDP MIB change event */
if (enable_mib_change) {
ret = ice_aq_cfg_lldp_mib_change(hw, true, NULL);
- if (!ret)
- pi->is_sw_lldp = false;
+ if (ret)
+ pi->is_sw_lldp = true;
}
return ret;
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 15/63] net/ice/base: add NVM pkg flag
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (13 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 14/63] net/ice/base: adjust DCB INIT for SW mode Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 16/63] net/ice/base: move VSI to VSI group Qi Zhang
` (48 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Ashish Shah, Paul M Stillwell Jr
Add flag for case where active package has been loaded from NVM.
Signed-off-by: Ashish Shah <ashish.n.shah@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flex_pipe.c | 1 +
drivers/net/ice/base/ice_type.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index afb867877..5a5dbff5b 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -1144,6 +1144,7 @@ static enum ice_status ice_get_pkg_info(struct ice_hw *hw)
pkg_info->pkg_info[i].name,
sizeof(hw->active_pkg_name),
ICE_NONDMA_TO_NONDMA);
+ hw->active_pkg_in_nvm = pkg_info->pkg_info[i].is_in_nvm;
}
if (pkg_info->pkg_info[i].is_active_at_boot)
flags[place++] = 'B';
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 0dba94a53..79d7bb1dd 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -773,6 +773,7 @@ struct ice_hw {
/* Active package version (currently active) */
struct ice_pkg_ver active_pkg_ver;
u8 active_pkg_name[ICE_PKG_NAME_SIZE];
+ u8 active_pkg_in_nvm;
/* Driver's package ver - (from the Metadata seg) */
struct ice_pkg_ver pkg_ver;
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 16/63] net/ice/base: move VSI to VSI group
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (14 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 15/63] net/ice/base: add NVM pkg flag Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 17/63] net/ice/base: enable masking for RSS and FD field vectors Qi Zhang
` (47 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Vignesh Sridhar, Paul M Stillwell Jr
Add function to add a VSI to a given VSIG and update package with this
entry. The usual flow in XLT management would iterate through all
characteristics of the input VSI and create a new VSIG and TCAMs till a
matching characteristic is found. When a match is found the VSI is moved
into a matching VSIG and entries are collapsed, leading to added package
update calls. This function serves as an optimization if we know
beforehand that the input VSI has characteristics same as VSI configured
previously added to a VSIG. This is particularly useful for VF VSIs
which are all usually programmed with the same configurations.
Signed-off-by: Vignesh Sridhar <vignesh.sridhar@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flex_pipe.c | 41 ++++++++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_flex_pipe.h | 2 ++
drivers/net/ice/base/ice_flow.c | 28 ++++++++++++++++++++++++
drivers/net/ice/base/ice_flow.h | 4 +++-
4 files changed, 74 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index 5a5dbff5b..00e1ec7bd 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -4772,6 +4772,47 @@ ice_find_prof_vsig(struct ice_hw *hw, enum ice_block blk, u64 hdl, u16 *vsig)
}
/**
+ * ice_add_vsi_flow - add VSI flow
+ * @hw: pointer to the HW struct
+ * @blk: hardware block
+ * @vsi: input VSI
+ * @vsig: target VSIG to include the input VSI
+ *
+ * Calling this function will add the VSI to a given VSIG and
+ * update the HW tables accordingly. This call can be used to
+ * add multiple VSIs to a VSIG if we know beforehand that those
+ * VSIs have the same characteristics of the VSIG. This will
+ * save time in generating a new VSIG and TCAMs till a match is
+ * found and subsequent rollback when a matching VSIG is found.
+ */
+enum ice_status
+ice_add_vsi_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u16 vsig)
+{
+ struct ice_chs_chg *tmp, *del;
+ struct LIST_HEAD_TYPE chg;
+ enum ice_status status;
+
+ /* if target VSIG is default the move is invalid */
+ if ((vsig & ICE_VSIG_IDX_M) == ICE_DEFAULT_VSIG)
+ return ICE_ERR_PARAM;
+
+ INIT_LIST_HEAD(&chg);
+
+ /* move VSI to the VSIG that matches */
+ status = ice_move_vsi(hw, blk, vsi, vsig, &chg);
+ /* update hardware if success */
+ if (!status)
+ status = ice_upd_prof_hw(hw, blk, &chg);
+
+ LIST_FOR_EACH_ENTRY_SAFE(del, tmp, &chg, ice_chs_chg, list_entry) {
+ LIST_DEL(&del->list_entry);
+ ice_free(hw, del);
+ }
+
+ return status;
+}
+
+/**
* ice_add_prof_id_flow - add profile flow
* @hw: pointer to the HW struct
* @blk: hardware block
diff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h
index 2801e1b50..f01dfbb98 100644
--- a/drivers/net/ice/base/ice_flex_pipe.h
+++ b/drivers/net/ice/base/ice_flex_pipe.h
@@ -50,6 +50,8 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],
struct ice_prof_map *
ice_search_prof_id(struct ice_hw *hw, enum ice_block blk, u64 id);
enum ice_status
+ice_add_vsi_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u16 vsig);
+enum ice_status
ice_add_prof_id_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u64 hdl);
enum ice_status
ice_rem_prof_id_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u64 hdl);
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 36d31fa13..fb9041b3e 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -1112,6 +1112,34 @@ ice_flow_rem_prof_sync(struct ice_hw *hw, enum ice_block blk,
}
/**
+ * ice_flow_assoc_vsig_vsi - associate a VSI with VSIG
+ * @hw: pointer to the hardware structure
+ * @blk: classification stage
+ * @vsi_handle: software VSI handle
+ * @vsig: target VSI group
+ *
+ * Assumption: the caller has already verified that the VSI to
+ * be added has the same characteristics as the VSIG and will
+ * thereby have access to all resources added to that VSIG.
+ */
+enum ice_status
+ice_flow_assoc_vsig_vsi(struct ice_hw *hw, enum ice_block blk, u16 vsi_handle,
+ u16 vsig)
+{
+ enum ice_status status;
+
+ if (!ice_is_vsi_valid(hw, vsi_handle) || blk >= ICE_BLK_COUNT)
+ return ICE_ERR_PARAM;
+
+ ice_acquire_lock(&hw->fl_profs_locks[blk]);
+ status = ice_add_vsi_flow(hw, blk, ice_get_hw_vsi_num(hw, vsi_handle),
+ vsig);
+ ice_release_lock(&hw->fl_profs_locks[blk]);
+
+ return status;
+}
+
+/**
* ice_flow_assoc_prof - associate a VSI with a flow profile
* @hw: pointer to the hardware structure
* @blk: classification stage
diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h
index c6442dc14..3a0fd23c4 100644
--- a/drivers/net/ice/base/ice_flow.h
+++ b/drivers/net/ice/base/ice_flow.h
@@ -317,7 +317,9 @@ ice_flow_add_prof(struct ice_hw *hw, enum ice_block blk, enum ice_flow_dir dir,
struct ice_flow_prof **prof);
enum ice_status
ice_flow_rem_prof(struct ice_hw *hw, enum ice_block blk, u64 prof_id);
-
+enum ice_status
+ice_flow_assoc_vsig_vsi(struct ice_hw *hw, enum ice_block blk, u16 vsi_handle,
+ u16 vsig);
enum ice_status
ice_flow_get_hw_prof(struct ice_hw *hw, enum ice_block blk, u64 prof_id,
u8 *hw_prof);
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 17/63] net/ice/base: enable masking for RSS and FD field vectors
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (15 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 16/63] net/ice/base: move VSI to VSI group Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 18/63] net/ice/base: resolve static analysis issues Qi Zhang
` (46 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
Allow masking per word field on RSS and FD field vectors.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flex_pipe.c | 540 ++++++++++++++++++++++++++++++++++-
drivers/net/ice/base/ice_flex_pipe.h | 5 +
drivers/net/ice/base/ice_flex_type.h | 17 ++
drivers/net/ice/base/ice_flow.c | 21 +-
4 files changed, 578 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index 00e1ec7bd..29888df76 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -2500,6 +2500,102 @@ ice_vsig_add_mv_vsi(struct ice_hw *hw, enum ice_block blk, u16 vsi, u16 vsig)
}
/**
+ * ice_prof_has_mask_idx - determine if profile index masking is identical
+ * @hw: pointer to the hardware structure
+ * @blk: HW block
+ * @prof: profile to check
+ * @idx: profile index to check
+ * @masks: masks to match
+ */
+static bool
+ice_prof_has_mask_idx(struct ice_hw *hw, enum ice_block blk, u8 prof, u16 idx,
+ u16 mask)
+{
+ bool expect_no_mask = false;
+ bool found = false;
+ bool match = false;
+ u16 i;
+
+ /* If mask is 0x0000 or 0xffff, then there is no masking */
+ if (mask == 0 || mask == 0xffff)
+ expect_no_mask = true;
+
+ /* Scan the enabled masks on this profile, for the specified idx */
+ for (i = 0; i < ICE_PROFILE_MASK_COUNT; i++)
+ if (hw->blk[blk].es.mask_ena[prof] & BIT(i))
+ if (hw->blk[blk].masks.masks[i].in_use &&
+ hw->blk[blk].masks.masks[i].idx == idx) {
+ found = true;
+ if (hw->blk[blk].masks.masks[i].mask == mask)
+ match = true;
+ break;
+ }
+
+ if (expect_no_mask) {
+ if (found)
+ return false;
+ } else {
+ if (!match)
+ return false;
+ }
+
+ return true;
+}
+
+/**
+ * ice_prof_has_mask - determine if profile masking is identical
+ * @hw: pointer to the hardware structure
+ * @blk: HW block
+ * @prof: profile to check
+ * @masks: masks to match
+ */
+static bool
+ice_prof_has_mask(struct ice_hw *hw, enum ice_block blk, u8 prof, u16 *masks)
+{
+ u16 i;
+
+ /* es->mask_ena[prof] will have the mask */
+ for (i = 0; i < hw->blk[blk].es.fvw; i++)
+ if (!ice_prof_has_mask_idx(hw, blk, prof, i, masks[i]))
+ return false;
+
+ return true;
+}
+
+/**
+ * ice_find_prof_id_with_mask - find profile ID for a given field vector
+ * @hw: pointer to the hardware structure
+ * @blk: HW block
+ * @fv: field vector to search for
+ * @masks: masks for fv
+ * @prof_id: receives the profile ID
+ */
+static enum ice_status
+ice_find_prof_id_with_mask(struct ice_hw *hw, enum ice_block blk,
+ struct ice_fv_word *fv, u16 *masks, u8 *prof_id)
+{
+ struct ice_es *es = &hw->blk[blk].es;
+ u16 i;
+
+ for (i = 0; i < es->count; i++) {
+ u16 off = i * es->fvw;
+ u16 j;
+
+ if (memcmp(&es->t[off], fv, es->fvw * sizeof(*fv)))
+ continue;
+
+ /* check if masks settings are the same for this profile */
+ if (!ice_prof_has_mask(hw, blk, i, masks))
+ continue;
+
+ *prof_id = i;
+ return ICE_SUCCESS;
+ }
+
+ return ICE_ERR_DOES_NOT_EXIST;
+}
+
+/**
* ice_find_prof_id - find profile ID for a given field vector
* @hw: pointer to the hardware structure
* @blk: HW block
@@ -2687,6 +2783,334 @@ ice_prof_inc_ref(struct ice_hw *hw, enum ice_block blk, u8 prof_id)
}
/**
+ * ice_write_prof_mask_reg - write profile mask register
+ * @hw: pointer to the HW struct
+ * @blk: hardware block
+ * @mask_idx: mask index
+ * @idx: index of the FV which will use the mask
+ * @mask: the 16-bit mask
+ */
+static void
+ice_write_prof_mask_reg(struct ice_hw *hw, enum ice_block blk, u16 mask_idx,
+ u16 idx, u16 mask)
+{
+ u32 offset;
+ u32 val;
+
+ switch (blk) {
+ case ICE_BLK_RSS:
+ offset = GLQF_HMASK(mask_idx);
+ val = (idx << GLQF_HMASK_MSK_INDEX_S) &
+ GLQF_HMASK_MSK_INDEX_M;
+ val |= (mask << GLQF_HMASK_MASK_S) & GLQF_HMASK_MASK_M;
+ break;
+ case ICE_BLK_FD:
+ offset = GLQF_FDMASK(mask_idx);
+ val = (idx << GLQF_FDMASK_MSK_INDEX_S) &
+ GLQF_FDMASK_MSK_INDEX_M;
+ val |= (mask << GLQF_FDMASK_MASK_S) &
+ GLQF_FDMASK_MASK_M;
+ break;
+ default:
+ ice_debug(hw, ICE_DBG_PKG, "No profile masks for block %d\n",
+ blk);
+ return;
+ }
+
+ wr32(hw, offset, val);
+ ice_debug(hw, ICE_DBG_PKG, "write mask, blk %d (%d): %x = %x\n",
+ blk, idx, offset, val);
+}
+
+/**
+ * ice_write_prof_mask_enable_res - write profile mask enable register
+ * @hw: pointer to the HW struct
+ * @blk: hardware block
+ * @prof_id: profile id
+ * @enable_mask: enable mask
+ */
+static void
+ice_write_prof_mask_enable_res(struct ice_hw *hw, enum ice_block blk,
+ u16 prof_id, u32 enable_mask)
+{
+ u32 offset;
+
+ switch (blk) {
+ case ICE_BLK_RSS:
+ offset = GLQF_HMASK_SEL(prof_id);
+ break;
+ case ICE_BLK_FD:
+ offset = GLQF_FDMASK_SEL(prof_id);
+ break;
+ default:
+ ice_debug(hw, ICE_DBG_PKG, "No profile masks for block %d\n",
+ blk);
+ return;
+ }
+
+ wr32(hw, offset, enable_mask);
+ ice_debug(hw, ICE_DBG_PKG, "write mask enable, blk %d (%d): %x = %x\n",
+ blk, prof_id, offset, enable_mask);
+}
+
+/**
+ * ice_init_prof_masks - initial prof masks
+ * @hw: pointer to the HW struct
+ * @blk: hardware block
+ */
+static void ice_init_prof_masks(struct ice_hw *hw, enum ice_block blk)
+{
+#define MAX_NUM_PORTS 8
+ u16 num_ports = MAX_NUM_PORTS;
+ u16 i;
+
+ ice_init_lock(&hw->blk[blk].masks.lock);
+
+ hw->blk[blk].masks.count = ICE_PROFILE_MASK_COUNT / num_ports;
+ hw->blk[blk].masks.first = hw->pf_id * hw->blk[blk].masks.count;
+
+ ice_memset(hw->blk[blk].masks.masks, 0,
+ sizeof(hw->blk[blk].masks.masks), ICE_NONDMA_MEM);
+
+ for (i = hw->blk[blk].masks.first;
+ i < hw->blk[blk].masks.first + hw->blk[blk].masks.count; i++)
+ ice_write_prof_mask_reg(hw, blk, i, 0, 0);
+}
+
+/**
+ * ice_init_all_prof_masks - initial all prof masks
+ * @hw: pointer to the HW struct
+ */
+void ice_init_all_prof_masks(struct ice_hw *hw)
+{
+ ice_init_prof_masks(hw, ICE_BLK_RSS);
+ ice_init_prof_masks(hw, ICE_BLK_FD);
+}
+
+/**
+ * ice_alloc_prof_mask - allocate profile mask
+ * @hw: pointer to the HW struct
+ * @blk: hardware block
+ * @idx: index of FV which will use the mask
+ * @mask: the 16-bit mask
+ * @mask_idx: variable to receive the mask index
+ */
+static enum ice_status
+ice_alloc_prof_mask(struct ice_hw *hw, enum ice_block blk, u16 idx, u16 mask,
+ u16 *mask_idx)
+{
+ bool found_unused = false, found_copy = false;
+ enum ice_status status = ICE_ERR_MAX_LIMIT;
+ u16 unused_idx = 0, copy_idx = 0;
+ u16 i;
+
+ if (blk != ICE_BLK_RSS && blk != ICE_BLK_FD)
+ return ICE_ERR_PARAM;
+
+ ice_acquire_lock(&hw->blk[blk].masks.lock);
+
+ for (i = hw->blk[blk].masks.first;
+ i < hw->blk[blk].masks.first + hw->blk[blk].masks.count; i++)
+ if (hw->blk[blk].masks.masks[i].in_use) {
+ /* if mask is in use and it exactly duplicates the
+ * desired mask and index, then in can be reused
+ */
+ if (hw->blk[blk].masks.masks[i].mask == mask &&
+ hw->blk[blk].masks.masks[i].idx == idx) {
+ found_copy = true;
+ copy_idx = i;
+ break;
+ }
+ } else {
+ /* save off unused index, but keep searching in case
+ * there is an exact match later on
+ */
+ if (!found_unused) {
+ found_unused = true;
+ unused_idx = i;
+ }
+ }
+
+ if (found_copy)
+ i = copy_idx;
+ else if (found_unused)
+ i = unused_idx;
+ else
+ goto err_ice_alloc_prof_mask;
+
+ /* update mask for a new entry */
+ if (found_unused) {
+ hw->blk[blk].masks.masks[i].in_use = true;
+ hw->blk[blk].masks.masks[i].mask = mask;
+ hw->blk[blk].masks.masks[i].idx = idx;
+ hw->blk[blk].masks.masks[i].ref = 0;
+ ice_write_prof_mask_reg(hw, blk, i, idx, mask);
+ }
+
+ hw->blk[blk].masks.masks[i].ref++;
+ *mask_idx = i;
+ status = ICE_SUCCESS;
+
+err_ice_alloc_prof_mask:
+ ice_release_lock(&hw->blk[blk].masks.lock);
+
+ return status;
+}
+
+/**
+ * ice_free_prof_mask - free profile mask
+ * @hw: pointer to the HW struct
+ * @blk: hardware block
+ * @mask_idx: index of mask
+ */
+static enum ice_status
+ice_free_prof_mask(struct ice_hw *hw, enum ice_block blk, u16 mask_idx)
+{
+ if (blk != ICE_BLK_RSS && blk != ICE_BLK_FD)
+ return ICE_ERR_PARAM;
+
+ if (!(mask_idx >= hw->blk[blk].masks.first &&
+ mask_idx < hw->blk[blk].masks.first + hw->blk[blk].masks.count))
+ return ICE_ERR_DOES_NOT_EXIST;
+
+ ice_acquire_lock(&hw->blk[blk].masks.lock);
+
+ if (!hw->blk[blk].masks.masks[mask_idx].in_use)
+ goto exit_ice_free_prof_mask;
+
+ if (hw->blk[blk].masks.masks[mask_idx].ref > 1) {
+ hw->blk[blk].masks.masks[mask_idx].ref--;
+ goto exit_ice_free_prof_mask;
+ }
+
+ /* remove mask */
+ hw->blk[blk].masks.masks[mask_idx].in_use = false;
+ hw->blk[blk].masks.masks[mask_idx].mask = 0;
+ hw->blk[blk].masks.masks[mask_idx].idx = 0;
+
+ /* update mask as unused entry */
+ ice_debug(hw, ICE_DBG_PKG, "Free mask, blk %d, mask %d", blk, mask_idx);
+ ice_write_prof_mask_reg(hw, blk, mask_idx, 0, 0);
+
+exit_ice_free_prof_mask:
+ ice_release_lock(&hw->blk[blk].masks.lock);
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_free_prof_masks - free all profile masks for a profile
+ * @hw: pointer to the HW struct
+ * @blk: hardware block
+ * @prof_id: profile id
+ */
+static enum ice_status
+ice_free_prof_masks(struct ice_hw *hw, enum ice_block blk, u16 prof_id)
+{
+ u32 mask_bm;
+ u16 i;
+
+ if (blk != ICE_BLK_RSS && blk != ICE_BLK_FD)
+ return ICE_ERR_PARAM;
+
+ mask_bm = hw->blk[blk].es.mask_ena[prof_id];
+ for (i = 0; i < BITS_PER_BYTE * sizeof(mask_bm); i++)
+ if (mask_bm & BIT(i))
+ ice_free_prof_mask(hw, blk, i);
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_shutdown_prof_masks - releases lock for masking
+ * @hw: pointer to the HW struct
+ * @blk: hardware block
+ *
+ * This should be called before unloading the driver
+ */
+static void ice_shutdown_prof_masks(struct ice_hw *hw, enum ice_block blk)
+{
+ u16 i;
+
+ ice_acquire_lock(&hw->blk[blk].masks.lock);
+
+ for (i = hw->blk[blk].masks.first;
+ i < hw->blk[blk].masks.first + hw->blk[blk].masks.count; i++) {
+ ice_write_prof_mask_reg(hw, blk, i, 0, 0);
+
+ hw->blk[blk].masks.masks[i].in_use = false;
+ hw->blk[blk].masks.masks[i].idx = 0;
+ hw->blk[blk].masks.masks[i].mask = 0;
+ }
+
+ ice_release_lock(&hw->blk[blk].masks.lock);
+ ice_destroy_lock(&hw->blk[blk].masks.lock);
+}
+
+/**
+ * ice_shutdown_all_prof_masks - releases all locks for masking
+ * @hw: pointer to the HW struct
+ * @blk: hardware block
+ *
+ * This should be called before unloading the driver
+ */
+void ice_shutdown_all_prof_masks(struct ice_hw *hw)
+{
+ ice_shutdown_prof_masks(hw, ICE_BLK_RSS);
+ ice_shutdown_prof_masks(hw, ICE_BLK_FD);
+}
+
+/**
+ * ice_update_prof_masking - set registers according to masking
+ * @hw: pointer to the HW struct
+ * @blk: hardware block
+ * @prof_id: profile id
+ * @es: field vector
+ * @masks: masks
+ */
+static enum ice_status
+ice_update_prof_masking(struct ice_hw *hw, enum ice_block blk, u16 prof_id,
+ struct ice_fv_word *es, u16 *masks)
+{
+ bool err = false;
+ u32 ena_mask = 0;
+ u16 idx;
+ u16 i;
+
+ /* Only support FD and RSS masking, otherwise nothing to be done */
+ if (blk != ICE_BLK_RSS && blk != ICE_BLK_FD)
+ return ICE_SUCCESS;
+
+ for (i = 0; i < hw->blk[blk].es.fvw; i++)
+ if (masks[i] && masks[i] != 0xFFFF) {
+ if (!ice_alloc_prof_mask(hw, blk, i, masks[i], &idx)) {
+ ena_mask |= BIT(idx);
+ } else {
+ /* not enough bitmaps */
+ err = true;
+ break;
+ }
+ }
+
+ if (err) {
+ /* free any bitmaps we have allocated */
+ for (i = 0; i < BITS_PER_BYTE * sizeof(ena_mask); i++)
+ if (ena_mask & BIT(i))
+ ice_free_prof_mask(hw, blk, i);
+
+ return ICE_ERR_OUT_OF_RANGE;
+ }
+
+ /* enable the masks for this profile */
+ ice_write_prof_mask_enable_res(hw, blk, prof_id, ena_mask);
+
+ /* store enabled masks with profile so that they can be freed later */
+ hw->blk[blk].es.mask_ena[prof_id] = ena_mask;
+
+ return ICE_SUCCESS;
+}
+
+/**
* ice_write_es - write an extraction sequence to hardware
* @hw: pointer to the HW struct
* @blk: the block in which to write the extraction sequence
@@ -2725,6 +3149,7 @@ ice_prof_dec_ref(struct ice_hw *hw, enum ice_block blk, u8 prof_id)
if (hw->blk[blk].es.ref_count[prof_id] > 0) {
if (!--hw->blk[blk].es.ref_count[prof_id]) {
ice_write_es(hw, blk, prof_id, NULL);
+ ice_free_prof_masks(hw, blk, prof_id);
return ice_free_prof_id(hw, blk, prof_id);
}
}
@@ -3089,6 +3514,7 @@ void ice_free_hw_tbls(struct ice_hw *hw)
ice_free(hw, hw->blk[i].es.t);
ice_free(hw, hw->blk[i].es.ref_count);
ice_free(hw, hw->blk[i].es.written);
+ ice_free(hw, hw->blk[i].es.mask_ena);
}
LIST_FOR_EACH_ENTRY_SAFE(r, rt, &hw->rss_list_head,
@@ -3097,6 +3523,7 @@ void ice_free_hw_tbls(struct ice_hw *hw)
ice_free(hw, r);
}
ice_destroy_lock(&hw->rss_locks);
+ ice_shutdown_all_prof_masks(hw);
ice_memset(hw->blk, 0, sizeof(hw->blk), ICE_NONDMA_MEM);
}
@@ -3121,6 +3548,7 @@ enum ice_status ice_init_hw_tbls(struct ice_hw *hw)
ice_init_lock(&hw->rss_locks);
INIT_LIST_HEAD(&hw->rss_list_head);
+ ice_init_all_prof_masks(hw);
for (i = 0; i < ICE_BLK_COUNT; i++) {
struct ice_prof_redir *prof_redir = &hw->blk[i].prof_redir;
struct ice_prof_tcam *prof = &hw->blk[i].prof;
@@ -3212,7 +3640,8 @@ enum ice_status ice_init_hw_tbls(struct ice_hw *hw)
es->written = (u8 *)
ice_calloc(hw, es->count, sizeof(*es->written));
-
+ es->mask_ena = (u32 *)
+ ice_calloc(hw, es->count, sizeof(*es->mask_ena));
if (!es->ref_count)
goto err;
}
@@ -3854,6 +4283,115 @@ ice_update_fd_swap(struct ice_hw *hw, u16 prof_id, struct ice_fv_word *es)
}
/**
+ * ice_add_prof_with_mask - add profile
+ * @hw: pointer to the HW struct
+ * @blk: hardware block
+ * @id: profile tracking ID
+ * @ptypes: array of bitmaps indicating ptypes (ICE_FLOW_PTYPE_MAX bits)
+ * @es: extraction sequence (length of array is determined by the block)
+ * @masks: extraction sequence (length of array is determined by the block)
+ *
+ * This function registers a profile, which matches a set of PTYPES with a
+ * particular extraction sequence. While the hardware profile is allocated
+ * it will not be written until the first call to ice_add_flow that specifies
+ * the ID value used here.
+ */
+enum ice_status
+ice_add_prof_with_mask(struct ice_hw *hw, enum ice_block blk, u64 id,
+ u8 ptypes[], struct ice_fv_word *es, u16 *masks)
+{
+ u32 bytes = DIVIDE_AND_ROUND_UP(ICE_FLOW_PTYPE_MAX, BITS_PER_BYTE);
+ struct ice_prof_map *prof;
+ enum ice_status status;
+ u32 byte = 0;
+ u8 prof_id;
+
+ ice_acquire_lock(&hw->blk[blk].es.prof_map_lock);
+
+ /* search for existing profile */
+ status = ice_find_prof_id_with_mask(hw, blk, es, masks, &prof_id);
+ if (status) {
+ /* allocate profile ID */
+ status = ice_alloc_prof_id(hw, blk, &prof_id);
+ if (status)
+ goto err_ice_add_prof;
+ if (blk == ICE_BLK_FD) {
+ /* For Flow Director block, the extraction sequence may
+ * need to be altered in the case where there are paired
+ * fields that have no match. This is necessary because
+ * for Flow Director, src and dest fields need to paired
+ * for filter programming and these values are swapped
+ * during Tx.
+ */
+ status = ice_update_fd_swap(hw, prof_id, es);
+ if (status)
+ goto err_ice_add_prof;
+ }
+ status = ice_update_prof_masking(hw, blk, prof_id, es, masks);
+ if (status)
+ goto err_ice_add_prof;
+
+ /* and write new es */
+ ice_write_es(hw, blk, prof_id, es);
+ }
+
+ ice_prof_inc_ref(hw, blk, prof_id);
+
+ /* add profile info */
+
+ prof = (struct ice_prof_map *)ice_malloc(hw, sizeof(*prof));
+ if (!prof)
+ goto err_ice_add_prof;
+
+ prof->profile_cookie = id;
+ prof->prof_id = prof_id;
+ prof->ptype_count = 0;
+ prof->context = 0;
+
+ /* build list of ptgs */
+ while (bytes && prof->ptype_count < ICE_MAX_PTYPE_PER_PROFILE) {
+ u32 bit;
+
+ if (!ptypes[byte]) {
+ bytes--;
+ byte++;
+ continue;
+ }
+ /* Examine 8 bits per byte */
+ for (bit = 0; bit < 8; bit++) {
+ if (ptypes[byte] & BIT(bit)) {
+ u16 ptype;
+ u8 m;
+
+ ptype = byte * BITS_PER_BYTE + bit;
+ if (ptype < ICE_FLOW_PTYPE_MAX) {
+ prof->ptype[prof->ptype_count] = ptype;
+
+ if (++prof->ptype_count >=
+ ICE_MAX_PTYPE_PER_PROFILE)
+ break;
+ }
+
+ /* nothing left in byte, then exit */
+ m = ~((1 << (bit + 1)) - 1);
+ if (!(ptypes[byte] & m))
+ break;
+ }
+ }
+
+ bytes--;
+ byte++;
+ }
+
+ LIST_ADD(&prof->list, &hw->blk[blk].es.prof_map);
+ status = ICE_SUCCESS;
+
+err_ice_add_prof:
+ ice_release_lock(&hw->blk[blk].es.prof_map_lock);
+ return status;
+}
+
+/**
* ice_add_prof - add profile
* @hw: pointer to the HW struct
* @blk: hardware block
diff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h
index f01dfbb98..6af24653b 100644
--- a/drivers/net/ice/base/ice_flex_pipe.h
+++ b/drivers/net/ice/base/ice_flex_pipe.h
@@ -45,8 +45,13 @@ ice_tunnel_get_type(struct ice_hw *hw, u16 port, enum ice_tunnel_type *type);
enum ice_status
ice_vsig_find_vsi(struct ice_hw *hw, enum ice_block blk, u16 vsi, u16 *vsig);
enum ice_status
+ice_add_prof_with_mask(struct ice_hw *hw, enum ice_block blk, u64 id,
+ u8 ptypes[], struct ice_fv_word *es, u16 *masks);
+enum ice_status
ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],
struct ice_fv_word *es);
+void ice_init_all_prof_masks(struct ice_hw *hw);
+void ice_shutdown_all_prof_masks(struct ice_hw *hw);
struct ice_prof_map *
ice_search_prof_id(struct ice_hw *hw, enum ice_block blk, u64 id);
enum ice_status
diff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h
index 837e1e872..634897a28 100644
--- a/drivers/net/ice/base/ice_flex_type.h
+++ b/drivers/net/ice/base/ice_flex_type.h
@@ -490,6 +490,7 @@ struct ice_es {
u16 count;
u16 fvw;
u16 *ref_count;
+ u32 *mask_ena;
struct LIST_HEAD_TYPE prof_map;
struct ice_fv_word *t;
struct ice_lock prof_map_lock; /* protect access to profiles list */
@@ -654,6 +655,21 @@ struct ice_prof_redir {
u16 count;
};
+struct ice_mask {
+ u16 mask; /* 16-bit mask */
+ u16 idx; /* index */
+ u16 ref; /* reference count */
+ u8 in_use; /* non-zero if used */
+};
+
+struct ice_masks {
+ struct ice_lock lock; /* lock to protect this structure */
+ u16 first; /* first mask owned by the PF */
+ u16 count; /* number of masks owned by the PF */
+#define ICE_PROFILE_MASK_COUNT 32
+ struct ice_mask masks[ICE_PROFILE_MASK_COUNT];
+};
+
/* Tables per block */
struct ice_blk_info {
struct ice_xlt1 xlt1;
@@ -661,6 +677,7 @@ struct ice_blk_info {
struct ice_prof_tcam prof;
struct ice_prof_redir prof_redir;
struct ice_es es;
+ struct ice_masks masks;
u8 overwrite; /* set to true to allow overwrite of table entries */
u8 is_list_init;
};
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index fb9041b3e..1530a72cc 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -34,12 +34,21 @@ struct ice_flow_field_info {
enum ice_flow_seg_hdr hdr;
s16 off; /* Offset from start of a protocol header, in bits */
u16 size; /* Size of fields in bits */
+ u16 mask; /* 16-bit mask for field */
};
#define ICE_FLOW_FLD_INFO(_hdr, _offset_bytes, _size_bytes) { \
.hdr = _hdr, \
- .off = _offset_bytes * BITS_PER_BYTE, \
- .size = _size_bytes * BITS_PER_BYTE, \
+ .off = (_offset_bytes) * BITS_PER_BYTE, \
+ .size = (_size_bytes) * BITS_PER_BYTE, \
+ .mask = 0, \
+}
+
+#define ICE_FLOW_FLD_INFO_MSK(_hdr, _offset_bytes, _size_bytes, _mask) { \
+ .hdr = _hdr, \
+ .off = (_offset_bytes) * BITS_PER_BYTE, \
+ .size = (_size_bytes) * BITS_PER_BYTE, \
+ .mask = _mask, \
}
/* Table containing properties of supported protocol header fields */
@@ -292,7 +301,7 @@ struct ice_flow_prof_params {
* This will give us the direction flags.
*/
struct ice_fv_word es[ICE_MAX_FV_WORDS];
-
+ u16 mask[ICE_MAX_FV_WORDS];
ice_declare_bitmap(ptypes, ICE_FLOW_PTYPE_MAX);
};
@@ -544,6 +553,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,
struct ice_flow_fld_info *flds;
u16 cnt, ese_bits, i;
s16 adj = 0;
+ u16 mask;
u16 off;
flds = params->prof->segs[seg].fields;
@@ -652,6 +662,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,
/* Fill in the extraction sequence entries needed for this field */
off = flds[fld].xtrct.off;
+ mask = ice_flds_info[fld].mask;
for (i = 0; i < cnt; i++) {
/* Only consume an extraction sequence entry if there is no
* sibling field associated with this field or the sibling entry
@@ -676,6 +687,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,
params->es[idx].prot_id = prot_id;
params->es[idx].off = off;
+ params->mask[idx] = mask;
params->es_cnt++;
}
@@ -1048,7 +1060,8 @@ ice_flow_add_prof_sync(struct ice_hw *hw, enum ice_block blk,
}
/* Add a HW profile for this flow profile */
- status = ice_add_prof(hw, blk, prof_id, (u8 *)params.ptypes, params.es);
+ status = ice_add_prof_with_mask(hw, blk, prof_id, (u8 *)params.ptypes,
+ params.es, params.mask);
if (status) {
ice_debug(hw, ICE_DBG_FLOW, "Error adding a HW flow profile\n");
goto out;
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 18/63] net/ice/base: resolve static analysis issues
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (16 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 17/63] net/ice/base: enable masking for RSS and FD field vectors Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 19/63] net/ice/base: fix memory leak issue Qi Zhang
` (45 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, stable, Dan Nowlin, Paul M Stillwell Jr
Coverity complains first_free can be -1 resulting in a negative shift left
when k equals 0; i.e. the expression 1 << (first_free - k). Fix this by
explicitly checking for this case.
Cc: stable@dpdk.org
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flex_pipe.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index 29888df76..73362c909 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -4200,7 +4200,7 @@ ice_update_fd_swap(struct ice_hw *hw, u16 prof_id, struct ice_fv_word *es)
index = i + 1;
/* check for room */
- if (first_free + 1 < ice_fd_pairs[index].count)
+ if (first_free + 1 < (s8)ice_fd_pairs[index].count)
return ICE_ERR_MAX_LIMIT;
/* place in extraction sequence */
@@ -4210,6 +4210,9 @@ ice_update_fd_swap(struct ice_hw *hw, u16 prof_id, struct ice_fv_word *es)
es[first_free - k].off =
ice_fd_pairs[index].off + (k * 2);
+ if (k > first_free)
+ return ICE_ERR_OUT_OF_RANGE;
+
/* keep track of non-relevant fields */
mask_sel |= 1 << (first_free - k);
}
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 19/63] net/ice/base: fix memory leak issue
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (17 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 18/63] net/ice/base: resolve static analysis issues Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 20/63] net/ice/base: check root pointer for validity Qi Zhang
` (44 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, stable, Paul M Stillwell Jr
Need to free new ice_vsig_prof if no valid ptype can be found.
Fixes: d935fb5bb091 ("net/ice/base: fix packet type size")
Cc: stable@dpdk.org
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flex_pipe.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index 73362c909..7daaf10b0 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -4918,8 +4918,10 @@ ice_add_prof_to_lst(struct ice_hw *hw, enum ice_block blk,
p->tcam[i].prof_id = map->prof_id;
p->tcam[i].tcam_idx = ICE_INVALID_TCAM;
- if (ice_ptg_find_ptype(hw, blk, map->ptype[i], &ptg))
+ if (ice_ptg_find_ptype(hw, blk, map->ptype[i], &ptg)) {
+ ice_free(hw, p);
return ICE_ERR_CFG;
+ }
p->tcam[i].ptg = ptg;
}
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 20/63] net/ice/base: check root pointer for validity
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (18 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 19/63] net/ice/base: fix memory leak issue Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 21/63] net/ice/base: fix type-mismatch Qi Zhang
` (43 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Anirudh Venkataramanan, Paul M Stillwell Jr
ice_sched_get_tc_node uses pi->root without checking for NULL. Add a
check to prevent NULL pointer dereference.
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_sched.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index d16f256c9..84a033f1c 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -284,7 +284,7 @@ struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc)
{
u8 i;
- if (!pi)
+ if (!pi || !pi->root)
return NULL;
for (i = 0; i < pi->root->num_children; i++)
if (pi->root->children[i]->tc_num == tc)
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 21/63] net/ice/base: fix type-mismatch
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (19 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 20/63] net/ice/base: check root pointer for validity Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 22/63] net/ice/base: correct overrun Coverty hit Qi Zhang
` (42 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, stable, Jeb Cramer, Paul M Stillwell Jr
The iterators are u8, but the values being compared against are u16s.
It may not ever be the case that the comparison is against a value
larger than the upper bound of the smaller type, but code analysis tools
don't know that.
Fixes: 93e84b1bfc92 ("net/ice/base: add basic Tx scheduler")
Cc: stable@dpdk.org
Signed-off-by: Jeb Cramer <jeb.j.cramer@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_sched.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index 84a033f1c..01c8defae 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -735,7 +735,7 @@ ice_sched_del_rl_profile(struct ice_hw *hw,
*/
static void ice_sched_clear_rl_prof(struct ice_port_info *pi)
{
- u8 ln;
+ u16 ln;
for (ln = 0; ln < pi->hw->num_tx_sched_layers; ln++) {
struct ice_aqc_rl_profile_info *rl_prof_elem;
@@ -2181,12 +2181,11 @@ static enum ice_status
ice_sched_move_nodes(struct ice_port_info *pi, struct ice_sched_node *parent,
u16 num_items, u32 *list)
{
+ enum ice_status status = ICE_SUCCESS;
struct ice_aqc_move_elem *buf;
struct ice_sched_node *node;
- enum ice_status status = ICE_SUCCESS;
+ u16 i, grps_movd = 0;
struct ice_hw *hw;
- u16 grps_movd = 0;
- u8 i;
hw = pi->hw;
@@ -2802,7 +2801,7 @@ ice_sched_assoc_vsi_to_agg(struct ice_port_info *pi, u32 agg_id,
*/
static void ice_sched_rm_unused_rl_prof(struct ice_port_info *pi)
{
- u8 ln;
+ u16 ln;
for (ln = 0; ln < pi->hw->num_tx_sched_layers; ln++) {
struct ice_aqc_rl_profile_info *rl_prof_elem;
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 22/63] net/ice/base: correct overrun Coverty hit
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (20 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 21/63] net/ice/base: fix type-mismatch Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 23/63] net/ice/base: update Boot Configuration Section read of NVM Qi Zhang
` (41 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, stable, Paul M Stillwell Jr
Added boundary check for layer_num in function ice_sched_rm_rl_profile,
and ice_sched_add_rl_profile.
Cc: stable@dpdk.org
Tarun Singh <tarun.k.singh@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_sched.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index 01c8defae..1cfc3bc20 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -3799,10 +3799,12 @@ ice_sched_add_rl_profile(struct ice_port_info *pi,
struct ice_aqc_rl_profile_generic_elem *buf;
struct ice_aqc_rl_profile_info *rl_prof_elem;
u16 profiles_added = 0, num_profiles = 1;
- enum ice_status status = ICE_ERR_PARAM;
+ enum ice_status status;
struct ice_hw *hw;
u8 profile_type;
+ if (layer_num >= ICE_AQC_TOPO_MAX_LEVEL_NUM)
+ return NULL;
switch (rl_type) {
case ICE_MIN_BW:
profile_type = ICE_AQC_RL_PROFILE_TYPE_CIR;
@@ -4049,6 +4051,8 @@ ice_sched_rm_rl_profile(struct ice_port_info *pi, u8 layer_num, u8 profile_type,
struct ice_aqc_rl_profile_info *rl_prof_elem;
enum ice_status status = ICE_SUCCESS;
+ if (layer_num >= ICE_AQC_TOPO_MAX_LEVEL_NUM)
+ return ICE_ERR_PARAM;
/* Check the existing list for RL profile */
LIST_FOR_EACH_ENTRY(rl_prof_elem, &pi->rl_prof_list[layer_num],
ice_aqc_rl_profile_info, list_entry)
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 23/63] net/ice/base: update Boot Configuration Section read of NVM
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (21 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 22/63] net/ice/base: correct overrun Coverty hit Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 24/63] net/ice/base: add support for NVM access commands Qi Zhang
` (40 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Md Fahad Iqbal Polash, Paul M Stillwell Jr
Boot Configuration Section Block has been moved to the
Preserved Field Area (PFA) of NVM. So, this patch updates
the NVM reads that involve Boot Configuration Section.
Signed-off-by: Md Fahad Iqbal Polash <md.fahad.iqbal.polash@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_devids.h | 6 +++
drivers/net/ice/base/ice_nvm.c | 39 +++++++++++++-----
drivers/net/ice/base/ice_nvm.h | 87 +++++++++++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_type.h | 4 +-
4 files changed, 124 insertions(+), 12 deletions(-)
create mode 100644 drivers/net/ice/base/ice_nvm.h
diff --git a/drivers/net/ice/base/ice_devids.h b/drivers/net/ice/base/ice_devids.h
index 5f1ac0422..c9a567fb1 100644
--- a/drivers/net/ice/base/ice_devids.h
+++ b/drivers/net/ice/base/ice_devids.h
@@ -13,5 +13,11 @@
#define ICE_DEV_ID_E810C_QSFP 0x1592
/* Intel(R) Ethernet Controller E810-C for SFP */
#define ICE_DEV_ID_E810C_SFP 0x1593
+/* Intel(R) Ethernet Connection C822N for backplane */
+#define ICE_DEV_ID_C822N_BACKPLANE 0x1890
+/* Intel(R) Ethernet Connection C822N for QSFP */
+#define ICE_DEV_ID_C822N_QSFP 0x1891
+/* Intel(R) Ethernet Connection C822N for SFP */
+#define ICE_DEV_ID_C822N_SFP 0x1892
#endif /* _ICE_DEVIDS_H_ */
diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c
index c0f9e353e..95a6c9ab6 100644
--- a/drivers/net/ice/base/ice_nvm.c
+++ b/drivers/net/ice/base/ice_nvm.c
@@ -263,9 +263,9 @@ enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
enum ice_status ice_init_nvm(struct ice_hw *hw)
{
struct ice_nvm_info *nvm = &hw->nvm;
- u16 oem_hi, oem_lo, cfg_ptr;
+ u16 oem_hi, oem_lo, boot_cfg_tlv, boot_cfg_tlv_len;
u16 eetrack_lo, eetrack_hi;
- enum ice_status status = ICE_SUCCESS;
+ enum ice_status status;
u32 fla, gens_stat;
u8 sr_size;
@@ -284,12 +284,12 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)
fla = rd32(hw, GLNVM_FLA);
if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */
nvm->blank_nvm_mode = false;
- } else { /* Blank programming mode */
+ } else {
+ /* Blank programming mode */
nvm->blank_nvm_mode = true;
- status = ICE_ERR_NVM_BLANK_MODE;
ice_debug(hw, ICE_DBG_NVM,
"NVM init error: unsupported blank mode.\n");
- return status;
+ return ICE_ERR_NVM_BLANK_MODE;
}
status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &nvm->ver);
@@ -312,19 +312,37 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)
nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
- status = ice_read_sr_word(hw, ICE_SR_BOOT_CFG_PTR, &cfg_ptr);
+ /* the following devices do not have boot_cfg_tlv yet */
+ if (hw->device_id == ICE_DEV_ID_C822N_BACKPLANE ||
+ hw->device_id == ICE_DEV_ID_C822N_QSFP ||
+ hw->device_id == ICE_DEV_ID_C822N_SFP)
+ return status;
+
+ status = ice_get_pfa_module_tlv(hw, &boot_cfg_tlv, &boot_cfg_tlv_len,
+ ICE_SR_BOOT_CFG_PTR);
if (status) {
- ice_debug(hw, ICE_DBG_INIT, "Failed to read BOOT_CONFIG_PTR.\n");
+ ice_debug(hw, ICE_DBG_INIT,
+ "Failed to read Boot Configuration Block TLV.\n");
return status;
}
- status = ice_read_sr_word(hw, (cfg_ptr + ICE_NVM_OEM_VER_OFF), &oem_hi);
+ /* Boot Configuration Block must have length at least 2 words
+ * (Combo Image Version High and Combo Image Version Low)
+ */
+ if (boot_cfg_tlv_len < 2) {
+ ice_debug(hw, ICE_DBG_INIT,
+ "Invalid Boot Configuration Block TLV size.\n");
+ return ICE_ERR_INVAL_SIZE;
+ }
+
+ status = ice_read_sr_word(hw, (boot_cfg_tlv + ICE_NVM_OEM_VER_OFF),
+ &oem_hi);
if (status) {
ice_debug(hw, ICE_DBG_INIT, "Failed to read OEM_VER hi.\n");
return status;
}
- status = ice_read_sr_word(hw, (cfg_ptr + (ICE_NVM_OEM_VER_OFF + 1)),
+ status = ice_read_sr_word(hw, (boot_cfg_tlv + ICE_NVM_OEM_VER_OFF + 1),
&oem_lo);
if (status) {
ice_debug(hw, ICE_DBG_INIT, "Failed to read OEM_VER lo.\n");
@@ -332,7 +350,8 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)
}
nvm->oem_ver = ((u32)oem_hi << 16) | oem_lo;
- return status;
+
+ return ICE_SUCCESS;
}
diff --git a/drivers/net/ice/base/ice_nvm.h b/drivers/net/ice/base/ice_nvm.h
new file mode 100644
index 000000000..da76b2674
--- /dev/null
+++ b/drivers/net/ice/base/ice_nvm.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2001-2019
+ */
+
+#ifndef _ICE_NVM_H_
+#define _ICE_NVM_H_
+
+#define ICE_NVM_CMD_READ 0x0000000B
+#define ICE_NVM_CMD_WRITE 0x0000000C
+
+/* NVM Access config bits */
+#define ICE_NVM_CFG_MODULE_M MAKEMASK(0xFF, 0)
+#define ICE_NVM_CFG_MODULE_S 0
+#define ICE_NVM_CFG_FLAGS_M MAKEMASK(0xF, 8)
+#define ICE_NVM_CFG_FLAGS_S 8
+#define ICE_NVM_CFG_EXT_FLAGS_M MAKEMASK(0xF, 12)
+#define ICE_NVM_CFG_EXT_FLAGS_S 12
+#define ICE_NVM_CFG_ADAPTER_INFO_M MAKEMASK(0xFFFF, 16)
+#define ICE_NVM_CFG_ADAPTER_INFO_S 16
+
+/* NVM Read Get Driver Features */
+#define ICE_NVM_GET_FEATURES_MODULE 0xE
+#define ICE_NVM_GET_FEATURES_FLAGS 0xF
+
+/* NVM Read/Write Mapped Space */
+#define ICE_NVM_REG_RW_MODULE 0x0
+#define ICE_NVM_REG_RW_FLAGS 0x1
+
+#define ICE_NVM_ACCESS_MAJOR_VER 0
+#define ICE_NVM_ACCESS_MINOR_VER 5
+
+/* NVM Access feature flags. Other bits in the features field are reserved and
+ * should be set to zero when reporting the ice_nvm_features structure.
+ */
+#define ICE_NVM_FEATURES_0_REG_ACCESS BIT(1)
+
+/* NVM Access Features */
+struct ice_nvm_features {
+ u8 major; /* Major version (informational only) */
+ u8 minor; /* Minor version (informational only) */
+ u16 size; /* size of ice_nvm_features structure */
+ u8 features[12]; /* Array of feature bits */
+};
+
+/* NVM Access command */
+struct ice_nvm_access_cmd {
+ u32 command; /* NVM command: READ or WRITE */
+ u32 config; /* NVM command configuration */
+ u32 offset; /* offset to read/write, in bytes */
+ u32 data_size; /* size of data field, in bytes */
+};
+
+/* NVM Access data */
+union ice_nvm_access_data {
+ u32 regval; /* Storage for register value */
+ struct ice_nvm_features drv_features; /* NVM features */
+};
+
+/* NVM Access registers */
+#define GL_HIDA(_i) (0x00082000 + ((_i) * 4))
+#define GL_HIBA(_i) (0x00081000 + ((_i) * 4))
+#define GL_HICR 0x00082040
+#define GL_HICR_EN 0x00082044
+#define GLGEN_CSR_DEBUG_C 0x00075750
+#define GLPCI_LBARCTRL 0x0009DE74
+#define GLNVM_GENS 0x000B6100
+#define GLNVM_FLA 0x000B6108
+
+#define ICE_NVM_ACCESS_GL_HIDA_MAX 15
+#define ICE_NVM_ACCESS_GL_HIBA_MAX 1023
+
+u32 ice_nvm_access_get_module(struct ice_nvm_access_cmd *cmd);
+u32 ice_nvm_access_get_flags(struct ice_nvm_access_cmd *cmd);
+u32 ice_nvm_access_get_adapter(struct ice_nvm_access_cmd *cmd);
+enum ice_status
+ice_nvm_access_read(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
+ union ice_nvm_access_data *data);
+enum ice_status
+ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
+ union ice_nvm_access_data *data);
+enum ice_status
+ice_nvm_access_get_features(struct ice_nvm_access_cmd *cmd,
+ union ice_nvm_access_data *data);
+enum ice_status
+ice_handle_nvm_access(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
+ union ice_nvm_access_data *data);
+#endif /* _ICE_NVM_H_ */
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 79d7bb1dd..dc041760d 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -916,9 +916,9 @@ enum ice_sw_fwd_act_type {
#define ICE_SR_MNG_CFG_PTR 0x0E
#define ICE_SR_EMP_MODULE_PTR 0x0F
#define ICE_SR_PBA_BLOCK_PTR 0x16
-#define ICE_SR_BOOT_CFG_PTR 0x17
+#define ICE_SR_BOOT_CFG_PTR 0x132
#define ICE_SR_NVM_WOL_CFG 0x19
-#define ICE_NVM_OEM_VER_OFF 0x83
+#define ICE_NVM_OEM_VER_OFF 0x02
#define ICE_SR_NVM_DEV_STARTER_VER 0x18
#define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27
#define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 24/63] net/ice/base: add support for NVM access commands
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (22 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 23/63] net/ice/base: update Boot Configuration Section read of NVM Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 25/63] net/ice/base: add support for GTP and PPPoE protocols Qi Zhang
` (39 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Jacob Keller, Paul M Stillwell Jr
Add a new structure, ice_nvm_access, used to request access to read or
write certain NVM related registers.
The structure is used by NVM Update to request read or write of specific
NVM registers in order to perform updates.
Additionally, there is a command to request the driver "features"
structure which represents data about what features of the NVM access
interface the driver supports.
Implement ice_handle_nvm_access to parse the access request and perform
the necessary function.
This function verifies that the access request is valid. If so, the
function will delegate to perform the register read, register write, or
copying of the driver ice_nvm_features structure.
If the request is invalid, the function will report a suitable error
codition that can be propagated out.
Only a subset of registers is accessible, and all other registers will
be rejected with ICE_ERR_OUT_OF_RANGE.
When reading, the contents of the variable sized data buffer will be
used as storage for returning the register value. When writing, the
contents will be used as input for the value to write to the register.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.h | 1 +
drivers/net/ice/base/ice_nvm.c | 237 ++++++++++++++++++++++++++++++++++++++
2 files changed, 238 insertions(+)
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index 1fd256a42..a55f7eeba 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -6,6 +6,7 @@
#define _ICE_COMMON_H_
#include "ice_type.h"
+#include "ice_nvm.h"
#include "ice_flex_pipe.h"
#include "ice_switch.h"
#include "ice_fdir.h"
diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c
index 95a6c9ab6..66cfec641 100644
--- a/drivers/net/ice/base/ice_nvm.c
+++ b/drivers/net/ice/base/ice_nvm.c
@@ -411,3 +411,240 @@ enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw)
return status;
}
+
+/**
+ * ice_nvm_access_get_features - Return the NVM access features structure
+ * @cmd: NVM access command to process
+ * @data: storage for the driver NVM features
+ *
+ * Fill in the data section of the NVM access request with a copy of the NVM
+ * features structure.
+ */
+enum ice_status
+ice_nvm_access_get_features(struct ice_nvm_access_cmd *cmd,
+ union ice_nvm_access_data *data)
+{
+ /* The provided data_size must be at least as large as our NVM
+ * features structure. A larger size should not be treated as an
+ * error, to allow future extensions to to the features structure to
+ * work on older drivers.
+ */
+ if (cmd->data_size < sizeof(struct ice_nvm_features))
+ return ICE_ERR_NO_MEMORY;
+
+ /* Initialize the data buffer to zeros */
+ ice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);
+
+ /* Fill in the features data */
+ data->drv_features.major = ICE_NVM_ACCESS_MAJOR_VER;
+ data->drv_features.minor = ICE_NVM_ACCESS_MINOR_VER;
+ data->drv_features.size = sizeof(struct ice_nvm_features);
+ data->drv_features.features[0] = ICE_NVM_FEATURES_0_REG_ACCESS;
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_nvm_access_get_module - Helper function to read module value
+ * @cmd: NVM access command structure
+ *
+ * Reads the module value out of the NVM access config field.
+ */
+u32 ice_nvm_access_get_module(struct ice_nvm_access_cmd *cmd)
+{
+ return ((cmd->config & ICE_NVM_CFG_MODULE_M) >> ICE_NVM_CFG_MODULE_S);
+}
+
+/**
+ * ice_nvm_access_get_flags - Helper function to read flags value
+ * @cmd: NVM access command structure
+ *
+ * Reads the flags value out of the NVM access config field.
+ */
+u32 ice_nvm_access_get_flags(struct ice_nvm_access_cmd *cmd)
+{
+ return ((cmd->config & ICE_NVM_CFG_FLAGS_M) >> ICE_NVM_CFG_FLAGS_S);
+}
+
+/**
+ * ice_nvm_access_get_adapter - Helper function to read adapter info
+ * @cmd: NVM access command structure
+ *
+ * Read the adapter info value out of the NVM access config field.
+ */
+u32 ice_nvm_access_get_adapter(struct ice_nvm_access_cmd *cmd)
+{
+ return ((cmd->config & ICE_NVM_CFG_ADAPTER_INFO_M) >>
+ ICE_NVM_CFG_ADAPTER_INFO_S);
+}
+
+/**
+ * ice_validate_nvm_rw_reg - Check than an NVM access request is valid
+ * @cmd: NVM access command structure
+ *
+ * Validates that an NVM access structure is request to read or write a valid
+ * register offset. First validates that the module and flags are correct, and
+ * then ensures that the register offset is one of the accepted registers.
+ */
+static enum ice_status
+ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd *cmd)
+{
+ u32 module, flags, offset;
+ u16 i;
+
+ module = ice_nvm_access_get_module(cmd);
+ flags = ice_nvm_access_get_flags(cmd);
+ offset = cmd->offset;
+
+ /* Make sure the module and flags indicate a read/write request */
+ if (module != ICE_NVM_REG_RW_MODULE ||
+ flags != ICE_NVM_REG_RW_FLAGS ||
+ cmd->data_size != FIELD_SIZEOF(union ice_nvm_access_data, regval))
+ return ICE_ERR_PARAM;
+
+ switch (offset) {
+ case GL_HICR:
+ case GL_HICR_EN: /* Note, this register is read only */
+ case GL_FWSTS:
+ case GL_MNG_FWSM:
+ case GLGEN_CSR_DEBUG_C:
+ case GLPCI_LBARCTRL:
+ case GLNVM_GENS:
+ case GLNVM_FLA:
+ case PF_FUNC_RID:
+ return ICE_SUCCESS;
+ default:
+ break;
+ }
+
+ for (i = 0; i <= ICE_NVM_ACCESS_GL_HIDA_MAX; i++)
+ if (offset == (u32)GL_HIDA(i))
+ return ICE_SUCCESS;
+
+ for (i = 0; i <= ICE_NVM_ACCESS_GL_HIBA_MAX; i++)
+ if (offset == (u32)GL_HIBA(i))
+ return ICE_SUCCESS;
+
+ /* All other register offsets are not valid */
+ return ICE_ERR_OUT_OF_RANGE;
+}
+
+/**
+ * ice_nvm_access_read - Handle an NVM read request
+ * @hw: pointer to the HW struct
+ * @cmd: NVM access command to process
+ * @data: storage for the register value read
+ *
+ * Process an NVM access request to read a register.
+ */
+enum ice_status
+ice_nvm_access_read(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
+ union ice_nvm_access_data *data)
+{
+ enum ice_status status;
+
+ ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
+
+ /* Always initialize the output data, even on failure */
+ ice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);
+
+ /* Make sure this is a valid read/write access request */
+ status = ice_validate_nvm_rw_reg(cmd);
+ if (status)
+ return status;
+
+ ice_debug(hw, ICE_DBG_NVM, "NVM access: reading register %08x\n",
+ cmd->offset);
+
+ /* Read the register and store the contents in the data field */
+ data->regval = rd32(hw, cmd->offset);
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_nvm_access_write - Handle an NVM write request
+ * @hw: pointer to the HW struct
+ * @cmd: NVM access command to process
+ * @data: NVM access data to write
+ *
+ * Process an NVM access request to write a register.
+ */
+enum ice_status
+ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
+ union ice_nvm_access_data *data)
+{
+ enum ice_status status;
+
+ ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
+
+ /* Make sure this is a valid read/write access request */
+ status = ice_validate_nvm_rw_reg(cmd);
+ if (status)
+ return status;
+
+ /* The HICR_EN register is read-only */
+ if (cmd->offset == GL_HICR_EN)
+ return ICE_ERR_OUT_OF_RANGE;
+
+ ice_debug(hw, ICE_DBG_NVM,
+ "NVM access: writing register %08x with value %08x\n",
+ cmd->offset, data->regval);
+
+ /* Write the data field to the specified register */
+ wr32(hw, cmd->offset, data->regval);
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_handle_nvm_access - Handle an NVM access request
+ * @hw: pointer to the HW struct
+ * @cmd: NVM access command info
+ * @data: pointer to read or return data
+ *
+ * Process an NVM access request. Read the command structure information and
+ * determine if it is valid. If not, report an error indicating the command
+ * was invalid.
+ *
+ * For valid commands, perform the necessary function, copying the data into
+ * the provided data buffer.
+ */
+enum ice_status
+ice_handle_nvm_access(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
+ union ice_nvm_access_data *data)
+{
+ u32 module, flags, adapter_info;
+
+ ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
+
+ /* Extended flags are currently reserved and must be zero */
+ if ((cmd->config & ICE_NVM_CFG_EXT_FLAGS_M) != 0)
+ return ICE_ERR_PARAM;
+
+ /* Adapter info must match the HW device ID */
+ adapter_info = ice_nvm_access_get_adapter(cmd);
+ if (adapter_info != hw->device_id)
+ return ICE_ERR_PARAM;
+
+ switch (cmd->command) {
+ case ICE_NVM_CMD_READ:
+ module = ice_nvm_access_get_module(cmd);
+ flags = ice_nvm_access_get_flags(cmd);
+
+ /* Getting the driver's NVM features structure shares the same
+ * command type as reading a register. Read the config field
+ * to determine if this is a request to get features.
+ */
+ if (module == ICE_NVM_GET_FEATURES_MODULE &&
+ flags == ICE_NVM_GET_FEATURES_FLAGS &&
+ cmd->offset == 0)
+ return ice_nvm_access_get_features(cmd, data);
+ else
+ return ice_nvm_access_read(hw, cmd, data);
+ case ICE_NVM_CMD_WRITE:
+ return ice_nvm_access_write(hw, cmd, data);
+ default:
+ return ICE_ERR_PARAM;
+ }
+}
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 25/63] net/ice/base: add support for GTP and PPPoE protocols
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (23 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 24/63] net/ice/base: add support for NVM access commands Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 26/63] net/ice/base: add locks for flow functions Qi Zhang
` (38 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
Added switch protocol segments for both GTP and PPPOE protocols.
Added RSS protocol segments for both GTP and PPPOE protocols.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flow.c | 105 ++++++++++++++++++++++++++-----
drivers/net/ice/base/ice_flow.h | 61 ++++++++++++++----
drivers/net/ice/base/ice_protocol_type.h | 33 +++++++++-
drivers/net/ice/base/ice_switch.c | 79 ++++++++++++++++++++++-
4 files changed, 251 insertions(+), 27 deletions(-)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 1530a72cc..0f52b3379 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -19,6 +19,8 @@
#define ICE_FLOW_FLD_SZ_ICMP_CODE 1
#define ICE_FLOW_FLD_SZ_ARP_OPER 2
#define ICE_FLOW_FLD_SZ_GRE_KEYID 4
+#define ICE_FLOW_FLD_SZ_GTP_TEID 4
+#define ICE_FLOW_FLD_SZ_PPPOE_SESS_ID 2
/* Protocol header fields are extracted at the word boundaries as word-sized
* values. Specify the displacement value of some non-word-aligned fields needed
@@ -115,6 +117,23 @@ struct ice_flow_field_info ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = {
/* GRE */
/* ICE_FLOW_FIELD_IDX_GRE_KEYID */
ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GRE, 12, ICE_FLOW_FLD_SZ_GRE_KEYID),
+ /* GTP */
+ /* ICE_FLOW_FIELD_IDX_GTPC_TEID */
+ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GTPC_TEID, 12,
+ ICE_FLOW_FLD_SZ_GTP_TEID),
+ /* ICE_FLOW_FIELD_IDX_GTPU_IP_TEID */
+ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GTPU_IP, 12,
+ ICE_FLOW_FLD_SZ_GTP_TEID),
+ /* ICE_FLOW_FIELD_IDX_GTPU_UP_TEID */
+ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GTPU_UP, 12,
+ ICE_FLOW_FLD_SZ_GTP_TEID),
+ /* ICE_FLOW_FIELD_IDX_GTPU_DWN_TEID */
+ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GTPU_DWN, 12,
+ ICE_FLOW_FLD_SZ_GTP_TEID),
+ /* PPPOE */
+ /* ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID */
+ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_PPPOE, 2,
+ ICE_FLOW_FLD_SZ_PPPOE_SESS_ID),
};
/* Bitmaps indicating relevant packet types for a particular protocol header
@@ -290,6 +309,42 @@ static const u32 ice_ptypes_mac_il[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
+/* Packet types for GTPC */
+static const u32 ice_ptypes_gtpc[] = {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000180, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+/* Packet types for GTPC with TEID */
+static const u32 ice_ptypes_gtpc_tid[] = {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000060, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+/* Packet types for GTPU */
+static const u32 ice_ptypes_gtpu[] = {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x7FFFF800, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
/* Manage parameters and info. used during the creation of a flow profile */
struct ice_flow_prof_params {
enum ice_block blk;
@@ -317,10 +372,13 @@ static bool ice_is_pow2(u64 val)
#define ICE_FLOW_SEG_HDRS_L2_MASK \
(ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN)
#define ICE_FLOW_SEG_HDRS_L3_MASK \
- (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_ARP)
+ (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6 | \
+ ICE_FLOW_SEG_HDR_ARP | ICE_FLOW_SEG_HDR_PPPOE)
#define ICE_FLOW_SEG_HDRS_L4_MASK \
(ICE_FLOW_SEG_HDR_ICMP | ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_UDP | \
- ICE_FLOW_SEG_HDR_SCTP)
+ ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_GTPC | \
+ ICE_FLOW_SEG_HDR_GTPC_TEID | ICE_FLOW_SEG_HDR_GTPU_IP | \
+ ICE_FLOW_SEG_HDR_GTPU_UP | ICE_FLOW_SEG_HDR_GTPU_DWN)
/**
* ice_flow_val_hdrs - validates packet segments for valid protocol headers
@@ -431,21 +489,18 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params)
(const ice_bitmap_t *)ice_ptypes_mac_il;
ice_and_bitmap(params->ptypes, params->ptypes, src,
ICE_FLOW_PTYPE_MAX);
- hdrs &= ~ICE_FLOW_SEG_HDR_ETH;
}
if (i && hdrs & ICE_FLOW_SEG_HDR_VLAN) {
src = (const ice_bitmap_t *)ice_ptypes_macvlan_il;
ice_and_bitmap(params->ptypes, params->ptypes, src,
ICE_FLOW_PTYPE_MAX);
- hdrs &= ~ICE_FLOW_SEG_HDR_VLAN;
}
if (!i && hdrs & ICE_FLOW_SEG_HDR_ARP) {
ice_and_bitmap(params->ptypes, params->ptypes,
(const ice_bitmap_t *)ice_ptypes_arp_of,
ICE_FLOW_PTYPE_MAX);
- hdrs &= ~ICE_FLOW_SEG_HDR_ARP;
}
if (hdrs & ICE_FLOW_SEG_HDR_IPV4) {
@@ -453,13 +508,11 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params)
(const ice_bitmap_t *)ice_ptypes_ipv4_il;
ice_and_bitmap(params->ptypes, params->ptypes, src,
ICE_FLOW_PTYPE_MAX);
- hdrs &= ~ICE_FLOW_SEG_HDR_IPV4;
} else if (hdrs & ICE_FLOW_SEG_HDR_IPV6) {
src = !i ? (const ice_bitmap_t *)ice_ptypes_ipv6_ofos :
(const ice_bitmap_t *)ice_ptypes_ipv6_il;
ice_and_bitmap(params->ptypes, params->ptypes, src,
ICE_FLOW_PTYPE_MAX);
- hdrs &= ~ICE_FLOW_SEG_HDR_IPV6;
}
if (hdrs & ICE_FLOW_SEG_HDR_ICMP) {
@@ -467,29 +520,42 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params)
(const ice_bitmap_t *)ice_ptypes_icmp_il;
ice_and_bitmap(params->ptypes, params->ptypes, src,
ICE_FLOW_PTYPE_MAX);
- hdrs &= ~ICE_FLOW_SEG_HDR_ICMP;
} else if (hdrs & ICE_FLOW_SEG_HDR_UDP) {
src = (const ice_bitmap_t *)ice_ptypes_udp_il;
ice_and_bitmap(params->ptypes, params->ptypes, src,
ICE_FLOW_PTYPE_MAX);
- hdrs &= ~ICE_FLOW_SEG_HDR_UDP;
} else if (hdrs & ICE_FLOW_SEG_HDR_TCP) {
ice_and_bitmap(params->ptypes, params->ptypes,
(const ice_bitmap_t *)ice_ptypes_tcp_il,
ICE_FLOW_PTYPE_MAX);
- hdrs &= ~ICE_FLOW_SEG_HDR_TCP;
} else if (hdrs & ICE_FLOW_SEG_HDR_SCTP) {
src = (const ice_bitmap_t *)ice_ptypes_sctp_il;
ice_and_bitmap(params->ptypes, params->ptypes, src,
ICE_FLOW_PTYPE_MAX);
- hdrs &= ~ICE_FLOW_SEG_HDR_SCTP;
} else if (hdrs & ICE_FLOW_SEG_HDR_GRE) {
if (!i) {
src = (const ice_bitmap_t *)ice_ptypes_gre_of;
ice_and_bitmap(params->ptypes, params->ptypes,
src, ICE_FLOW_PTYPE_MAX);
}
- hdrs &= ~ICE_FLOW_SEG_HDR_GRE;
+ } else if (hdrs & ICE_FLOW_SEG_HDR_GTPC) {
+ if (!i) {
+ src = (const ice_bitmap_t *)ice_ptypes_gtpc;
+ ice_and_bitmap(params->ptypes, params->ptypes,
+ src, ICE_FLOW_PTYPE_MAX);
+ }
+ } else if (hdrs & ICE_FLOW_SEG_HDR_GTPC_TEID) {
+ if (!i) {
+ src = (const ice_bitmap_t *)ice_ptypes_gtpc_tid;
+ ice_and_bitmap(params->ptypes, params->ptypes,
+ src, ICE_FLOW_PTYPE_MAX);
+ }
+ } else if (hdrs & ICE_FLOW_SEG_HDR_GTPU) {
+ if (!i) {
+ src = (const ice_bitmap_t *)ice_ptypes_gtpu;
+ ice_and_bitmap(params->ptypes, params->ptypes,
+ src, ICE_FLOW_PTYPE_MAX);
+ }
}
}
@@ -619,6 +685,16 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,
case ICE_FLOW_FIELD_IDX_SCTP_DST_PORT:
prot_id = ICE_PROT_SCTP_IL;
break;
+ case ICE_FLOW_FIELD_IDX_GTPC_TEID:
+ case ICE_FLOW_FIELD_IDX_GTPU_IP_TEID:
+ case ICE_FLOW_FIELD_IDX_GTPU_UP_TEID:
+ case ICE_FLOW_FIELD_IDX_GTPU_DWN_TEID:
+ /* GTP is accessed through UDP OF protocol */
+ prot_id = ICE_PROT_UDP_OF;
+ break;
+ case ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID:
+ prot_id = ICE_PROT_PPPOE;
+ break;
case ICE_FLOW_FIELD_IDX_ARP_SIP:
case ICE_FLOW_FIELD_IDX_ARP_DIP:
case ICE_FLOW_FIELD_IDX_ARP_SHA:
@@ -1601,11 +1677,12 @@ ice_flow_add_fld_raw(struct ice_flow_seg_info *seg, u16 off, u8 len,
}
#define ICE_FLOW_RSS_SEG_HDR_L3_MASKS \
- (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6)
+ (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_PPPOE)
#define ICE_FLOW_RSS_SEG_HDR_L4_MASKS \
(ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_UDP | \
- ICE_FLOW_SEG_HDR_SCTP)
+ ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_GTPC_TEID)
+
#define ICE_FLOW_RSS_SEG_HDR_VAL_MASKS \
(ICE_FLOW_RSS_SEG_HDR_L3_MASKS | \
diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h
index 3a0fd23c4..eb8e1b733 100644
--- a/drivers/net/ice/base/ice_flow.h
+++ b/drivers/net/ice/base/ice_flow.h
@@ -41,6 +41,17 @@
#define ICE_HASH_SCTP_IPV4 (ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_SCTP_PORT)
#define ICE_HASH_SCTP_IPV6 (ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_SCTP_PORT)
+#define ICE_FLOW_HASH_GTP_TEID \
+ (ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_GTPC_TEID))
+
+#define ICE_FLOW_HASH_GTP_IPV4_TEID \
+ (ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_GTP_TEID)
+#define ICE_FLOW_HASH_GTP_IPV6_TEID \
+ (ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_GTP_TEID)
+
+#define ICE_FLOW_HASH_PPPOE_SESS_ID \
+ (ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID))
+
/* Protocol header fields within a packet segment. A segment consists of one or
* more protocol headers that make up a logical group of protocol headers. Each
* logical group of protocol headers encapsulates or is encapsulated using/by
@@ -48,19 +59,37 @@
* VxLAN, etc.
*/
enum ice_flow_seg_hdr {
- ICE_FLOW_SEG_HDR_NONE = 0x00000000,
- ICE_FLOW_SEG_HDR_ETH = 0x00000001,
- ICE_FLOW_SEG_HDR_VLAN = 0x00000002,
- ICE_FLOW_SEG_HDR_IPV4 = 0x00000004,
- ICE_FLOW_SEG_HDR_IPV6 = 0x00000008,
- ICE_FLOW_SEG_HDR_ARP = 0x00000010,
- ICE_FLOW_SEG_HDR_ICMP = 0x00000020,
- ICE_FLOW_SEG_HDR_TCP = 0x00000040,
- ICE_FLOW_SEG_HDR_UDP = 0x00000080,
- ICE_FLOW_SEG_HDR_SCTP = 0x00000100,
- ICE_FLOW_SEG_HDR_GRE = 0x00000200,
+ ICE_FLOW_SEG_HDR_NONE = 0x00000000,
+ ICE_FLOW_SEG_HDR_ETH = 0x00000001,
+ ICE_FLOW_SEG_HDR_VLAN = 0x00000002,
+ ICE_FLOW_SEG_HDR_IPV4 = 0x00000004,
+ ICE_FLOW_SEG_HDR_IPV6 = 0x00000008,
+ ICE_FLOW_SEG_HDR_ARP = 0x00000010,
+ ICE_FLOW_SEG_HDR_ICMP = 0x00000020,
+ ICE_FLOW_SEG_HDR_TCP = 0x00000040,
+ ICE_FLOW_SEG_HDR_UDP = 0x00000080,
+ ICE_FLOW_SEG_HDR_SCTP = 0x00000100,
+ ICE_FLOW_SEG_HDR_GRE = 0x00000200,
+ ICE_FLOW_SEG_HDR_GTPC = 0x00000400,
+ ICE_FLOW_SEG_HDR_GTPC_TEID = 0x00000800,
+ ICE_FLOW_SEG_HDR_GTPU_IP = 0x00001000,
+ ICE_FLOW_SEG_HDR_GTPU_DWN = 0x00002000,
+ ICE_FLOW_SEG_HDR_GTPU_UP = 0x00004000,
+ ICE_FLOW_SEG_HDR_PPPOE = 0x00008000,
};
+/* These segements all have the same PTYPES, but are otherwise distinguished by
+ * the value of the gtp_eh_pdu and gtp_eh_pdu_link flags:
+ *
+ * gtp_eh_pdu gtp_eh_pdu_link
+ * ICE_FLOW_SEG_HDR_GTPU_IP 0 0
+ * ICE_FLOW_SEG_HDR_GTPU_DWN 1 0
+ * ICE_FLOW_SEG_HDR_GTPU_UP 1 1
+ */
+#define ICE_FLOW_SEG_HDR_GTPU (ICE_FLOW_SEG_HDR_GTPU_IP | \
+ ICE_FLOW_SEG_HDR_GTPU_DWN | \
+ ICE_FLOW_SEG_HDR_GTPU_UP)
+
enum ice_flow_field {
/* L2 */
ICE_FLOW_FIELD_IDX_ETH_DA,
@@ -95,6 +124,16 @@ enum ice_flow_field {
ICE_FLOW_FIELD_IDX_ICMP_CODE,
/* GRE */
ICE_FLOW_FIELD_IDX_GRE_KEYID,
+ /* GTPC_TEID */
+ ICE_FLOW_FIELD_IDX_GTPC_TEID,
+ /* GTPU_IP */
+ ICE_FLOW_FIELD_IDX_GTPU_IP_TEID,
+ /* GTPU_UP */
+ ICE_FLOW_FIELD_IDX_GTPU_UP_TEID,
+ /* GTPU_DWN */
+ ICE_FLOW_FIELD_IDX_GTPU_DWN_TEID,
+ /* PPPOE */
+ ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID,
/* The total number of enums must not exceed 64 */
ICE_FLOW_FIELD_IDX_MAX
};
diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h
index cfbe3fbfa..29375d3ae 100644
--- a/drivers/net/ice/base/ice_protocol_type.h
+++ b/drivers/net/ice/base/ice_protocol_type.h
@@ -43,6 +43,8 @@ enum ice_protocol_type {
ICE_GENEVE,
ICE_VXLAN_GPE,
ICE_NVGRE,
+ ICE_GTP,
+ ICE_PPPOE,
ICE_PROTOCOL_LAST
};
@@ -55,6 +57,8 @@ enum ice_sw_tunnel_type {
ICE_SW_TUN_UDP, /* This means all "UDP" tunnel types: VXLAN-GPE, VXLAN
* and GENEVE
*/
+ ICE_SW_TUN_GTP,
+ ICE_SW_TUN_PPPOE,
ICE_ALL_TUNNELS /* All tunnel types including NVGRE */
};
@@ -97,6 +101,7 @@ enum ice_prot_id {
ICE_PROT_ICMPV6_IL = 100,
ICE_PROT_VRRP_F = 101,
ICE_PROT_OSPF = 102,
+ ICE_PROT_PPPOE = 103,
ICE_PROT_ATAOE_OF = 114,
ICE_PROT_CTRL_OF = 116,
ICE_PROT_LLDP_OF = 117,
@@ -115,9 +120,9 @@ enum ice_prot_id {
#define ICE_IPV6_OFOS_HW 40
#define ICE_IPV6_IL_HW 41
#define ICE_TCP_IL_HW 49
-#define ICE_UDP_OF_HW 52
#define ICE_UDP_ILOS_HW 53
#define ICE_SCTP_IL_HW 96
+#define ICE_PPPOE_HW 103
/* ICE_UDP_OF is used to identify all 3 tunnel types
* VXLAN, GENEVE and VXLAN_GPE. To differentiate further
@@ -198,6 +203,30 @@ struct ice_udp_tnl_hdr {
u32 vni; /* only use lower 24-bits */
};
+#pragma pack(1)
+struct ice_udp_gtp_hdr {
+ u8 flags;
+ u8 msg_type;
+ u16 rsrvd_len;
+ u32 teid;
+ u16 rsrvd_seq_nbr;
+ u8 rsrvd_n_pdu_nbr;
+ u8 rsrvd_next_ext;
+ u8 rsvrd_ext_len;
+ u8 pdu_type;
+ u8 qfi;
+ u8 rsvrd;
+};
+
+struct ice_pppoe_hdr {
+ u8 rsrvd_ver_type;
+ u8 rsrved_code;
+ u16 session_id;
+ u16 length;
+ u16 ppp_prot_id; /* control and data only */
+};
+#pragma pack()
+
struct ice_nvgre {
u16 flags;
u16 protocol;
@@ -213,6 +242,8 @@ union ice_prot_hdr {
struct ice_sctp_hdr sctp_hdr;
struct ice_udp_tnl_hdr tnl_hdr;
struct ice_nvgre nvgre_hdr;
+ struct ice_udp_gtp_hdr gtp_hdr;
+ struct ice_pppoe_hdr pppoe_hdr;
};
/* This is mapping table entry that maps every word within a given protocol
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index b249a3036..f88addec6 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -380,7 +380,64 @@ dummy_udp_ipv6_packet[] = {
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
-/* this is a recipe to profile bitmap association */
+static const
+struct ice_dummy_pkt_offsets dummy_udp_gtp_packet_offsets[] = {
+ { ICE_MAC_OFOS, 0 },
+ { ICE_IPV4_OFOS, 14 },
+ { ICE_UDP_OF, 34 },
+ { ICE_GTP, 42 },
+ { ICE_PROTOCOL_LAST, 0 },
+};
+
+static const u8
+dummy_udp_gtp_packet[] = {
+ 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x08, 0x00,
+
+ 0x45, 0x00, 0x00, 0x30, /* ICE_IPV4_OFOS 14 */
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x11, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+
+ 0x00, 0x00, 0x08, 0x68, /* ICE_UDP_OF 34 */
+ 0x00, 0x1c, 0x00, 0x00,
+
+ 0x34, 0xff, 0x00, 0x0c, /* ICE_GTP 42 */
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x85,
+
+ 0x02, 0x00, 0x00, 0x00, /* PDU Session extension header */
+ 0x00, 0x00, 0x00, 0x00,
+};
+
+static const
+struct ice_dummy_pkt_offsets dummy_pppoe_packet_offsets[] = {
+ { ICE_MAC_OFOS, 0 },
+ { ICE_PPPOE, 14 },
+ { ICE_PROTOCOL_LAST, 0 },
+};
+
+static const u8
+dummy_pppoe_packet[] = {
+ 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x88, 0x64,
+
+ 0x11, 0x00, 0x00, 0x01, /* ICE_PPPOE 14 */
+ 0x00, 0x4e, 0x00, 0x21,
+
+ 0x45, 0x00, 0x00, 0x30, /* PDU */
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x11, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+};
+
+/* this is a recipe to profile association bitmap */
static ice_declare_bitmap(recipe_to_profile[ICE_MAX_NUM_RECIPES],
ICE_MAX_NUM_PROFILES);
static ice_declare_bitmap(available_result_ids, ICE_CHAIN_FV_INDEX_START + 1);
@@ -4541,6 +4598,8 @@ static const struct ice_prot_ext_tbl_entry ice_prot_ext[] = {
{ ICE_GENEVE, { 8, 10, 12, 14 } },
{ ICE_VXLAN_GPE, { 0, 2, 4 } },
{ ICE_NVGRE, { 0, 2, 4, 6 } },
+ { ICE_GTP, { 8, 10, 12, 14, 16, 18, 20 } },
+ { ICE_PPPOE, { 0, 2, 4, 6 } },
{ ICE_PROTOCOL_LAST, { 0 } }
};
@@ -4577,6 +4636,8 @@ static const struct ice_protocol_entry ice_prot_id_tbl[] = {
{ ICE_GENEVE, ICE_UDP_OF_HW },
{ ICE_VXLAN_GPE, ICE_UDP_OF_HW },
{ ICE_NVGRE, ICE_GRE_OF_HW },
+ { ICE_GTP, ICE_UDP_OF_HW },
+ { ICE_PPPOE, ICE_PPPOE_HW },
{ ICE_PROTOCOL_LAST, 0 }
};
@@ -5418,6 +5479,18 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,
bool tcp = false, udp = false, ipv6 = false;
u16 i;
+ if (tun_type == ICE_SW_TUN_GTP) {
+ *pkt = dummy_udp_gtp_packet;
+ *pkt_len = sizeof(dummy_udp_gtp_packet);
+ *offsets = dummy_udp_gtp_packet_offsets;
+ return;
+ }
+ if (tun_type == ICE_SW_TUN_PPPOE) {
+ *pkt = dummy_pppoe_packet;
+ *pkt_len = sizeof(dummy_pppoe_packet);
+ *offsets = dummy_pppoe_packet_offsets;
+ return;
+ }
for (i = 0; i < lkups_cnt; i++) {
if (lkups[i].type == ICE_UDP_ILOS)
udp = true;
@@ -5564,6 +5637,10 @@ ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,
case ICE_VXLAN_GPE:
len = sizeof(struct ice_udp_tnl_hdr);
break;
+
+ case ICE_GTP:
+ len = sizeof(struct ice_udp_gtp_hdr);
+ break;
default:
return ICE_ERR_PARAM;
}
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 26/63] net/ice/base: add locks for flow functions
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (24 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 25/63] net/ice/base: add support for GTP and PPPoE protocols Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 27/63] net/ice/base: improve switch advanced rule Qi Zhang
` (37 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Vignesh Sridhar, Paul M Stillwell Jr
Wrap functions to search for flow profiles, add and remove RSS
configurations with flow profile locks. This is to ensure that if
several VFs and PFs are disabled at the same time functions that access
the flow profile lists are thread safe.
Signed-off-by: Vignesh Sridhar <vignesh.sridhar@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flow.c | 29 +++++++++++++++++------------
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 0f52b3379..9e93a1078 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -949,8 +949,9 @@ ice_flow_find_prof_conds(struct ice_hw *hw, enum ice_block blk,
enum ice_flow_dir dir, struct ice_flow_seg_info *segs,
u8 segs_cnt, u16 vsi_handle, u32 conds)
{
- struct ice_flow_prof *p;
+ struct ice_flow_prof *p, *prof = NULL;
+ ice_acquire_lock(&hw->fl_profs_locks[blk]);
LIST_FOR_EACH_ENTRY(p, &hw->fl_profs[blk], ice_flow_prof, l_entry) {
if ((p->dir == dir || conds & ICE_FLOW_FIND_PROF_NOT_CHK_DIR) &&
segs_cnt && segs_cnt == p->segs_cnt) {
@@ -972,12 +973,15 @@ ice_flow_find_prof_conds(struct ice_hw *hw, enum ice_block blk,
break;
/* A match is found if all segments are matched */
- if (i == segs_cnt)
- return p;
+ if (i == segs_cnt) {
+ prof = p;
+ break;
+ }
}
}
+ ice_release_lock(&hw->fl_profs_locks[blk]);
- return NULL;
+ return prof;
}
/**
@@ -994,10 +998,8 @@ ice_flow_find_prof(struct ice_hw *hw, enum ice_block blk, enum ice_flow_dir dir,
{
struct ice_flow_prof *p;
- ice_acquire_lock(&hw->fl_profs_locks[blk]);
p = ice_flow_find_prof_conds(hw, blk, dir, segs, segs_cnt,
ICE_MAX_VSI, ICE_FLOW_FIND_PROF_CHK_FLDS);
- ice_release_lock(&hw->fl_profs_locks[blk]);
return p ? p->id : ICE_FLOW_PROF_ID_INVAL;
}
@@ -1497,9 +1499,12 @@ ice_flow_add_entry(struct ice_hw *hw, enum ice_block blk, u64 prof_id,
goto out;
}
- ice_acquire_lock(&prof->entries_lock);
- LIST_ADD(&e->l_entry, &prof->entries);
- ice_release_lock(&prof->entries_lock);
+ if (blk != ICE_BLK_ACL) {
+ /* ACL will handle the entry management */
+ ice_acquire_lock(&prof->entries_lock);
+ LIST_ADD(&e->l_entry, &prof->entries);
+ ice_release_lock(&prof->entries_lock);
+ }
*entry_h = ICE_FLOW_ENTRY_HNDL(e);
@@ -1930,7 +1935,7 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
/* Remove profile if it has no VSIs associated */
if (!ice_is_any_bit_set(prof->vsis, ICE_MAX_VSI)) {
- status = ice_flow_rem_prof_sync(hw, blk, prof);
+ status = ice_flow_rem_prof(hw, blk, prof->id);
if (status)
goto exit;
}
@@ -1963,7 +1968,7 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
* be removed.
*/
if (status) {
- ice_flow_rem_prof_sync(hw, blk, prof);
+ ice_flow_rem_prof(hw, blk, prof->id);
goto exit;
}
@@ -2047,7 +2052,7 @@ ice_rem_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
ice_rem_rss_list(hw, vsi_handle, prof);
if (!ice_is_any_bit_set(prof->vsis, ICE_MAX_VSI))
- status = ice_flow_rem_prof_sync(hw, blk, prof);
+ status = ice_flow_rem_prof(hw, blk, prof->id);
out:
ice_free(hw, segs);
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 27/63] net/ice/base: improve switch advanced rule
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (25 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 26/63] net/ice/base: add locks for flow functions Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 28/63] net/ice/base: move function declaration Qi Zhang
` (36 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
Correct algorithm to detect free field vector indexes to be
used for recipe line result values. The code now scans all
recipes that are associated with all the field vector being
targed for a new recipe to detect which result indexes are
unused.
Change recipe chaining code to place recipe on a single line
if it will fit, rather than looking to break things apart
according to preferred combinations.
These improvements fix a condition where recipes were getting
added with conflicting result index values.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_bitops.h | 31 ++++
drivers/net/ice/base/ice_switch.c | 354 +++++++++++++++++++++++++++++---------
drivers/net/ice/base/ice_switch.h | 5 +
3 files changed, 309 insertions(+), 81 deletions(-)
diff --git a/drivers/net/ice/base/ice_bitops.h b/drivers/net/ice/base/ice_bitops.h
index a3a67eb4b..f0aa8ce88 100644
--- a/drivers/net/ice/base/ice_bitops.h
+++ b/drivers/net/ice/base/ice_bitops.h
@@ -229,6 +229,37 @@ ice_or_bitmap(ice_bitmap_t *dst, const ice_bitmap_t *bmp1,
}
/**
+ * ice_xor_bitmap - bitwise XOR 2 bitmaps and store result in dst bitmap
+ * @dst: Destination bitmap that receive the result of the operation
+ * @bmp1: The first bitmap of XOR operation
+ * @bmp2: The second bitmap to XOR with the first
+ * @size: Size of the bitmaps in bits
+ *
+ * This function performs a bitwise XOR on two "source" bitmaps of the same size
+ * and stores the result to "dst" bitmap. The "dst" bitmap must be of the same
+ * size as the "source" bitmaps to avoid buffer overflows.
+ */
+static inline void
+ice_xor_bitmap(ice_bitmap_t *dst, const ice_bitmap_t *bmp1,
+ const ice_bitmap_t *bmp2, u16 size)
+{
+ ice_bitmap_t mask;
+ u16 i;
+
+ /* Handle all but last chunk*/
+ for (i = 0; i < BITS_TO_CHUNKS(size) - 1; i++)
+ dst[i] = bmp1[i] ^ bmp2[i];
+
+ /* We want to only XOR bits within the size. Furthermore, we also do
+ * not want to modify destination bits which are beyond the specified
+ * size. Use a bitmask to ensure that we only modify the bits that are
+ * within the specified size.
+ */
+ mask = LAST_CHUNK_MASK(size);
+ dst[i] = (dst[i] & ~mask) | ((bmp1[i] ^ bmp2[i]) & mask);
+}
+
+/**
* ice_find_next_bit - Find the index of the next set bit of a bitmap
* @bitmap: the bitmap to scan
* @size: the size in bits of the bitmap
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index f88addec6..2b0c7c7a3 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -440,11 +440,47 @@ dummy_pppoe_packet[] = {
/* this is a recipe to profile association bitmap */
static ice_declare_bitmap(recipe_to_profile[ICE_MAX_NUM_RECIPES],
ICE_MAX_NUM_PROFILES);
-static ice_declare_bitmap(available_result_ids, ICE_CHAIN_FV_INDEX_START + 1);
+
+/* this is a profile to recipe association bitmap */
+static ice_declare_bitmap(profile_to_recipe[ICE_MAX_NUM_PROFILES],
+ ICE_MAX_NUM_RECIPES);
static void ice_get_recp_to_prof_map(struct ice_hw *hw);
/**
+ * ice_collect_result_idx - copy result index values
+ * @buf: buffer that contains the result index
+ * @recp: the recipe struct to copy data into
+ */
+static void ice_collect_result_idx(struct ice_aqc_recipe_data_elem *buf,
+ struct ice_sw_recipe *recp)
+{
+ if (buf->content.result_indx & ICE_AQ_RECIPE_ID_IS_ROOT)
+ ice_set_bit(buf->content.result_indx &
+ ~ICE_AQ_RECIPE_ID_IS_ROOT, recp->res_idxs);
+}
+
+/**
+ * ice_collect_result_idx_from_bitmap - copy result index values using bitmap
+ * @hw: pointer to hardware structure
+ * @recp: the recipe struct to copy data into
+ */
+static void
+ice_collect_result_idx_from_bitmap(struct ice_hw *hw,
+ struct ice_sw_recipe *recp)
+{
+ u16 bit = 0;
+
+ while (ICE_MAX_NUM_RECIPES >
+ (bit = ice_find_next_bit(recp->r_bitmap, ICE_MAX_NUM_RECIPES,
+ bit))) {
+ ice_collect_result_idx(hw->switch_info->recp_list[bit].root_buf,
+ recp);
+ bit++;
+ }
+}
+
+/**
* ice_get_recp_frm_fw - update SW bookkeeping from FW recipe entries
* @hw: pointer to hardware structure
* @recps: struct that we need to populate
@@ -466,6 +502,7 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
u16 num_recps = ICE_MAX_NUM_RECIPES;
struct ice_prot_lkup_ext *lkup_exts;
enum ice_status status;
+ u8 is_root;
/* we need a buffer big enough to accommodate all the recipes */
tmp = (struct ice_aqc_recipe_data_elem *)ice_calloc(hw,
@@ -507,14 +544,10 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
status = ICE_ERR_NO_MEMORY;
goto err_unroll;
}
- /* Avoid 8th bit since its result enable bit */
+ /* When copying, clear the result index enable bit */
result_idxs[result_idx] = root_bufs.content.result_indx &
~ICE_AQ_RECIPE_RESULT_EN;
- /* Check if result enable bit is set */
- if (root_bufs.content.result_indx & ICE_AQ_RECIPE_RESULT_EN)
- ice_clear_bit(ICE_CHAIN_FV_INDEX_START -
- result_idxs[result_idx++],
- available_result_ids);
+
ice_memcpy(r_bitmap,
recipe_to_profile[tmp[sub_recps].recipe_indx],
sizeof(r_bitmap), ICE_NONDMA_TO_NONDMA);
@@ -566,9 +599,29 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
ice_memcpy(recps[rid].root_buf, tmp, recps[rid].n_grp_count *
sizeof(*recps[rid].root_buf), ICE_NONDMA_TO_NONDMA);
+
+ ice_memcpy(recps[rid].r_bitmap, tmp->recipe_bitmap,
+ sizeof(recps[rid].r_bitmap), ICE_NONDMA_TO_NONDMA);
+
+ if (tmp->content.result_indx & ICE_AQ_RECIPE_RESULT_EN)
+ recps[rid].chain_idx = tmp->content.result_indx &
+ ~ICE_AQ_RECIPE_RESULT_EN;
+ else
+ recps[rid].chain_idx = ICE_INVAL_CHAIN_IND;
+
+ recps[rid].root_rid = tmp->content.rid & ~ICE_AQ_RECIPE_ID_IS_ROOT;
+ is_root = (tmp->content.rid & ICE_AQ_RECIPE_ID_IS_ROOT) != 0;
+ recps[rid].is_root = is_root;
+ recps[rid].big_recp = (is_root && recps[rid].n_grp_count > 1);
+
+ /* Copy non-result fv index values to recipe. This call will also update
+ * the result index bitmap appropriately.
+ */
+ ice_collect_result_idx_from_bitmap(hw, &recps[rid]);
+
+ recps[rid].priority = tmp->content.act_ctrl_fwd_priority;
recps[rid].recp_created = true;
- if (tmp[sub_recps].content.rid & ICE_AQ_RECIPE_ID_IS_ROOT)
- recps[rid].root_rid = rid;
+
err_unroll:
ice_free(hw, tmp);
return status;
@@ -591,10 +644,12 @@ ice_get_recp_to_prof_map(struct ice_hw *hw)
for (i = 0; i < ICE_MAX_NUM_PROFILES; i++) {
u16 j;
+ ice_zero_bitmap(profile_to_recipe[i], ICE_MAX_NUM_RECIPES);
ice_zero_bitmap(r_bitmap, ICE_MAX_NUM_RECIPES);
if (ice_aq_get_recipe_to_profile(hw, i, (u8 *)r_bitmap, NULL))
continue;
-
+ ice_memcpy(profile_to_recipe[i], r_bitmap,
+ sizeof(profile_to_recipe[i]), ICE_NONDMA_TO_NONDMA);
for (j = 0; j < ICE_MAX_NUM_RECIPES; j++)
if (ice_is_bit_set(r_bitmap, j))
ice_set_bit(i, recipe_to_profile[j]);
@@ -1443,7 +1498,7 @@ ice_aq_sw_rules(struct ice_hw *hw, void *rule_list, u16 rule_list_sz,
{
struct ice_aq_desc desc;
- ice_debug(hw, ICE_DBG_TRACE, "ice_aq_sw_rules");
+ ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
if (opc != ice_aqc_opc_add_sw_rules &&
opc != ice_aqc_opc_update_sw_rules &&
@@ -1476,7 +1531,7 @@ ice_aq_add_recipe(struct ice_hw *hw,
struct ice_aq_desc desc;
u16 buf_size;
- ice_debug(hw, ICE_DBG_TRACE, "ice_aq_add_recipe");
+ ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
cmd = &desc.params.add_get_recipe;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_recipe);
@@ -1518,7 +1573,7 @@ ice_aq_get_recipe(struct ice_hw *hw,
if (*num_recipes != ICE_MAX_NUM_RECIPES)
return ICE_ERR_PARAM;
- ice_debug(hw, ICE_DBG_TRACE, "ice_aq_get_recipe");
+ ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
cmd = &desc.params.add_get_recipe;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_recipe);
@@ -1549,7 +1604,7 @@ ice_aq_map_recipe_to_profile(struct ice_hw *hw, u32 profile_id, u8 *r_bitmap,
struct ice_aqc_recipe_to_profile *cmd;
struct ice_aq_desc desc;
- ice_debug(hw, ICE_DBG_TRACE, "ice_aq_assoc_recipe_to_prof");
+ ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
cmd = &desc.params.recipe_to_profile;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_recipe_to_profile);
cmd->profile_id = CPU_TO_LE16(profile_id);
@@ -1578,7 +1633,7 @@ ice_aq_get_recipe_to_profile(struct ice_hw *hw, u32 profile_id, u8 *r_bitmap,
struct ice_aq_desc desc;
enum ice_status status;
- ice_debug(hw, ICE_DBG_TRACE, "ice_aq_get_recipe_to_prof");
+ ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
cmd = &desc.params.recipe_to_profile;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_recipe_to_profile);
cmd->profile_id = CPU_TO_LE16(profile_id);
@@ -2917,7 +2972,7 @@ ice_aq_get_res_descs(struct ice_hw *hw, u16 num_entries,
struct ice_aq_desc desc;
enum ice_status status;
- ice_debug(hw, ICE_DBG_TRACE, "ice_aq_get_res_descs");
+ ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
cmd = &desc.params.get_res_desc;
@@ -4001,7 +4056,7 @@ ice_set_vsi_promisc(struct ice_hw *hw, u16 vsi_handle, u8 promisc_mask, u16 vid)
int pkt_type;
u8 recipe_id;
- ice_debug(hw, ICE_DBG_TRACE, "ice_set_vsi_promisc\n");
+ ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
if (!ice_is_vsi_valid(hw, vsi_handle))
return ICE_ERR_PARAM;
@@ -4219,7 +4274,7 @@ ice_remove_vsi_lkup_fltr(struct ice_hw *hw, u16 vsi_handle,
*/
void ice_remove_vsi_fltr(struct ice_hw *hw, u16 vsi_handle)
{
- ice_debug(hw, ICE_DBG_TRACE, "ice_remove_vsi_fltr\n");
+ ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
ice_remove_vsi_lkup_fltr(hw, vsi_handle, ICE_SW_LKUP_MAC);
ice_remove_vsi_lkup_fltr(hw, vsi_handle, ICE_SW_LKUP_MAC_VLAN);
@@ -4654,11 +4709,6 @@ static u16 ice_find_recp(struct ice_hw *hw, struct ice_prot_lkup_ext *lkup_exts)
struct ice_sw_recipe *recp;
u16 i;
- /* Initialize available_result_ids which tracks available result idx */
- for (i = 0; i <= ICE_CHAIN_FV_INDEX_START; i++)
- ice_set_bit(ICE_CHAIN_FV_INDEX_START - i,
- available_result_ids);
-
/* Walk through existing recipes to find a match */
recp = hw->switch_info->recp_list;
for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
@@ -4942,19 +4992,102 @@ ice_fill_fv_word_index(struct ice_hw *hw, struct LIST_HEAD_TYPE *fv_list,
}
/**
+ * ice_find_free_recp_res_idx - find free result indexes for recipe
+ * @hw: pointer to hardware structure
+ * @profiles: bitmap of profiles that will be associated with the new recipe
+ * @free_idx: pointer to variable to receive the free index bitmap
+ *
+ * The algorithm used here is:
+ * 1. When creating a new recipe, create a set P which contains all
+ * Profiles that will be associated with our new recipe
+ *
+ * 2. For each Profile p in set P:
+ * a. Add all recipes associated with Profile p into set R
+ * b. Optional : PossibleIndexes &= profile[p].possibleIndexes
+ * [initially PossibleIndexes should be 0xFFFFFFFFFFFFFFFF]
+ * i. Or just assume they all have the same possible indexes:
+ * 44, 45, 46, 47
+ * i.e., PossibleIndexes = 0x0000F00000000000
+ *
+ * 3. For each Recipe r in set R:
+ * a. UsedIndexes |= (bitwise or ) recipe[r].res_indexes
+ * b. FreeIndexes = UsedIndexes ^ PossibleIndexes
+ *
+ * FreeIndexes will contain the bits indicating the indexes free for use,
+ * then the code needs to update the recipe[r].used_result_idx_bits to
+ * indicate which indexes were selected for use by this recipe.
+ */
+static u16
+ice_find_free_recp_res_idx(struct ice_hw *hw, const ice_bitmap_t *profiles,
+ ice_bitmap_t *free_idx)
+{
+ ice_declare_bitmap(possible_idx, ICE_MAX_FV_WORDS);
+ ice_declare_bitmap(used_idx, ICE_MAX_FV_WORDS);
+ ice_declare_bitmap(recipes, ICE_MAX_NUM_RECIPES);
+ u16 count = 0;
+ u16 bit;
+
+ ice_zero_bitmap(possible_idx, ICE_MAX_FV_WORDS);
+ ice_zero_bitmap(free_idx, ICE_MAX_FV_WORDS);
+ ice_zero_bitmap(used_idx, ICE_MAX_FV_WORDS);
+ ice_zero_bitmap(recipes, ICE_MAX_NUM_RECIPES);
+
+ for (bit = 0; bit < ICE_MAX_FV_WORDS; bit++)
+ if (ICE_POSSIBLE_RES_IDX & BIT_ULL(bit))
+ ice_set_bit(bit, possible_idx);
+
+ /* For each profile we are going to associate the recipe with, add the
+ * recipes that are associated with that profile. This will give us
+ * the set of recipes that our recipe may collide with.
+ */
+ bit = 0;
+ while (ICE_MAX_NUM_PROFILES >
+ (bit = ice_find_next_bit(profiles, ICE_MAX_NUM_PROFILES, bit))) {
+ ice_or_bitmap(recipes, recipes, profile_to_recipe[bit],
+ ICE_MAX_NUM_RECIPES);
+
+ bit++;
+ }
+
+ /* For each recipe that our new recipe may collide with, determine
+ * which indexes have been used.
+ */
+ for (bit = 0; bit < ICE_MAX_NUM_RECIPES; bit++)
+ if (ice_is_bit_set(recipes, bit))
+ ice_or_bitmap(used_idx, used_idx,
+ hw->switch_info->recp_list[bit].res_idxs,
+ ICE_MAX_FV_WORDS);
+
+ ice_xor_bitmap(free_idx, used_idx, possible_idx, ICE_MAX_FV_WORDS);
+
+ /* return number of free indexes */
+ bit = 0;
+ while (ICE_MAX_FV_WORDS >
+ (bit = ice_find_next_bit(free_idx, ICE_MAX_FV_WORDS, bit))) {
+ count++;
+ bit++;
+ }
+
+ return count;
+}
+
+/**
* ice_add_sw_recipe - function to call AQ calls to create switch recipe
* @hw: pointer to hardware structure
* @rm: recipe management list entry
* @match_tun: if field vector index for tunnel needs to be programmed
+ * @profiles: bitmap of profiles that will be assocated.
*/
static enum ice_status
ice_add_sw_recipe(struct ice_hw *hw, struct ice_sw_recipe *rm,
- bool match_tun)
+ bool match_tun, ice_bitmap_t *profiles)
{
+ ice_declare_bitmap(result_idx_bm, ICE_MAX_FV_WORDS);
struct ice_aqc_recipe_data_elem *tmp;
struct ice_aqc_recipe_data_elem *buf;
struct ice_recp_grp_entry *entry;
enum ice_status status;
+ u16 free_res_idx;
u16 recipe_count;
u8 chain_idx;
u8 recps = 0;
@@ -4964,11 +5097,16 @@ ice_add_sw_recipe(struct ice_hw *hw, struct ice_sw_recipe *rm,
* the match fields in the chaining recipe reducing the number of
* chained recipes by one.
*/
- if (rm->n_grp_count > 1)
+ /* check number of free result indices */
+ ice_zero_bitmap(result_idx_bm, ICE_MAX_FV_WORDS);
+ free_res_idx = ice_find_free_recp_res_idx(hw, profiles, result_idx_bm);
+
+ if (rm->n_grp_count > 1) {
+ if (rm->n_grp_count > free_res_idx)
+ return ICE_ERR_MAX_LIMIT;
+
rm->n_grp_count++;
- if (rm->n_grp_count > ICE_MAX_CHAIN_RECIPE ||
- (match_tun && rm->n_grp_count > (ICE_MAX_CHAIN_RECIPE - 1)))
- return ICE_ERR_MAX_LIMIT;
+ }
tmp = (struct ice_aqc_recipe_data_elem *)ice_calloc(hw,
ICE_MAX_NUM_RECIPES,
@@ -4993,9 +5131,7 @@ ice_add_sw_recipe(struct ice_hw *hw, struct ice_sw_recipe *rm,
/* Allocate the recipe resources, and configure them according to the
* match fields from protocol headers and extracted field vectors.
*/
- chain_idx = ICE_CHAIN_FV_INDEX_START -
- ice_find_first_bit(available_result_ids,
- ICE_CHAIN_FV_INDEX_START + 1);
+ chain_idx = ice_find_first_bit(result_idx_bm, ICE_MAX_FV_WORDS);
LIST_FOR_EACH_ENTRY(entry, &rm->rg_list, ice_recp_grp_entry, l_entry) {
u8 i;
@@ -5037,17 +5173,24 @@ ice_add_sw_recipe(struct ice_hw *hw, struct ice_sw_recipe *rm,
}
if (rm->n_grp_count > 1) {
+ /* Checks to see if there really is a valid result index
+ * that can be used.
+ */
+ if (chain_idx >= ICE_MAX_FV_WORDS) {
+ ice_debug(hw, ICE_DBG_SW,
+ "No chain index available\n");
+ status = ICE_ERR_MAX_LIMIT;
+ goto err_unroll;
+ }
+
entry->chain_idx = chain_idx;
buf[recps].content.result_indx =
ICE_AQ_RECIPE_RESULT_EN |
((chain_idx << ICE_AQ_RECIPE_RESULT_DATA_S) &
ICE_AQ_RECIPE_RESULT_DATA_M);
- ice_clear_bit(ICE_CHAIN_FV_INDEX_START - chain_idx,
- available_result_ids);
- chain_idx = ICE_CHAIN_FV_INDEX_START -
- ice_find_first_bit(available_result_ids,
- ICE_CHAIN_FV_INDEX_START +
- 1);
+ ice_clear_bit(chain_idx, result_idx_bm);
+ chain_idx = ice_find_first_bit(result_idx_bm,
+ ICE_MAX_FV_WORDS);
}
/* fill recipe dependencies */
@@ -5172,19 +5315,55 @@ ice_add_sw_recipe(struct ice_hw *hw, struct ice_sw_recipe *rm,
*/
LIST_FOR_EACH_ENTRY(entry, &rm->rg_list, ice_recp_grp_entry, l_entry) {
struct ice_switch_info *sw = hw->switch_info;
+ bool is_root, idx_found = false;
struct ice_sw_recipe *recp;
+ u16 idx, buf_idx = 0;
+
+ /* find buffer index for copying some data */
+ for (idx = 0; idx < rm->n_grp_count; idx++)
+ if (buf[idx].recipe_indx == entry->rid) {
+ buf_idx = idx;
+ idx_found = true;
+ }
+
+ if (!idx_found) {
+ status = ICE_ERR_OUT_OF_RANGE;
+ goto err_unroll;
+ }
recp = &sw->recp_list[entry->rid];
+ is_root = (rm->root_rid == entry->rid);
+ recp->is_root = is_root;
+
recp->root_rid = entry->rid;
+ recp->big_recp = (is_root && rm->n_grp_count > 1);
+
ice_memcpy(&recp->ext_words, entry->r_group.pairs,
entry->r_group.n_val_pairs *
sizeof(struct ice_fv_word),
ICE_NONDMA_TO_NONDMA);
+ ice_memcpy(recp->r_bitmap, buf[buf_idx].recipe_bitmap,
+ sizeof(recp->r_bitmap), ICE_NONDMA_TO_NONDMA);
+
+ /* Copy non-result fv index values and masks to recipe. This
+ * call will also update the result recipe bitmask.
+ */
+ ice_collect_result_idx(&buf[buf_idx], recp);
+
+ /* for non-root recipes, also copy to the root, this allows
+ * easier matching of a complete chained recipe
+ */
+ if (!is_root)
+ ice_collect_result_idx(&buf[buf_idx],
+ &sw->recp_list[rm->root_rid]);
+
recp->n_ext_words = entry->r_group.n_val_pairs;
recp->chain_idx = entry->chain_idx;
+ recp->priority = buf[buf_idx].content.act_ctrl_fwd_priority;
+ recp->tun_type = rm->tun_type;
recp->recp_created = true;
- recp->big_recp = false;
+ recp->adv_rule = 1;
}
rm->root_buf = buf;
ice_free(hw, tmp);
@@ -5215,36 +5394,42 @@ ice_create_recipe_group(struct ice_hw *hw, struct ice_sw_recipe *rm,
rm->n_grp_count = 0;
- /* Each switch recipe can match up to 5 words or metadata. One word in
- * each recipe is used to match the switch ID. Four words are left for
- * matching other values. If the new advanced recipe requires more than
- * 4 words, it needs to be split into multiple recipes which are chained
- * together using the intermediate result that each produces as input to
- * the other recipes in the sequence.
- */
- groups = ARRAY_SIZE(ice_recipe_pack);
- /* Check if any of the preferred recipes from the grouping policy
- * matches.
- */
- for (i = 0; i < groups; i++)
- /* Check if the recipe from the preferred grouping matches
- * or is a subset of the fields that needs to be looked up.
+ if (lkup_exts->n_val_words > ICE_NUM_WORDS_RECIPE) {
+ /* Each switch recipe can match up to 5 words or metadata. One
+ * word in each recipe is used to match the switch ID. Four
+ * words are left for matching other values. If the new advanced
+ * recipe requires more than 4 words, it needs to be split into
+ * multiple recipes which are chained together using the
+ * intermediate result that each produces as input to the other
+ * recipes in the sequence.
*/
- if (ice_is_recipe_subset(lkup_exts, &ice_recipe_pack[i])) {
- /* This recipe can be used by itself or grouped with
- * other recipes.
+ groups = ARRAY_SIZE(ice_recipe_pack);
+
+ /* Check if any of the preferred recipes from the grouping
+ * policy matches.
+ */
+ for (i = 0; i < groups; i++)
+ /* Check if the recipe from the preferred grouping
+ * matches or is a subset of the fields that needs to be
+ * looked up.
*/
- entry = (struct ice_recp_grp_entry *)
- ice_malloc(hw, sizeof(*entry));
- if (!entry) {
- status = ICE_ERR_NO_MEMORY;
- goto err_unroll;
+ if (ice_is_recipe_subset(lkup_exts,
+ &ice_recipe_pack[i])) {
+ /* This recipe can be used by itself or grouped
+ * with other recipes.
+ */
+ entry = (struct ice_recp_grp_entry *)
+ ice_malloc(hw, sizeof(*entry));
+ if (!entry) {
+ status = ICE_ERR_NO_MEMORY;
+ goto err_unroll;
+ }
+ entry->r_group = ice_recipe_pack[i];
+ LIST_ADD(&entry->l_entry, &rm->rg_list);
+ rm->n_grp_count++;
}
- entry->r_group = ice_recipe_pack[i];
- LIST_ADD(&entry->l_entry, &rm->rg_list);
- rm->n_grp_count++;
- }
+ }
/* Create recipes for words that are marked not done by packing them
* as best fit.
@@ -5319,6 +5504,7 @@ static enum ice_status
ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
u16 lkups_cnt, struct ice_adv_rule_info *rinfo, u16 *rid)
{
+ ice_declare_bitmap(profiles, ICE_MAX_NUM_PROFILES);
struct ice_prot_lkup_ext *lkup_exts;
struct ice_recp_grp_entry *r_entry;
struct ice_sw_fv_list_entry *fvit;
@@ -5355,13 +5541,6 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
}
}
- *rid = ice_find_recp(hw, lkup_exts);
- if (*rid < ICE_MAX_NUM_RECIPES)
- /* Success if found a recipe that match the existing criteria */
- goto err_free_lkup_exts;
-
- /* Recipe we need does not exist, add a recipe */
-
rm = (struct ice_sw_recipe *)ice_malloc(hw, sizeof(*rm));
if (!rm) {
status = ICE_ERR_NO_MEMORY;
@@ -5401,7 +5580,23 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
* recipes.
*/
ice_fill_fv_word_index(hw, &rm->fv_list, &rm->rg_list);
- status = ice_add_sw_recipe(hw, rm, match_tun);
+
+ /* get bitmap of all profiles the recipe will be associated with */
+ ice_zero_bitmap(profiles, ICE_MAX_NUM_PROFILES);
+ LIST_FOR_EACH_ENTRY(fvit, &rm->fv_list, ice_sw_fv_list_entry,
+ list_entry) {
+ ice_debug(hw, ICE_DBG_SW, "profile: %d\n", fvit->profile_id);
+ ice_set_bit((u16)fvit->profile_id, profiles);
+ }
+
+ /* Look for a recipe which matches our requested fv / mask list */
+ *rid = ice_find_recp(hw, lkup_exts);
+ if (*rid < ICE_MAX_NUM_RECIPES)
+ /* Success if found a recipe that match the existing criteria */
+ goto err_unroll;
+
+ /* Recipe we need does not exist, add a recipe */
+ status = ice_add_sw_recipe(hw, rm, match_tun, profiles);
if (status)
goto err_unroll;
@@ -5851,27 +6046,24 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
struct ice_switch_info *sw;
enum ice_status status;
const u8 *pkt = NULL;
- bool found = false;
+ u16 word_cnt;
u32 act = 0;
u8 q_rgn;
if (!lkups_cnt)
return ICE_ERR_PARAM;
+ /* get # of words we need to match */
+ word_cnt = 0;
for (i = 0; i < lkups_cnt; i++) {
u16 j, *ptr;
- /* Validate match masks to make sure that there is something
- * to match.
- */
ptr = (u16 *)&lkups[i].m_u;
for (j = 0; j < sizeof(lkups->m_u) / sizeof(u16); j++)
- if (ptr[j] != 0) {
- found = true;
- break;
- }
+ if (ptr[j] != 0)
+ word_cnt++;
}
- if (!found)
+ if (!word_cnt || word_cnt > ICE_MAX_CHAIN_WORDS)
return ICE_ERR_PARAM;
/* make sure that we can locate a dummy packet */
diff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h
index 4c34bc2ea..515ad3bb6 100644
--- a/drivers/net/ice/base/ice_switch.h
+++ b/drivers/net/ice/base/ice_switch.h
@@ -183,6 +183,7 @@ struct ice_sw_recipe {
/* For a chained recipe the root recipe is what should be used for
* programming rules
*/
+ u8 is_root;
u8 root_rid;
u8 recp_created;
@@ -226,6 +227,10 @@ struct ice_sw_recipe {
/* Profiles this recipe is associated with */
u8 num_profs, *prof_ids;
+ /* Possible result indexes are 44, 45, 46 and 47 */
+#define ICE_POSSIBLE_RES_IDX 0x0000F00000000000ULL
+ ice_declare_bitmap(res_idxs, ICE_MAX_FV_WORDS);
+
/* This allows user to specify the recipe priority.
* For now, this becomes 'fwd_priority' when recipe
* is created, usually recipes can have 'fwd' and 'join'
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 28/63] net/ice/base: move function declaration
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (26 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 27/63] net/ice/base: improve switch advanced rule Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 29/63] net/ice/base: add 16-byte Flex Rx Descriptor Qi Zhang
` (35 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang; +Cc: dev, xiaolong.ye, Qi Zhang, Paul M Stillwell Jr
Improve code orgnization, move declaration of ice_cfg_tc_nod_bw_alloc and
ice_cfg_rl_burst_size from ice_common.h to ice_nvm.h.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.h | 8 --------
drivers/net/ice/base/ice_nvm.h | 4 ++++
drivers/net/ice/base/ice_sched.h | 4 ++++
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index a55f7eeba..67adc9c59 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -50,10 +50,6 @@ enum ice_status
ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
enum ice_adminq_opc opc, struct ice_sq_cd *cd);
-enum ice_status ice_init_nvm(struct ice_hw *hw);
-enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data);
-enum ice_status
-ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data);
enum ice_status
ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
struct ice_aq_desc *desc, void *buf, u16 buf_size,
@@ -201,10 +197,6 @@ enum ice_status
ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx);
struct ice_q_ctx *
ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle);
-enum ice_status
-ice_cfg_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc,
- enum ice_rl_type rl_type, u8 bw_alloc);
-enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes);
void
ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
u64 *prev_stat, u64 *cur_stat);
diff --git a/drivers/net/ice/base/ice_nvm.h b/drivers/net/ice/base/ice_nvm.h
index da76b2674..d5b7b2d19 100644
--- a/drivers/net/ice/base/ice_nvm.h
+++ b/drivers/net/ice/base/ice_nvm.h
@@ -84,4 +84,8 @@ ice_nvm_access_get_features(struct ice_nvm_access_cmd *cmd,
enum ice_status
ice_handle_nvm_access(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
union ice_nvm_access_data *data);
+enum ice_status ice_init_nvm(struct ice_hw *hw);
+enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data);
+enum ice_status
+ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data);
#endif /* _ICE_NVM_H_ */
diff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h
index 932ae075f..d6b467477 100644
--- a/drivers/net/ice/base/ice_sched.h
+++ b/drivers/net/ice/base/ice_sched.h
@@ -185,4 +185,8 @@ ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw);
enum ice_status
ice_sched_cfg_sibl_node_prio(struct ice_port_info *pi,
struct ice_sched_node *node, u8 priority);
+enum ice_status
+ice_cfg_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc,
+ enum ice_rl_type rl_type, u8 bw_alloc);
+enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes);
#endif /* _ICE_SCHED_H_ */
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 29/63] net/ice/base: add 16-byte Flex Rx Descriptor
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (27 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 28/63] net/ice/base: move function declaration Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 30/63] net/ice/base: add 32-byte Flex Rx Desc Qi Zhang
` (34 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
Add 16-byte Flex RX descriptor structure definition.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_lan_tx_rx.h | 28 ++++++++++++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h
index 2cba6bc1e..7c3927ac2 100644
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -373,10 +373,34 @@ enum ice_rx_prog_status_desc_error_bits {
ICE_RX_PROG_STATUS_DESC_NO_FD_ENTRY_S = 1,
};
-/* Rx Flex Descriptor
- * This descriptor is used instead of the legacy version descriptor when
+/* Rx Flex Descriptors
+ * These descriptors are used instead of the legacy version descriptors when
* ice_rlan_ctx.adv_desc is set
*/
+union ice_16b_rx_flex_desc {
+ struct {
+ __le64 pkt_addr; /* Packet buffer address */
+ __le64 hdr_addr; /* Header buffer address */
+ /* bit 0 of hdr_addr is DD bit */
+ } read;
+ struct {
+ /* Qword 0 */
+ u8 rxdid; /* descriptor builder profile ID */
+ u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
+ __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
+ __le16 pkt_len; /* [15:14] are reserved */
+ __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
+ /* sph=[11:11] */
+ /* ff1/ext=[15:12] */
+
+ /* Qword 1 */
+ __le16 status_error0;
+ __le16 l2tag1;
+ __le16 flex_meta0;
+ __le16 flex_meta1;
+ } wb; /* writeback */
+};
+
union ice_32b_rx_flex_desc {
struct {
__le64 pkt_addr; /* Packet buffer address */
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 30/63] net/ice/base: add 32-byte Flex Rx Desc
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (28 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 29/63] net/ice/base: add 16-byte Flex Rx Descriptor Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 31/63] net/ice/base: update flag bits Qi Zhang
` (33 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Junfeng Guo, Paul M Stillwell Jr
Add 32-byte Flex RX Descriptor structure definition.
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_lan_tx_rx.h | 40 ++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h
index 7c3927ac2..e1c2f0d01 100644
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -619,6 +619,46 @@ struct ice_32b_rx_flex_desc_nic_2 {
} flex_ts;
};
+/* Rx Flex Descriptor for Comms Package Profile
+ * RxDID Profile ID 16-21
+ * Flex-field 0: RSS hash lower 16-bits
+ * Flex-field 1: RSS hash upper 16-bits
+ * Flex-field 2: Flow ID lower 16-bits
+ * Flex-field 3: Flow ID upper 16-bits
+ * Flex-field 4: AUX0
+ * Flex-field 5: AUX1
+ */
+struct ice_32b_rx_flex_desc_comms {
+ /* Qword 0 */
+ u8 rxdid;
+ u8 mir_id_umb_cast;
+ __le16 ptype_flexi_flags0;
+ __le16 pkt_len;
+ __le16 hdr_len_sph_flex_flags1;
+
+ /* Qword 1 */
+ __le16 status_error0;
+ __le16 l2tag1;
+ __le32 rss_hash;
+
+ /* Qword 2 */
+ __le16 status_error1;
+ u8 flexi_flags2;
+ u8 ts_low;
+ __le16 l2tag2_1st;
+ __le16 l2tag2_2nd;
+
+ /* Qword 3 */
+ __le32 flow_id;
+ union {
+ struct {
+ __le16 aux0;
+ __le16 aux1;
+ } flex;
+ __le32 ts_high;
+ } flex_ts;
+};
+
/* Receive Flex Descriptor profile IDs: There are a total
* of 64 profiles where profile IDs 0/1 are for legacy; and
* profiles 2-63 are flex profiles that can be programmed
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 31/63] net/ice/base: update flag bits
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (29 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 30/63] net/ice/base: add 32-byte Flex Rx Desc Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 32/63] net/ice/base: add more opcode and macros Qi Zhang
` (32 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Brett Creeley, Paul M Stillwell Jr
Currently the VLAN ice_flg64_bits are off by 1. Fix this by
setting the ICE_FLG_EVLAN_x8100 flag to 14, which also updates
ICE_FLG_EVLAN_x9100 to 15 and ICE_FLG_VLAN_x8100 to 16.
Signed-off-by: Brett Creeley <brett.creeley@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_lan_tx_rx.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h
index e1c2f0d01..e77d4bf50 100644
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -737,7 +737,7 @@ enum ice_flg64_bits {
ICE_FLG_PKT_DSI = 0,
/* If there is a 1 in this bit position then that means Rx packet */
ICE_FLG_PKT_DIR = 4,
- ICE_FLG_EVLAN_x8100 = 15,
+ ICE_FLG_EVLAN_x8100 = 14,
ICE_FLG_EVLAN_x9100,
ICE_FLG_VLAN_x8100,
ICE_FLG_TNL_MAC = 22,
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 32/63] net/ice/base: add more opcode and macros
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (30 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 31/63] net/ice/base: update flag bits Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 33/63] net/ice/base: set status when global cfg lock is unavailable Qi Zhang
` (31 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang; +Cc: dev, xiaolong.ye, Qi Zhang, Paul M Stillwell Jr
Add more opcode and macros:
1. Add opcode for the NVM Update EMPR command.
2. Add opcode for NVM save factory settings
3. Add opcode for NVM Write/Write Activate calls
4. Add loopback reporting to get link response macros
5. Add link event defines macros
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_adminq_cmd.h | 28 +++++++++++++++++++++++-----
1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index cc42180ea..b9e3bd5fa 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1575,7 +1575,12 @@ struct ice_aqc_get_link_status_data {
#define ICE_AQ_LINK_TX_ACTIVE 0
#define ICE_AQ_LINK_TX_DRAINED 1
#define ICE_AQ_LINK_TX_FLUSHED 3
- u8 reserved2;
+ u8 lb_status;
+#define ICE_AQ_LINK_LB_PHY_LCL BIT(0)
+#define ICE_AQ_LINK_LB_PHY_RMT BIT(1)
+#define ICE_AQ_LINK_LB_MAC_LCL BIT(2)
+#define ICE_AQ_LINK_LB_PHY_IDX_S 3
+#define ICE_AQ_LINK_LB_PHY_IDX_M (0x7 << ICE_AQ_LB_PHY_IDX_S)
__le16 max_frame_size;
u8 cfg;
#define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
@@ -1631,6 +1636,8 @@ struct ice_aqc_set_event_mask {
#define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
#define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
#define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
+#define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10)
+#define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11)
u8 reserved1[6];
};
@@ -1690,20 +1697,26 @@ struct ice_aqc_sff_eeprom {
/* NVM Read command (indirect 0x0701)
* NVM Erase commands (direct 0x0702)
- * NVM Update commands (indirect 0x0703)
+ * NVM Write commands (indirect 0x0703)
+ * NVM Write Activate commands (direct 0x0707)
+ * NVM Shadow RAM Dump commands (direct 0x0707)
*/
struct ice_aqc_nvm {
__le16 offset_low;
u8 offset_high;
u8 cmd_flags;
#define ICE_AQC_NVM_LAST_CMD BIT(0)
-#define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */
-#define ICE_AQC_NVM_PRESERVATION_S 1
+#define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */
+#define ICE_AQC_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */
#define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
#define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
#define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
#define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S)
#define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
+#define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */
+#define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4)
+#define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5)
+#define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3)
#define ICE_AQC_NVM_FLASH_ONLY BIT(7)
__le16 module_typeid;
__le16 length;
@@ -2292,6 +2305,7 @@ struct ice_aq_desc {
struct ice_aqc_set_mac_cfg set_mac_cfg;
struct ice_aqc_set_event_mask set_event_mask;
struct ice_aqc_get_link_status get_link_status;
+ struct ice_aqc_event_lan_overflow lan_overflow;
} params;
};
@@ -2465,10 +2479,14 @@ enum ice_adminq_opc {
/* NVM commands */
ice_aqc_opc_nvm_read = 0x0701,
ice_aqc_opc_nvm_erase = 0x0702,
- ice_aqc_opc_nvm_update = 0x0703,
+ ice_aqc_opc_nvm_write = 0x0703,
ice_aqc_opc_nvm_cfg_read = 0x0704,
ice_aqc_opc_nvm_cfg_write = 0x0705,
ice_aqc_opc_nvm_checksum = 0x0706,
+ ice_aqc_opc_nvm_write_activate = 0x0707,
+ ice_aqc_opc_nvm_sr_dump = 0x0707,
+ ice_aqc_opc_nvm_save_factory_settings = 0x0708,
+ ice_aqc_opc_nvm_update_empr = 0x0709,
/* LLDP commands */
ice_aqc_opc_lldp_get_mib = 0x0A00,
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 33/63] net/ice/base: set status when global cfg lock is unavailable
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (31 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 32/63] net/ice/base: add more opcode and macros Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 34/63] net/ice/base: initialize driver NVM data earlier Qi Zhang
` (30 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Anirudh Venkataramanan, Paul M Stillwell Jr
To download the DDP file to the device, a PF first has to grab the
global configuration lock. When a PF can't grab this lock, set
hw->pkg_dwnld_status to ICE_AQ_RC_EEXIST.
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flex_pipe.c | 15 ++++++++++++++-
drivers/net/ice/base/ice_type.h | 2 ++
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index 7daaf10b0..f8dd1c4d1 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -961,9 +961,19 @@ ice_dwnld_cfg_bufs(struct ice_hw *hw, struct ice_buf *bufs, u32 count)
if (LE32_TO_CPU(bh->section_entry[0].type) & ICE_METADATA_BUF)
return ICE_SUCCESS;
+ /* reset pkg_dwnld_status in case this function is called in the
+ * reset/rebuild flow
+ */
+ hw->pkg_dwnld_status = ICE_AQ_RC_OK;
+
status = ice_acquire_global_cfg_lock(hw, ICE_RES_WRITE);
- if (status)
+ if (status) {
+ if (status == ICE_ERR_AQ_NO_WORK)
+ hw->pkg_dwnld_status = ICE_AQ_RC_EEXIST;
+ else
+ hw->pkg_dwnld_status = hw->adminq.sq_last_status;
return status;
+ }
for (i = 0; i < count; i++) {
bool last = ((i + 1) == count);
@@ -986,6 +996,9 @@ ice_dwnld_cfg_bufs(struct ice_hw *hw, struct ice_buf *bufs, u32 count)
status = ice_aq_download_pkg(hw, bh, ICE_PKG_BUF_SIZE, last,
&offset, &info, NULL);
+
+ /* Save AQ status from download package */
+ hw->pkg_dwnld_status = hw->adminq.sq_last_status;
if (status) {
ice_debug(hw, ICE_DBG_PKG,
"Pkg download failed: err %d off %d inf %d\n",
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index dc041760d..541e29851 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -775,6 +775,8 @@ struct ice_hw {
u8 active_pkg_name[ICE_PKG_NAME_SIZE];
u8 active_pkg_in_nvm;
+ enum ice_aq_err pkg_dwnld_status;
+
/* Driver's package ver - (from the Metadata seg) */
struct ice_pkg_ver pkg_ver;
u8 pkg_name[ICE_PKG_NAME_SIZE];
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 34/63] net/ice/base: initialize driver NVM data earlier
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (32 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 33/63] net/ice/base: set status when global cfg lock is unavailable Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 35/63] net/ice/base: add function to configure Tx AQ command Qi Zhang
` (29 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Anirudh Venkataramanan, Paul M Stillwell Jr
The driver detects and warns about FW rollback mode before getting the NVM
version (through ice_init_nvm) which results in "0.00 0x0 0.0.0" being
printed. Fix this by calling ice_init_nvm earlier.
This could have been fixed by moving ice_print_rollback_msg as well, but
it made more sense to move ice_init_nvm closer to the flow that gets the
FW version information (i.e. control queue init flow).
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 36434ee42..e19ce733c 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -759,10 +759,13 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
if (status)
goto err_unroll_cqinit;
+ status = ice_init_nvm(hw);
+ if (status)
+ goto err_unroll_cqinit;
+
if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
ice_print_rollback_msg(hw);
-
status = ice_clear_pf_cfg(hw);
if (status)
goto err_unroll_cqinit;
@@ -773,9 +776,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
ice_clear_pxe_mode(hw);
- status = ice_init_nvm(hw);
- if (status)
- goto err_unroll_cqinit;
status = ice_get_caps(hw);
if (status)
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 35/63] net/ice/base: add function to configure Tx AQ command
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (33 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 34/63] net/ice/base: initialize driver NVM data earlier Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 36/63] net/ice/base: add support for not locking sideband queue Qi Zhang
` (28 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Ben Shelton, Paul M Stillwell Jr
This function is needed by the driver to move PSM leaf nodes to a new
parent.
Additionally, add struct ice_aqc_move_txqs to struct ice_aq_desc so
driver code can access it.
Signed-off-by: Ben Shelton <benjamin.h.shelton@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_adminq_cmd.h | 1 +
drivers/net/ice/base/ice_common.c | 71 +++++++++++++++++++++++++++++++++++
drivers/net/ice/base/ice_common.h | 6 +++
3 files changed, 78 insertions(+)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index b9e3bd5fa..9a063592f 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -2292,6 +2292,7 @@ struct ice_aq_desc {
struct ice_aqc_clear_fd_table clear_fd_table;
struct ice_aqc_add_txqs add_txqs;
struct ice_aqc_dis_txqs dis_txqs;
+ struct ice_aqc_move_txqs move_txqs;
struct ice_aqc_txqs_cleanup txqs_cleanup;
struct ice_aqc_add_get_update_free_vsi vsi_cmd;
struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index e19ce733c..c2d4f1f05 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -3415,6 +3415,77 @@ ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
return status;
}
+/**
+ * ice_aq_move_recfg_lan_txq
+ * @hw: pointer to the hardware structure
+ * @num_qs: number of queues to move/reconfigure
+ * @is_move: true if this operation involves node movement
+ * @is_tc_change: true if this operation involves a TC change
+ * @subseq_call: true if this operation is a subsequent call
+ * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN
+ * @timeout: timeout in units of 100 usec (valid values 0-50)
+ * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN
+ * @buf: struct containing src/dest TEID and per-queue info
+ * @buf_size: size of buffer for indirect command
+ * @txqs_moved: out param, number of queues successfully moved
+ * @cd: pointer to command details structure or NULL
+ *
+ * Move / Reconfigure Tx LAN queues (0x0C32)
+ */
+enum ice_status
+ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
+ bool is_tc_change, bool subseq_call, bool flush_pipe,
+ u8 timeout, u32 *blocked_cgds,
+ struct ice_aqc_move_txqs_data *buf, u16 buf_size,
+ u8 *txqs_moved, struct ice_sq_cd *cd)
+{
+ struct ice_aqc_move_txqs *cmd;
+ struct ice_aq_desc desc;
+ enum ice_status status;
+
+ cmd = &desc.params.move_txqs;
+ ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs);
+
+#define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50
+ if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX)
+ return ICE_ERR_PARAM;
+
+ if (is_tc_change && !flush_pipe && !blocked_cgds)
+ return ICE_ERR_PARAM;
+
+ if (!is_move && !is_tc_change)
+ return ICE_ERR_PARAM;
+
+ desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
+
+ if (is_move)
+ cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE;
+
+ if (is_tc_change)
+ cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE;
+
+ if (subseq_call)
+ cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL;
+
+ if (flush_pipe)
+ cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE;
+
+ cmd->num_qs = num_qs;
+ cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) &
+ ICE_AQC_Q_CMD_TIMEOUT_M);
+
+ status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
+
+ if (!status && txqs_moved)
+ *txqs_moved = cmd->num_qs;
+
+ if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN &&
+ is_tc_change && !flush_pipe)
+ *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds);
+
+ return status;
+}
+
/* End of FW Admin Queue command wrappers */
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index 67adc9c59..c42c58670 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -106,6 +106,12 @@ enum ice_status
ice_aq_add_lan_txq(struct ice_hw *hw, u8 count,
struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
struct ice_sq_cd *cd);
+enum ice_status
+ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
+ bool is_tc_change, bool subseq_call, bool flush_pipe,
+ u8 timeout, u32 *blocked_cgds,
+ struct ice_aqc_move_txqs_data *buf, u16 buf_size,
+ u8 *txqs_moved, struct ice_sq_cd *cd);
bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq);
enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 36/63] net/ice/base: add support for not locking sideband queue
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (34 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 35/63] net/ice/base: add function to configure Tx AQ command Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 37/63] net/ice/base: associate recipes by profile type Qi Zhang
` (27 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Ben Shelton, Paul M Stillwell Jr
For certain PTP clock adjustments, there is a use case for locking the
sideband queue at a higher level and performing an atomic series of
operations while the sideband queue is locked. To accommodate this use
case, split ice_sw_send_cmd() into a version that takes the lock and a
version that does not.
Signed-off-by: Ben Shelton <benjamin.h.shelton@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_controlq.c | 40 +++++++++++++++++++++++++++++++------
1 file changed, 34 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c
index 8070bb9a7..70a50bff4 100644
--- a/drivers/net/ice/base/ice_controlq.c
+++ b/drivers/net/ice/base/ice_controlq.c
@@ -859,7 +859,7 @@ static bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq)
}
/**
- * ice_sq_send_cmd - send command to Control Queue (ATQ)
+ * ice_sq_send_cmd_nolock - send command to Control Queue (ATQ)
* @hw: pointer to the HW struct
* @cq: pointer to the specific Control queue
* @desc: prefilled descriptor describing the command (non DMA mem)
@@ -870,10 +870,10 @@ static bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq)
* This is the main send command routine for the ATQ. It runs the queue,
* cleans the queue, etc.
*/
-enum ice_status
-ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
- struct ice_aq_desc *desc, void *buf, u16 buf_size,
- struct ice_sq_cd *cd)
+static enum ice_status
+ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
+ struct ice_aq_desc *desc, void *buf, u16 buf_size,
+ struct ice_sq_cd *cd)
{
struct ice_dma_mem *dma_buf = NULL;
struct ice_aq_desc *desc_on_ring;
@@ -887,7 +887,6 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
/* if reset is in progress return a soft error */
if (hw->reset_ongoing)
return ICE_ERR_RESET_ONGOING;
- ice_acquire_lock(&cq->sq_lock);
cq->sq_last_status = ICE_AQ_RC_OK;
@@ -1040,7 +1039,36 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
}
sq_send_command_error:
+ return status;
+}
+
+/**
+ * ice_sq_send_cmd - send command to Control Queue (ATQ)
+ * @hw: pointer to the HW struct
+ * @cq: pointer to the specific Control queue
+ * @desc: prefilled descriptor describing the command (non DMA mem)
+ * @buf: buffer to use for indirect commands (or NULL for direct commands)
+ * @buf_size: size of buffer for indirect commands (or 0 for direct commands)
+ * @cd: pointer to command details structure
+ *
+ * This is the main send command routine for the ATQ. It runs the queue,
+ * cleans the queue, etc.
+ */
+enum ice_status
+ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
+ struct ice_aq_desc *desc, void *buf, u16 buf_size,
+ struct ice_sq_cd *cd)
+{
+ enum ice_status status = ICE_SUCCESS;
+
+ /* if reset is in progress return a soft error */
+ if (hw->reset_ongoing)
+ return ICE_ERR_RESET_ONGOING;
+
+ ice_acquire_lock(&cq->sq_lock);
+ status = ice_sq_send_cmd_nolock(hw, cq, desc, buf, buf_size, cd);
ice_release_lock(&cq->sq_lock);
+
return status;
}
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 37/63] net/ice/base: associate recipes by profile type
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (35 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 36/63] net/ice/base: add support for not locking sideband queue Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 38/63] net/ice/base: return switch error on invalid match criteria Qi Zhang
` (26 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
Change recipe to profile association logic to determine the profile type
to determine if a profile is compatible with the rule being added.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flex_pipe.c | 87 ++++++++++++++++++++++++++++++--
drivers/net/ice/base/ice_flex_pipe.h | 5 +-
drivers/net/ice/base/ice_flex_type.h | 8 +++
drivers/net/ice/base/ice_protocol_type.h | 5 +-
drivers/net/ice/base/ice_switch.c | 54 ++++++++++++++++++--
5 files changed, 151 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index f8dd1c4d1..3beb4d961 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -1506,10 +1506,83 @@ ice_sw_fv_handler(u32 sect_type, void *section, u32 index, u32 *offset)
}
/**
+ * ice_get_sw_prof_type - determine switch profile type
+ * @hw: pointer to the HW structure
+ * @fv: pointer to the switch field vector
+ */
+static enum ice_prof_type
+ice_get_sw_prof_type(struct ice_hw *hw, struct ice_fv *fv)
+{
+ u16 i;
+
+ for (i = 0; i < hw->blk[ICE_BLK_SW].es.fvw; i++) {
+ /* UDP tunnel will have UDP_OF protocol ID and VNI offset */
+ if (fv->ew[i].prot_id == (u8)ICE_PROT_UDP_OF &&
+ fv->ew[i].off == ICE_VNI_OFFSET)
+ return ICE_PROF_TUN_UDP;
+
+ /* GRE tunnel will have GRE protocol */
+ if (fv->ew[i].prot_id == (u8)ICE_PROT_GRE_OF)
+ return ICE_PROF_TUN_GRE;
+
+ /* PPPOE tunnel will have PPPOE protocol */
+ if (fv->ew[i].prot_id == (u8)ICE_PROT_PPPOE)
+ return ICE_PROF_TUN_PPPOE;
+ }
+
+ return ICE_PROF_NON_TUN;
+}
+
+/**
+ * ice_get_sw_fv_bitmap - Get switch field vector bitmap based on profile type
+ * @hw: pointer to hardware structure
+ * @type: type of profiles requested
+ * @bm: pointer to memory for returning the bitmap of field vectors
+ */
+void
+ice_get_sw_fv_bitmap(struct ice_hw *hw, enum ice_prof_type type,
+ ice_bitmap_t *bm)
+{
+ struct ice_pkg_enum state;
+ struct ice_seg *ice_seg;
+ struct ice_fv *fv;
+
+ if (type == ICE_PROF_ALL) {
+ u16 i;
+
+ for (i = 0; i < ICE_MAX_NUM_PROFILES; i++)
+ ice_set_bit(i, bm);
+ return;
+ }
+
+ ice_zero_bitmap(bm, ICE_MAX_NUM_PROFILES);
+
+ ice_seg = hw->seg;
+ do {
+ enum ice_prof_type prof_type;
+ u32 offset;
+
+ fv = (struct ice_fv *)
+ ice_pkg_enum_entry(ice_seg, &state, ICE_SID_FLD_VEC_SW,
+ &offset, ice_sw_fv_handler);
+ ice_seg = NULL;
+
+ if (fv) {
+ /* Determine field vector type */
+ prof_type = ice_get_sw_prof_type(hw, fv);
+
+ if (type & prof_type)
+ ice_set_bit((u16)offset, bm);
+ }
+ } while (fv);
+}
+
+/**
* ice_get_sw_fv_list
* @hw: pointer to the HW structure
* @prot_ids: field vector to search for with a given protocol ID
* @ids_cnt: lookup/protocol count
+ * @bm: bitmap of field vectors to consider
* @fv_list: Head of a list
*
* Finds all the field vector entries from switch block that contain
@@ -1521,7 +1594,7 @@ ice_sw_fv_handler(u32 sect_type, void *section, u32 index, u32 *offset)
*/
enum ice_status
ice_get_sw_fv_list(struct ice_hw *hw, u16 *prot_ids, u8 ids_cnt,
- struct LIST_HEAD_TYPE *fv_list)
+ ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list)
{
struct ice_sw_fv_list_entry *fvl;
struct ice_sw_fv_list_entry *tmp;
@@ -1540,8 +1613,17 @@ ice_get_sw_fv_list(struct ice_hw *hw, u16 *prot_ids, u8 ids_cnt,
fv = (struct ice_fv *)
ice_pkg_enum_entry(ice_seg, &state, ICE_SID_FLD_VEC_SW,
&offset, ice_sw_fv_handler);
+ if (!fv)
+ break;
+ ice_seg = NULL;
- for (i = 0; i < ids_cnt && fv; i++) {
+ /* If field vector is not in the bitmap list, then skip this
+ * profile.
+ */
+ if (!ice_is_bit_set(bm, (u16)offset))
+ continue;
+
+ for (i = 0; i < ids_cnt; i++) {
int j;
/* This code assumes that if a switch field vector line
@@ -1565,7 +1647,6 @@ ice_get_sw_fv_list(struct ice_hw *hw, u16 *prot_ids, u8 ids_cnt,
break;
}
}
- ice_seg = NULL;
} while (fv);
if (LIST_EMPTY(fv_list))
return ICE_ERR_CFG;
diff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h
index 6af24653b..17285efe0 100644
--- a/drivers/net/ice/base/ice_flex_pipe.h
+++ b/drivers/net/ice/base/ice_flex_pipe.h
@@ -30,9 +30,12 @@ ice_find_prot_off(struct ice_hw *hw, enum ice_block blk, u8 prof, u8 fv_idx,
enum ice_status
ice_find_label_value(struct ice_seg *ice_seg, char const *name, u32 type,
u16 *value);
+void
+ice_get_sw_fv_bitmap(struct ice_hw *hw, enum ice_prof_type type,
+ ice_bitmap_t *bm);
enum ice_status
ice_get_sw_fv_list(struct ice_hw *hw, u16 *prot_ids, u8 ids_cnt,
- struct LIST_HEAD_TYPE *fv_list);
+ ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list);
enum ice_status
ice_create_tunnel(struct ice_hw *hw, enum ice_tunnel_type type, u16 port);
enum ice_status ice_destroy_tunnel(struct ice_hw *hw, u16 port, bool all);
diff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h
index 634897a28..3a70668d9 100644
--- a/drivers/net/ice/base/ice_flex_type.h
+++ b/drivers/net/ice/base/ice_flex_type.h
@@ -710,4 +710,12 @@ struct ice_chs_chg {
#define ICE_FLOW_PTYPE_MAX ICE_XLT1_CNT
+enum ice_prof_type {
+ ICE_PROF_NON_TUN = 0x1,
+ ICE_PROF_TUN_UDP = 0x2,
+ ICE_PROF_TUN_GRE = 0x4,
+ ICE_PROF_TUN_PPPOE = 0x8,
+ ICE_PROF_TUN_ALL = 0xE,
+ ICE_PROF_ALL = 0xFF,
+};
#endif /* _ICE_FLEX_TYPE_H_ */
diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h
index 29375d3ae..ee40bdc30 100644
--- a/drivers/net/ice/base/ice_protocol_type.h
+++ b/drivers/net/ice/base/ice_protocol_type.h
@@ -49,7 +49,8 @@ enum ice_protocol_type {
};
enum ice_sw_tunnel_type {
- ICE_NON_TUN,
+ ICE_NON_TUN = 0,
+ ICE_SW_TUN_AND_NON_TUN,
ICE_SW_TUN_VXLAN_GPE,
ICE_SW_TUN_GENEVE,
ICE_SW_TUN_VXLAN,
@@ -111,6 +112,8 @@ enum ice_prot_id {
ICE_PROT_INVALID = 255 /* when offset == 0xFF */
};
+#define ICE_VNI_OFFSET 12 /* offset of VNI from ICE_PROT_UDP_OF */
+
#define ICE_MAC_OFOS_HW 1
#define ICE_MAC_IL_HW 4
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 2b0c7c7a3..2a7ffc7aa 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -5463,11 +5463,12 @@ ice_create_recipe_group(struct ice_hw *hw, struct ice_sw_recipe *rm,
* @lkups: lookup elements or match criteria for the advanced recipe, one
* structure per protocol header
* @lkups_cnt: number of protocols
+ * @bm: bitmap of field vectors to consider
* @fv_list: pointer to a list that holds the returned field vectors
*/
static enum ice_status
ice_get_fv(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,
- struct LIST_HEAD_TYPE *fv_list)
+ ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list)
{
enum ice_status status;
u16 *prot_ids;
@@ -5484,13 +5485,53 @@ ice_get_fv(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,
}
/* Find field vectors that include all specified protocol types */
- status = ice_get_sw_fv_list(hw, prot_ids, lkups_cnt, fv_list);
+ status = ice_get_sw_fv_list(hw, prot_ids, lkups_cnt, bm, fv_list);
free_mem:
ice_free(hw, prot_ids);
return status;
}
+/* ice_get_compat_fv_bitmap - Get compatible field vector bitmap for rule
+ * @hw: pointer to hardware structure
+ * @rinfo: other information regarding the rule e.g. priority and action info
+ * @bm: pointer to memory for returning the bitmap of field vectors
+ */
+static void
+ice_get_compat_fv_bitmap(struct ice_hw *hw, struct ice_adv_rule_info *rinfo,
+ ice_bitmap_t *bm)
+{
+ enum ice_prof_type type;
+
+ switch (rinfo->tun_type) {
+ case ICE_NON_TUN:
+ type = ICE_PROF_NON_TUN;
+ break;
+ case ICE_ALL_TUNNELS:
+ type = ICE_PROF_TUN_ALL;
+ break;
+ case ICE_SW_TUN_VXLAN_GPE:
+ case ICE_SW_TUN_GENEVE:
+ case ICE_SW_TUN_VXLAN:
+ case ICE_SW_TUN_UDP:
+ case ICE_SW_TUN_GTP:
+ type = ICE_PROF_TUN_UDP;
+ break;
+ case ICE_SW_TUN_NVGRE:
+ type = ICE_PROF_TUN_GRE;
+ break;
+ case ICE_SW_TUN_PPPOE:
+ type = ICE_PROF_TUN_PPPOE;
+ break;
+ case ICE_SW_TUN_AND_NON_TUN:
+ default:
+ type = ICE_PROF_ALL;
+ break;
+ }
+
+ ice_get_sw_fv_bitmap(hw, type, bm);
+}
+
/**
* ice_add_adv_recipe - Add an advanced recipe that is not part of the default
* @hw: pointer to hardware structure
@@ -5504,6 +5545,7 @@ static enum ice_status
ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
u16 lkups_cnt, struct ice_adv_rule_info *rinfo, u16 *rid)
{
+ ice_declare_bitmap(fv_bitmap, ICE_MAX_NUM_PROFILES);
ice_declare_bitmap(profiles, ICE_MAX_NUM_PROFILES);
struct ice_prot_lkup_ext *lkup_exts;
struct ice_recp_grp_entry *r_entry;
@@ -5553,7 +5595,13 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
INIT_LIST_HEAD(&rm->fv_list);
INIT_LIST_HEAD(&rm->rg_list);
- status = ice_get_fv(hw, lkups, lkups_cnt, &rm->fv_list);
+ /* Get bitmap of field vectors (profiles) that are compatible with the
+ * rule request; only these will be searched in the subsequent call to
+ * ice_get_fv.
+ */
+ ice_get_compat_fv_bitmap(hw, rinfo, fv_bitmap);
+
+ status = ice_get_fv(hw, lkups, lkups_cnt, fv_bitmap, &rm->fv_list);
if (status)
goto err_unroll;
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 38/63] net/ice/base: return switch error on invalid match criteria
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (36 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 37/63] net/ice/base: associate recipes by profile type Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 39/63] net/ice/base: update UDP tunnel switch training packets Qi Zhang
` (25 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
Modify ice_add_adv_rule to return an error when an invalid match
criteria is requested by the caller. This happens when the protocol
and offset pair is not supported by the package.
This change required a fix for the offset in the VXLAN GPE header,
and also found an issue with NVGRE where the package does not seem
to extract the correct offsets.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 21 +++++++++++++++++----
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 2a7ffc7aa..bc7caf1a8 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -4651,7 +4651,7 @@ static const struct ice_prot_ext_tbl_entry ice_prot_ext[] = {
{ ICE_SCTP_IL, { 0, 2 } },
{ ICE_VXLAN, { 8, 10, 12, 14 } },
{ ICE_GENEVE, { 8, 10, 12, 14 } },
- { ICE_VXLAN_GPE, { 0, 2, 4 } },
+ { ICE_VXLAN_GPE, { 8, 10, 12, 14 } },
{ ICE_NVGRE, { 0, 2, 4, 6 } },
{ ICE_GTP, { 8, 10, 12, 14, 16, 18, 20 } },
{ ICE_PPPOE, { 0, 2, 4, 6 } },
@@ -4950,7 +4950,7 @@ ice_create_first_fit_recp_def(struct ice_hw *hw,
* Helper function to fill in the field vector indices for protocol-offset
* pairs. These indexes are then ultimately programmed into a recipe.
*/
-static void
+static enum ice_status
ice_fill_fv_word_index(struct ice_hw *hw, struct LIST_HEAD_TYPE *fv_list,
struct LIST_HEAD_TYPE *rg_list)
{
@@ -4959,7 +4959,7 @@ ice_fill_fv_word_index(struct ice_hw *hw, struct LIST_HEAD_TYPE *fv_list,
struct ice_fv_word *fv_ext;
if (LIST_EMPTY(fv_list))
- return;
+ return ICE_SUCCESS;
fv = LIST_FIRST_ENTRY(fv_list, struct ice_sw_fv_list_entry, list_entry);
fv_ext = fv->fv_ptr->ew;
@@ -4969,6 +4969,7 @@ ice_fill_fv_word_index(struct ice_hw *hw, struct LIST_HEAD_TYPE *fv_list,
for (i = 0; i < rg->r_group.n_val_pairs; i++) {
struct ice_fv_word *pr;
+ bool found = false;
u16 mask;
u8 j;
@@ -4978,6 +4979,8 @@ ice_fill_fv_word_index(struct ice_hw *hw, struct LIST_HEAD_TYPE *fv_list,
for (j = 0; j < hw->blk[ICE_BLK_SW].es.fvw; j++)
if (fv_ext[j].prot_id == pr->prot_id &&
fv_ext[j].off == pr->off) {
+ found = true;
+
/* Store index of field vector */
rg->fv_idx[i] = j;
/* Mask is given by caller as big
@@ -4987,8 +4990,16 @@ ice_fill_fv_word_index(struct ice_hw *hw, struct LIST_HEAD_TYPE *fv_list,
rg->fv_mask[i] = mask << 8 | mask >> 8;
break;
}
+
+ /* Protocol/offset could not be found, caller gave an
+ * invalid pair
+ */
+ if (!found)
+ return ICE_ERR_PARAM;
}
}
+
+ return ICE_SUCCESS;
}
/**
@@ -5627,7 +5638,9 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
/* Find offsets from the field vector. Pick the first one for all the
* recipes.
*/
- ice_fill_fv_word_index(hw, &rm->fv_list, &rm->rg_list);
+ status = ice_fill_fv_word_index(hw, &rm->fv_list, &rm->rg_list);
+ if (status)
+ goto err_unroll;
/* get bitmap of all profiles the recipe will be associated with */
ice_zero_bitmap(profiles, ICE_MAX_NUM_PROFILES);
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 39/63] net/ice/base: update UDP tunnel switch training packets
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (37 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 38/63] net/ice/base: return switch error on invalid match criteria Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 40/63] net/ice/base: improve switch chained recipe Qi Zhang
` (24 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
Change UDP tunnel training packets for the switch to work for both
Geneve and VXLAN cases.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index bc7caf1a8..65ec1bb93 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -179,7 +179,7 @@ u8 dummy_udp_tun_tcp_packet[] = {
0x00, 0x00, 0x12, 0xb5, /* ICE_UDP_OF 34 */
0x00, 0x46, 0x00, 0x00,
- 0x04, 0x00, 0x00, 0x03, /* ICE_VXLAN 42 */
+ 0x00, 0x00, 0x65, 0x58, /* ICE_VXLAN 42 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 50 */
@@ -230,7 +230,7 @@ u8 dummy_udp_tun_udp_packet[] = {
0x00, 0x00, 0x12, 0xb5, /* ICE_UDP_OF 34 */
0x00, 0x3a, 0x00, 0x00,
- 0x0c, 0x00, 0x00, 0x03, /* ICE_VXLAN 42 */
+ 0x00, 0x00, 0x65, 0x58, /* ICE_VXLAN 42 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 50 */
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 40/63] net/ice/base: improve switch chained recipe
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (38 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 39/63] net/ice/base: update UDP tunnel switch training packets Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 41/63] net/ice/base: move and add some help function and macros Qi Zhang
` (23 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
When updating switch database with chained recipes from
firmware, where a null pointer derefence was occurring due to looking
into a sub-recipe entry which is not filled in.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_protocol_type.h | 2 +
drivers/net/ice/base/ice_switch.c | 164 ++++++++++++++++++++-----------
2 files changed, 108 insertions(+), 58 deletions(-)
diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h
index ee40bdc30..91f56f3fa 100644
--- a/drivers/net/ice/base/ice_protocol_type.h
+++ b/drivers/net/ice/base/ice_protocol_type.h
@@ -135,6 +135,8 @@ enum ice_prot_id {
#define ICE_GRE_OF_HW 64 /* NVGRE */
#define ICE_META_DATA_ID_HW 255 /* this is used for tunnel type */
+#define ICE_MDID_SIZE 2
+#define ICE_TUN_FLAG_MDID 21
#define ICE_TUN_FLAG_MASK 0xFF
#define ICE_TUN_FLAG_FV_IND 2
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 65ec1bb93..b4f50e0e5 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -455,29 +455,24 @@ static void ice_get_recp_to_prof_map(struct ice_hw *hw);
static void ice_collect_result_idx(struct ice_aqc_recipe_data_elem *buf,
struct ice_sw_recipe *recp)
{
- if (buf->content.result_indx & ICE_AQ_RECIPE_ID_IS_ROOT)
+ if (buf->content.result_indx & ICE_AQ_RECIPE_RESULT_EN)
ice_set_bit(buf->content.result_indx &
- ~ICE_AQ_RECIPE_ID_IS_ROOT, recp->res_idxs);
+ ~ICE_AQ_RECIPE_RESULT_EN, recp->res_idxs);
}
/**
- * ice_collect_result_idx_from_bitmap - copy result index values using bitmap
- * @hw: pointer to hardware structure
- * @recp: the recipe struct to copy data into
+ * ice_init_possible_res_bm - initialize possible result bitmap
+ * @pos_result_bm: pointer to the bitmap to initialize
*/
-static void
-ice_collect_result_idx_from_bitmap(struct ice_hw *hw,
- struct ice_sw_recipe *recp)
+static void ice_init_possible_res_bm(ice_bitmap_t *pos_result_bm)
{
- u16 bit = 0;
+ u16 bit;
- while (ICE_MAX_NUM_RECIPES >
- (bit = ice_find_next_bit(recp->r_bitmap, ICE_MAX_NUM_RECIPES,
- bit))) {
- ice_collect_result_idx(hw->switch_info->recp_list[bit].root_buf,
- recp);
- bit++;
- }
+ ice_zero_bitmap(pos_result_bm, ICE_MAX_FV_WORDS);
+
+ for (bit = 0; bit < ICE_MAX_FV_WORDS; bit++)
+ if (ICE_POSSIBLE_RES_IDX & BIT_ULL(bit))
+ ice_set_bit(bit, pos_result_bm);
}
/**
@@ -495,14 +490,16 @@ static enum ice_status
ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
bool *refresh_required)
{
- u16 i, sub_recps, fv_word_idx = 0, result_idx = 0;
- ice_declare_bitmap(r_bitmap, ICE_MAX_NUM_PROFILES);
- u16 result_idxs[ICE_MAX_CHAIN_RECIPE] = { 0 };
+ ice_declare_bitmap(possible_idx, ICE_MAX_FV_WORDS);
+ ice_declare_bitmap(result_bm, ICE_MAX_FV_WORDS);
struct ice_aqc_recipe_data_elem *tmp;
u16 num_recps = ICE_MAX_NUM_RECIPES;
struct ice_prot_lkup_ext *lkup_exts;
+ u16 i, sub_recps, fv_word_idx = 0;
enum ice_status status;
- u8 is_root;
+
+ ice_zero_bitmap(result_bm, ICE_MAX_FV_WORDS);
+ ice_init_possible_res_bm(possible_idx);
/* we need a buffer big enough to accommodate all the recipes */
tmp = (struct ice_aqc_recipe_data_elem *)ice_calloc(hw,
@@ -528,14 +525,18 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
ice_get_recp_to_prof_map(hw);
*refresh_required = false;
}
- lkup_exts = &recps[rid].lkup_exts;
- /* start populating all the entries for recps[rid] based on lkups from
- * firmware
+
+ /* Start populating all the entries for recps[rid] based on lkups from
+ * firmware. Note that we are only creating the root recipe in our
+ * database.
*/
+ lkup_exts = &recps[rid].lkup_exts;
+
for (sub_recps = 0; sub_recps < num_recps; sub_recps++) {
struct ice_aqc_recipe_data_elem root_bufs = tmp[sub_recps];
struct ice_recp_grp_entry *rg_entry;
- u8 prof_id, prot = 0;
+ u8 prof_id, idx, prot = 0;
+ bool is_root;
u16 off = 0;
rg_entry = (struct ice_recp_grp_entry *)
@@ -544,15 +545,18 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
status = ICE_ERR_NO_MEMORY;
goto err_unroll;
}
- /* When copying, clear the result index enable bit */
- result_idxs[result_idx] = root_bufs.content.result_indx &
- ~ICE_AQ_RECIPE_RESULT_EN;
- ice_memcpy(r_bitmap,
- recipe_to_profile[tmp[sub_recps].recipe_indx],
- sizeof(r_bitmap), ICE_NONDMA_TO_NONDMA);
+ idx = root_bufs.recipe_indx;
+ is_root = root_bufs.content.rid & ICE_AQ_RECIPE_ID_IS_ROOT;
+
+ /* Mark all result indices in this chain */
+ if (root_bufs.content.result_indx & ICE_AQ_RECIPE_RESULT_EN)
+ ice_set_bit(root_bufs.content.result_indx &
+ ~ICE_AQ_RECIPE_RESULT_EN, result_bm);
+
/* get the first profile that is associated with rid */
- prof_id = ice_find_first_bit(r_bitmap, ICE_MAX_NUM_PROFILES);
+ prof_id = ice_find_first_bit(recipe_to_profile[idx],
+ ICE_MAX_NUM_PROFILES);
for (i = 0; i < ICE_NUM_WORDS_RECIPE; i++) {
u8 lkup_indx = root_bufs.content.lkup_indx[i + 1];
@@ -569,12 +573,8 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
* has ICE_AQ_RECIPE_LKUP_IGNORE or 0 since it isn't a
* valid offset value.
*/
- if (result_idxs[0] == rg_entry->fv_idx[i] ||
- result_idxs[1] == rg_entry->fv_idx[i] ||
- result_idxs[2] == rg_entry->fv_idx[i] ||
- result_idxs[3] == rg_entry->fv_idx[i] ||
- result_idxs[4] == rg_entry->fv_idx[i] ||
- rg_entry->fv_idx[i] == ICE_AQ_RECIPE_LKUP_IGNORE ||
+ if (ice_is_bit_set(possible_idx, rg_entry->fv_idx[i]) ||
+ rg_entry->fv_idx[i] & ICE_AQ_RECIPE_LKUP_IGNORE ||
rg_entry->fv_idx[i] == 0)
continue;
@@ -588,7 +588,29 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
* recipe
*/
LIST_ADD(&rg_entry->l_entry, &recps[rid].rg_list);
+
+ /* Propagate some data to the recipe database */
+ recps[idx].is_root = is_root;
+ recps[idx].priority = root_bufs.content.act_ctrl_fwd_priority;
+ if (root_bufs.content.result_indx & ICE_AQ_RECIPE_RESULT_EN)
+ recps[idx].chain_idx = root_bufs.content.result_indx &
+ ~ICE_AQ_RECIPE_RESULT_EN;
+ else
+ recps[idx].chain_idx = ICE_INVAL_CHAIN_IND;
+
+ if (!is_root)
+ continue;
+
+ /* Only do the following for root recipes entries */
+ ice_memcpy(recps[idx].r_bitmap, root_bufs.recipe_bitmap,
+ sizeof(recps[idx].r_bitmap), ICE_NONDMA_TO_NONDMA);
+ recps[idx].root_rid = root_bufs.content.rid &
+ ~ICE_AQ_RECIPE_ID_IS_ROOT;
+ recps[idx].priority = root_bufs.content.act_ctrl_fwd_priority;
+ recps[idx].big_recp = (recps[rid].n_grp_count > 1);
}
+
+ /* Complete initialization of the root recipe entry */
lkup_exts->n_val_words = fv_word_idx;
recps[rid].n_grp_count = num_recps;
recps[rid].root_buf = (struct ice_aqc_recipe_data_elem *)
@@ -600,26 +622,9 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
ice_memcpy(recps[rid].root_buf, tmp, recps[rid].n_grp_count *
sizeof(*recps[rid].root_buf), ICE_NONDMA_TO_NONDMA);
- ice_memcpy(recps[rid].r_bitmap, tmp->recipe_bitmap,
- sizeof(recps[rid].r_bitmap), ICE_NONDMA_TO_NONDMA);
-
- if (tmp->content.result_indx & ICE_AQ_RECIPE_RESULT_EN)
- recps[rid].chain_idx = tmp->content.result_indx &
- ~ICE_AQ_RECIPE_RESULT_EN;
- else
- recps[rid].chain_idx = ICE_INVAL_CHAIN_IND;
-
- recps[rid].root_rid = tmp->content.rid & ~ICE_AQ_RECIPE_ID_IS_ROOT;
- is_root = (tmp->content.rid & ICE_AQ_RECIPE_ID_IS_ROOT) != 0;
- recps[rid].is_root = is_root;
- recps[rid].big_recp = (is_root && recps[rid].n_grp_count > 1);
-
- /* Copy non-result fv index values to recipe. This call will also update
- * the result index bitmap appropriately.
- */
- ice_collect_result_idx_from_bitmap(hw, &recps[rid]);
-
- recps[rid].priority = tmp->content.act_ctrl_fwd_priority;
+ /* Copy result indexes */
+ ice_memcpy(recps[rid].res_idxs, result_bm, sizeof(recps[rid].res_idxs),
+ ICE_NONDMA_TO_NONDMA);
recps[rid].recp_created = true;
err_unroll:
@@ -5038,10 +5043,10 @@ ice_find_free_recp_res_idx(struct ice_hw *hw, const ice_bitmap_t *profiles,
u16 count = 0;
u16 bit;
- ice_zero_bitmap(possible_idx, ICE_MAX_FV_WORDS);
ice_zero_bitmap(free_idx, ICE_MAX_FV_WORDS);
ice_zero_bitmap(used_idx, ICE_MAX_FV_WORDS);
ice_zero_bitmap(recipes, ICE_MAX_NUM_RECIPES);
+ ice_init_possible_res_bm(possible_idx);
for (bit = 0; bit < ICE_MAX_FV_WORDS; bit++)
if (ICE_POSSIBLE_RES_IDX & BIT_ULL(bit))
@@ -5503,6 +5508,34 @@ ice_get_fv(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,
return status;
}
+/**
+ * ice_add_special_words - Add words that are not protocols, such as metadata
+ * @rinfo: other information regarding the rule e.g. priority and action info
+ * @lkup_exts: lookup word structure
+ */
+static enum ice_status
+ice_add_special_words(struct ice_adv_rule_info *rinfo,
+ struct ice_prot_lkup_ext *lkup_exts)
+{
+ /* If this is a tunneled packet, then add recipe index to match the
+ * tunnel bit in the packet metadata flags.
+ */
+ if (rinfo->tun_type != ICE_NON_TUN) {
+ if (lkup_exts->n_val_words < ICE_MAX_CHAIN_WORDS) {
+ u8 word = lkup_exts->n_val_words++;
+
+ lkup_exts->fv_words[word].prot_id = ICE_META_DATA_ID_HW;
+ lkup_exts->fv_words[word].off = ICE_TUN_FLAG_MDID *
+ ICE_MDID_SIZE;
+ lkup_exts->field_mask[word] = ICE_TUN_FLAG_MASK;
+ } else {
+ return ICE_ERR_MAX_LIMIT;
+ }
+ }
+
+ return ICE_SUCCESS;
+}
+
/* ice_get_compat_fv_bitmap - Get compatible field vector bitmap for rule
* @hw: pointer to hardware structure
* @rinfo: other information regarding the rule e.g. priority and action info
@@ -5650,6 +5683,13 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
ice_set_bit((u16)fvit->profile_id, profiles);
}
+ /* Create any special protocol/offset pairs, such as looking at tunnel
+ * bits by extracting metadata
+ */
+ status = ice_add_special_words(rinfo, lkup_exts);
+ if (status)
+ goto err_free_lkup_exts;
+
/* Look for a recipe which matches our requested fv / mask list */
*rid = ice_find_recp(hw, lkup_exts);
if (*rid < ICE_MAX_NUM_RECIPES)
@@ -6424,6 +6464,14 @@ ice_rem_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
if (!count)
return ICE_ERR_CFG;
}
+
+ /* Create any special protocol/offset pairs, such as looking at tunnel
+ * bits by extracting metadata
+ */
+ status = ice_add_special_words(rinfo, &lkup_exts);
+ if (status)
+ return status;
+
rid = ice_find_recp(hw, &lkup_exts);
/* If did not find a recipe that match the existing criteria */
if (rid == ICE_MAX_NUM_RECIPES)
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 41/63] net/ice/base: move and add some help function and macros
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (39 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 40/63] net/ice/base: improve switch chained recipe Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 42/63] net/ice/base: add routine for tunnel port query Qi Zhang
` (22 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Bruce Allan, Paul M Stillwell Jr
The patch move ice_ilog2 and ice_is_pow2 to ice_type.h, also add help
macro ROUND_UP and IS_ETHER_ADDR_EQUAL.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flow.c | 9 ---------
drivers/net/ice/base/ice_switch.c | 15 ---------------
drivers/net/ice/base/ice_type.h | 39 +++++++++++++++++++++++++++++++++++++++
3 files changed, 39 insertions(+), 24 deletions(-)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 9e93a1078..477cf5dfe 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -360,15 +360,6 @@ struct ice_flow_prof_params {
ice_declare_bitmap(ptypes, ICE_FLOW_PTYPE_MAX);
};
-/**
- * ice_is_pow2 - check if integer value is a power of 2
- * @val: unsigned integer to be validated
- */
-static bool ice_is_pow2(u64 val)
-{
- return (val && !(val & (val - 1)));
-}
-
#define ICE_FLOW_SEG_HDRS_L2_MASK \
(ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN)
#define ICE_FLOW_SEG_HDRS_L3_MASK \
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index b4f50e0e5..ef3a919ec 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -1849,21 +1849,6 @@ static void ice_fill_sw_info(struct ice_hw *hw, struct ice_fltr_info *fi)
}
/**
- * ice_ilog2 - Calculates integer log base 2 of a number
- * @n: number on which to perform operation
- */
-static int ice_ilog2(u64 n)
-{
- int i;
-
- for (i = 63; i >= 0; i--)
- if (((u64)1 << i) & n)
- return i;
-
- return -1;
-}
-
-/**
* ice_fill_sw_rule - Helper function to fill switch rule structure
* @hw: pointer to the hardware structure
* @f_info: entry containing packet forwarding information
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 541e29851..403fb7668 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -22,6 +22,16 @@
#define ICE_BYTES_PER_DWORD 4
#define ICE_MAX_TRAFFIC_CLASS 8
+/**
+ * ROUND_UP - round up to next arbitrary multiple (not a power of 2)
+ * @a: value to round up
+ * @b: arbitrary multiple
+ *
+ * Round up to the next multiple of the arbitrary b.
+ * Note, when b is a power of 2 use ICE_ALIGN() instead.
+ */
+#define ROUND_UP(a, b) ((b) * DIVIDE_AND_ROUND_UP((a), (b)))
+
#define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b))
#define IS_ASCII(_ch) ((_ch) < 0x80)
@@ -36,6 +46,30 @@
#include "ice_flex_type.h"
#include "ice_protocol_type.h"
+/**
+ * ice_is_pow2 - check if integer value is a power of 2
+ * @val: unsigned integer to be validated
+ */
+static inline bool ice_is_pow2(u64 val)
+{
+ return (val && !(val & (val - 1)));
+}
+
+/**
+ * ice_ilog2 - Calculates integer log base 2 of a number
+ * @n: number on which to perform operation
+ */
+static inline int ice_ilog2(u64 n)
+{
+ int i;
+
+ for (i = 63; i >= 0; i--)
+ if (((u64)1 << i) & n)
+ return i;
+
+ return -1;
+}
+
static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
{
return ice_is_bit_set(&bitmap, tc);
@@ -104,6 +138,11 @@ static inline u32 ice_round_to_num(u32 N, u32 R)
+#define IS_ETHER_ADDR_EQUAL(addr1, addr2) \
+ (((bool)((((u16 *)(addr1))[0] == ((u16 *)(addr2))[0]))) && \
+ ((bool)((((u16 *)(addr1))[1] == ((u16 *)(addr2))[1]))) && \
+ ((bool)((((u16 *)(addr1))[2] == ((u16 *)(addr2))[2]))))
+
enum ice_aq_res_ids {
ICE_NVM_RES_ID = 1,
ICE_SPD_RES_ID,
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 42/63] net/ice/base: add routine for tunnel port query
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (40 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 41/63] net/ice/base: move and add some help function and macros Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 43/63] net/ice/base: ptype group consolidation Qi Zhang
` (21 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
Add ice_get_open_tunnel_port routine, which can be used to find
an open tunnel port for creating switch and flow director training
packets.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flex_pipe.c | 22 ++++++++++++++++++++++
drivers/net/ice/base/ice_flex_pipe.h | 3 +++
2 files changed, 25 insertions(+)
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index 3beb4d961..8161ccaec 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -1874,6 +1874,28 @@ ice_find_free_tunnel_entry(struct ice_hw *hw, enum ice_tunnel_type type,
}
/**
+ * ice_get_tunnel_port - retrieve an open tunnel port
+ * @hw: pointer to the HW structure
+ * @type: tunnel type (TNL_ALL will return any open port)
+ * @port: returns open port
+ */
+bool
+ice_get_open_tunnel_port(struct ice_hw *hw, enum ice_tunnel_type type,
+ u16 *port)
+{
+ u16 i;
+
+ for (i = 0; i < hw->tnl.count && i < ICE_TUNNEL_MAX_ENTRIES; i++)
+ if (hw->tnl.tbl[i].valid && hw->tnl.tbl[i].in_use &&
+ (type == TNL_ALL || hw->tnl.tbl[i].type == type)) {
+ *port = hw->tnl.tbl[i].port;
+ return true;
+ }
+
+ return false;
+}
+
+/**
* ice_create_tunnel
* @hw: pointer to the HW structure
* @type: type of tunnel
diff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h
index 17285efe0..ab1663574 100644
--- a/drivers/net/ice/base/ice_flex_pipe.h
+++ b/drivers/net/ice/base/ice_flex_pipe.h
@@ -36,6 +36,9 @@ ice_get_sw_fv_bitmap(struct ice_hw *hw, enum ice_prof_type type,
enum ice_status
ice_get_sw_fv_list(struct ice_hw *hw, u16 *prot_ids, u8 ids_cnt,
ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list);
+bool
+ice_get_open_tunnel_port(struct ice_hw *hw, enum ice_tunnel_type type,
+ u16 *port);
enum ice_status
ice_create_tunnel(struct ice_hw *hw, enum ice_tunnel_type type, u16 port);
enum ice_status ice_destroy_tunnel(struct ice_hw *hw, u16 port, bool all);
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 43/63] net/ice/base: ptype group consolidation
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (41 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 42/63] net/ice/base: add routine for tunnel port query Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 44/63] net/ice/base: fix for RSS hash on inner UDP port Qi Zhang
` (20 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
This patch is an optimization to decrease the number of TCAM entries
used in the profile blocks, especially for RSS. To be most effective
this will also require a package change in order to decrease the number
of PTYPE groups necessary to program RSS, FD and ACL rules.
Change required package version to 1.3.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flex_pipe.c | 214 ++++++++++++++---------------------
drivers/net/ice/base/ice_flex_pipe.h | 2 +-
drivers/net/ice/base/ice_flex_type.h | 8 +-
3 files changed, 89 insertions(+), 135 deletions(-)
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index 8161ccaec..6ae71e698 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -2121,29 +2121,6 @@ void ice_ptg_alloc_val(struct ice_hw *hw, enum ice_block blk, u8 ptg)
hw->blk[blk].xlt1.ptg_tbl[ptg].in_use = true;
}
-/**
- * ice_ptg_alloc - Find a free entry and allocates a new packet type group ID
- * @hw: pointer to the hardware structure
- * @blk: HW block
- *
- * This function allocates and returns a new packet type group ID. Note
- * that 0 is the default packet type group, so successfully created PTGs will
- * have a non-zero ID value; which means a 0 return value indicates an error.
- */
-static u8 ice_ptg_alloc(struct ice_hw *hw, enum ice_block blk)
-{
- u16 i;
-
- /* Skip the default PTG of 0 */
- for (i = 1; i < ICE_MAX_PTGS; i++)
- if (!hw->blk[blk].xlt1.ptg_tbl[i].in_use) {
- /* found a free PTG ID */
- ice_ptg_alloc_val(hw, blk, i);
- return (u8)i;
- }
-
- return 0;
-}
/**
* ice_ptg_remove_ptype - Removes ptype from a particular packet type group
@@ -3884,43 +3861,6 @@ ice_vsig_get_ref(struct ice_hw *hw, enum ice_block blk, u16 vsig, u16 *refs)
}
/**
- * ice_get_ptg - get or allocate a ptg for a ptype
- * @hw: pointer to the hardware structure
- * @blk: HW block
- * @ptype: the ptype to retrieve the PTG for
- * @ptg: receives the PTG of the ptype
- * @add: receive boolean indicating whether PTG was added or not
- */
-static enum ice_status
-ice_get_ptg(struct ice_hw *hw, enum ice_block blk, u16 ptype, u8 *ptg,
- bool *add)
-{
- enum ice_status status;
-
- *ptg = ICE_DEFAULT_PTG;
- *add = false;
-
- status = ice_ptg_find_ptype(hw, blk, ptype, ptg);
- if (status)
- return status;
-
- if (*ptg == ICE_DEFAULT_PTG) {
- /* need to allocate a PTG, and add ptype to it */
- *ptg = ice_ptg_alloc(hw, blk);
- if (*ptg == ICE_DEFAULT_PTG)
- return ICE_ERR_HW_TABLE;
-
- status = ice_ptg_add_mv_ptype(hw, blk, ptype, *ptg);
- if (status)
- return ICE_ERR_HW_TABLE;
-
- *add = true;
- }
-
- return ICE_SUCCESS;
-};
-
-/**
* ice_has_prof_vsig - check to see if VSIG has a specific profile
* @hw: pointer to the hardware structure
* @blk: HW block
@@ -4420,11 +4360,14 @@ ice_add_prof_with_mask(struct ice_hw *hw, enum ice_block blk, u64 id,
u8 ptypes[], struct ice_fv_word *es, u16 *masks)
{
u32 bytes = DIVIDE_AND_ROUND_UP(ICE_FLOW_PTYPE_MAX, BITS_PER_BYTE);
+ ice_declare_bitmap(ptgs_used, ICE_XLT1_CNT);
struct ice_prof_map *prof;
enum ice_status status;
u32 byte = 0;
u8 prof_id;
+ ice_zero_bitmap(ptgs_used, ICE_XLT1_CNT);
+
ice_acquire_lock(&hw->blk[blk].es.prof_map_lock);
/* search for existing profile */
@@ -4464,11 +4407,11 @@ ice_add_prof_with_mask(struct ice_hw *hw, enum ice_block blk, u64 id,
prof->profile_cookie = id;
prof->prof_id = prof_id;
- prof->ptype_count = 0;
+ prof->ptg_cnt = 0;
prof->context = 0;
/* build list of ptgs */
- while (bytes && prof->ptype_count < ICE_MAX_PTYPE_PER_PROFILE) {
+ while (bytes && prof->ptg_cnt < ICE_MAX_PTG_PER_PROFILE) {
u32 bit;
if (!ptypes[byte]) {
@@ -4480,16 +4423,27 @@ ice_add_prof_with_mask(struct ice_hw *hw, enum ice_block blk, u64 id,
for (bit = 0; bit < 8; bit++) {
if (ptypes[byte] & BIT(bit)) {
u16 ptype;
+ u8 ptg;
u8 m;
ptype = byte * BITS_PER_BYTE + bit;
- if (ptype < ICE_FLOW_PTYPE_MAX) {
- prof->ptype[prof->ptype_count] = ptype;
- if (++prof->ptype_count >=
- ICE_MAX_PTYPE_PER_PROFILE)
- break;
- }
+ /* The package should place all ptypes in a
+ * non-zero PTG, so the following call should
+ * never fail.
+ */
+ if (ice_ptg_find_ptype(hw, blk, ptype, &ptg))
+ continue;
+
+ /* If PTG is already added, skip and continue */
+ if (ice_is_bit_set(ptgs_used, ptg))
+ continue;
+
+ ice_set_bit(ptg, ptgs_used);
+ prof->ptg[prof->ptg_cnt] = ptg;
+
+ if (++prof->ptg_cnt >= ICE_MAX_PTG_PER_PROFILE)
+ break;
/* nothing left in byte, then exit */
m = ~((1 << (bit + 1)) - 1);
@@ -4518,7 +4472,7 @@ ice_add_prof_with_mask(struct ice_hw *hw, enum ice_block blk, u64 id,
* @ptypes: array of bitmaps indicating ptypes (ICE_FLOW_PTYPE_MAX bits)
* @es: extraction sequence (length of array is determined by the block)
*
- * This function registers a profile, which matches a set of PTYPES with a
+ * This function registers a profile, which matches a set of PTGs with a
* particular extraction sequence. While the hardware profile is allocated
* it will not be written until the first call to ice_add_flow that specifies
* the ID value used here.
@@ -4528,11 +4482,14 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],
struct ice_fv_word *es)
{
u32 bytes = DIVIDE_AND_ROUND_UP(ICE_FLOW_PTYPE_MAX, BITS_PER_BYTE);
+ ice_declare_bitmap(ptgs_used, ICE_XLT1_CNT);
struct ice_prof_map *prof;
enum ice_status status;
u32 byte = 0;
u8 prof_id;
+ ice_zero_bitmap(ptgs_used, ICE_XLT1_CNT);
+
ice_acquire_lock(&hw->blk[blk].es.prof_map_lock);
/* search for existing profile */
@@ -4569,11 +4526,11 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],
prof->profile_cookie = id;
prof->prof_id = prof_id;
- prof->ptype_count = 0;
+ prof->ptg_cnt = 0;
prof->context = 0;
/* build list of ptgs */
- while (bytes && prof->ptype_count < ICE_MAX_PTYPE_PER_PROFILE) {
+ while (bytes && prof->ptg_cnt < ICE_MAX_PTG_PER_PROFILE) {
u32 bit;
if (!ptypes[byte]) {
@@ -4583,18 +4540,29 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],
}
/* Examine 8 bits per byte */
for (bit = 0; bit < 8; bit++) {
- if (ptypes[byte] & 1 << bit) {
+ if (ptypes[byte] & BIT(bit)) {
u16 ptype;
+ u8 ptg;
u8 m;
ptype = byte * BITS_PER_BYTE + bit;
- if (ptype < ICE_FLOW_PTYPE_MAX) {
- prof->ptype[prof->ptype_count] = ptype;
- if (++prof->ptype_count >=
- ICE_MAX_PTYPE_PER_PROFILE)
- break;
- }
+ /* The package should place all ptypes in a
+ * non-zero PTG, so the following call should
+ * never fail.
+ */
+ if (ice_ptg_find_ptype(hw, blk, ptype, &ptg))
+ continue;
+
+ /* If PTG is already added, skip and continue */
+ if (ice_is_bit_set(ptgs_used, ptg))
+ continue;
+
+ ice_set_bit(ptg, ptgs_used);
+ prof->ptg[prof->ptg_cnt] = ptg;
+
+ if (++prof->ptg_cnt >= ICE_MAX_PTG_PER_PROFILE)
+ break;
/* nothing left in byte, then exit */
m = ~((1 << (bit + 1)) - 1);
@@ -4722,10 +4690,13 @@ ice_rem_prof_id(struct ice_hw *hw, enum ice_block blk,
u16 i;
for (i = 0; i < prof->tcam_count; i++) {
- prof->tcam[i].in_use = false;
- status = ice_rel_tcam_idx(hw, blk, prof->tcam[i].tcam_idx);
- if (status)
- return ICE_ERR_HW_TABLE;
+ if (prof->tcam[i].in_use) {
+ prof->tcam[i].in_use = false;
+ status = ice_rel_tcam_idx(hw, blk,
+ prof->tcam[i].tcam_idx);
+ if (status)
+ return ICE_ERR_HW_TABLE;
+ }
}
return ICE_SUCCESS;
@@ -4905,15 +4876,15 @@ enum ice_status ice_rem_prof(struct ice_hw *hw, enum ice_block blk, u64 id)
}
/**
- * ice_get_prof_ptgs - get ptgs for profile
+ * ice_get_prof - get profile
* @hw: pointer to the HW struct
* @blk: hardware block
* @hdl: profile handle
* @chg: change list
*/
static enum ice_status
-ice_get_prof_ptgs(struct ice_hw *hw, enum ice_block blk, u64 hdl,
- struct LIST_HEAD_TYPE *chg)
+ice_get_prof(struct ice_hw *hw, enum ice_block blk, u64 hdl,
+ struct LIST_HEAD_TYPE *chg)
{
struct ice_prof_map *map;
struct ice_chs_chg *p;
@@ -4924,27 +4895,19 @@ ice_get_prof_ptgs(struct ice_hw *hw, enum ice_block blk, u64 hdl,
if (!map)
return ICE_ERR_DOES_NOT_EXIST;
- for (i = 0; i < map->ptype_count; i++) {
- enum ice_status status;
- bool add;
- u8 ptg;
-
- status = ice_get_ptg(hw, blk, map->ptype[i], &ptg, &add);
- if (status)
- goto err_ice_get_prof_ptgs;
-
- if (add || !hw->blk[blk].es.written[map->prof_id]) {
- /* add PTG to change list */
+ for (i = 0; i < map->ptg_cnt; i++) {
+ if (!hw->blk[blk].es.written[map->prof_id]) {
+ /* add ES to change list */
p = (struct ice_chs_chg *)ice_malloc(hw, sizeof(*p));
if (!p)
- goto err_ice_get_prof_ptgs;
+ goto err_ice_get_prof;
p->type = ICE_PTG_ES_ADD;
- p->ptype = map->ptype[i];
- p->ptg = ptg;
- p->add_ptg = add;
+ p->ptype = 0;
+ p->ptg = map->ptg[i];
+ p->add_ptg = 0;
- p->add_prof = !hw->blk[blk].es.written[map->prof_id];
+ p->add_prof = 1;
p->prof_id = map->prof_id;
hw->blk[blk].es.written[map->prof_id] = true;
@@ -4955,7 +4918,7 @@ ice_get_prof_ptgs(struct ice_hw *hw, enum ice_block blk, u64 hdl,
return ICE_SUCCESS;
-err_ice_get_prof_ptgs:
+err_ice_get_prof:
/* let caller clean up the change list */
return ICE_ERR_NO_MEMORY;
}
@@ -5026,20 +4989,12 @@ ice_add_prof_to_lst(struct ice_hw *hw, enum ice_block blk,
p->profile_cookie = map->profile_cookie;
p->prof_id = map->prof_id;
- p->tcam_count = map->ptype_count;
-
- for (i = 0; i < map->ptype_count; i++) {
- u8 ptg;
+ p->tcam_count = map->ptg_cnt;
+ for (i = 0; i < map->ptg_cnt; i++) {
p->tcam[i].prof_id = map->prof_id;
p->tcam[i].tcam_idx = ICE_INVALID_TCAM;
-
- if (ice_ptg_find_ptype(hw, blk, map->ptype[i], &ptg)) {
- ice_free(hw, p);
- return ICE_ERR_CFG;
- }
-
- p->tcam[i].ptg = ptg;
+ p->tcam[i].ptg = map->ptg[i];
}
LIST_ADD(&p->list, lst);
@@ -5110,12 +5065,19 @@ ice_prof_tcam_ena_dis(struct ice_hw *hw, enum ice_block blk, bool enable,
u8 nm_msk[ICE_TCAM_KEY_VAL_SZ] = { 0x00, 0x00, 0x00, 0x00, 0x00 };
u8 vl_msk[ICE_TCAM_KEY_VAL_SZ] = { 0x01, 0x00, 0x00, 0x00, 0x00 };
- /* If disabled, change the low flag bit to never match */
+ /* if disabling, free the tcam */
if (!enable) {
- dc_msk[0] = 0x00;
- nm_msk[0] = 0x01;
+ status = ice_free_tcam_ent(hw, blk, tcam->tcam_idx);
+ tcam->tcam_idx = 0;
+ tcam->in_use = 0;
+ return status;
}
+ /* for re-enabling, reallocate a tcam */
+ status = ice_alloc_tcam_ent(hw, blk, &tcam->tcam_idx);
+ if (status)
+ return status;
+
/* add TCAM to change list */
p = (struct ice_chs_chg *)ice_malloc(hw, sizeof(*p));
if (!p)
@@ -5127,7 +5089,7 @@ ice_prof_tcam_ena_dis(struct ice_hw *hw, enum ice_block blk, bool enable,
if (status)
goto err_ice_prof_tcam_ena_dis;
- tcam->in_use = enable;
+ tcam->in_use = 1;
p->type = ICE_TCAM_ADD;
p->add_tcam_idx = true;
@@ -5252,21 +5214,12 @@ ice_add_prof_id_vsig(struct ice_hw *hw, enum ice_block blk, u16 vsig, u64 hdl,
t->profile_cookie = map->profile_cookie;
t->prof_id = map->prof_id;
- t->tcam_count = map->ptype_count;
+ t->tcam_count = map->ptg_cnt;
/* create TCAM entries */
- for (i = 0; i < map->ptype_count; i++) {
+ for (i = 0; i < map->ptg_cnt; i++) {
enum ice_status status;
u16 tcam_idx;
- bool add;
- u8 ptg;
-
- /* If properly sequenced, we should never have to allocate new
- * PTGs
- */
- status = ice_get_ptg(hw, blk, map->ptype[i], &ptg, &add);
- if (status)
- goto err_ice_add_prof_id_vsig;
/* add TCAM to change list */
p = (struct ice_chs_chg *)ice_malloc(hw, sizeof(*p));
@@ -5280,7 +5233,7 @@ ice_add_prof_id_vsig(struct ice_hw *hw, enum ice_block blk, u16 vsig, u64 hdl,
goto err_ice_add_prof_id_vsig;
}
- t->tcam[i].ptg = ptg;
+ t->tcam[i].ptg = map->ptg[i];
t->tcam[i].prof_id = map->prof_id;
t->tcam[i].tcam_idx = tcam_idx;
t->tcam[i].in_use = true;
@@ -5497,7 +5450,8 @@ ice_add_prof_id_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u64 hdl)
INIT_LIST_HEAD(&chrs);
INIT_LIST_HEAD(&chg);
- status = ice_get_prof_ptgs(hw, blk, hdl, &chg);
+ /* Get profile */
+ status = ice_get_prof(hw, blk, hdl, &chg);
if (status)
return status;
diff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h
index ab1663574..3b5c1c39a 100644
--- a/drivers/net/ice/base/ice_flex_pipe.h
+++ b/drivers/net/ice/base/ice_flex_pipe.h
@@ -9,7 +9,7 @@
/* Package minimal version supported */
#define ICE_PKG_SUPP_VER_MAJ 1
-#define ICE_PKG_SUPP_VER_MNR 2
+#define ICE_PKG_SUPP_VER_MNR 3
/* Package format version */
#define ICE_PKG_FMT_VER_MAJ 1
diff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h
index 3a70668d9..baf53d881 100644
--- a/drivers/net/ice/base/ice_flex_type.h
+++ b/drivers/net/ice/base/ice_flex_type.h
@@ -518,16 +518,16 @@ struct ice_ptg_ptype {
u8 ptg;
};
-#define ICE_MAX_TCAM_PER_PROFILE 8
-#define ICE_MAX_PTYPE_PER_PROFILE 8
+#define ICE_MAX_TCAM_PER_PROFILE 32
+#define ICE_MAX_PTG_PER_PROFILE 32
struct ice_prof_map {
struct LIST_ENTRY_TYPE list;
u64 profile_cookie;
u64 context;
u8 prof_id;
- u8 ptype_count;
- u16 ptype[ICE_MAX_PTYPE_PER_PROFILE];
+ u8 ptg_cnt;
+ u8 ptg[ICE_MAX_PTG_PER_PROFILE];
};
#define ICE_INVALID_TCAM 0xFFFF
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 44/63] net/ice/base: fix for RSS hash on inner UDP port
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (42 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 43/63] net/ice/base: ptype group consolidation Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 45/63] net/ice/base: packet encapsulation for RSS Qi Zhang
` (19 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, stable, Zhirun Yan, Paul M Stillwell Jr
Before this patch, only outer IP with inner UDP port can appear in
RSS hash, because the extraction sequence uses outer IP protocol
ID with Inner UDP protocol ID. ICE_PROT_UDP_OF always extracts the
TUNNELED UDP port values (i.e., 4789 for VXLAN). ICE_PROT_UDP_IL_OR_S
will extract NON-TUNNELED UDP port or inner UDP port.
Fixes: aa1cd410fa64 ("net/ice/base: add flow module")
Cc: stable@dpdk.org
Signed-off-by: Zhirun Yan <zhirun.yan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flow.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 477cf5dfe..9a35a11d5 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -670,7 +670,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,
break;
case ICE_FLOW_FIELD_IDX_UDP_SRC_PORT:
case ICE_FLOW_FIELD_IDX_UDP_DST_PORT:
- prot_id = seg == 0 ? ICE_PROT_UDP_IL_OR_S : ICE_PROT_UDP_OF;
+ prot_id = ICE_PROT_UDP_IL_OR_S;
break;
case ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT:
case ICE_FLOW_FIELD_IDX_SCTP_DST_PORT:
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 45/63] net/ice/base: packet encapsulation for RSS
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (43 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 44/63] net/ice/base: fix for RSS hash on inner UDP port Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 46/63] net/ice/base: add RSS support for PPPoE and GTPU Qi Zhang
` (18 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Vignesh Sridhar, Paul M Stillwell Jr
RSS configurations calls currently support only non-tunneled packets,
which uses outer-first IPs. Adding another call to configure RSS for
tunneled packets which will enable hashing on inner-last IP. RSS hash
will only be done on the innermost IP.
- Update RSS configuration calls to take packet segment count as input
argument
- Update flow profile ID to include identifier for encapsulated packet
[0:31] : Packet match fields
[32:62]: Protocol header header
[63]: Encapsulation flag, 0 if non-tunneled, 1 if tunneled
Signed-off-by: Vignesh Sridhar <vignesh.sridhar@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flow.c | 132 ++++++++++++++++++++++++----------------
1 file changed, 80 insertions(+), 52 deletions(-)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 9a35a11d5..a49196c1c 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -379,16 +379,9 @@ struct ice_flow_prof_params {
static enum ice_status
ice_flow_val_hdrs(struct ice_flow_seg_info *segs, u8 segs_cnt)
{
- const u32 masks = (ICE_FLOW_SEG_HDRS_L2_MASK |
- ICE_FLOW_SEG_HDRS_L3_MASK |
- ICE_FLOW_SEG_HDRS_L4_MASK);
u8 i;
for (i = 0; i < segs_cnt; i++) {
- /* No header specified */
- if (!(segs[i].hdrs & masks) || (segs[i].hdrs & ~masks))
- return ICE_ERR_PARAM;
-
/* Multiple L3 headers */
if (segs[i].hdrs & ICE_FLOW_SEG_HDRS_L3_MASK &&
!ice_is_pow2(segs[i].hdrs & ICE_FLOW_SEG_HDRS_L3_MASK))
@@ -1866,11 +1859,22 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof)
#define ICE_FLOW_PROF_HASH_S 0
#define ICE_FLOW_PROF_HASH_M (0xFFFFFFFFULL << ICE_FLOW_PROF_HASH_S)
#define ICE_FLOW_PROF_HDR_S 32
-#define ICE_FLOW_PROF_HDR_M (0xFFFFFFFFULL << ICE_FLOW_PROF_HDR_S)
+#define ICE_FLOW_PROF_HDR_M (0x3FFFFFFFULL << ICE_FLOW_PROF_HDR_S)
+#define ICE_FLOW_PROF_ENCAP_S 63
+#define ICE_FLOW_PROF_ENCAP_M (BIT_ULL(ICE_FLOW_PROF_ENCAP_S))
+
+#define ICE_RSS_OUTER_HEADERS 1
+#define ICE_RSS_INNER_HEADERS 2
-#define ICE_FLOW_GEN_PROFID(hash, hdr) \
+/* Flow profile ID format:
+ * [0:31] - Packet match fields
+ * [32:62] - Protocol header
+ * [63] - Encapsulation flag, 0 if non-tunneled, 1 if tunneled
+ */
+#define ICE_FLOW_GEN_PROFID(hash, hdr, segs_cnt) \
(u64)(((u64)(hash) & ICE_FLOW_PROF_HASH_M) | \
- (((u64)(hdr) << ICE_FLOW_PROF_HDR_S) & ICE_FLOW_PROF_HDR_M))
+ (((u64)(hdr) << ICE_FLOW_PROF_HDR_S) & ICE_FLOW_PROF_HDR_M) | \
+ ((u8)((segs_cnt) - 1) ? ICE_FLOW_PROF_ENCAP_M : 0))
/**
* ice_add_rss_cfg_sync - add an RSS configuration
@@ -1878,24 +1882,30 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof)
* @vsi_handle: software VSI handle
* @hashed_flds: hash bit fields (ICE_FLOW_HASH_*) to configure
* @addl_hdrs: protocol header fields
+ * @segs_cnt: packet segment count
*
* Assumption: lock has already been acquired for RSS list
*/
static enum ice_status
ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
- u32 addl_hdrs)
+ u32 addl_hdrs, u8 segs_cnt)
{
const enum ice_block blk = ICE_BLK_RSS;
struct ice_flow_prof *prof = NULL;
struct ice_flow_seg_info *segs;
enum ice_status status = ICE_SUCCESS;
- segs = (struct ice_flow_seg_info *)ice_malloc(hw, sizeof(*segs));
+ if (!segs_cnt || segs_cnt > ICE_FLOW_SEG_MAX)
+ return ICE_ERR_PARAM;
+
+ segs = (struct ice_flow_seg_info *)ice_calloc(hw, segs_cnt,
+ sizeof(*segs));
if (!segs)
return ICE_ERR_NO_MEMORY;
/* Construct the packet segment info from the hashed fields */
- status = ice_flow_set_rss_seg_info(segs, hashed_flds, addl_hdrs);
+ status = ice_flow_set_rss_seg_info(&segs[segs_cnt - 1], hashed_flds,
+ addl_hdrs);
if (status)
goto exit;
@@ -1903,7 +1913,7 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
* and has the input VSI associated to it. If found, no further
* operations required and exit.
*/
- prof = ice_flow_find_prof_conds(hw, blk, ICE_FLOW_RX, segs, 1,
+ prof = ice_flow_find_prof_conds(hw, blk, ICE_FLOW_RX, segs, segs_cnt,
vsi_handle,
ICE_FLOW_FIND_PROF_CHK_FLDS |
ICE_FLOW_FIND_PROF_CHK_VSI);
@@ -1915,7 +1925,7 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
* this profile. The VSI will be added to a new profile created with
* the protocol header and new hash field configuration.
*/
- prof = ice_flow_find_prof_conds(hw, blk, ICE_FLOW_RX, segs, 1,
+ prof = ice_flow_find_prof_conds(hw, blk, ICE_FLOW_RX, segs, segs_cnt,
vsi_handle, ICE_FLOW_FIND_PROF_CHK_VSI);
if (prof) {
status = ice_flow_disassoc_prof(hw, blk, prof, vsi_handle);
@@ -1935,7 +1945,7 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
/* Search for a profile that has same match fields only. If this
* exists then associate the VSI to this profile.
*/
- prof = ice_flow_find_prof_conds(hw, blk, ICE_FLOW_RX, segs, 1,
+ prof = ice_flow_find_prof_conds(hw, blk, ICE_FLOW_RX, segs, segs_cnt,
vsi_handle,
ICE_FLOW_FIND_PROF_CHK_FLDS);
if (prof) {
@@ -1949,8 +1959,10 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
* segment information.
*/
status = ice_flow_add_prof(hw, blk, ICE_FLOW_RX,
- ICE_FLOW_GEN_PROFID(hashed_flds, segs->hdrs),
- segs, 1, NULL, 0, &prof);
+ ICE_FLOW_GEN_PROFID(hashed_flds,
+ segs[segs_cnt - 1].hdrs,
+ segs_cnt),
+ segs, segs_cnt, NULL, 0, &prof);
if (status)
goto exit;
@@ -1992,7 +2004,11 @@ ice_add_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
return ICE_ERR_PARAM;
ice_acquire_lock(&hw->rss_locks);
- status = ice_add_rss_cfg_sync(hw, vsi_handle, hashed_flds, addl_hdrs);
+ status = ice_add_rss_cfg_sync(hw, vsi_handle, hashed_flds, addl_hdrs,
+ ICE_RSS_OUTER_HEADERS);
+ if (!status)
+ status = ice_add_rss_cfg_sync(hw, vsi_handle, hashed_flds,
+ addl_hdrs, ICE_RSS_INNER_HEADERS);
ice_release_lock(&hw->rss_locks);
return status;
@@ -2004,12 +2020,13 @@ ice_add_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
* @vsi_handle: software VSI handle
* @hashed_flds: Packet hash types (ICE_FLOW_HASH_*) to remove
* @addl_hdrs: Protocol header fields within a packet segment
+ * @segs_cnt: packet segment count
*
* Assumption: lock has already been acquired for RSS list
*/
static enum ice_status
ice_rem_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
- u32 addl_hdrs)
+ u32 addl_hdrs, u8 segs_cnt)
{
const enum ice_block blk = ICE_BLK_RSS;
struct ice_flow_seg_info *segs;
@@ -2025,7 +2042,7 @@ ice_rem_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
if (status)
goto out;
- prof = ice_flow_find_prof_conds(hw, blk, ICE_FLOW_RX, segs, 1,
+ prof = ice_flow_find_prof_conds(hw, blk, ICE_FLOW_RX, segs, segs_cnt,
vsi_handle,
ICE_FLOW_FIND_PROF_CHK_FLDS);
if (!prof) {
@@ -2050,6 +2067,40 @@ ice_rem_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
return status;
}
+/**
+ * ice_rem_rss_cfg - remove an existing RSS config with matching hashed fields
+ * @hw: pointer to the hardware structure
+ * @vsi_handle: software VSI handle
+ * @hashed_flds: Packet hash types (ICE_FLOW_HASH_*) to remove
+ * @addl_hdrs: Protocol header fields within a packet segment
+ *
+ * This function will lookup the flow profile based on the input
+ * hash field bitmap, iterate through the profile entry list of
+ * that profile and find entry associated with input VSI to be
+ * removed. Calls are made to underlying flow apis which will in
+ * turn build or update buffers for RSS XLT1 section.
+ */
+enum ice_status
+ice_rem_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
+ u32 addl_hdrs)
+{
+ enum ice_status status;
+
+ if (hashed_flds == ICE_HASH_INVALID ||
+ !ice_is_vsi_valid(hw, vsi_handle))
+ return ICE_ERR_PARAM;
+
+ ice_acquire_lock(&hw->rss_locks);
+ status = ice_rem_rss_cfg_sync(hw, vsi_handle, hashed_flds, addl_hdrs,
+ ICE_RSS_OUTER_HEADERS);
+ if (!status)
+ status = ice_rem_rss_cfg_sync(hw, vsi_handle, hashed_flds,
+ addl_hdrs, ICE_RSS_INNER_HEADERS);
+ ice_release_lock(&hw->rss_locks);
+
+ return status;
+}
+
/* Mapping of AVF hash bit fields to an L3-L4 hash combination.
* As the ice_flow_avf_hdr_field represent individual bit shifts in a hash,
* convert its values to their appropriate flow L3, L4 values.
@@ -2179,36 +2230,6 @@ ice_add_avf_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 avf_hash)
}
/**
- * ice_rem_rss_cfg - remove an existing RSS config with matching hashed fields
- * @hw: pointer to the hardware structure
- * @vsi_handle: software VSI handle
- * @hashed_flds: Packet hash types (ICE_FLOW_HASH_*) to remove
- * @addl_hdrs: Protocol header fields within a packet segment
- *
- * This function will lookup the flow profile based on the input
- * hash field bitmap, iterate through the profile entry list of
- * that profile and find entry associated with input VSI to be
- * removed. Calls are made to underlying flow apis which will in
- * turn build or update buffers for RSS XLT1 section.
- */
-enum ice_status
-ice_rem_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
- u32 addl_hdrs)
-{
- enum ice_status status;
-
- if (hashed_flds == ICE_HASH_INVALID ||
- !ice_is_vsi_valid(hw, vsi_handle))
- return ICE_ERR_PARAM;
-
- ice_acquire_lock(&hw->rss_locks);
- status = ice_rem_rss_cfg_sync(hw, vsi_handle, hashed_flds, addl_hdrs);
- ice_release_lock(&hw->rss_locks);
-
- return status;
-}
-
-/**
* ice_replay_rss_cfg - replay RSS configurations associated with VSI
* @hw: pointer to the hardware structure
* @vsi_handle: software VSI handle
@@ -2227,7 +2248,14 @@ enum ice_status ice_replay_rss_cfg(struct ice_hw *hw, u16 vsi_handle)
if (ice_is_bit_set(r->vsis, vsi_handle)) {
status = ice_add_rss_cfg_sync(hw, vsi_handle,
r->hashed_flds,
- r->packet_hdr);
+ r->packet_hdr,
+ ICE_RSS_OUTER_HEADERS);
+ if (status)
+ break;
+ status = ice_add_rss_cfg_sync(hw, vsi_handle,
+ r->hashed_flds,
+ r->packet_hdr,
+ ICE_RSS_INNER_HEADERS);
if (status)
break;
}
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 46/63] net/ice/base: add RSS support for PPPoE and GTPU
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (44 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 45/63] net/ice/base: packet encapsulation for RSS Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 47/63] net/ice/base: remove unnecessary conditional check Qi Zhang
` (17 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Zhirun Yan, Paul M Stillwell Jr
Added RSS support for PPPoE with inner TCP and UDP.
Added RSS support for GTPU with IPv4 and IPv6.
Signed-off-by: Zhirun Yan <zhirun.yan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flow.c | 38 ++++++++++++++++++++++++++++----------
drivers/net/ice/base/ice_flow.h | 17 +++++++++++++++--
2 files changed, 43 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index a49196c1c..f71ac50d6 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -167,7 +167,7 @@ static const u32 ice_ptypes_macvlan_il[] = {
static const u32 ice_ptypes_ipv4_ofos[] = {
0xFDC00000, 0xBFBF7F7E, 0x00EFDFDF, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x0003000F, 0x00000000, 0x00000000, 0x00000000,
+ 0x0003000F, 0x000FC000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -179,7 +179,7 @@ static const u32 ice_ptypes_ipv4_ofos[] = {
static const u32 ice_ptypes_ipv4_il[] = {
0xE0000000, 0xB807700E, 0x8001DC03, 0xE01DC03B,
0x0007700E, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x000FF800, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -191,7 +191,7 @@ static const u32 ice_ptypes_ipv4_il[] = {
static const u32 ice_ptypes_ipv6_ofos[] = {
0x00000000, 0x00000000, 0xF7000000, 0xFEFDFDFB,
0x03BF7F7E, 0x00000000, 0x00000000, 0x00000000,
- 0x00080F00, 0x00000000, 0x00000000, 0x00000000,
+ 0x00080F00, 0x03F00000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -203,7 +203,7 @@ static const u32 ice_ptypes_ipv6_ofos[] = {
static const u32 ice_ptypes_ipv6_il[] = {
0x00000000, 0x03B80770, 0x00EE01DC, 0x0EE00000,
0x03B80770, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x7FE00000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -229,7 +229,7 @@ static const u32 ice_ptypes_arp_of[] = {
static const u32 ice_ptypes_udp_il[] = {
0x81000000, 0x20204040, 0x04081010, 0x80810102,
0x00204040, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00410000, 0x10842000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -241,7 +241,7 @@ static const u32 ice_ptypes_udp_il[] = {
static const u32 ice_ptypes_tcp_il[] = {
0x04000000, 0x80810102, 0x10204040, 0x42040408,
0x00810102, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00820000, 0x21084000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -277,7 +277,7 @@ static const u32 ice_ptypes_icmp_of[] = {
static const u32 ice_ptypes_icmp_il[] = {
0x00000000, 0x02040408, 0x40810102, 0x08101020,
0x02040408, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x42108000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -345,6 +345,18 @@ static const u32 ice_ptypes_gtpu[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
+/* Packet types for pppoe */
+static const u32 ice_ptypes_pppoe[] = {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x03FFF000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
/* Manage parameters and info. used during the creation of a flow profile */
struct ice_flow_prof_params {
enum ice_block blk;
@@ -368,8 +380,7 @@ struct ice_flow_prof_params {
#define ICE_FLOW_SEG_HDRS_L4_MASK \
(ICE_FLOW_SEG_HDR_ICMP | ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_UDP | \
ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_GTPC | \
- ICE_FLOW_SEG_HDR_GTPC_TEID | ICE_FLOW_SEG_HDR_GTPU_IP | \
- ICE_FLOW_SEG_HDR_GTPU_UP | ICE_FLOW_SEG_HDR_GTPU_DWN)
+ ICE_FLOW_SEG_HDR_GTPC_TEID | ICE_FLOW_SEG_HDR_GTPU)
/**
* ice_flow_val_hdrs - validates packet segments for valid protocol headers
@@ -487,6 +498,12 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params)
ICE_FLOW_PTYPE_MAX);
}
+ if (hdrs & ICE_FLOW_SEG_HDR_PPPOE) {
+ src = (const ice_bitmap_t *)ice_ptypes_pppoe;
+ ice_and_bitmap(params->ptypes, params->ptypes, src,
+ ICE_FLOW_PTYPE_MAX);
+ }
+
if (hdrs & ICE_FLOW_SEG_HDR_IPV4) {
src = !i ? (const ice_bitmap_t *)ice_ptypes_ipv4_ofos :
(const ice_bitmap_t *)ice_ptypes_ipv4_il;
@@ -1670,7 +1687,8 @@ ice_flow_add_fld_raw(struct ice_flow_seg_info *seg, u16 off, u8 len,
#define ICE_FLOW_RSS_SEG_HDR_L4_MASKS \
(ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_UDP | \
- ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_GTPC_TEID)
+ ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_GTPC_TEID | \
+ ICE_FLOW_SEG_HDR_GTPU)
#define ICE_FLOW_RSS_SEG_HDR_VAL_MASKS \
diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h
index eb8e1b733..0bb3efca0 100644
--- a/drivers/net/ice/base/ice_flow.h
+++ b/drivers/net/ice/base/ice_flow.h
@@ -42,15 +42,28 @@
#define ICE_HASH_SCTP_IPV6 (ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_SCTP_PORT)
#define ICE_FLOW_HASH_GTP_TEID \
- (ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_GTPC_TEID))
+ (BIT_ULL(ICE_FLOW_FIELD_IDX_GTPC_TEID))
#define ICE_FLOW_HASH_GTP_IPV4_TEID \
(ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_GTP_TEID)
#define ICE_FLOW_HASH_GTP_IPV6_TEID \
(ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_GTP_TEID)
+#define ICE_FLOW_HASH_GTP_U_TEID \
+ (BIT_ULL(ICE_FLOW_FIELD_IDX_GTPU_IP_TEID))
+
+#define ICE_FLOW_HASH_GTP_U_IPV4_TEID \
+ (ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_GTP_U_TEID)
+#define ICE_FLOW_HASH_GTP_U_IPV6_TEID \
+ (ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_GTP_U_TEID)
+
#define ICE_FLOW_HASH_PPPOE_SESS_ID \
- (ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID))
+ (BIT_ULL(ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID))
+
+#define ICE_FLOW_HASH_PPPOE_TCP_ID \
+ (ICE_FLOW_HASH_TCP_PORT | ICE_FLOW_HASH_PPPOE_SESS_ID)
+#define ICE_FLOW_HASH_PPPOE_UDP_ID \
+ (ICE_FLOW_HASH_UDP_PORT | ICE_FLOW_HASH_PPPOE_SESS_ID)
/* Protocol header fields within a packet segment. A segment consists of one or
* more protocol headers that make up a logical group of protocol headers. Each
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 47/63] net/ice/base: remove unnecessary conditional check
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (45 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 46/63] net/ice/base: add RSS support for PPPoE and GTPU Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 48/63] net/ice/base: fix flag settings in AQ call Qi Zhang
` (16 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Bruce Allan, Paul M Stillwell Jr
There is no reason to do this conditional check before the assignment so
simply remove it.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index ef3a919ec..a4966d0a1 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -1145,8 +1145,7 @@ ice_add_vsi(struct ice_hw *hw, u16 vsi_handle, struct ice_vsi_ctx *vsi_ctx,
ice_save_vsi_ctx(hw, vsi_handle, tmp_vsi_ctx);
} else {
/* update with new HW VSI num */
- if (tmp_vsi_ctx->vsi_num != vsi_ctx->vsi_num)
- tmp_vsi_ctx->vsi_num = vsi_ctx->vsi_num;
+ tmp_vsi_ctx->vsi_num = vsi_ctx->vsi_num;
}
return ICE_SUCCESS;
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 48/63] net/ice/base: fix flag settings in AQ call
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (46 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 47/63] net/ice/base: remove unnecessary conditional check Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 49/63] net/ice/base: refactor removal of VLAN promiscuous rules Qi Zhang
` (15 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, stable, Dan Nowlin, Paul M Stillwell Jr
Removed setting Read flag in the Get Allocated Resource Descriptors AQ
command (0x020A). The read flag is not required for this command and
causes the FW to return an error.
Fixes: d781ccbdd15d ("net/ice/base: add functions to get allocated resources")
Cc: stable@dpdk.org
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index a4966d0a1..9e85da530 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -2978,8 +2978,6 @@ ice_aq_get_res_descs(struct ice_hw *hw, u16 num_entries,
ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
cmd->ops.cmd.first_desc = CPU_TO_LE16(*desc_id);
- desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
-
status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
if (!status)
*desc_id = LE16_TO_CPU(cmd->ops.resp.next_desc);
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 49/63] net/ice/base: refactor removal of VLAN promiscuous rules
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (47 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 48/63] net/ice/base: fix flag settings in AQ call Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 50/63] net/ice/base: maximize switch recipe words per line Qi Zhang
` (14 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Brett Creeley, Paul M Stillwell Jr
Currently ice_clear_vsi_promisc() detects if the VLAN ID sent is not 0
and sets the recipe_id to ICE_SW_LKUP_PROMISC_VLAN in that case and
ICE_SW_LKUP_PROMISC if the VLAN_ID is 0. However this doesn't allow VLAN
0 promiscuous rules to be removed, but they can be added. Fix this by
checking if the promisc_mask contains ICE_PROMISC_VLAN_RX or
ICE_PROMISC_VLAN_TX. This change was made to match what is being done
for ice_set_vsi_promisc().
Signed-off-by: Brett Creeley <brett.creeley@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 9e85da530..1f077d562 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -3977,7 +3977,7 @@ ice_clear_vsi_promisc(struct ice_hw *hw, u16 vsi_handle, u8 promisc_mask,
if (!ice_is_vsi_valid(hw, vsi_handle))
return ICE_ERR_PARAM;
- if (vid)
+ if (promisc_mask & (ICE_PROMISC_VLAN_RX | ICE_PROMISC_VLAN_TX))
recipe_id = ICE_SW_LKUP_PROMISC_VLAN;
else
recipe_id = ICE_SW_LKUP_PROMISC;
@@ -3990,13 +3990,18 @@ ice_clear_vsi_promisc(struct ice_hw *hw, u16 vsi_handle, u8 promisc_mask,
ice_acquire_lock(rule_lock);
LIST_FOR_EACH_ENTRY(itr, rule_head,
ice_fltr_mgmt_list_entry, list_entry) {
+ struct ice_fltr_info *fltr_info;
u8 fltr_promisc_mask = 0;
if (!ice_vsi_uses_fltr(itr, vsi_handle))
continue;
+ fltr_info = &itr->fltr_info;
+
+ if (recipe_id == ICE_SW_LKUP_PROMISC_VLAN &&
+ vid != fltr_info->l_data.mac_vlan.vlan_id)
+ continue;
- fltr_promisc_mask |=
- ice_determine_promisc_mask(&itr->fltr_info);
+ fltr_promisc_mask |= ice_determine_promisc_mask(fltr_info);
/* Skip if filter is not completely specified by given mask */
if (fltr_promisc_mask & ~promisc_mask)
@@ -4004,7 +4009,7 @@ ice_clear_vsi_promisc(struct ice_hw *hw, u16 vsi_handle, u8 promisc_mask,
status = ice_add_entry_to_vsi_fltr_list(hw, vsi_handle,
&remove_list_head,
- &itr->fltr_info);
+ fltr_info);
if (status) {
ice_release_lock(rule_lock);
goto free_fltr_list;
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 50/63] net/ice/base: maximize switch recipe words per line
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (48 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 49/63] net/ice/base: refactor removal of VLAN promiscuous rules Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 51/63] net/ice/base: update switch training packets with open ports Qi Zhang
` (13 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
Remove grouping rules to maximize the number of words placed into
a recipe line. This will allow more recipes to be added by reducing
the number of result indices required.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 128 --------------------------------------
1 file changed, 128 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 1f077d562..ef12df5db 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -4655,17 +4655,6 @@ static const struct ice_prot_ext_tbl_entry ice_prot_ext[] = {
* following combinations, then the recipe needs to be chained as per the
* following policy.
*/
-static const struct ice_pref_recipe_group ice_recipe_pack[] = {
- {3, { { ICE_MAC_OFOS_HW, 0, 0 }, { ICE_MAC_OFOS_HW, 2, 0 },
- { ICE_MAC_OFOS_HW, 4, 0 } }, { 0xffff, 0xffff, 0xffff, 0xffff } },
- {4, { { ICE_MAC_IL_HW, 0, 0 }, { ICE_MAC_IL_HW, 2, 0 },
- { ICE_MAC_IL_HW, 4, 0 }, { ICE_META_DATA_ID_HW, 44, 0 } },
- { 0xffff, 0xffff, 0xffff, 0xffff } },
- {2, { { ICE_IPV4_IL_HW, 0, 0 }, { ICE_IPV4_IL_HW, 2, 0 } },
- { 0xffff, 0xffff, 0xffff, 0xffff } },
- {2, { { ICE_IPV4_IL_HW, 12, 0 }, { ICE_IPV4_IL_HW, 14, 0 } },
- { 0xffff, 0xffff, 0xffff, 0xffff } },
-};
static const struct ice_protocol_entry ice_prot_id_tbl[] = {
{ ICE_MAC_OFOS, ICE_MAC_OFOS_HW },
@@ -4812,75 +4801,7 @@ ice_fill_valid_words(struct ice_adv_lkup_elem *rule,
return ret_val;
}
-/**
- * ice_find_prot_off_ind - check for specific ID and offset in rule
- * @lkup_exts: an array of protocol header extractions
- * @prot_type: protocol type to check
- * @off: expected offset of the extraction
- *
- * Check if the prot_ext has given protocol ID and offset
- */
-static u8
-ice_find_prot_off_ind(struct ice_prot_lkup_ext *lkup_exts, u8 prot_type,
- u16 off)
-{
- u8 j;
-
- for (j = 0; j < lkup_exts->n_val_words; j++)
- if (lkup_exts->fv_words[j].off == off &&
- lkup_exts->fv_words[j].prot_id == prot_type)
- return j;
-
- return ICE_MAX_CHAIN_WORDS;
-}
-
-/**
- * ice_is_recipe_subset - check if recipe group policy is a subset of lookup
- * @lkup_exts: an array of protocol header extractions
- * @r_policy: preferred recipe grouping policy
- *
- * Helper function to check if given recipe group is subset we need to check if
- * all the words described by the given recipe group exist in the advanced rule
- * look up information
- */
-static bool
-ice_is_recipe_subset(struct ice_prot_lkup_ext *lkup_exts,
- const struct ice_pref_recipe_group *r_policy)
-{
- u8 ind[ICE_NUM_WORDS_RECIPE];
- u8 count = 0;
- u8 i;
-
- /* check if everything in the r_policy is part of the entire rule */
- for (i = 0; i < r_policy->n_val_pairs; i++) {
- u8 j;
-
- j = ice_find_prot_off_ind(lkup_exts, r_policy->pairs[i].prot_id,
- r_policy->pairs[i].off);
- if (j >= ICE_MAX_CHAIN_WORDS)
- return false;
-
- /* store the indexes temporarily found by the find function
- * this will be used to mark the words as 'done'
- */
- ind[count++] = j;
- }
-
- /* If the entire policy recipe was a true match, then mark the fields
- * that are covered by the recipe as 'done' meaning that these words
- * will be clumped together in one recipe.
- * "Done" here means in our searching if certain recipe group
- * matches or is subset of the given rule, then we mark all
- * the corresponding offsets as found. So the remaining recipes should
- * be created with whatever words that were left.
- */
- for (i = 0; i < count; i++) {
- u8 in = ind[i];
- ice_set_bit(in, lkup_exts->done);
- }
- return true;
-}
/**
* ice_create_first_fit_recp_def - Create a recipe grouping
@@ -5389,51 +5310,11 @@ static enum ice_status
ice_create_recipe_group(struct ice_hw *hw, struct ice_sw_recipe *rm,
struct ice_prot_lkup_ext *lkup_exts)
{
- struct ice_recp_grp_entry *entry;
- struct ice_recp_grp_entry *tmp;
enum ice_status status;
u8 recp_count = 0;
- u16 groups, i;
rm->n_grp_count = 0;
-
- if (lkup_exts->n_val_words > ICE_NUM_WORDS_RECIPE) {
- /* Each switch recipe can match up to 5 words or metadata. One
- * word in each recipe is used to match the switch ID. Four
- * words are left for matching other values. If the new advanced
- * recipe requires more than 4 words, it needs to be split into
- * multiple recipes which are chained together using the
- * intermediate result that each produces as input to the other
- * recipes in the sequence.
- */
- groups = ARRAY_SIZE(ice_recipe_pack);
-
- /* Check if any of the preferred recipes from the grouping
- * policy matches.
- */
- for (i = 0; i < groups; i++)
- /* Check if the recipe from the preferred grouping
- * matches or is a subset of the fields that needs to be
- * looked up.
- */
- if (ice_is_recipe_subset(lkup_exts,
- &ice_recipe_pack[i])) {
- /* This recipe can be used by itself or grouped
- * with other recipes.
- */
- entry = (struct ice_recp_grp_entry *)
- ice_malloc(hw, sizeof(*entry));
- if (!entry) {
- status = ICE_ERR_NO_MEMORY;
- goto err_unroll;
- }
- entry->r_group = ice_recipe_pack[i];
- LIST_ADD(&entry->l_entry, &rm->rg_list);
- rm->n_grp_count++;
- }
- }
-
/* Create recipes for words that are marked not done by packing them
* as best fit.
*/
@@ -5446,17 +5327,8 @@ ice_create_recipe_group(struct ice_hw *hw, struct ice_sw_recipe *rm,
sizeof(rm->ext_words), ICE_NONDMA_TO_NONDMA);
ice_memcpy(rm->word_masks, lkup_exts->field_mask,
sizeof(rm->word_masks), ICE_NONDMA_TO_NONDMA);
- goto out;
}
-err_unroll:
- LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rm->rg_list, ice_recp_grp_entry,
- l_entry) {
- LIST_DEL(&entry->l_entry);
- ice_free(hw, entry);
- }
-
-out:
return status;
}
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 51/63] net/ice/base: update switch training packets with open ports
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (49 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 50/63] net/ice/base: maximize switch recipe words per line Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 52/63] net/ice/base: remove unnecessary dummy packet finding Qi Zhang
` (12 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
This patch updates UDP tunneled training packets with an appropriate
UDP dest port. For the correct profile to be chosen, an open tunnel
port must be included in the training packet.
Added GENEVE tunnel labels in the test package in order to test GENEVE
tunnel rule creation.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 57 +++++++++++++++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index ef12df5db..c39a77a0f 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -5826,6 +5826,55 @@ ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,
}
/**
+ * ice_fill_adv_packet_tun - fill dummy packet with udp tunnel port
+ * @hw: pointer to the hardware structure
+ * @tun_type: tunnel type
+ * @pkt: dummy packet to fill in
+ * @offsets: offset info for the dummy packet
+ */
+static enum ice_status
+ice_fill_adv_packet_tun(struct ice_hw *hw, enum ice_sw_tunnel_type tun_type,
+ u8 *pkt, const struct ice_dummy_pkt_offsets *offsets)
+{
+ u16 open_port, i;
+
+ switch (tun_type) {
+ case ICE_SW_TUN_AND_NON_TUN:
+ case ICE_SW_TUN_VXLAN_GPE:
+ case ICE_SW_TUN_VXLAN:
+ case ICE_SW_TUN_UDP:
+ if (!ice_get_open_tunnel_port(hw, TNL_VXLAN, &open_port))
+ return ICE_ERR_CFG;
+ break;
+
+ case ICE_SW_TUN_GENEVE:
+ if (!ice_get_open_tunnel_port(hw, TNL_GENEVE, &open_port))
+ return ICE_ERR_CFG;
+ break;
+
+ default:
+ /* Nothing needs to be done for this tunnel type */
+ return ICE_SUCCESS;
+ }
+
+ /* Find the outer UDP protocol header and insert the port number */
+ for (i = 0; offsets[i].type != ICE_PROTOCOL_LAST; i++) {
+ if (offsets[i].type == ICE_UDP_OF) {
+ struct ice_l4_hdr *hdr;
+ u16 offset;
+
+ offset = offsets[i].offset;
+ hdr = (struct ice_l4_hdr *)&pkt[offset];
+ hdr->dst_port = open_port << 8 | open_port >> 8;
+
+ return ICE_SUCCESS;
+ }
+ }
+
+ return ICE_ERR_CFG;
+}
+
+/**
* ice_find_adv_rule_entry - Search a rule entry
* @hw: pointer to the hardware structure
* @lkups: lookup elements or match criteria for the advanced recipe, one
@@ -6129,6 +6178,14 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
ice_fill_adv_dummy_packet(lkups, lkups_cnt, s_rule, pkt, pkt_len,
pkt_offsets);
+ if (rinfo->tun_type != ICE_NON_TUN) {
+ status = ice_fill_adv_packet_tun(hw, rinfo->tun_type,
+ s_rule->pdata.lkup_tx_rx.hdr,
+ pkt_offsets);
+ if (status)
+ goto err_ice_add_adv_rule;
+ }
+
status = ice_aq_sw_rules(hw, (struct ice_aqc_sw_rules *)s_rule,
rule_buf_sz, 1, ice_aqc_opc_add_sw_rules,
NULL);
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 52/63] net/ice/base: remove unnecessary dummy packet finding
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (50 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 51/63] net/ice/base: update switch training packets with open ports Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 53/63] net/ice/base: remove unnecessary if branch Qi Zhang
` (11 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang; +Cc: dev, xiaolong.ye, Qi Zhang, Paul M Stillwell Jr
We don't need to find a dummy packet when removing a rule so remove
the call to get the dummy packet. This also obviates some variables
so remove them also.
Also reduce the scope of rule_buf_sz.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 10 +++-------
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index c39a77a0f..063a26ec5 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -6360,14 +6360,11 @@ ice_rem_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
u16 lkups_cnt, struct ice_adv_rule_info *rinfo)
{
struct ice_adv_fltr_mgmt_list_entry *list_elem;
- const struct ice_dummy_pkt_offsets *offsets;
struct ice_prot_lkup_ext lkup_exts;
- u16 rule_buf_sz, pkt_len, i, rid;
struct ice_lock *rule_lock; /* Lock to protect filter rule list */
enum ice_status status = ICE_SUCCESS;
bool remove_rule = false;
- const u8 *pkt = NULL;
- u16 vsi_handle;
+ u16 i, rid, vsi_handle;
ice_memset(&lkup_exts, 0, sizeof(lkup_exts), ICE_NONDMA_MEM);
for (i = 0; i < lkups_cnt; i++) {
@@ -6419,10 +6416,9 @@ ice_rem_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
ice_release_lock(rule_lock);
if (remove_rule) {
struct ice_aqc_sw_rules_elem *s_rule;
+ u16 rule_buf_sz;
- ice_find_dummy_packet(lkups, lkups_cnt, rinfo->tun_type, &pkt,
- &pkt_len, &offsets);
- rule_buf_sz = ICE_SW_RULE_RX_TX_NO_HDR_SIZE + pkt_len;
+ rule_buf_sz = ICE_SW_RULE_RX_TX_NO_HDR_SIZE;
s_rule =
(struct ice_aqc_sw_rules_elem *)ice_malloc(hw,
rule_buf_sz);
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 53/63] net/ice/base: remove unnecessary if branch
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (51 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 52/63] net/ice/base: remove unnecessary dummy packet finding Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 54/63] net/ice/base: correct abbreviations Qi Zhang
` (10 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang; +Cc: dev, xiaolong.ye, Qi Zhang, Paul M Stillwell Jr
We are already in the branch "if (fm_list->vsi_count == 1)"
no need to exit and re-enter.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 063a26ec5..3ae53d3d8 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -6319,9 +6319,7 @@ ice_adv_rem_update_vsi_list(struct ice_hw *hw, u16 vsi_handle,
tmp_fltr.fwd_id.hw_vsi_id, status);
return status;
}
- }
- if (fm_list->vsi_count == 1) {
/* Remove the VSI list since it is no longer used */
status = ice_remove_vsi_list_rule(hw, vsi_list_id, lkup_type);
if (status) {
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 54/63] net/ice/base: correct abbreviations
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (52 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 53/63] net/ice/base: remove unnecessary if branch Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 55/63] net/ice/base: update to register definition file Qi Zhang
` (9 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Tony Nguyen, Paul M Stillwell Jr
Correct abbreviation issues found by running abbrevcheck.
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 4 ++--
drivers/net/ice/base/ice_controlq.c | 2 +-
drivers/net/ice/base/ice_controlq.h | 2 +-
drivers/net/ice/base/ice_flex_pipe.c | 22 +++++++++++-----------
drivers/net/ice/base/ice_flex_type.h | 2 +-
drivers/net/ice/base/ice_flow.c | 2 +-
drivers/net/ice/base/ice_type.h | 2 +-
7 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index c2d4f1f05..feb7676f8 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -655,10 +655,10 @@ static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
/**
- * ice_get_itr_intrl_gran - determine int/intrl granularity
+ * ice_get_itr_intrl_gran
* @hw: pointer to the HW struct
*
- * Determines the itr/intrl granularities based on the maximum aggregate
+ * Determines the ITR/INTRL granularities based on the maximum aggregate
* bandwidth according to the device's configuration during power-on.
*/
static void ice_get_itr_intrl_gran(struct ice_hw *hw)
diff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c
index 70a50bff4..501f986b9 100644
--- a/drivers/net/ice/base/ice_controlq.c
+++ b/drivers/net/ice/base/ice_controlq.c
@@ -412,7 +412,7 @@ do { \
/* free the buffer info list */ \
if ((qi)->ring.cmd_buf) \
ice_free(hw, (qi)->ring.cmd_buf); \
- /* free dma head */ \
+ /* free DMA head */ \
ice_free(hw, (qi)->ring.dma_head); \
} while (0)
diff --git a/drivers/net/ice/base/ice_controlq.h b/drivers/net/ice/base/ice_controlq.h
index 21c8722e5..acb4ab49e 100644
--- a/drivers/net/ice/base/ice_controlq.h
+++ b/drivers/net/ice/base/ice_controlq.h
@@ -37,7 +37,7 @@ enum ice_ctl_q {
#define ICE_CTL_Q_SQ_CMD_TIMEOUT 250 /* msecs */
struct ice_ctl_q_ring {
- void *dma_head; /* Virtual address to dma head */
+ void *dma_head; /* Virtual address to DMA head */
struct ice_dma_mem desc_buf; /* descriptor ring memory */
void *cmd_buf; /* command buffer memory */
diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c
index 6ae71e698..4ad816874 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -1921,7 +1921,7 @@ ice_create_tunnel(struct ice_hw *hw, enum ice_tunnel_type type, u16 port)
if (!bld)
return ICE_ERR_NO_MEMORY;
- /* allocate 2 sections, one for RX parser, one for TX parser */
+ /* allocate 2 sections, one for Rx parser, one for Tx parser */
if (ice_pkg_buf_reserve_section(bld, 2))
goto ice_create_tunnel_err;
@@ -1951,7 +1951,7 @@ ice_create_tunnel(struct ice_hw *hw, enum ice_tunnel_type type, u16 port)
offsetof(struct ice_boost_key_value, hv_dst_port_key),
sizeof(sect_rx->tcam[0].key.key.hv_dst_port_key));
- /* exact copy of entry to TX section entry */
+ /* exact copy of entry to Tx section entry */
ice_memcpy(sect_tx->tcam, sect_rx->tcam, sizeof(*sect_tx->tcam),
ICE_NONDMA_TO_NONDMA);
@@ -2002,7 +2002,7 @@ enum ice_status ice_destroy_tunnel(struct ice_hw *hw, u16 port, bool all)
if (!bld)
return ICE_ERR_NO_MEMORY;
- /* allocate 2 sections, one for RX parser, one for TX parser */
+ /* allocate 2 sections, one for Rx parser, one for Tx parser */
if (ice_pkg_buf_reserve_section(bld, 2))
goto ice_destroy_tunnel_err;
@@ -2020,8 +2020,8 @@ enum ice_status ice_destroy_tunnel(struct ice_hw *hw, u16 port, bool all)
goto ice_destroy_tunnel_err;
sect_tx->count = CPU_TO_LE16(1);
- /* copy original boost entry to update package buffer, one copy to RX
- * section, another copy to the TX section
+ /* copy original boost entry to update package buffer, one copy to Rx
+ * section, another copy to the Tx section
*/
for (i = 0; i < hw->tnl.count && i < ICE_TUNNEL_MAX_ENTRIES; i++)
if (hw->tnl.tbl[i].valid && hw->tnl.tbl[i].in_use &&
@@ -2919,7 +2919,7 @@ ice_write_prof_mask_reg(struct ice_hw *hw, enum ice_block blk, u16 mask_idx,
* ice_write_prof_mask_enable_res - write profile mask enable register
* @hw: pointer to the HW struct
* @blk: hardware block
- * @prof_id: profile id
+ * @prof_id: profile ID
* @enable_mask: enable mask
*/
static void
@@ -3095,7 +3095,7 @@ ice_free_prof_mask(struct ice_hw *hw, enum ice_block blk, u16 mask_idx)
* ice_free_prof_masks - free all profile masks for a profile
* @hw: pointer to the HW struct
* @blk: hardware block
- * @prof_id: profile id
+ * @prof_id: profile ID
*/
static enum ice_status
ice_free_prof_masks(struct ice_hw *hw, enum ice_block blk, u16 prof_id)
@@ -3157,7 +3157,7 @@ void ice_shutdown_all_prof_masks(struct ice_hw *hw)
* ice_update_prof_masking - set registers according to masking
* @hw: pointer to the HW struct
* @blk: hardware block
- * @prof_id: profile id
+ * @prof_id: profile ID
* @es: field vector
* @masks: masks
*/
@@ -3377,7 +3377,7 @@ static void ice_fill_tbl(struct ice_hw *hw, enum ice_block block_id, u32 sid)
void *sect;
/* if the HW segment pointer is null then the first iteration of
- * ice_pkg_enum_section() will fail. In this case the Hw tables will
+ * ice_pkg_enum_section() will fail. In this case the HW tables will
* not be filled and return success.
*/
if (!hw->seg) {
@@ -3469,7 +3469,7 @@ static void ice_fill_tbl(struct ice_hw *hw, enum ice_block block_id, u32 sid)
return;
/* if the sum of section size and offset exceed destination size
- * then we are out of bounds of the Hw table size for that PF.
+ * then we are out of bounds of the HW table size for that PF.
* Changing section length to fill the remaining table space
* of that PF.
*/
@@ -3488,7 +3488,7 @@ static void ice_fill_tbl(struct ice_hw *hw, enum ice_block block_id, u32 sid)
*
* Reads the current package contents and populates the driver
* database with the data iteratively for all advanced feature
- * blocks. Assume that the Hw tables have been allocated.
+ * blocks. Assume that the HW tables have been allocated.
*/
void ice_fill_blk_tbls(struct ice_hw *hw)
{
diff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h
index baf53d881..c30d407c2 100644
--- a/drivers/net/ice/base/ice_flex_type.h
+++ b/drivers/net/ice/base/ice_flex_type.h
@@ -577,7 +577,7 @@ struct ice_xlt1 {
/* Vsig bit layout:
* [0:12]: incremental vsig index 1 to ICE_MAX_VSIGS
- * [13:15]: pf number of device
+ * [13:15]: PF number of device
*/
#define ICE_VSIG_IDX_M (0x1FFF)
#define ICE_PF_NUM_S 13
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index f71ac50d6..abdf10b94 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -567,7 +567,7 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params)
* ice_flow_xtract_pkt_flags - Create an extr sequence entry for packet flags
* @hw: pointer to the HW struct
* @params: information about the flow to be processed
- * @flags: The value of pkt_flags[x:x] in RX/TX MDID metadata.
+ * @flags: The value of pkt_flags[x:x] in Rx/Tx MDID metadata.
*
* This function will allocate an extraction sequence entries for a DWORD size
* chunk of the packet flags.
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 403fb7668..deb614e37 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -789,7 +789,7 @@ struct ice_hw {
/* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
- * register. Used for determining the itr/intrl granularity during
+ * register. Used for determining the ITR/INTRL granularity during
* initialization.
*/
#define ICE_MAX_AGG_BW_200G 0x0
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 55/63] net/ice/base: update to register definition file
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (53 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 54/63] net/ice/base: correct abbreviations Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 56/63] net/ice/base: replace open-code duplication Qi Zhang
` (8 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Bruce Allan, Paul M Stillwell Jr
Added register definitions for GL_MDCK_TX_TDPU and GL_MDET_TX_TDPU.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_hw_autogen.h | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/drivers/net/ice/base/ice_hw_autogen.h b/drivers/net/ice/base/ice_hw_autogen.h
index 2b423baf8..6f227adb8 100644
--- a/drivers/net/ice/base/ice_hw_autogen.h
+++ b/drivers/net/ice/base/ice_hw_autogen.h
@@ -5330,6 +5330,29 @@
#define GL_MDCK_RX 0x0029422C /* Reset Source: CORER */
#define GL_MDCK_RX_DESC_ADDR_S 0
#define GL_MDCK_RX_DESC_ADDR_M BIT(0)
+#define GL_MDCK_TX_TDPU 0x00049348 /* Reset Source: CORER */
+#define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_S 0
+#define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_M BIT(0)
+#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_S 1
+#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)
+#define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_S 2
+#define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_M BIT(2)
+#define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_S 3
+#define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_M BIT(3)
+#define GL_MDCK_TX_TDPU_MAL_CMD_ITR_DIS_S 4
+#define GL_MDCK_TX_TDPU_MAL_CMD_ITR_DIS_M BIT(4)
+#define GL_MDCK_TX_TDPU_BIG_PKT_SIZE_ITR_DIS_S 5
+#define GL_MDCK_TX_TDPU_BIG_PKT_SIZE_ITR_DIS_M BIT(5)
+#define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_S 6
+#define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_M BIT(6)
+#define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_S 7
+#define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_M BIT(7)
+#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_S 8
+#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_M BIT(8)
+#define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_S 9
+#define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_M BIT(9)
+#define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_S 10
+#define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_M BIT(10)
#define GL_MDET_RX 0x00294C00 /* Reset Source: CORER */
#define GL_MDET_RX_QNUM_S 0
#define GL_MDET_RX_QNUM_M MAKEMASK(0x7FFF, 0)
@@ -5363,6 +5386,17 @@
#define GL_MDET_TX_TCLAN_MAL_TYPE_M MAKEMASK(0x1F, 26)
#define GL_MDET_TX_TCLAN_VALID_S 31
#define GL_MDET_TX_TCLAN_VALID_M BIT(31)
+#define GL_MDET_TX_TDPU 0x00049350 /* Reset Source: CORER */
+#define GL_MDET_TX_TDPU_QNUM_S 0
+#define GL_MDET_TX_TDPU_QNUM_M MAKEMASK(0x7FFF, 0)
+#define GL_MDET_TX_TDPU_VF_NUM_S 15
+#define GL_MDET_TX_TDPU_VF_NUM_M MAKEMASK(0xFF, 15)
+#define GL_MDET_TX_TDPU_PF_NUM_S 23
+#define GL_MDET_TX_TDPU_PF_NUM_M MAKEMASK(0x7, 23)
+#define GL_MDET_TX_TDPU_MAL_TYPE_S 26
+#define GL_MDET_TX_TDPU_MAL_TYPE_M MAKEMASK(0x1F, 26)
+#define GL_MDET_TX_TDPU_VALID_S 31
+#define GL_MDET_TX_TDPU_VALID_M BIT(31)
#define GLRLAN_MDET 0x00294200 /* Reset Source: CORER */
#define GLRLAN_MDET_PCKT_EXTRCT_ERR_S 0
#define GLRLAN_MDET_PCKT_EXTRCT_ERR_M BIT(0)
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 56/63] net/ice/base: replace open-code duplication
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (54 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 55/63] net/ice/base: update to register definition file Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 57/63] net/ice/base: delay less Qi Zhang
` (7 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Bruce Allan, Paul M Stillwell Jr
Use BIT_ULL() instead of ICE_FLOW_HASH_FLD() which does the same bit shift
operation.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flow.h | 24 +++++++++++-------------
1 file changed, 11 insertions(+), 13 deletions(-)
diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h
index 0bb3efca0..2ec9bb022 100644
--- a/drivers/net/ice/base/ice_flow.h
+++ b/drivers/net/ice/base/ice_flow.h
@@ -14,24 +14,22 @@
#define ICE_FLOW_VSI_INVAL 0xffff
#define ICE_FLOW_FLD_OFF_INVAL 0xffff
-/* Use any of the type from flow field to generate a equivalent hash field */
-#define ICE_FLOW_HASH_FLD(t) (1ULL << (t))
-
+/* Generate flow hash field from flow field type(s) */
#define ICE_FLOW_HASH_IPV4 \
- (ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_IPV4_SA) | \
- ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_IPV4_DA))
+ (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) | \
+ BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA))
#define ICE_FLOW_HASH_IPV6 \
- (ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_IPV6_SA) | \
- ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_IPV6_DA))
+ (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_SA) | \
+ BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_DA))
#define ICE_FLOW_HASH_TCP_PORT \
- (ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_TCP_SRC_PORT) | \
- ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_TCP_DST_PORT))
+ (BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_SRC_PORT) | \
+ BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_DST_PORT))
#define ICE_FLOW_HASH_UDP_PORT \
- (ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_UDP_SRC_PORT) | \
- ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_UDP_DST_PORT))
+ (BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_SRC_PORT) | \
+ BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_DST_PORT))
#define ICE_FLOW_HASH_SCTP_PORT \
- (ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT) | \
- ICE_FLOW_HASH_FLD(ICE_FLOW_FIELD_IDX_SCTP_DST_PORT))
+ (BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT) | \
+ BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_DST_PORT))
#define ICE_HASH_INVALID 0
#define ICE_HASH_TCP_IPV4 (ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_TCP_PORT)
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 57/63] net/ice/base: delay less
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (55 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 56/63] net/ice/base: replace open-code duplication Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 58/63] net/ice/base: add AQC get link topology handle support Qi Zhang
` (6 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Mitch Williams, Paul M Stillwell Jr
Shorten the delay for SQ responses, but increase the number of loops.
Max delay time is unchanged, but some operations complete much more
quickly.
In the process, add a new define to make the delay count and delay time
more explicit, and simplify the code so it's the same for both switch
and NIC mode. Add comments to make things more explicit.
Signed-off-by: Mitch Williams <mitch.a.williams@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_controlq.c | 2 +-
drivers/net/ice/base/ice_controlq.h | 5 +++--
drivers/net/ice/base/ice_osdep.h | 2 +-
3 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c
index 501f986b9..1ea8f3a24 100644
--- a/drivers/net/ice/base/ice_controlq.c
+++ b/drivers/net/ice/base/ice_controlq.c
@@ -982,7 +982,7 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
if (ice_sq_done(hw, cq))
break;
- ice_msec_delay(1, false);
+ ice_usec_delay(ICE_CTL_Q_SQ_CMD_USEC, false);
total_delay++;
} while (total_delay < cq->sq_cmd_timeout);
diff --git a/drivers/net/ice/base/ice_controlq.h b/drivers/net/ice/base/ice_controlq.h
index acb4ab49e..b1214f670 100644
--- a/drivers/net/ice/base/ice_controlq.h
+++ b/drivers/net/ice/base/ice_controlq.h
@@ -33,8 +33,9 @@ enum ice_ctl_q {
ICE_CTL_Q_MAILBOX,
};
-/* Control Queue default settings */
-#define ICE_CTL_Q_SQ_CMD_TIMEOUT 250 /* msecs */
+/* Control Queue timeout settings - max delay 250ms */
+#define ICE_CTL_Q_SQ_CMD_TIMEOUT 2500 /* Count 2500 times */
+#define ICE_CTL_Q_SQ_CMD_USEC 100 /* Check every 100usec */
struct ice_ctl_q_ring {
void *dma_head; /* Virtual address to DMA head */
diff --git a/drivers/net/ice/base/ice_osdep.h b/drivers/net/ice/base/ice_osdep.h
index 35a17b941..27c1830c5 100644
--- a/drivers/net/ice/base/ice_osdep.h
+++ b/drivers/net/ice/base/ice_osdep.h
@@ -292,7 +292,7 @@ ice_hweight32(u32 num)
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
#define DELAY(x) rte_delay_us(x)
-#define ice_usec_delay(x) rte_delay_us(x)
+#define ice_usec_delay(x, y) rte_delay_us(x)
#define ice_msec_delay(x, y) rte_delay_us(1000 * (x))
#define udelay(x) DELAY(x)
#define msleep(x) DELAY(1000 * (x))
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 58/63] net/ice/base: add AQC get link topology handle support
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (56 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 57/63] net/ice/base: delay less Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 59/63] net/ice/base: remove Rx flex descriptor programming Qi Zhang
` (5 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Paul Greenwalt, Paul M Stillwell Jr
Add AQC get link topology handle support. This is needed to determine
Direct Attach (DA) or backplane media type for PHY types that support
either. Get link topology handle cage node type request can be used to
determine if a cage is present or not. If a cage is present for PHY
types that supports both DA and backplane media type, then the media
type is DA, else the media type is backplane.
Signed-off-by: Paul Greenwalt <paul.greenwalt@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_adminq_cmd.h | 52 +++++++++++++++++++++++++++
drivers/net/ice/base/ice_common.c | 68 ++++++++++++++++++++++++++++++++++-
2 files changed, 119 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index 9a063592f..8e1d6a07d 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1654,6 +1654,56 @@ struct ice_aqc_set_mac_lb {
+struct ice_aqc_link_topo_addr {
+ u8 lport_num;
+ u8 lport_num_valid;
+#define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)
+ u8 node_type_ctx;
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8
+#define ICE_AQC_LINK_TOPO_NODE_CTX_S 4
+#define ICE_AQC_LINK_TOPO_NODE_CTX_M \
+ (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
+#define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0
+#define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1
+#define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2
+#define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3
+#define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4
+#define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5
+ u8 index;
+ __le16 handle;
+#define ICE_AQC_LINK_TOPO_HANDLE_S 0
+#define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
+/* Used to decode the handle field */
+#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9)
+#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9)
+#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0
+#define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0
+/* In case of a Mezzanine type */
+#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \
+ (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
+#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6
+#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)
+/* In case of a LOM type */
+#define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \
+ (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
+};
+
+/* Get Link Topology Handle (direct, 0x06E0) */
+struct ice_aqc_get_link_topo {
+ struct ice_aqc_link_topo_addr addr;
+ u8 node_part_num;
+ u8 rsvd[9];
+};
/* Set Port Identification LED (direct, 0x06E9) */
struct ice_aqc_set_port_id_led {
@@ -2307,6 +2357,7 @@ struct ice_aq_desc {
struct ice_aqc_set_event_mask set_event_mask;
struct ice_aqc_get_link_status get_link_status;
struct ice_aqc_event_lan_overflow lan_overflow;
+ struct ice_aqc_get_link_topo get_link_topo;
} params;
};
@@ -2470,6 +2521,7 @@ enum ice_adminq_opc {
ice_aqc_opc_get_link_status = 0x0607,
ice_aqc_opc_set_event_mask = 0x0613,
ice_aqc_opc_set_mac_lb = 0x0620,
+ ice_aqc_opc_get_link_topo = 0x06E0,
ice_aqc_opc_set_port_id_led = 0x06E9,
ice_aqc_opc_get_port_options = 0x06EA,
ice_aqc_opc_set_port_option = 0x06EB,
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index feb7676f8..d2f903329 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -188,6 +188,59 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
}
/**
+ * ice_aq_get_link_topo_handle - get link topology node return status
+ * @pi: port information structure
+ * @node_type: requested node type
+ * @cd: pointer to command details structure or NULL
+ *
+ * Get link topology node return status for specified node type (0x06E0)
+ *
+ * Node type cage can be used to determine if cage is present. If AQC
+ * returns error (ENOENT), then no cage present. If no cage present, then
+ * connection type is backplane or BASE-T.
+ */
+static enum ice_status
+ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
+ struct ice_sq_cd *cd)
+{
+ struct ice_aqc_get_link_topo *cmd;
+ struct ice_aq_desc desc;
+
+ cmd = &desc.params.get_link_topo;
+
+ if (!cmd)
+ return ICE_ERR_PARAM;
+
+ ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
+
+ cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
+ ICE_AQC_LINK_TOPO_NODE_CTX_S);
+
+ /* set node type */
+ cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
+
+ return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
+}
+
+/**
+ * ice_is_media_cage_present
+ * @pi: port information structure
+ *
+ * Returns true if media cage is present, else false. If no cage, then
+ * media type is backplane or BASE-T.
+ */
+static bool ice_is_media_cage_present(struct ice_port_info *pi)
+{
+ /* Node type cage can be used to determine if cage is present. If AQC
+ * returns error (ENOENT), then no cage present. If no cage present then
+ * connection type is backplane or BASE-T.
+ */
+ return !ice_aq_get_link_topo_handle(pi,
+ ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
+ NULL);
+}
+
+/**
* ice_get_media_type - Gets media type
* @pi: port information structure
*/
@@ -212,7 +265,6 @@ static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
case ICE_PHY_TYPE_LOW_25GBASE_SR:
case ICE_PHY_TYPE_LOW_25GBASE_LR:
- case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
case ICE_PHY_TYPE_LOW_40GBASE_SR4:
case ICE_PHY_TYPE_LOW_40GBASE_LR4:
case ICE_PHY_TYPE_LOW_50GBASE_SR2:
@@ -243,6 +295,16 @@ static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
case ICE_PHY_TYPE_LOW_100GBASE_CP2:
return ICE_MEDIA_DA;
+ case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
+ case ICE_PHY_TYPE_LOW_40G_XLAUI:
+ case ICE_PHY_TYPE_LOW_50G_LAUI2:
+ case ICE_PHY_TYPE_LOW_50G_AUI2:
+ case ICE_PHY_TYPE_LOW_50G_AUI1:
+ case ICE_PHY_TYPE_LOW_100G_AUI4:
+ case ICE_PHY_TYPE_LOW_100G_CAUI4:
+ if (ice_is_media_cage_present(pi))
+ return ICE_MEDIA_DA;
+ /* fall-through */
case ICE_PHY_TYPE_LOW_1000BASE_KX:
case ICE_PHY_TYPE_LOW_2500BASE_KX:
case ICE_PHY_TYPE_LOW_2500BASE_X:
@@ -260,6 +322,10 @@ static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
}
} else {
switch (hw_link_info->phy_type_high) {
+ case ICE_PHY_TYPE_HIGH_100G_AUI2:
+ if (ice_is_media_cage_present(pi))
+ return ICE_MEDIA_DA;
+ /* fall-through */
case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
return ICE_MEDIA_BACKPLANE;
}
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 59/63] net/ice/base: remove Rx flex descriptor programming
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (57 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 58/63] net/ice/base: add AQC get link topology handle support Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 60/63] net/ice/base: enable RSS with ether layer for PPPoE Qi Zhang
` (4 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Vignesh Sridhar, Paul M Stillwell Jr
Removing Rx flex descriptor metadata and flag programming from the code,
these registers cannot be written to as they are read only.
The programming for all fields per RxDID is now handled differently.
Signed-off-by: Vignesh Sridhar <vignesh.sridhar@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_common.c | 195 --------------------------------------
1 file changed, 195 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index d2f903329..11e902ea1 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -11,35 +11,6 @@
#define ICE_PF_RESET_WAIT_COUNT 200
-#define ICE_PROG_FLEX_ENTRY(hw, rxdid, mdid, idx) \
- wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \
- ((ICE_RX_OPC_MDID << \
- GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
- GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
- (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
- GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M))
-
-#define ICE_PROG_FLEX_ENTRY_EXTRACT(hw, rxdid, protid, off, idx) \
- wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \
- ((ICE_RX_OPC_EXTRACT << \
- GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
- GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
- (((protid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
- GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M) | \
- (((off) << GLFLXP_RXDID_FLX_WRD_##idx##_EXTRACTION_OFFSET_S) & \
- GLFLXP_RXDID_FLX_WRD_##idx##_EXTRACTION_OFFSET_M))
-
-#define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \
- wr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \
- (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \
- GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \
- (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \
- GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \
- (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \
- GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \
- (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \
- GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M))
-
/**
* ice_set_mac_type - Sets MAC type
@@ -431,163 +402,6 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
}
/**
- * ice_init_flex_flags
- * @hw: pointer to the hardware structure
- * @prof_id: Rx Descriptor Builder profile ID
- *
- * Function to initialize Rx flex flags
- */
-static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)
-{
- u8 idx = 0;
-
- /* Flex-flag fields (0-2) are programmed with FLG64 bits with layout:
- * flexiflags0[5:0] - TCP flags, is_packet_fragmented, is_packet_UDP_GRE
- * flexiflags1[3:0] - Not used for flag programming
- * flexiflags2[7:0] - Tunnel and VLAN types
- * 2 invalid fields in last index
- */
- switch (prof_id) {
- /* Rx flex flags are currently programmed for the NIC profiles only.
- * Different flag bit programming configurations can be added per
- * profile as needed.
- */
- case ICE_RXDID_FLEX_NIC:
- case ICE_RXDID_FLEX_NIC_2:
- ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_FRG,
- ICE_FLG_UDP_GRE, ICE_FLG_PKT_DSI,
- ICE_FLG_FIN, idx++);
- /* flex flag 1 is not used for flexi-flag programming, skipping
- * these four FLG64 bits.
- */
- ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_SYN, ICE_FLG_RST,
- ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx++);
- ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_DSI,
- ICE_FLG_PKT_DSI, ICE_FLG_EVLAN_x8100,
- ICE_FLG_EVLAN_x9100, idx++);
- ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_VLAN_x8100,
- ICE_FLG_TNL_VLAN, ICE_FLG_TNL_MAC,
- ICE_FLG_TNL0, idx++);
- ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_TNL1, ICE_FLG_TNL2,
- ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx);
- break;
-
- default:
- ice_debug(hw, ICE_DBG_INIT,
- "Flag programming for profile ID %d not supported\n",
- prof_id);
- }
-}
-
-/**
- * ice_init_flex_flds
- * @hw: pointer to the hardware structure
- * @prof_id: Rx Descriptor Builder profile ID
- *
- * Function to initialize flex descriptors
- */
-static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)
-{
- enum ice_prot_id protid_0, protid_1;
- u16 offset_0, offset_1;
- enum ice_flex_mdid mdid;
-
- switch (prof_id) {
- case ICE_RXDID_FLEX_NIC:
- case ICE_RXDID_FLEX_NIC_2:
- ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_LOW, 0);
- ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_HIGH, 1);
- ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_LOWER, 2);
-
- mdid = (prof_id == ICE_RXDID_FLEX_NIC_2) ?
- ICE_MDID_SRC_VSI : ICE_MDID_FLOW_ID_HIGH;
-
- ICE_PROG_FLEX_ENTRY(hw, prof_id, mdid, 3);
-
- ice_init_flex_flags(hw, prof_id);
- break;
- case ICE_RXDID_COMMS_GENERIC:
- case ICE_RXDID_COMMS_AUX_VLAN:
- case ICE_RXDID_COMMS_AUX_IPV4:
- case ICE_RXDID_COMMS_AUX_IPV6:
- case ICE_RXDID_COMMS_AUX_IPV6_FLOW:
- case ICE_RXDID_COMMS_AUX_TCP:
- ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_LOW, 0);
- ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_HIGH, 1);
- ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_LOWER, 2);
- ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_HIGH, 3);
-
- if (prof_id == ICE_RXDID_COMMS_AUX_VLAN) {
- /* FlexiMD.4: VLAN1 - single or EVLAN (first for QinQ).
- * FlexiMD.5: VLAN2 - C-VLAN (second for QinQ).
- */
- protid_0 = ICE_PROT_EVLAN_O;
- offset_0 = 0;
- protid_1 = ICE_PROT_VLAN_O;
- offset_1 = 0;
- } else if (prof_id == ICE_RXDID_COMMS_AUX_IPV4) {
- /* FlexiMD.4: IPHDR1 - IPv4 header word 4, "TTL" and
- * "Protocol" fields.
- * FlexiMD.5: IPHDR0 - IPv4 header word 0, "Ver",
- * "Hdr Len" and "Type of Service" fields.
- */
- protid_0 = ICE_PROT_IPV4_OF_OR_S;
- offset_0 = 8;
- protid_1 = ICE_PROT_IPV4_OF_OR_S;
- offset_1 = 0;
- } else if (prof_id == ICE_RXDID_COMMS_AUX_IPV6) {
- /* FlexiMD.4: IPHDR1 - IPv6 header word 3,
- * "Next Header" and "Hop Limit" fields.
- * FlexiMD.5: IPHDR0 - IPv6 header word 0,
- * "Ver", "Traffic class" and high 4 bits of
- * "Flow Label" fields.
- */
- protid_0 = ICE_PROT_IPV6_OF_OR_S;
- offset_0 = 6;
- protid_1 = ICE_PROT_IPV6_OF_OR_S;
- offset_1 = 0;
- } else if (prof_id == ICE_RXDID_COMMS_AUX_IPV6_FLOW) {
- /* FlexiMD.4: IPHDR1 - IPv6 header word 1,
- * 16 low bits of the "Flow Label" field.
- * FlexiMD.5: IPHDR0 - IPv6 header word 0,
- * "Ver", "Traffic class" and high 4 bits
- * of "Flow Label" fields.
- */
- protid_0 = ICE_PROT_IPV6_OF_OR_S;
- offset_0 = 2;
- protid_1 = ICE_PROT_IPV6_OF_OR_S;
- offset_1 = 0;
- } else if (prof_id == ICE_RXDID_COMMS_AUX_TCP) {
- /* FlexiMD.4: TCPHDR - TCP header word 6,
- * "Data Offset" and "Flags" fields.
- * FlexiMD.5: Reserved
- */
- protid_0 = ICE_PROT_TCP_IL;
- offset_0 = 12;
- protid_1 = ICE_PROT_ID_INVAL;
- offset_1 = 0;
- } else {
- protid_0 = ICE_PROT_ID_INVAL;
- offset_0 = 0;
- protid_1 = ICE_PROT_ID_INVAL;
- offset_1 = 0;
- }
-
- ICE_PROG_FLEX_ENTRY_EXTRACT(hw, prof_id,
- protid_0, offset_0, 4);
- ICE_PROG_FLEX_ENTRY_EXTRACT(hw, prof_id,
- protid_1, offset_1, 5);
-
- ice_init_flex_flags(hw, prof_id);
- break;
- default:
- ice_debug(hw, ICE_DBG_INIT,
- "Field init for profile ID %d not supported\n",
- prof_id);
- }
-}
-
-/**
* ice_aq_set_mac_cfg
* @hw: pointer to the HW struct
* @max_frame_size: Maximum Frame Size to be supported
@@ -928,15 +742,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
if (status)
goto err_unroll_fltr_mgmt_struct;
-
- ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC);
- ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC_2);
- ice_init_flex_flds(hw, ICE_RXDID_COMMS_GENERIC);
- ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_VLAN);
- ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_IPV4);
- ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_IPV6);
- ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_IPV6_FLOW);
- ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_TCP);
/* Obtain counter base index which would be used by flow director */
status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
if (status)
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 60/63] net/ice/base: enable RSS with ether layer for PPPoE
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (58 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 59/63] net/ice/base: remove Rx flex descriptor programming Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 61/63] net/ice/base: add GENEVE offset Qi Zhang
` (3 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Zhirun Yan, Paul M Stillwell Jr
Add these two ptype(MAC_PPPOD_PAY and MAC_PPPOE_PAY) in outer mac
bitmap, so it can hash for outer mac.
Signed-off-by: Zhirun Yan <zhirun.yan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_flow.c | 8 ++++++--
drivers/net/ice/base/ice_flow.h | 5 +++++
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index abdf10b94..769fd2da7 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -143,7 +143,7 @@ struct ice_flow_field_info ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = {
static const u32 ice_ptypes_mac_ofos[] = {
0xFDC00CC6, 0xBFBF7F7E, 0xF7EFDFDF, 0xFEFDFDFB,
0x03BF7F7E, 0x00000000, 0x00000000, 0x00000000,
- 0x000B0F0F, 0x00000000, 0x00000000, 0x00000000,
+ 0x000B0F0F, 0x00003000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -1682,6 +1682,9 @@ ice_flow_add_fld_raw(struct ice_flow_seg_info *seg, u16 off, u8 len,
seg->raws_cnt++;
}
+#define ICE_FLOW_RSS_SEG_HDR_L2_MASKS \
+(ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN)
+
#define ICE_FLOW_RSS_SEG_HDR_L3_MASKS \
(ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_PPPOE)
@@ -1692,7 +1695,8 @@ ice_flow_add_fld_raw(struct ice_flow_seg_info *seg, u16 off, u8 len,
#define ICE_FLOW_RSS_SEG_HDR_VAL_MASKS \
- (ICE_FLOW_RSS_SEG_HDR_L3_MASKS | \
+ (ICE_FLOW_RSS_SEG_HDR_L2_MASKS | \
+ ICE_FLOW_RSS_SEG_HDR_L3_MASKS | \
ICE_FLOW_RSS_SEG_HDR_L4_MASKS)
/**
diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h
index 2ec9bb022..3afd201c4 100644
--- a/drivers/net/ice/base/ice_flow.h
+++ b/drivers/net/ice/base/ice_flow.h
@@ -15,6 +15,9 @@
#define ICE_FLOW_FLD_OFF_INVAL 0xffff
/* Generate flow hash field from flow field type(s) */
+#define ICE_FLOW_HASH_ETH \
+ (BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_DA) | \
+ BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_SA))
#define ICE_FLOW_HASH_IPV4 \
(BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) | \
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA))
@@ -58,6 +61,8 @@
#define ICE_FLOW_HASH_PPPOE_SESS_ID \
(BIT_ULL(ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID))
+#define ICE_FLOW_HASH_PPPOE_SESS_ID_ETH \
+ (ICE_FLOW_HASH_ETH | ICE_FLOW_HASH_PPPOE_SESS_ID)
#define ICE_FLOW_HASH_PPPOE_TCP_ID \
(ICE_FLOW_HASH_TCP_PORT | ICE_FLOW_HASH_PPPOE_SESS_ID)
#define ICE_FLOW_HASH_PPPOE_UDP_ID \
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 61/63] net/ice/base: add GENEVE offset
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (59 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 60/63] net/ice/base: enable RSS with ether layer for PPPoE Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 62/63] net/ice/base: update profile to recipe bitmap array Qi Zhang
` (2 subsequent siblings)
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Doug Dziggel, Paul M Stillwell Jr
Add Geneve offset for tunneled packets to allow dummy packets to be
properly created.
Signed-off-by: Doug Dziggel <douglas.a.dziggel@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 3ae53d3d8..8f20b9ed6 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -156,6 +156,7 @@ struct ice_dummy_pkt_offsets dummy_udp_tun_tcp_packet_offsets[] = {
{ ICE_IPV4_OFOS, 14 },
{ ICE_UDP_OF, 34 },
{ ICE_VXLAN, 42 },
+ { ICE_GENEVE, 42 },
{ ICE_MAC_IL, 50 },
{ ICE_IPV4_IL, 64 },
{ ICE_TCP_IL, 84 },
@@ -207,6 +208,7 @@ struct ice_dummy_pkt_offsets dummy_udp_tun_udp_packet_offsets[] = {
{ ICE_IPV4_OFOS, 14 },
{ ICE_UDP_OF, 34 },
{ ICE_VXLAN, 42 },
+ { ICE_GENEVE, 42 },
{ ICE_MAC_IL, 50 },
{ ICE_IPV4_IL, 64 },
{ ICE_UDP_ILOS, 84 },
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 62/63] net/ice/base: update profile to recipe bitmap array
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (60 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 61/63] net/ice/base: add GENEVE offset Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 63/63] net/ice/base: ignore inverse switch recipes Qi Zhang
2019-08-30 9:44 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Ye Xiaolong
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
Correctly update profile to recipe bitmap array after adding and
associating recipes. This fixes an issue where determining unused
recipe result index slots was incorrect.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 21 ++++++++++++++++++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 8f20b9ed6..59da7eaa8 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -594,11 +594,14 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
/* Propagate some data to the recipe database */
recps[idx].is_root = is_root;
recps[idx].priority = root_bufs.content.act_ctrl_fwd_priority;
- if (root_bufs.content.result_indx & ICE_AQ_RECIPE_RESULT_EN)
+ ice_zero_bitmap(recps[idx].res_idxs, ICE_MAX_FV_WORDS);
+ if (root_bufs.content.result_indx & ICE_AQ_RECIPE_RESULT_EN) {
recps[idx].chain_idx = root_bufs.content.result_indx &
~ICE_AQ_RECIPE_RESULT_EN;
- else
+ ice_set_bit(recps[idx].chain_idx, recps[idx].res_idxs);
+ } else {
recps[idx].chain_idx = ICE_INVAL_CHAIN_IND;
+ }
if (!is_root)
continue;
@@ -609,11 +612,11 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,
recps[idx].root_rid = root_bufs.content.rid &
~ICE_AQ_RECIPE_ID_IS_ROOT;
recps[idx].priority = root_bufs.content.act_ctrl_fwd_priority;
- recps[idx].big_recp = (recps[rid].n_grp_count > 1);
}
/* Complete initialization of the root recipe entry */
lkup_exts->n_val_words = fv_word_idx;
+ recps[rid].big_recp = (num_recps > 1);
recps[rid].n_grp_count = num_recps;
recps[rid].root_buf = (struct ice_aqc_recipe_data_elem *)
ice_calloc(hw, recps[rid].n_grp_count,
@@ -5287,6 +5290,7 @@ ice_add_sw_recipe(struct ice_hw *hw, struct ice_sw_recipe *rm,
recp->n_ext_words = entry->r_group.n_val_pairs;
recp->chain_idx = entry->chain_idx;
recp->priority = buf[buf_idx].content.act_ctrl_fwd_priority;
+ recp->n_grp_count = rm->n_grp_count;
recp->tun_type = rm->tun_type;
recp->recp_created = true;
recp->adv_rule = 1;
@@ -5568,6 +5572,7 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
LIST_FOR_EACH_ENTRY(fvit, &rm->fv_list, ice_sw_fv_list_entry,
list_entry) {
ice_declare_bitmap(r_bitmap, ICE_MAX_NUM_RECIPES);
+ u16 j;
status = ice_aq_get_recipe_to_profile(hw, fvit->profile_id,
(u8 *)r_bitmap, NULL);
@@ -5587,6 +5592,16 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
if (status)
goto err_unroll;
+
+ /* Update profile to recipe bitmap array */
+ ice_memcpy(profile_to_recipe[fvit->profile_id], rm->r_bitmap,
+ sizeof(rm->r_bitmap), ICE_NONDMA_TO_NONDMA);
+
+ /* Update recipe to profile bitmap array */
+ for (j = 0; j < ICE_MAX_NUM_RECIPES; j++)
+ if (ice_is_bit_set(rm->r_bitmap, j))
+ ice_set_bit((u16)fvit->profile_id,
+ recipe_to_profile[j]);
}
*rid = rm->root_rid;
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* [dpdk-dev] [PATCH v2 63/63] net/ice/base: ignore inverse switch recipes
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (61 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 62/63] net/ice/base: update profile to recipe bitmap array Qi Zhang
@ 2019-08-29 2:36 ` Qi Zhang
2019-08-30 9:44 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Ye Xiaolong
63 siblings, 0 replies; 130+ messages in thread
From: Qi Zhang @ 2019-08-29 2:36 UTC (permalink / raw)
To: wenzhuo.lu, qiming.yang
Cc: dev, xiaolong.ye, Qi Zhang, Dan Nowlin, Paul M Stillwell Jr
When looking for an existing recipes, never choose an inverse
recipe as these are used for anti-spoofing. Choosing inverse
recipes for source MAC address rules was causing errors while
adding the rule.
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_switch.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 59da7eaa8..2437faead 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -4709,6 +4709,11 @@ static u16 ice_find_recp(struct ice_hw *hw, struct ice_prot_lkup_ext *lkup_exts)
&refresh_required))
continue;
+ /* Skip inverse action recipes */
+ if (recp[i].root_buf && recp[i].root_buf->content.act_ctrl &
+ ICE_AQ_RECIPE_ACT_INV_ACT)
+ continue;
+
/* if number of words we are looking for match */
if (lkup_exts->n_val_words == recp[i].lkup_exts.n_val_words) {
struct ice_fv_word *a = lkup_exts->fv_words;
--
2.13.6
^ permalink raw reply [flat|nested] 130+ messages in thread* Re: [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code
2019-08-29 2:35 ` [dpdk-dev] [PATCH 00/63 v2] net/ice/base: update base code Qi Zhang
` (62 preceding siblings ...)
2019-08-29 2:36 ` [dpdk-dev] [PATCH v2 63/63] net/ice/base: ignore inverse switch recipes Qi Zhang
@ 2019-08-30 9:44 ` Ye Xiaolong
63 siblings, 0 replies; 130+ messages in thread
From: Ye Xiaolong @ 2019-08-30 9:44 UTC (permalink / raw)
To: Qi Zhang; +Cc: wenzhuo.lu, qiming.yang, dev
On 08/29, Qi Zhang wrote:
>Key Features:
>
>1) Add PPPoE, GTP protocol support for switch, FDIR, RSS
>2) Add Flexible Descriptor support.
>3) Improved package download.
>4) Improved RSS to support inner header
>5) Improved recipe management for switch rule
>
>v2:
>- improved commit log
>
>Qi Zhang (63):
> net/ice/base: enhance NVM read
> net/ice/base: add function to get FW mode
> net/ice/base: add support for NVM rollback detection
> net/ice/base: add support to init RXDID descs fields
> net/ice/base: store number of functions for the device
> net/ice/base: add read PBA module function
> net/ice/base: correct argument port info
> net/ice/base: remove debug code
> net/ice/base: add SFF EEPROM AQ Command
> net/ice/base: improve debug print message
> net/ice/base: add capabilities when in safe mode
> net/ice/base: add helper functions for PHY caching
> net/ice/base: add support for reading REPC statistics
> net/ice/base: adjust DCB INIT for SW mode
> net/ice/base: add NVM pkg flag
> net/ice/base: move VSI to VSI group
> net/ice/base: enable masking for RSS and FD field vectors
> net/ice/base: resolve static analysis issues
> net/ice/base: fix memory leak issue
> net/ice/base: check root pointer for validity
> net/ice/base: fix type-mismatch
> net/ice/base: correct overrun Coverty hit
> net/ice/base: update Boot Configuration Section read of NVM
> net/ice/base: add support for NVM access commands
> net/ice/base: add support for GTP and PPPoE protocols
> net/ice/base: add locks for flow functions
> net/ice/base: improve switch advanced rule
> net/ice/base: move function declaration
> net/ice/base: add 16-byte Flex Rx Descriptor
> net/ice/base: add 32-byte Flex Rx Desc for Comms package
> net/ice/base: update flag bits to current specification
> net/ice/base: add more opcode and macros
> net/ice/base: set status when global cfg lock is unavailable
> net/ice/base: initialize driver NVM data earlier
> net/ice/base: add function to configure Tx AQ command
> net/ice/base: add support for not locking sideband queue
> net/ice/base: associate recipes by profile type
> net/ice/base: return switch error on invalid match criteria
> net/ice/base: update UDP tunnel switch training packets
> net/ice/base: improve switch chained recipe
> net/ice/base: move and add some help function and macros
> net/ice/base: add routine for tunnel port query
> net/ice/base: ptype group consolidation
> net/ice/base: fix for RSS hash on inner UDP port
> net/ice/base: packet encapsulation for RSS
> net/ice/base: add RSS support for PPPoE and GTPU
> net/ice/base: remove unnecessary conditional check
> net/ice/base: fix flag settings in AQ call
> net/ice/base: refactor removal of VLAN promiscuous rules
> net/ice/base: maximize switch recipe words per line
> net/ice/base: update switch training packets with open ports
> net/ice/base: remove unnecessary dummy packet finding
> net/ice/base: remove unnecessary if branch
> net/ice/base: correct abbreviations
> net/ice/base: update to register definition file
> net/ice/base: replace open-code duplication
> net/ice/base: delay less
> net/ice/base: add AQC get link topology handle support
> net/ice/base: remove Rx flex descriptor programming
> net/ice/base: enable RSS with ether layer for PPPoE
> net/ice/base: add GENEVE offset
> net/ice/base: update profile to recipe bitmap array
> net/ice/base: ignore inverse switch recipes
>
> drivers/net/ice/base/ice_adminq_cmd.h | 221 ++++----
> drivers/net/ice/base/ice_bitops.h | 31 ++
> drivers/net/ice/base/ice_common.c | 902 ++++++++++++++++++------------
> drivers/net/ice/base/ice_common.h | 48 +-
> drivers/net/ice/base/ice_controlq.c | 54 +-
> drivers/net/ice/base/ice_controlq.h | 7 +-
> drivers/net/ice/base/ice_dcb.c | 6 +-
> drivers/net/ice/base/ice_dcb.h | 1 +
> drivers/net/ice/base/ice_devids.h | 6 +
> drivers/net/ice/base/ice_flex_pipe.c | 923 ++++++++++++++++++++++++++-----
> drivers/net/ice/base/ice_flex_pipe.h | 17 +-
> drivers/net/ice/base/ice_flex_type.h | 35 +-
> drivers/net/ice/base/ice_flow.c | 368 ++++++++----
> drivers/net/ice/base/ice_flow.h | 107 +++-
> drivers/net/ice/base/ice_hw_autogen.h | 34 ++
> drivers/net/ice/base/ice_lan_tx_rx.h | 76 ++-
> drivers/net/ice/base/ice_nvm.c | 294 +++++++++-
> drivers/net/ice/base/ice_nvm.h | 91 +++
> drivers/net/ice/base/ice_osdep.h | 2 +-
> drivers/net/ice/base/ice_protocol_type.h | 40 +-
> drivers/net/ice/base/ice_sched.c | 87 +--
> drivers/net/ice/base/ice_sched.h | 8 +-
> drivers/net/ice/base/ice_switch.c | 784 ++++++++++++++++++--------
> drivers/net/ice/base/ice_switch.h | 5 +
> drivers/net/ice/base/ice_type.h | 77 ++-
> 25 files changed, 3142 insertions(+), 1082 deletions(-)
> create mode 100644 drivers/net/ice/base/ice_nvm.h
>
>--
>2.13.6
>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
Series applied to dpdk-next-net-intel/master with some tweak on patch 13's commit log.
Thanks,
Xiaolong
^ permalink raw reply [flat|nested] 130+ messages in thread